1 /* CONTROL.C (c) Copyright Roger Bowler, 1994-2010 */
2 /* ESA/390 CPU Emulator */
3
4 /* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */
5 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */
6
7 /*-------------------------------------------------------------------*/
8 /* This module implements all control instructions of the */
9 /* S/370 and ESA/390 architectures, as described in the manuals */
10 /* GA22-7000-03 System/370 Principles of Operation */
11 /* SA22-7201-06 ESA/390 Principles of Operation */
12 /*-------------------------------------------------------------------*/
13
14 /*-------------------------------------------------------------------*/
15 /* Additional credits: */
16 /* Bad frame support by Jan Jaeger */
17 /* Branch tracing by Jan Jaeger */
18 /* CSP instructions by Jan Jaeger */
19 /* Instruction decode by macros - Jan Jaeger */
20 /* Prevent TOD from going backwards in time - Jan Jaeger */
21 /* Instruction decode rework - Jan Jaeger */
22 /* PR may lose pending interrupts - Jan Jaeger */
23 /* Modifications for Interpretive Execution (SIE) by Jan Jaeger */
24 /* ESAME low-address protection - Roger Bowler */
25 /* ESAME linkage stack operations - Roger Bowler */
26 /* ESAME BSA instruction - Roger Bowler v209c*/
27 /* ASN-and-LX-reuse facility - Roger Bowler June 2004*/
28 /* SIGP orders 11,12.2,13,15 - Fish Oct 2005*/
29 /* Configuration topology facility fixes by PaoloG Oct 2013*/
30 /*-------------------------------------------------------------------*/
31
32 #include "hstdinc.h"
33
34 #if !defined(_HENGINE_DLL_)
35 #define _HENGINE_DLL_
36 #endif
37
38 #if !defined(_CONTROL_C_)
39 #define _CONTROL_C_
40 #endif
41
42 #include "hercules.h"
43
44 #include "opcode.h"
45
46 #include "inline.h"
47
48 #if defined(OPTION_FISHIO)
49 #include "w32chan.h"
50 #endif // defined(OPTION_FISHIO)
51
52 /* Temporary debug */
53 extern int ipending_cmd(int,void *,void *);
54
55 #if defined(FEATURE_BRANCH_AND_SET_AUTHORITY)
56 /*-------------------------------------------------------------------*/
57 /* B25A BSA - Branch and Set Authority [RRE] */
58 /*-------------------------------------------------------------------*/
DEF_INST(branch_and_set_authority)59 DEF_INST(branch_and_set_authority)
60 {
61 int r1, r2; /* Values of R fields */
62 U32 ducto; /* DUCT origin */
63 U32 duct_pkrp; /* DUCT PKM/Key/RA/P word */
64 RADR duct_reta; /* DUCT return address/amode */
65 BYTE key; /* New PSW key */
66 #ifdef FEATURE_TRACING
67 CREG newcr12 = 0; /* CR12 upon completion */
68 #endif /*FEATURE_TRACING*/
69
70 RRE(inst, regs, r1, r2);
71
72 /* Special operation exception if ASF is not enabled */
73 if (!ASF_ENABLED(regs))
74 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
75
76 #if defined(_FEATURE_SIE)
77 if(SIE_STATB(regs, IC1, BSA))
78 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
79 #endif /*defined(_FEATURE_SIE)*/
80
81 /* Load real address of dispatchable unit control table */
82 ducto = regs->CR(2) & CR2_DUCTO;
83
84 /* Apply low-address protection to stores into the DUCT */
85 if (ARCH_DEP(is_low_address_protected) (ducto, regs))
86 {
87 #ifdef FEATURE_SUPPRESSION_ON_PROTECTION
88 regs->TEA = (ducto & STORAGE_KEY_PAGEMASK);
89 regs->excarid = 0;
90 #endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
91 ARCH_DEP(program_interrupt) (regs, PGM_PROTECTION_EXCEPTION);
92 }
93
94 /* Convert DUCT real address to absolute address */
95 ducto = APPLY_PREFIXING (ducto, regs->PX);
96
97 /* Program check if DUCT origin address is invalid */
98 if (ducto > regs->mainlim)
99 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
100
101 #if defined(FEATURE_ESAME)
102 /* For ESAME, load the PKM/Key/RA/P from DUCT word 5, and load
103 the return address and amode from DUCT words 8 and 9
104 (note: the DUCT cannot cross a page boundary) */
105 duct_pkrp = ARCH_DEP(fetch_fullword_absolute) (ducto+20, regs);
106 duct_reta = ARCH_DEP(fetch_doubleword_absolute) (ducto+32, regs);
107 #else /*!defined(FEATURE_ESAME)*/
108 /* For ESA/390, load the PKM/Key/RA/P from DUCT word 9, and load
109 the return address and amode from DUCT word 8
110 (note: the DUCT cannot cross a page boundary) */
111 duct_pkrp = ARCH_DEP(fetch_fullword_absolute) (ducto+36, regs);
112 duct_reta = ARCH_DEP(fetch_fullword_absolute) (ducto+32, regs);
113 #endif /*!defined(FEATURE_ESAME)*/
114
115 /* Perform base authority or reduced authority operation */
116 if ((duct_pkrp & DUCT_RA) == 0)
117 {
118 /* In base authority state R2 cannot specify register zero */
119 if (r2 == 0)
120 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
121
122 #ifdef FEATURE_TRACING
123 /* Perform tracing */
124 if (regs->CR(12) & CR12_BRTRACE)
125 newcr12 = ARCH_DEP(trace_br) (regs->GR_L(r2) & 0x80000000,
126 regs->GR_L(r2), regs);
127 #endif /*FEATURE_TRACING*/
128
129 /* Obtain the new PSW key from R1 register bits 24-27 */
130 key = regs->GR_L(r1) & 0x000000F0;
131
132 /* Privileged operation exception if in problem state and
133 current PSW key mask does not permit new key value */
134 if (PROBSTATE(®s->psw)
135 && ((regs->CR(3) << (key >> 4)) & 0x80000000) == 0 )
136 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
137
138 /* Save current PSW amode and instruction address */
139 #if defined(FEATURE_ESAME)
140 if (regs->psw.amode64)
141 {
142 duct_reta = PSW_IA(regs, 0);
143 }
144 else
145 #endif /*!defined(FEATURE_ESAME)*/
146 {
147 duct_reta = PSW_IA(regs, 0) & DUCT_IA31;
148 if (regs->psw.amode) duct_reta |= DUCT_AM31;
149 }
150
151 /* Save current PSW key mask, PSW key, and problem state */
152 duct_pkrp = (regs->CR(3) & CR3_KEYMASK) | regs->psw.pkey;
153 if (PROBSTATE(®s->psw)) duct_pkrp |= DUCT_PROB;
154
155 /* Set the reduced authority bit */
156 duct_pkrp |= DUCT_RA;
157
158 #if defined(FEATURE_ESAME)
159 /* For ESAME, store the PKM/Key/RA/P into DUCT word 5, and
160 store the return address and amode into DUCT words 8 and 9
161 (note: the DUCT cannot cross a page boundary) */
162 ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+20, regs);
163 ARCH_DEP(store_doubleword_absolute) (duct_reta, ducto+32, regs);
164 #else /*!defined(FEATURE_ESAME)*/
165 /* For ESA/390, store the PKM/Key/RA/P into DUCT word 9, and
166 store the return address and amode into DUCT word 8
167 (note: the DUCT cannot cross a page boundary) */
168 ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+36, regs);
169 ARCH_DEP(store_fullword_absolute) (duct_reta, ducto+32, regs);
170 #endif /*!defined(FEATURE_ESAME)*/
171
172 /* Load new PSW key and PSW key mask from R1 register */
173 regs->psw.pkey = key;
174 regs->CR_LHH(3) &= regs->GR_LHH(r1);
175
176 /* Set the problem state bit in the current PSW */
177 regs->psw.states |= BIT(PSW_PROB_BIT);
178
179 /* Set the breaking event address register */
180 SET_BEAR_REG(regs, regs->ip - 4);
181
182 /* Set PSW instruction address and amode from R2 register */
183 #if defined(FEATURE_ESAME)
184 if (regs->psw.amode64)
185 {
186 UPD_PSW_IA(regs, regs->GR_G(r2));
187 }
188 else
189 #endif /*defined(FEATURE_ESAME)*/
190 if (regs->GR_L(r2) & 0x80000000)
191 {
192 #if defined(FEATURE_ESAME)
193 regs->psw.amode64 = 0;
194 #endif /*defined(FEATURE_ESAME)*/
195 regs->psw.amode = 1;
196 regs->psw.AMASK = AMASK31;
197 UPD_PSW_IA(regs, regs->GR_L(r2));
198 }
199 else
200 {
201 #if defined(FEATURE_ESAME)
202 regs->psw.amode64 =
203 #endif /*defined(FEATURE_ESAME)*/
204 regs->psw.amode = 0;
205 regs->psw.AMASK = AMASK24;
206 UPD_PSW_IA(regs, regs->GR_L(r2));
207 }
208
209 } /* end if(BSA-ba) */
210 else
211 { /* BSA-ra */
212
213 /* In reduced authority state R2 must specify register zero */
214 if (r2 != 0)
215 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
216
217 #ifdef FEATURE_TRACING
218 /* Perform tracing */
219 if (regs->CR(12) & CR12_BRTRACE)
220 newcr12 = ARCH_DEP(trace_br) (duct_reta & DUCT_AM31,
221 duct_reta &DUCT_IA31, regs);
222 #endif /*FEATURE_TRACING*/
223
224 /* Set the breaking event address register */
225 SET_BEAR_REG(regs, regs->ip - 4);
226
227 /* If R1 is non-zero, save the current PSW addressing mode
228 and instruction address in the R1 register */
229 if (r1 != 0)
230 {
231 #if defined(FEATURE_ESAME)
232 if (regs->psw.amode64)
233 {
234 regs->GR_G(r1) = PSW_IA(regs, 0);
235 }
236 else
237 #endif /*defined(FEATURE_ESAME)*/
238 {
239 regs->GR_L(r1) = PSW_IA(regs, 0);
240 if (regs->psw.amode) regs->GR_L(r1) |= 0x80000000;
241 }
242 }
243
244 /* Restore PSW amode and instruction address from the DUCT */
245 #if defined(FEATURE_ESAME)
246 if (regs->psw.amode64)
247 {
248 UPD_PSW_IA(regs, duct_reta);
249 }
250 else
251 #endif /*defined(FEATURE_ESAME)*/
252 {
253 regs->psw.amode = (duct_reta & DUCT_AM31) ? 1 : 0;
254 regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
255 UPD_PSW_IA(regs, duct_reta & DUCT_IA31);
256 }
257
258 /* Restore the PSW key mask from the DUCT */
259 regs->CR_L(3) &= 0x0000FFFF;
260 regs->CR_L(3) |= duct_pkrp & DUCT_PKM;
261
262 /* Restore the PSW key from the DUCT */
263 regs->psw.pkey = duct_pkrp & DUCT_KEY;
264
265 /* Restore the problem state bit from the DUCT */
266 if (duct_pkrp & DUCT_PROB)
267 regs->psw.states |= BIT(PSW_PROB_BIT);
268 else
269 regs->psw.states &= ~BIT(PSW_PROB_BIT);
270
271 /* Reset the reduced authority bit in the DUCT */
272 duct_pkrp &= ~DUCT_RA;
273 #if defined(FEATURE_ESAME)
274 ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+20, regs);
275 #else /*!defined(FEATURE_ESAME)*/
276 ARCH_DEP(store_fullword_absolute) (duct_pkrp, ducto+36, regs);
277 #endif /*!defined(FEATURE_ESAME)*/
278
279 /* Specification exception if the PSW is now invalid. */
280 /* (Since UPD_PSW_IA used above masks off inval bits */
281 /* in psw.IA, test duct_reta for invalid bits). */
282 if ((duct_reta & 1)
283 #if defined(FEATURE_ESAME)
284 || (regs->psw.amode64 == 0 && regs->psw.amode == 0
285 && (duct_reta & 0x7F000000)))
286 #else /*!defined(FEATURE_ESAME)*/
287 || (regs->psw.amode == 0 && duct_reta > 0x00FFFFFF))
288 #endif /*!defined(FEATURE_ESAME)*/
289 {
290 /* program_interrupt will invoke INVALIDATE_AIA which */
291 /* will apply address mask to psw.IA if aie valid. */
292 regs->aie = NULL;
293 regs->psw.IA = duct_reta;
294 regs->psw.zeroilc = 1;
295 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
296 }
297
298 } /* end if(BSA-ra) */
299
300 #ifdef FEATURE_TRACING
301 /* Update trace table address if branch tracing is on */
302 if (regs->CR(12) & CR12_BRTRACE)
303 regs->CR(12) = newcr12;
304 #endif /*FEATURE_TRACING*/
305
306 /* Check for Successful Branch PER event */
307 PER_SB(regs, regs->psw.IA);
308
309 } /* end DEF_INST(branch_and_set_authority) */
310 #endif /*defined(FEATURE_BRANCH_AND_SET_AUTHORITY)*/
311
312
313 #if defined(FEATURE_SUBSPACE_GROUP)
314 /*-------------------------------------------------------------------*/
315 /* B258 BSG - Branch in Subspace Group [RRE] */
316 /*-------------------------------------------------------------------*/
DEF_INST(branch_in_subspace_group)317 DEF_INST(branch_in_subspace_group)
318 {
319 int r1, r2; /* Values of R fields */
320 U32 alet; /* Destination subspace ALET */
321 U32 dasteo=0; /* Destination ASTE origin */
322 U32 daste[16]; /* ASN second table entry */
323 RADR ducto; /* DUCT origin */
324 U32 duct0; /* DUCT word 0 */
325 U32 duct1; /* DUCT word 1 */
326 U32 duct3; /* DUCT word 3 */
327 RADR abs; /* Absolute address */
328 BYTE *mn; /* Mainstor address */
329 VADR newia; /* New instruction address */
330 U16 xcode; /* Exception code */
331 #ifdef FEATURE_TRACING
332 CREG newcr12 = 0; /* CR12 upon completion */
333 #endif /*FEATURE_TRACING*/
334 CREG inst_cr; /* Instruction CR */
335
336 RRE(inst, regs, r1, r2);
337
338 SIE_XC_INTERCEPT(regs);
339
340 /* Special operation exception if DAT is off or ASF not enabled */
341 if (REAL_MODE(&(regs->psw))
342 || !ASF_ENABLED(regs))
343 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
344
345 inst_cr = regs->CR(regs->aea_ar[USE_INST_SPACE]);
346
347 #ifdef FEATURE_TRACING
348 /* Perform tracing */
349 if (regs->CR(12) & CR12_ASNTRACE)
350 newcr12 = ARCH_DEP(trace_bsg) ((r2 == 0) ? 0 : regs->AR(r2),
351 regs->GR_L(r2), regs);
352 else
353 if (regs->CR(12) & CR12_BRTRACE)
354 newcr12 = ARCH_DEP(trace_br) (regs->GR_L(r2) & 0x80000000,
355 regs->GR_L(r2), regs);
356 #endif /*FEATURE_TRACING*/
357
358 /* Load real address of dispatchable unit control table */
359 ducto = regs->CR(2) & CR2_DUCTO;
360
361 /* Apply low-address protection to stores into the DUCT */
362 if (ARCH_DEP(is_low_address_protected) (ducto, regs))
363 {
364 #ifdef FEATURE_SUPPRESSION_ON_PROTECTION
365 regs->TEA = (ducto & STORAGE_KEY_PAGEMASK);
366 regs->excarid = 0;
367 #endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
368 ARCH_DEP(program_interrupt) (regs, PGM_PROTECTION_EXCEPTION);
369 }
370
371 /* Convert DUCT real address to absolute address */
372 ducto = APPLY_PREFIXING (ducto, regs->PX);
373
374 /* Program check if DUCT origin address is invalid */
375 if (ducto > regs->mainlim)
376 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
377
378 /* Fetch DUCT words 0, 1, and 3 from absolute storage
379 (note: the DUCT cannot cross a page boundary) */
380 mn = FETCH_MAIN_ABSOLUTE (ducto, regs, 16);
381 duct0 = fetch_fw (mn);
382 duct1 = fetch_fw (mn+4);
383 duct3 = fetch_fw (mn+12);
384
385 /* Special operation exception if the current primary ASTE origin
386 is not the same as the base ASTE for the dispatchable unit */
387 if ((regs->CR_L(5) & CR5_PASTEO) != (duct0 & DUCT0_BASTEO))
388 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
389
390 /* Obtain the destination ALET from the R2 access register,
391 except that register zero means destination ALET is zero */
392 alet = (r2 == 0) ? 0 : regs->AR(r2);
393
394 /* Perform special ALET translation to obtain destination ASTE */
395 switch (alet) {
396
397 case ALET_PRIMARY: /* Branch to base space */
398
399 /* Load the base space ASTE origin from the DUCT */
400 dasteo = duct0 & DUCT0_BASTEO;
401
402 /* Convert the ASTE origin to an absolute address */
403 abs = APPLY_PREFIXING (dasteo, regs->PX);
404
405 /* Program check if ASTE origin address is invalid */
406 if (abs > regs->mainlim)
407 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
408
409 /* Fetch destination ASTE words 2 and 3 from absolute storage
410 (note: the ASTE cannot cross a page boundary) */
411 mn = FETCH_MAIN_ABSOLUTE (abs, regs, 16);
412 daste[2] = fetch_fw (mn+8);
413 daste[3] = fetch_fw (mn+12);
414
415 break;
416
417 case ALET_SECONDARY: /* Branch to last-used subspace */
418
419 /* Load the subspace ASTE origin from the DUCT */
420 dasteo = duct1 & DUCT1_SSASTEO;
421
422 /* Special operation exception if SSASTEO is zero */
423 if (dasteo == 0)
424 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
425
426 /* Convert the ASTE origin to an absolute address */
427 abs = APPLY_PREFIXING (dasteo, regs->PX);
428
429 /* Program check if ASTE origin address is invalid */
430 if (abs > regs->mainlim)
431 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
432
433 /* Fetch subspace ASTE words 0, 2, 3, and 5 from absolute
434 storage (note: the ASTE cannot cross a page boundary) */
435 mn = FETCH_MAIN_ABSOLUTE (abs, regs, 24);
436 daste[0] = fetch_fw (mn);
437 daste[2] = fetch_fw (mn+8);
438 daste[3] = fetch_fw (mn+12);
439 daste[5] = fetch_fw (mn+20);
440
441 /* ASTE validity exception if ASTE invalid bit is one */
442 if (daste[0] & ASTE0_INVALID)
443 {
444 regs->excarid = r2;
445 ARCH_DEP(program_interrupt) (regs, PGM_ASTE_VALIDITY_EXCEPTION);
446 }
447
448 /* ASTE sequence exception if the subspace ASTE sequence
449 number does not match the sequence number in the DUCT */
450 if ((daste[5] & ASTE5_ASTESN) != (duct3 & DUCT3_SSASTESN))
451 {
452 regs->excarid = r2;
453 ARCH_DEP(program_interrupt) (regs, PGM_ASTE_SEQUENCE_EXCEPTION);
454 }
455
456 break;
457
458 default: /* ALET not 0 or 1 */
459
460 /* Perform special ART to obtain destination ASTE */
461 xcode = ARCH_DEP(translate_alet) (alet, 0, ACCTYPE_BSG, regs,
462 &dasteo, daste);
463
464 /* Program check if ALET translation error */
465 if (xcode != 0)
466 {
467 regs->excarid = r2;
468 ARCH_DEP(program_interrupt) (regs, xcode);
469 }
470
471 /* Special operation exception if the destination ASTE
472 is the base space of a different subspace group */
473 if (dasteo != (duct0 & DUCT0_BASTEO)
474 && ((ASTE_AS_DESIGNATOR(daste) & SSGROUP_BIT) == 0
475 || (daste[0] & ASTE0_BASE) ))
476 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
477
478 } /* end switch(alet) */
479
480 /* Update the primary STD (or ASCE) from the destination ASTE */
481 if ((dasteo == (duct0 & DUCT0_BASTEO)) && (alet != ALET_SECONDARY))
482 {
483 /* When the destination ASTE is the base space, replace the
484 primary STD (or ASCE) by the STD (or ASCE) in the ASTE */
485 regs->CR(1) = ASTE_AS_DESIGNATOR(daste);
486 }
487 else
488 {
489 /* When the destination ASTE is a subspace, replace
490 the primary STD or ASCE by the STD or ASTE in the
491 ASTE, except for the space-switch event and storage
492 alteration event bits, which remain unchanged */
493 regs->CR(1) &= (SSEVENT_BIT | SAEVENT_BIT);
494 regs->CR(1) |= (ASTE_AS_DESIGNATOR(daste)
495 & ~((RADR)(SSEVENT_BIT | SAEVENT_BIT)));
496 }
497
498 /* Compute the branch address from the R2 operand */
499 newia = regs->GR(r2);
500
501 /* If R1 is non-zero, save the current PSW addressing mode
502 and instruction address in the R1 register */
503 if (r1 != 0)
504 {
505 #if defined(FEATURE_ESAME)
506 if (regs->psw.amode64)
507 regs->GR_G(r1) = PSW_IA(regs, 0);
508 else
509 #endif /*!defined(FEATURE_ESAME)*/
510 regs->GR_L(r1) = PSW_IA(regs, 0) |
511 (regs->psw.amode ? 0x80000000 : 0);
512 }
513
514 /* Update the breaking event address register */
515 SET_BEAR_REG(regs, regs->ip - 4);
516
517 #if defined(FEATURE_ESAME)
518 if (regs->psw.amode64 == 0 && (newia & 0x80000000))
519 #else /*!defined(FEATURE_ESAME)*/
520 if (newia & 0x80000000)
521 #endif /*!defined(FEATURE_ESAME)*/
522 {
523 regs->psw.amode = 1;
524 regs->psw.AMASK = AMASK31;
525 }
526 else
527 {
528 regs->psw.amode = 0;
529 regs->psw.AMASK = AMASK24;
530 }
531
532 /* Set mode and branch to address specified by R2 operand */
533 UPD_PSW_IA(regs, newia);
534
535 /* Set the SSTD (or SASCE) equal to PSTD (or PASCE) */
536 regs->CR(7) = regs->CR(1);
537
538 /* Set SASN equal to PASN */
539 regs->CR_LHL(3) = regs->CR_LHL(4);
540
541 /* When ASN-and-LX-reuse is installed and enabled by CR0,
542 set the SASTEIN in CR3 equal to the PASTEIN in CR4 */
543 if (ASN_AND_LX_REUSE_ENABLED(regs))
544 {
545 regs->CR_H(3) = regs->CR_H(4);
546 } /* end if (ASN_AND_LX_REUSE_ENABLED) */
547
548 /* Reset the subspace fields in the DUCT */
549 if (alet == ALET_SECONDARY)
550 {
551 /* When the destination ASTE specifies a subspace by means
552 of ALET 1, set the subspace active bit in the DUCT */
553 duct1 |= DUCT1_SA;
554 ARCH_DEP(store_fullword_absolute) (duct1, ducto+4, regs);
555 }
556 else if (dasteo == (duct0 & DUCT0_BASTEO))
557 {
558 /* When the destination ASTE is the base space,
559 reset the subspace active bit in the DUCT */
560 duct1 &= ~DUCT1_SA;
561 ARCH_DEP(store_fullword_absolute) (duct1, ducto+4, regs);
562 }
563 else
564 {
565 /* When the destination ASTE specifies a subspace by means
566 of an ALET other than ALET 1, set the subspace active
567 bit and store the subspace ASTE origin in the DUCT */
568 duct1 = DUCT1_SA | dasteo;
569 ARCH_DEP(store_fullword_absolute) (duct1, ducto+4, regs);
570
571 /* Set the subspace ASTE sequence number in the DUCT
572 equal to the destination ASTE sequence number */
573 duct3 = daste[5];
574 ARCH_DEP(store_fullword_absolute) (duct3, ducto+12, regs);
575 }
576
577 #ifdef FEATURE_TRACING
578 /* Update trace table address if ASN tracing or branch tracing */
579 if (regs->CR(12) & (CR12_ASNTRACE | CR12_BRTRACE))
580 regs->CR(12) = newcr12;
581 #endif /*FEATURE_TRACING*/
582
583 SET_AEA_COMMON(regs);
584 if (inst_cr != regs->CR(regs->aea_ar[USE_INST_SPACE]))
585 INVALIDATE_AIA(regs);
586
587 /* Check for Successful Branch PER event */
588 PER_SB(regs, regs->psw.IA);
589
590 } /* end DEF_INST(branch_in_subspace_group) */
591 #endif /*defined(FEATURE_SUBSPACE_GROUP)*/
592
593
594 #if defined(FEATURE_LINKAGE_STACK)
595 /*-------------------------------------------------------------------*/
596 /* B240 BAKR - Branch and Stack Register [RRE] */
597 /*-------------------------------------------------------------------*/
DEF_INST(branch_and_stack)598 DEF_INST(branch_and_stack)
599 {
600 int r1, r2; /* Values of R fields */
601 VADR n1, n2; /* Operand values */
602 #ifdef FEATURE_TRACING
603 VADR n = 0; /* Work area */
604 #endif /*FEATURE_TRACING*/
605
606 RRE(inst, regs, r1, r2);
607
608 SIE_XC_INTERCEPT(regs);
609
610 #if defined(_FEATURE_SIE)
611 if(SIE_STATB(regs, IC3, BAKR))
612 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
613 #endif /*defined(_FEATURE_SIE)*/
614
615 /* [5.12.3]/ Fig 10-2 Special operation exception if ASF is not enabled,
616 or if DAT is off, or if not primary-space mode or AR-mode */
617 if (!ASF_ENABLED(regs)
618 || REAL_MODE(®s->psw)
619 || SPACE_BIT(®s->psw))
620 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
621
622 /* Obtain the return address and addressing mode from
623 the R1 register, or use updated PSW if R1 is zero */
624 if ( r1 != 0 )
625 {
626 n1 = regs->GR(r1);
627 #if defined(FEATURE_ESAME)
628 if ( (n1 & 0x01) == 0 )
629 n1 &= (n1 & 0x80000000) ? 0xFFFFFFFF : 0x00FFFFFF;
630 #else /*!defined(FEATURE_ESAME)*/
631 if ( (n1 & 0x80000000) == 0 )
632 n1 &= 0x00FFFFFF;
633 #endif /*!defined(FEATURE_ESAME)*/
634 }
635 else
636 {
637 n1 = PSW_IA(regs, 0);
638 #if defined(FEATURE_ESAME)
639 if ( regs->psw.amode64 )
640 n1 |= 0x01;
641 else
642 #endif /*defined(FEATURE_ESAME)*/
643 if ( regs->psw.amode )
644 n1 |= 0x80000000;
645 }
646
647 /* Obtain the branch address from the R2 register, or use
648 the updated PSW instruction address if R2 is zero */
649 n2 = (r2 != 0) ? regs->GR(r2) : PSW_IA(regs, 0);
650 n2 &= ADDRESS_MAXWRAP(regs);
651
652 /* Set the addressing mode bit in the branch address */
653 #if defined(FEATURE_ESAME)
654 if ( regs->psw.amode64 )
655 n2 |= 0x01;
656 else
657 #endif /*defined(FEATURE_ESAME)*/
658 if ( regs->psw.amode )
659 n2 |= 0x80000000;
660
661 #ifdef FEATURE_TRACING
662 /* Form the branch trace entry */
663 if((regs->CR(12) & CR12_BRTRACE) && (r2 != 0))
664 n = ARCH_DEP(trace_br)(regs->psw.amode, regs->GR_L(r2), regs);
665 #endif /*FEATURE_TRACING*/
666
667 /* Form the linkage stack entry */
668 ARCH_DEP(form_stack_entry) (LSED_UET_BAKR, n1, n2, 0, 0, regs);
669
670 #ifdef FEATURE_TRACING
671 /* Update CR12 to reflect the new branch trace entry */
672 if((regs->CR(12) & CR12_BRTRACE) && (r2 != 0))
673 regs->CR(12) = n;
674 #endif /*FEATURE_TRACING*/
675
676 /* Execute the branch unless R2 specifies register 0 */
677 if ( r2 != 0 )
678 {
679 UPDATE_BEAR(regs, -4);
680 UPD_PSW_IA(regs, regs->GR(r2));
681 PER_SB(regs, regs->psw.IA);
682 }
683
684 } /* end DEF_INST(branch_and_stack) */
685 #endif /*defined(FEATURE_LINKAGE_STACK)*/
686
687
688 #if defined(FEATURE_BROADCASTED_PURGING)
689 /*-------------------------------------------------------------------*/
690 /* B250 CSP - Compare and Swap and Purge [RRE] */
691 /*-------------------------------------------------------------------*/
DEF_INST(compare_and_swap_and_purge)692 DEF_INST(compare_and_swap_and_purge)
693 {
694 int r1, r2; /* Values of R fields */
695 U64 n2; /* virtual address of op2 */
696 BYTE *main2; /* mainstor address of op2 */
697 U32 old; /* old value */
698
699 RRE(inst, regs, r1, r2);
700
701 PRIV_CHECK(regs);
702
703 ODD_CHECK(r1, regs);
704
705 #if defined(_FEATURE_SIE)
706 if(SIE_STATB(regs,IC0, IPTECSP))
707 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
708 #endif /*defined(_FEATURE_SIE)*/
709
710 #if defined(_FEATURE_SIE)
711 if(SIE_MODE(regs) && regs->sie_scao)
712 {
713 STORAGE_KEY(regs->sie_scao, regs) |= STORKEY_REF;
714 if(regs->mainstor[regs->sie_scao] & 0x80)
715 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
716 }
717 #endif /*defined(_FEATURE_SIE)*/
718
719 /* Perform serialization before starting operation */
720 PERFORM_SERIALIZATION (regs);
721
722 /* Obtain 2nd operand address from r2 */
723 n2 = regs->GR(r2) & 0xFFFFFFFFFFFFFFFCULL & ADDRESS_MAXWRAP(regs);
724 main2 = MADDR (n2, r2, regs, ACCTYPE_WRITE, regs->psw.pkey);
725
726 old = CSWAP32 (regs->GR_L(r1));
727
728 /* Obtain main-storage access lock */
729 OBTAIN_MAINLOCK(regs);
730
731 /* Attempt to exchange the values */
732 regs->psw.cc = cmpxchg4 (&old, CSWAP32(regs->GR_L(r1+1)), main2);
733
734 /* Release main-storage access lock */
735 RELEASE_MAINLOCK(regs);
736
737 if (regs->psw.cc == 0)
738 {
739 /* Perform requested funtion specified as per request code in r2 */
740 if (regs->GR_L(r2) & 3)
741 {
742 OBTAIN_INTLOCK(regs);
743 SYNCHRONIZE_CPUS(regs);
744 if (regs->GR_L(r2) & 1)
745 ARCH_DEP(purge_tlb_all)();
746 if (regs->GR_L(r2) & 2)
747 ARCH_DEP(purge_alb_all)();
748 RELEASE_INTLOCK(regs);
749 }
750 }
751 else
752 {
753 PTT(PTT_CL_CSF,"*CSP",regs->GR_L(r1),regs->GR_L(r2),regs->psw.IA_L);
754
755 /* Otherwise yield */
756 regs->GR_L(r1) = CSWAP32(old);
757 if (sysblk.cpus > 1)
758 sched_yield();
759 }
760
761 /* Perform serialization after completing operation */
762 PERFORM_SERIALIZATION (regs);
763
764 } /* end DEF_INST(compare_and_swap_and_purge) */
765 #endif /*defined(FEATURE_BROADCASTED_PURGING)*/
766
767
768 /*-------------------------------------------------------------------*/
769 /* 83 DIAG - Diagnose [RS] */
770 /*-------------------------------------------------------------------*/
DEF_INST(diagnose)771 DEF_INST(diagnose)
772 {
773 int r1, r3; /* Register numbers */
774 int b2; /* Base of effective addr */
775 VADR effective_addr2; /* Effective address */
776
777 RS(inst, regs, r1, r3, b2, effective_addr2);
778
779 #if defined(FEATURE_ECPSVM)
780 if(ecpsvm_dodiag(regs,r1,r3,b2,effective_addr2)==0)
781 {
782 return;
783 }
784 #endif
785
786 #ifdef FEATURE_HERCULES_DIAGCALLS
787 if (
788 #if defined(_FEATURE_SIE)
789 !SIE_MODE(regs) &&
790 #endif /* defined(_FEATURE_SIE) */
791 effective_addr2 != 0xF08)
792 #endif
793
794 PRIV_CHECK(regs);
795
796 SIE_INTERCEPT(regs);
797
798 PTT(PTT_CL_INF,"DIAG",regs->GR_L(r1),regs->GR_L(r3),(U32)(effective_addr2 & 0xffffff));
799
800 /* Process diagnose instruction */
801 ARCH_DEP(diagnose_call) (effective_addr2, b2, r1, r3, regs);
802
803 /* Perform serialization and checkpoint-synchronization */
804 PERFORM_SERIALIZATION (regs);
805 PERFORM_CHKPT_SYNC (regs);
806
807 #ifdef FEATURE_HERCULES_DIAGCALLS
808 RETURN_INTCHECK(regs);
809 #endif
810
811 } /* end DEF_INST(diagnose) */
812
813
814 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
815 /*-------------------------------------------------------------------*/
816 /* B226 EPAR - Extract Primary ASN [RRE] */
817 /*-------------------------------------------------------------------*/
DEF_INST(extract_primary_asn)818 DEF_INST(extract_primary_asn)
819 {
820 int r1, r2; /* Values of R fields */
821
822 RRE(inst, regs, r1, r2);
823
824 SIE_XC_INTERCEPT(regs);
825
826 /* Special operation exception if DAT is off */
827 if ( (regs->psw.sysmask & PSW_DATMODE) == 0 )
828 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
829
830 /* Privileged operation exception if in problem state
831 and the extraction-authority control bit is zero */
832 if ( PROBSTATE(®s->psw)
833 && (regs->CR(0) & CR0_EXT_AUTH) == 0 )
834 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
835
836 /* Load R1 bits 48-63 with PASN from control register 4 bits 48-63
837 and zeroize R1 bits 32-47 */
838 regs->GR_L(r1) = regs->CR_LHL(4);
839
840 } /* end DEF_INST(extract_primary_asn) */
841 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
842
843
844 #if defined(FEATURE_ASN_AND_LX_REUSE)
845 /*-------------------------------------------------------------------*/
846 /* B99A EPAIR - Extract Primary ASN and Instance [RRE] */
847 /*-------------------------------------------------------------------*/
DEF_INST(extract_primary_asn_and_instance)848 DEF_INST(extract_primary_asn_and_instance)
849 {
850 int r1, r2; /* Values of R fields */
851
852 /* Operation exception if ASN-and-LX-reuse is not enabled */
853 if(!sysblk.asnandlxreuse)
854 {
855 ARCH_DEP(operation_exception)(inst,regs);
856 }
857
858 RRE(inst, regs, r1, r2);
859
860 SIE_XC_INTERCEPT(regs);
861
862 /* Special operation exception if DAT is off */
863 if ( (regs->psw.sysmask & PSW_DATMODE) == 0 )
864 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
865
866 /* Privileged operation exception if in problem state
867 and the extraction-authority control bit is zero */
868 if ( PROBSTATE(®s->psw)
869 && (regs->CR(0) & CR0_EXT_AUTH) == 0 )
870 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
871
872 /* Load R1 bits 48-63 with PASN from control register 4 bits 48-63
873 and zeroize R1 bits 32-47 */
874 regs->GR_L(r1) = regs->CR_LHL(4);
875
876 /* Load R1 bits 0-31 with PASTEIN from control register 4 bits 0-31 */
877 regs->GR_H(r1) = regs->CR_H(4);
878
879 } /* end DEF_INST(extract_primary_asn_and_instance) */
880 #endif /*defined(FEATURE_ASN_AND_LX_REUSE)*/
881
882
883 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
884 /*-------------------------------------------------------------------*/
885 /* B227 ESAR - Extract Secondary ASN [RRE] */
886 /*-------------------------------------------------------------------*/
DEF_INST(extract_secondary_asn)887 DEF_INST(extract_secondary_asn)
888 {
889 int r1, r2; /* Values of R fields */
890
891 RRE(inst, regs, r1, r2);
892
893 SIE_XC_INTERCEPT(regs);
894
895 /* Special operation exception if DAT is off */
896 if ( (regs->psw.sysmask & PSW_DATMODE) == 0 )
897 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
898
899 /* Privileged operation exception if in problem state
900 and the extraction-authority control bit is zero */
901 if ( PROBSTATE(®s->psw)
902 && (regs->CR(0) & CR0_EXT_AUTH) == 0 )
903 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
904
905 /* Load R1 bits 48-63 with SASN from control register 3 bits 48-63
906 and zeroize R1 bits 32-47 */
907 regs->GR_L(r1) = regs->CR_LHL(3);
908
909 } /* end DEF_INST(extract_secondary_asn) */
910 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
911
912
913 #if defined(FEATURE_ASN_AND_LX_REUSE)
914 /*-------------------------------------------------------------------*/
915 /* B99B ESAIR - Extract Secondary ASN and Instance [RRE] */
916 /*-------------------------------------------------------------------*/
DEF_INST(extract_secondary_asn_and_instance)917 DEF_INST(extract_secondary_asn_and_instance)
918 {
919 int r1, r2; /* Values of R fields */
920
921
922 /* Operation exception if ASN-and-LX-reuse is not enabled */
923 if(!sysblk.asnandlxreuse)
924 {
925 ARCH_DEP(operation_exception)(inst,regs);
926 }
927
928 RRE(inst, regs, r1, r2);
929
930 SIE_XC_INTERCEPT(regs);
931
932 /* Special operation exception if DAT is off */
933 if ( (regs->psw.sysmask & PSW_DATMODE) == 0 )
934 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
935
936 /* Privileged operation exception if in problem state
937 and the extraction-authority control bit is zero */
938 if ( PROBSTATE(®s->psw)
939 && (regs->CR(0) & CR0_EXT_AUTH) == 0 )
940 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
941
942 /* Load R1 bits 48-63 with SASN from control register 3 bits 48-63
943 and zeroize R1 bits 32-47 */
944 regs->GR_L(r1) = regs->CR_LHL(3);
945
946 /* Load R1 bits 0-31 with SASTEIN from control register 3 bits 0-31 */
947 regs->GR_H(r1) = regs->CR_H(3);
948
949 } /* end DEF_INST(extract_secondary_asn_and_instance) */
950 #endif /*defined(FEATURE_ASN_AND_LX_REUSE)*/
951
952
953 #if defined(FEATURE_LINKAGE_STACK)
954 /*-------------------------------------------------------------------*/
955 /* B249 EREG - Extract Stacked Registers [RRE] */
956 /*-------------------------------------------------------------------*/
DEF_INST(extract_stacked_registers)957 DEF_INST(extract_stacked_registers)
958 {
959 int r1, r2; /* Values of R fields */
960 LSED lsed; /* Linkage stack entry desc. */
961 VADR lsea; /* Linkage stack entry addr */
962
963 RRE(inst, regs, r1, r2);
964
965 SIE_XC_INTERCEPT(regs);
966
967 /* Find the virtual address of the entry descriptor
968 of the current state entry in the linkage stack */
969 lsea = ARCH_DEP(locate_stack_entry) (0, &lsed, regs);
970
971 /* Load registers from the stack entry */
972 ARCH_DEP(unstack_registers) (0, lsea, r1, r2, regs);
973
974 }
975 #endif /*defined(FEATURE_LINKAGE_STACK)*/
976
977
978 #if defined(FEATURE_LINKAGE_STACK)
979 /*-------------------------------------------------------------------*/
980 /* B24A ESTA - Extract Stacked State [RRE] */
981 /*-------------------------------------------------------------------*/
DEF_INST(extract_stacked_state)982 DEF_INST(extract_stacked_state)
983 {
984 int r1, r2; /* Values of R fields */
985 BYTE code; /* Extraction code */
986 LSED lsed; /* Linkage stack entry desc. */
987 VADR lsea; /* Linkage stack entry addr */
988 int max_esta_code;
989
990
991 RRE(inst, regs, r1, r2);
992
993 SIE_XC_INTERCEPT(regs);
994
995 if (REAL_MODE(®s->psw)
996 || SECONDARY_SPACE_MODE(®s->psw)
997 || !ASF_ENABLED(regs))
998 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
999
1000 /* Load the extraction code from low-order byte of R2 register */
1001 code = regs->GR_LHLCL(r2);
1002
1003 #if defined(FEATURE_ASN_AND_LX_REUSE)
1004 max_esta_code=sysblk.asnandlxreuse?5:4;
1005 #elif defined(FEATURE_ESAME)
1006 max_esta_code=4;
1007 #else /*!defined(FEATURE_ESAME)*/
1008 max_esta_code=3;
1009 #endif /*!defined(FEATURE_ESAME)*/
1010
1011 /* Program check if r1 is odd, or if extraction code is invalid */
1012 if ((r1 & 1) || code > max_esta_code)
1013 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
1014
1015 /* Find the virtual address of the entry descriptor
1016 of the current state entry in the linkage stack */
1017 lsea = ARCH_DEP(locate_stack_entry) (0, &lsed, regs);
1018
1019 /* Load general register pair from state entry */
1020 ARCH_DEP(stack_extract) (lsea, r1, code, regs);
1021
1022 /* Set condition code depending on entry type */
1023 regs->psw.cc = ((lsed.uet & LSED_UET_ET) == LSED_UET_PC) ? 1 : 0;
1024
1025 }
1026 #endif /*defined(FEATURE_LINKAGE_STACK)*/
1027
1028
1029 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
1030 /*-------------------------------------------------------------------*/
1031 /* B224 IAC - Insert Address Space Control [RRE] */
1032 /*-------------------------------------------------------------------*/
DEF_INST(insert_address_space_control)1033 DEF_INST(insert_address_space_control)
1034 {
1035 int r1, r2; /* Values of R fields */
1036
1037 RRE(inst, regs, r1, r2);
1038
1039 /* Special operation exception if DAT is off */
1040 if ( REAL_MODE(&(regs->psw))
1041 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
1042 /* Except in XC mode */
1043 && !SIE_STATB(regs, MX, XC)
1044 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
1045 )
1046 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
1047
1048 /* Privileged operation exception if in problem state
1049 and the extraction-authority control bit is zero */
1050 if ( PROBSTATE(®s->psw)
1051 && !(regs->CR(0) & CR0_EXT_AUTH)
1052 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
1053 /* Ignore extraction control in XC mode */
1054 && !SIE_STATB(regs, MX, XC)
1055 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
1056 )
1057 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
1058
1059 /* Extract the address-space control bits from the PSW */
1060 regs->psw.cc = (AR_BIT(®s->psw) << 1) | SPACE_BIT(®s->psw);
1061
1062 /* Insert address-space mode into register bits 22-23 */
1063 regs->GR_LHLCH(r1) = regs->psw.cc;
1064
1065 }
1066 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
1067
1068
1069 /*-------------------------------------------------------------------*/
1070 /* B20B IPK - Insert PSW Key [S] */
1071 /*-------------------------------------------------------------------*/
DEF_INST(insert_psw_key)1072 DEF_INST(insert_psw_key)
1073 {
1074 int b2; /* Base of effective addr */
1075 VADR effective_addr2; /* Effective address */
1076
1077 S(inst, regs, b2, effective_addr2);
1078
1079 /* Privileged operation exception if in problem state
1080 and the extraction-authority control bit is zero */
1081 if ( PROBSTATE(®s->psw)
1082 && (regs->CR(0) & CR0_EXT_AUTH) == 0 )
1083 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
1084
1085 /* Insert PSW key into bits 24-27 of general register 2
1086 and set bits 28-31 of general register 2 to zero */
1087 regs->GR_LHLCL(2) = regs->psw.pkey & 0xF0;
1088
1089 }
1090
1091
1092 #if defined(FEATURE_BASIC_STORAGE_KEYS)
1093 /*-------------------------------------------------------------------*/
1094 /* 09 ISK - Insert Storage Key [RR] */
1095 /*-------------------------------------------------------------------*/
DEF_INST(insert_storage_key)1096 DEF_INST(insert_storage_key)
1097 {
1098 int r1, r2; /* Values of R fields */
1099 RADR n; /* Absolute storage addr */
1100 #if defined(_FEATURE_SIE)
1101 BYTE storkey;
1102 #endif /*defined(_FEATURE_SIE)*/
1103
1104 RR(inst, regs, r1, r2);
1105
1106 PRIV_CHECK(regs);
1107
1108 #if defined(FEATURE_4K_STORAGE_KEYS) || defined(_FEATURE_SIE)
1109 if(
1110 #if defined(_FEATURE_SIE) && !defined(FEATURE_4K_STORAGE_KEYS)
1111 SIE_MODE(regs) &&
1112 #endif
1113 !(regs->CR(0) & CR0_STORKEY_4K) )
1114 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
1115 #endif
1116
1117 /* Program check if R2 bits 28-31 are not zeroes */
1118 if ( regs->GR_L(r2) & 0x0000000F )
1119 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
1120
1121 /* Load 2K block address from R2 register */
1122 n = regs->GR_L(r2) & 0x00FFF800;
1123
1124 /* Convert real address to absolute address */
1125 n = APPLY_PREFIXING (n, regs->PX);
1126
1127 /* Addressing exception if block is outside main storage */
1128 if ( n > regs->mainlim )
1129 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
1130
1131 #if defined(_FEATURE_SIE)
1132 if(SIE_MODE(regs))
1133 {
1134 if(SIE_STATB(regs, IC2, ISKE))
1135 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1136
1137 if(!regs->sie_pref)
1138 {
1139 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1140 if(SIE_STATB(regs, RCPO0, SKA)
1141 && SIE_STATB(regs, RCPO2, RCPBY))
1142 {
1143 SIE_TRANSLATE(&n, ACCTYPE_SIE, regs);
1144
1145 #if !defined(_FEATURE_2K_STORAGE_KEYS)
1146 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xFE;
1147 #else
1148 regs->GR_LHLCL(r1) = (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE;
1149 #endif
1150 }
1151 else
1152 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1153 {
1154 RADR rcpa;
1155 BYTE rcpkey;
1156
1157 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1158 if(SIE_STATB(regs, RCPO0, SKA))
1159 {
1160 /* guest absolute to host PTE addr */
1161 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
1162 regs->hostregs, ACCTYPE_PTE))
1163 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1164
1165 /* Convert real address to absolute address */
1166 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
1167
1168 /* The reference and change byte is located directly
1169 beyond the page table and is located at offset 1 in
1170 the entry. S/370 mode cannot be emulated in ESAME
1171 mode, so no provision is made for ESAME mode tables */
1172 rcpa += 1025;
1173 }
1174 else
1175 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1176 {
1177 /* Obtain address of the RCP area from the state desc */
1178 rcpa = regs->sie_rcpo &= 0x7FFFF000;
1179
1180 /* frame index as byte offset to 4K keys in RCP area */
1181 rcpa += n >> 12;
1182
1183 /* host primary to host absolute */
1184 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
1185 regs->hostregs, ACCTYPE_SIE, 0);
1186 }
1187
1188 /* fetch the RCP key */
1189 rcpkey = regs->mainstor[rcpa];
1190 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
1191 /* The storage key is obtained by logical or
1192 or the real and guest RC bits */
1193 storkey = rcpkey & (STORKEY_REF | STORKEY_CHANGE);
1194
1195 /* guest absolute to host real */
1196 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
1197 regs->hostregs, ACCTYPE_SIE))
1198 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1199 {
1200 /* In case of storage key assist obtain the
1201 key and fetch bit from the PGSTE */
1202 if(SIE_STATB(regs, RCPO0, SKA))
1203 regs->GR_LHLCL(r1) = storkey | (regs->mainstor[rcpa-1]
1204 & (STORKEY_KEY | STORKEY_FETCH));
1205 else
1206 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1207 }
1208 else
1209 #else /*!defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1210 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1211 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1212 {
1213 /* host real to host absolute */
1214 n = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
1215
1216 #if !defined(_FEATURE_2K_STORAGE_KEYS)
1217 regs->GR_LHLCL(r1) = storkey
1218 | (STORAGE_KEY(n, regs) & 0xFE);
1219 #else
1220 regs->GR_LHLCL(r1) = storkey
1221 | ((STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE);
1222 #endif
1223 }
1224 }
1225 }
1226 else /* !sie_pref */
1227 #if !defined(_FEATURE_2K_STORAGE_KEYS)
1228 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xFE;
1229 #else
1230 regs->GR_LHLCL(r1) = (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE;
1231 #endif
1232 }
1233 else /* !SIE_MODE */
1234 #endif /*defined(_FEATURE_SIE)*/
1235 /* Insert the storage key into R1 register bits 24-31 */
1236 #if defined(_FEATURE_2K_STORAGE_KEYS)
1237 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xFE;
1238 #else
1239 regs->GR_LHLCL(r1) = (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE;
1240 #endif
1241
1242 /* In BC mode, clear bits 29-31 of R1 register */
1243 if ( !ECMODE(®s->psw) )
1244 regs->GR_LHLCL(r1) &= 0xF8;
1245
1246 // /*debug*/logmsg("ISK storage block %8.8X key %2.2X\n",
1247 // regs->GR_L(r2), regs->GR_L(r1) & 0xFE);
1248
1249 }
1250 #endif /*defined(FEATURE_BASIC_STORAGE_KEYS)*/
1251
1252
1253 #if defined(FEATURE_EXTENDED_STORAGE_KEYS)
1254 /*-------------------------------------------------------------------*/
1255 /* B229 ISKE - Insert Storage Key Extended [RRE] */
1256 /*-------------------------------------------------------------------*/
DEF_INST(insert_storage_key_extended)1257 DEF_INST(insert_storage_key_extended)
1258 {
1259 int r1, r2; /* Values of R fields */
1260 RADR n; /* Workarea */
1261 #if defined(_FEATURE_SIE)
1262 BYTE storkey;
1263 #endif /*defined(_FEATURE_SIE)*/
1264
1265 RRE(inst, regs, r1, r2);
1266
1267 PRIV_CHECK(regs);
1268
1269 /* Load 4K block address from R2 register */
1270 n = regs->GR(r2) & ADDRESS_MAXWRAP_E(regs);
1271
1272 /* Convert real address to absolute address */
1273 n = APPLY_PREFIXING (n, regs->PX);
1274
1275 /* Addressing exception if block is outside main storage */
1276 if ( n > regs->mainlim )
1277 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
1278
1279 #if defined(_FEATURE_SIE)
1280 if(SIE_MODE(regs))
1281 {
1282 if(SIE_STATB(regs, IC2, ISKE))
1283 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1284
1285 if(!regs->sie_pref)
1286 {
1287 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1288 if((SIE_STATB(regs, RCPO0, SKA)
1289 #if defined(_FEATURE_ZSIE)
1290 || (regs->hostregs->arch_mode == ARCH_900)
1291 #endif /*defined(_FEATURE_ZSIE)*/
1292 ) && SIE_STATB(regs, RCPO2, RCPBY))
1293 {
1294 SIE_TRANSLATE(&n, ACCTYPE_SIE, regs);
1295
1296 /* Insert the storage key into R1 register bits 24-31 */
1297 #if !defined(_FEATURE_2K_STORAGE_KEYS)
1298 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xFE;
1299 #else
1300 regs->GR_LHLCL(r1) = (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE;
1301 #endif
1302 }
1303 else
1304 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1305 {
1306 RADR rcpa;
1307 BYTE rcpkey;
1308
1309 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1310 if(SIE_STATB(regs, RCPO0, SKA)
1311 #if defined(_FEATURE_ZSIE)
1312 || (regs->hostregs->arch_mode == ARCH_900)
1313 #endif /*defined(_FEATURE_ZSIE)*/
1314 )
1315 {
1316 /* guest absolute to host PTE addr */
1317 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
1318 regs->hostregs, ACCTYPE_PTE))
1319 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1320
1321 /* Convert real address to absolute address */
1322 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
1323
1324 /* For ESA/390 the RCP byte entry is at offset 1 in a
1325 four byte entry directly beyond the page table,
1326 for ESAME mode, this entry is eight bytes long */
1327 rcpa += regs->hostregs->arch_mode == ARCH_900 ? 2049 : 1025;
1328 }
1329 else
1330 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1331 {
1332 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
1333 if(SIE_STATB(regs, MX, XC))
1334 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1335 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
1336
1337 /* Obtain address of the RCP area from the state desc */
1338 rcpa = regs->sie_rcpo &= 0x7FFFF000;
1339
1340 /* frame index as byte offset to 4K keys in RCP area */
1341 rcpa += n >> 12;
1342
1343 /* host primary to host absolute */
1344 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
1345 regs->hostregs, ACCTYPE_SIE, 0);
1346 }
1347
1348 /* fetch the RCP key */
1349 rcpkey = regs->mainstor[rcpa];
1350 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
1351 /* The storage key is obtained by logical or
1352 or the real and guest RC bits */
1353 storkey = rcpkey & (STORKEY_REF | STORKEY_CHANGE);
1354
1355 /* guest absolute to host real */
1356 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
1357 regs->hostregs, ACCTYPE_SIE))
1358 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1359 {
1360 /* In case of storage key assist obtain the
1361 key and fetch bit from the PGSTE */
1362 if(SIE_STATB(regs, RCPO0, SKA))
1363 regs->GR_LHLCL(r1) = storkey | (regs->mainstor[rcpa-1]
1364 & (STORKEY_KEY | STORKEY_FETCH));
1365 else
1366 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1367 }
1368 else
1369 #else /*!defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1370 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1371 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1372 {
1373 /* host real to host absolute */
1374 n = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
1375
1376 /* Insert the storage key into R1 register bits 24-31 */
1377 #if !defined(_FEATURE_2K_STORAGE_KEYS)
1378 regs->GR_LHLCL(r1) = storkey | (STORAGE_KEY(n, regs) & 0xFE);
1379 #else
1380 regs->GR_LHLCL(r1) = storkey | ((STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE);
1381 #endif
1382 }
1383 }
1384 }
1385 else /* sie_pref */
1386 /* Insert the storage key into R1 register bits 24-31 */
1387 #if !defined(_FEATURE_2K_STORAGE_KEYS)
1388 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xFE;
1389 #else
1390 regs->GR_LHLCL(r1) = (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE;
1391 #endif
1392 }
1393 else /* !SIE_MODE */
1394 #endif /*defined(_FEATURE_SIE)*/
1395 /* Insert the storage key into R1 register bits 24-31 */
1396 #if !defined(_FEATURE_2K_STORAGE_KEYS)
1397 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xFE;
1398 #else
1399 regs->GR_LHLCL(r1) = (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)) & 0xFE;
1400 #endif
1401
1402 } /* end DEF_INST(insert_storage_key_extended) */
1403 #endif /*defined(FEATURE_EXTENDED_STORAGE_KEYS)*/
1404
1405
1406 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
1407 /*-------------------------------------------------------------------*/
1408 /* B223 IVSK - Insert Virtual Storage Key [RRE] */
1409 /*-------------------------------------------------------------------*/
DEF_INST(insert_virtual_storage_key)1410 DEF_INST(insert_virtual_storage_key)
1411 {
1412 int r1, r2; /* Values of R fields */
1413 VADR effective_addr; /* Virtual storage addr */
1414 RADR n; /* 32-bit operand values */
1415 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1416 int sr; /* SIE_TRANSLATE_ADDR rc */
1417 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1418
1419 RRE(inst, regs, r1, r2);
1420
1421 /* Special operation exception if DAT is off */
1422 if ( (regs->psw.sysmask & PSW_DATMODE) == 0 )
1423 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
1424
1425 /* Privileged operation exception if in problem state
1426 and the extraction-authority control bit is zero */
1427 if ( PROBSTATE(®s->psw)
1428 && (regs->CR(0) & CR0_EXT_AUTH) == 0 )
1429 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
1430
1431 /* Load virtual storage address from R2 register */
1432 effective_addr = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
1433
1434 /* Translate virtual address to real address */
1435 if (ARCH_DEP(translate_addr) (effective_addr, r2, regs, ACCTYPE_IVSK))
1436 ARCH_DEP(program_interrupt) (regs, regs->dat.xcode);
1437
1438 /* Convert real address to absolute address */
1439 n = APPLY_PREFIXING (regs->dat.raddr, regs->PX);
1440
1441 /* Addressing exception if block is outside main storage */
1442 if ( n > regs->mainlim )
1443 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
1444
1445 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
1446 /* When running under SIE, and the guest absolute address
1447 is paged out, then obtain the storage key from the
1448 SPGTE rather then causing a host page fault. */
1449 if(SIE_MODE(regs)
1450 && !regs->sie_pref
1451 && (SIE_STATB(regs, RCPO0, SKA)
1452 #if defined(_FEATURE_ZSIE)
1453 || (regs->hostregs->arch_mode == ARCH_900)
1454 #endif /*defined(_FEATURE_ZSIE)*/
1455 ) && !SIE_FEATB(regs, RCPO2, RCPBY))
1456 {
1457 /* guest absolute to host absolute addr or PTE addr in case of rc2 */
1458 sr = SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
1459 regs->hostregs, ACCTYPE_SIE);
1460
1461 n = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
1462
1463 if(sr != 0 && sr != 2)
1464 ARCH_DEP(program_interrupt) (regs->hostregs, regs->hostregs->dat.xcode);
1465
1466 if(sr == 2)
1467 {
1468 /* For ESA/390 the RCP byte entry is at offset 0 in a
1469 four byte entry directly beyond the page table,
1470 for ESAME mode, this entry is eight bytes long */
1471 n += regs->hostregs->arch_mode == ARCH_900 ? 2048 : 1024;
1472
1473 /* Insert PGSTE key bits 0-4 into R1 register bits
1474 56-60 and set bits 61-63 to zeroes */
1475 regs->GR_LHLCL(r1) = regs->mainstor[n] & 0xF8;
1476 }
1477 else
1478 /* Insert storage key bits 0-4 into R1 register bits
1479 56-60 and set bits 61-63 to zeroes */
1480 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xF8;
1481 }
1482 else
1483 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
1484 {
1485 SIE_TRANSLATE(&n, ACCTYPE_SIE, regs);
1486 /* Insert storage key bits 0-4 into R1 register bits
1487 56-60 and set bits 61-63 to zeroes */
1488 regs->GR_LHLCL(r1) = STORAGE_KEY(n, regs) & 0xF8;
1489 }
1490
1491 } /* end DEF_INST(insert_virtual_storage_key) */
1492 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
1493
1494
1495 /*-------------------------------------------------------------------*/
1496 /* B221 IPTE - Invalidate Page Table Entry [RRE] */
1497 /*-------------------------------------------------------------------*/
DEF_INST(invalidate_page_table_entry)1498 DEF_INST(invalidate_page_table_entry)
1499 {
1500 int r1, r2; /* Values of R fields */
1501 RADR op1;
1502 U32 op2;
1503 #if defined(FEATURE_IPTE_RANGE_FACILITY)
1504 int r3;
1505 int op3;
1506 #endif /*defined(FEATURE_IPTE_RANGE_FACILITY)*/
1507
1508 #if defined(FEATURE_IPTE_RANGE_FACILITY)
1509 RRR(inst, regs, r1, r2, r3);
1510 #else /*defined(FEATURE_IPTE_RANGE_FACILITY)*/
1511 RRE(inst, regs, r1, r2);
1512 #endif /*defined(FEATURE_IPTE_RANGE_FACILITY)*/
1513
1514 PRIV_CHECK(regs);
1515
1516 op1 = regs->GR(r1);
1517 op2 = regs->GR_L(r2);
1518 #if defined(FEATURE_IPTE_RANGE_FACILITY)
1519 if (r3)
1520 {
1521 op3 = regs->GR_LHLCL(r3);
1522
1523 if(op3 + ((op2 >> 12) & 0xFF) > 0xFF)
1524 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
1525 }
1526 else
1527 op3 = 0;
1528 #endif /*defined(FEATURE_IPTE_RANGE_FACILITY)*/
1529
1530 #if defined(_FEATURE_SIE)
1531 if(SIE_STATB(regs, IC0, IPTECSP))
1532 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1533 #endif /*defined(_FEATURE_SIE)*/
1534
1535 /* Perform serialization before operation */
1536 PERFORM_SERIALIZATION (regs);
1537 OBTAIN_INTLOCK(regs);
1538 SYNCHRONIZE_CPUS(regs);
1539
1540 #if defined(_FEATURE_SIE)
1541 if(SIE_MODE(regs) && regs->sie_scao)
1542 {
1543 STORAGE_KEY(regs->sie_scao, regs) |= STORKEY_REF;
1544 if(regs->mainstor[regs->sie_scao] & 0x80)
1545 {
1546 RELEASE_INTLOCK(regs);
1547 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1548 }
1549 regs->mainstor[regs->sie_scao] |= 0x80;
1550 STORAGE_KEY(regs->sie_scao, regs) |= (STORKEY_REF|STORKEY_CHANGE);
1551 }
1552 #endif /*defined(_FEATURE_SIE)*/
1553
1554 #if defined(FEATURE_IPTE_RANGE_FACILITY)
1555 /* Invalidate the additional ptes as specfied by op3 */
1556 for( ; op3; op3--, op2 += 0x1000)
1557 ARCH_DEP(invalidate_pte) (inst[1], op1, op2, regs);
1558 #endif /*defined(FEATURE_IPTE_RANGE_FACILITY)*/
1559
1560 /* Invalidate page table entry */
1561 ARCH_DEP(invalidate_pte) (inst[1], op1, op2, regs);
1562
1563 #if defined(_FEATURE_SIE)
1564 if(SIE_MODE(regs) && regs->sie_scao)
1565 {
1566 regs->mainstor[regs->sie_scao] &= 0x7F;
1567 STORAGE_KEY(regs->sie_scao, regs) |= (STORKEY_REF|STORKEY_CHANGE);
1568 }
1569 #endif /*defined(_FEATURE_SIE)*/
1570
1571 RELEASE_INTLOCK(regs);
1572
1573 } /* DEF_INST(invalidate_page_table_entry) */
1574
1575
1576 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
1577 /*-------------------------------------------------------------------*/
1578 /* E500 LASP - Load Address Space Parameters [SSE] */
1579 /*-------------------------------------------------------------------*/
DEF_INST(load_address_space_parameters)1580 DEF_INST(load_address_space_parameters)
1581 {
1582 int b1, b2; /* Values of base field */
1583 VADR effective_addr1,
1584 effective_addr2; /* Effective addresses */
1585 U64 dreg;
1586 U32 sastein_d = 0; /* Designated SASTEIN */
1587 U32 pastein_d = 0; /* Designated PASTEIN */
1588 U32 sastein_new = 0; /* New SASTEIN */
1589 U32 pastein_new = 0; /* New PASTEIN */
1590 U16 pkm_d; /* Designated PKM */
1591 U16 sasn_d; /* Designated SASN */
1592 U16 ax_d; /* Designated AX */
1593 U16 pasn_d; /* Designated PASN */
1594 U32 aste[16]; /* ASN second table entry */
1595 RADR pstd; /* Primary STD */
1596 RADR sstd; /* Secondary STD */
1597 U32 ltd; /* Linkage table designation */
1598 U32 pasteo=0; /* Primary ASTE origin */
1599 U32 sasteo=0; /* Secondary ASTE origin */
1600 U16 ax; /* Authorisation index */
1601 #ifdef FEATURE_SUBSPACE_GROUP
1602 U16 xcode; /* Exception code */
1603 #endif /*FEATURE_SUBSPACE_GROUP*/
1604 CREG inst_cr; /* Instruction CR */
1605
1606 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
1607
1608 SIE_XC_INTERCEPT(regs);
1609
1610 PRIV_CHECK(regs);
1611
1612 /* Special operation exception if ASN translation control
1613 (bit 12 of control register 14) is zero */
1614 if ( (regs->CR(14) & CR14_ASN_TRAN) == 0 )
1615 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
1616
1617 DW_CHECK(effective_addr1, regs);
1618
1619 #if defined(_FEATURE_SIE)
1620 if(SIE_STATB(regs, IC2, LASP))
1621 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1622 #endif /*defined(_FEATURE_SIE)*/
1623
1624 inst_cr = regs->CR(regs->aea_ar[USE_INST_SPACE]);
1625
1626 /* Fetch LASP parameters from first operand location
1627 (note that the storage-operand references for LASP
1628 may be multiple-access references) */
1629 if (ASN_AND_LX_REUSE_ENABLED(regs))
1630 {
1631 /* When ASN-and-LX-reuse is installed and enabled by CR0,
1632 the first operand consists of two doublewords */
1633
1634 /* The first doubleword contains the SASTEIN-d (32 bits),
1635 PKM-d (16 bits), and SASN-d (16 bits) */
1636 dreg = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
1637 sastein_d = (dreg >> 32);
1638 pkm_d = (dreg >> 16) & 0xFFFF;
1639 sasn_d = dreg & 0xFFFF;
1640
1641 /* The second doubleword contains the PASTEIN-d (32 bits),
1642 AX-d (16 bits), and PASN-d (16 bits) */
1643 effective_addr1 += 8;
1644 effective_addr1 &= ADDRESS_MAXWRAP(regs);
1645 dreg = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
1646 pastein_d = (dreg >> 32);
1647 ax_d = (dreg >> 16) & 0xFFFF;
1648 pasn_d = dreg & 0xFFFF;
1649 }
1650 else /* !ASN_AND_LX_REUSE_ENABLED */
1651 {
1652 /* When ASN-and-LX-reuse is not installed or not enabled,
1653 the first operand is one doubleword containing the
1654 PKM-d, SASN-d, AX-d, and PASN-d (16 bits each) */
1655 dreg = ARCH_DEP(vfetch8) ( effective_addr1, b1, regs );
1656 pkm_d = (dreg >> 48) & 0xFFFF;
1657 sasn_d = (dreg >> 32) & 0xFFFF;
1658 ax_d = (dreg >> 16) & 0xFFFF;
1659 pasn_d = dreg & 0xFFFF;
1660 } /* end else !ASN_AND_LX_REUSE_ENABLED */
1661
1662 /* PASN translation */
1663
1664 /* Perform PASN translation if PASN not equal to current
1665 PASN, or if LASP function bit 29 is set */
1666 if ((effective_addr2 & 0x00000004)
1667 || pasn_d != regs->CR_LHL(4) )
1668 {
1669 /* Translate PASN and return condition code 1 if
1670 AFX- or ASX-translation exception condition */
1671 if (ARCH_DEP(translate_asn) (pasn_d, regs, &pasteo, aste))
1672 {
1673 regs->psw.cc = 1;
1674 return;
1675 }
1676
1677 /* When ASN-and-LX-reuse is installed and enabled by CR0,
1678 condition code 1 is also set if the PASTEIN-d does not
1679 equal the ASTEIN in word 11 of the ASTE */
1680 if (ASN_AND_LX_REUSE_ENABLED(regs)
1681 && pastein_d != aste[11])
1682 {
1683 regs->psw.cc = 1;
1684 return;
1685 } /* end if(ASN_AND_LX_REUSE_ENABLED && pastein_d!=aste[11]) */
1686
1687 /* Obtain new PSTD and LTD from ASTE */
1688 pstd = ASTE_AS_DESIGNATOR(aste);
1689 ltd = ASTE_LT_DESIGNATOR(aste);
1690 ax = (aste[1] & ASTE1_AX) >> 16;
1691
1692 /* When ASN-and-LX-reuse is installed and enabled by CR0,
1693 set the new PASTEIN equal to the PASTEIN-d */
1694 if (ASN_AND_LX_REUSE_ENABLED(regs))
1695 pastein_new = pastein_d;
1696
1697 #ifdef FEATURE_SUBSPACE_GROUP
1698 /* Perform subspace replacement on new PSTD */
1699 pstd = ARCH_DEP(subspace_replace) (pstd, pasteo, &xcode, regs);
1700
1701 /* Return with condition code 1 if ASTE exception recognized */
1702 if (xcode != 0)
1703 {
1704 regs->psw.cc = 1;
1705 return;
1706 }
1707 #endif /*FEATURE_SUBSPACE_GROUP*/
1708
1709 /* Return with condition code 3 if either current STD
1710 or new STD indicates a space switch event */
1711 if ((regs->CR(1) & SSEVENT_BIT)
1712 || (ASTE_AS_DESIGNATOR(aste) & SSEVENT_BIT))
1713 {
1714 regs->psw.cc = 3;
1715 return;
1716 }
1717
1718 }
1719 else
1720 {
1721 /* Load current PSTD and LTD or PASTEO */
1722 pstd = regs->CR(1);
1723 ltd = regs->CR_L(5); /* ZZZ1 NOT SURE ABOUT THE MEANING OF THIS CODE: REFER TO ZZZ2 */
1724 pasteo = regs->CR_L(5); /* ZZZ1 NOT SURE ABOUT THE MEANING OF THIS CODE: REFER TO ZZZ2 */
1725 ax = (regs->CR(4) & CR4_AX) >> 16;
1726
1727 /* When ASN-and-LX-reuse is installed and enabled by CR0,
1728 load the current PASTEIN */
1729 if (ASN_AND_LX_REUSE_ENABLED(regs))
1730 pastein_new = regs->CR_H(4);
1731 }
1732
1733 /* If bit 30 of the LASP function bits is zero,
1734 use the current AX instead of the AX specified
1735 in the first operand */
1736 if ((effective_addr2 & 0x00000002))
1737 ax = ax_d;
1738
1739 /* SASN translation */
1740
1741 /* If new SASN = new PASN then set new SSTD = new PSTD,
1742 also set the new SASTEIN equal to new PASTEIN when
1743 ASN-and-LX-reuse is installed and enabled by CR0 */
1744 if (sasn_d == pasn_d)
1745 {
1746 sstd = pstd;
1747 if (ASN_AND_LX_REUSE_ENABLED(regs))
1748 sastein_new = pastein_new;
1749 }
1750 else
1751 {
1752 /* If new SASN = current SASN, and bit 29 of the LASP
1753 function bits is 0, and bit 31 of the LASP function bits
1754 is 1, use current SSTD/SASCE in control register 7, also
1755 use current SASTEIN if ASN-and-LX-reuse is installed and
1756 enabled by CR0 */
1757 if (!(effective_addr2 & 0x00000004)
1758 && (effective_addr2 & 0x00000001)
1759 && (sasn_d == regs->CR_LHL(3)))
1760 {
1761 sstd = regs->CR(7);
1762 if (ASN_AND_LX_REUSE_ENABLED(regs))
1763 sastein_new = regs->CR_H(3);
1764 }
1765 else
1766 {
1767 /* Translate SASN and return condition code 2 if
1768 AFX- or ASX-translation exception condition */
1769 if (ARCH_DEP(translate_asn) (sasn_d, regs, &sasteo, aste))
1770 {
1771 regs->psw.cc = 2;
1772 return;
1773 }
1774
1775 /* When ASN-and-LX-reuse is installed and enabled by CR0,
1776 condition code 2 is also set if the SASTEIN-d does not
1777 equal the ASTEIN in word 11 of the ASTE */
1778 if (ASN_AND_LX_REUSE_ENABLED(regs)
1779 && sastein_d != aste[11])
1780 {
1781 regs->psw.cc = 2;
1782 return;
1783 } /* end if(ASN_AND_LX_REUSE_ENABLED && sastein_d!=aste[11]) */
1784
1785 /* Obtain new SSTD or SASCE from secondary ASTE */
1786 sstd = ASTE_AS_DESIGNATOR(aste);
1787
1788 /* When ASN-and-LX-reuse is installed and enabled by CR0,
1789 set the new SASTEIN equal to the SASTEIN-d */
1790 if (ASN_AND_LX_REUSE_ENABLED(regs))
1791 sastein_new = sastein_d;
1792
1793 #ifdef FEATURE_SUBSPACE_GROUP
1794 /* Perform subspace replacement on new SSTD */
1795 sstd = ARCH_DEP(subspace_replace) (sstd, sasteo,
1796 &xcode, regs);
1797
1798 /* Return condition code 2 if ASTE exception recognized */
1799 if (xcode != 0)
1800 {
1801 regs->psw.cc = 2;
1802 return;
1803 }
1804 #endif /*FEATURE_SUBSPACE_GROUP*/
1805
1806 /* Perform SASN authorization if bit 31 of the
1807 LASP function bits is 0 */
1808 if (!(effective_addr2 & 0x00000001))
1809 {
1810 /* Condition code 2 if SASN authorization fails */
1811 if (ARCH_DEP(authorize_asn) (ax, aste, ATE_SECONDARY,
1812 regs))
1813 {
1814 regs->psw.cc = 2;
1815 return;
1816 }
1817
1818 } /* end if(SASN authorization) */
1819
1820 } /* end if(SASN translation) */
1821
1822 } /* end if(SASN = PASN) */
1823
1824 /* Perform control-register loading */
1825 regs->CR(1) = pstd;
1826 regs->CR_LHH(3) = pkm_d;
1827 regs->CR_LHL(3) = sasn_d;
1828 regs->CR_LHH(4) = ax;
1829 regs->CR_LHL(4) = pasn_d;
1830 regs->CR_L(5) = ASF_ENABLED(regs) ? pasteo : ltd; /* ZZZ2 NOT SURE ABOUT THE MEANING OF THIS CODE: REFER TO ZZZ1 */
1831 regs->CR(7) = sstd;
1832 if (ASN_AND_LX_REUSE_ENABLED(regs))
1833 {
1834 regs->CR_H(3) = sastein_new;
1835 regs->CR_H(4) = pastein_new;
1836 } /* end if(ASN_AND_LX_REUSE_ENABLED) */
1837
1838 SET_AEA_COMMON(regs);
1839 if (inst_cr != regs->CR(regs->aea_ar[USE_INST_SPACE]))
1840 INVALIDATE_AIA(regs);
1841
1842 /* Return condition code zero */
1843 regs->psw.cc = 0;
1844
1845 } /* end DEF_INST(load_address_space_parameters) */
1846 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
1847
1848
1849 /*-------------------------------------------------------------------*/
1850 /* B7 LCTL - Load Control [RS] */
1851 /*-------------------------------------------------------------------*/
DEF_INST(load_control)1852 DEF_INST(load_control)
1853 {
1854 int r1, r3; /* Register numbers */
1855 int b2; /* Base of effective addr */
1856 VADR effective_addr2; /* Effective address */
1857 int i, m, n; /* Integer work areas */
1858 U32 *p1, *p2 = NULL; /* Mainstor pointers */
1859 U16 updated = 0; /* Updated control regs */
1860
1861 RS(inst, regs, r1, r3, b2, effective_addr2);
1862
1863 #if defined(FEATURE_ECPSVM)
1864 if(ecpsvm_dolctl(regs,r1,r3,b2,effective_addr2)==0)
1865 {
1866 return;
1867 }
1868 #endif
1869
1870 PRIV_CHECK(regs);
1871
1872 FW_CHECK(effective_addr2, regs);
1873
1874 /* Calculate number of regs to load */
1875 n = ((r3 - r1) & 0xF) + 1;
1876
1877 ITIMER_SYNC(effective_addr2,(n*4)-1,regs);
1878
1879 #if defined(_FEATURE_SIE)
1880 if (SIE_MODE(regs))
1881 {
1882 U16 cr_mask = fetch_hw (regs->siebk->lctl_ctl);
1883 for (i = 0; i < n; i++)
1884 if (cr_mask & BIT(15 - ((r1 + i) & 0xF)))
1885 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1886 }
1887 #endif /*defined(_FEATURE_SIE)*/
1888
1889 /* Calculate number of words to next boundary */
1890 m = (0x800 - (effective_addr2 & 0x7ff)) >> 2;
1891
1892 /* Address of operand beginning */
1893 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_READ, regs->psw.pkey);
1894
1895 /* Get address of next page if boundary crossed */
1896 if (unlikely (m < n))
1897 p2 = (U32*)MADDR(effective_addr2 + (m*4), b2, regs, ACCTYPE_READ, regs->psw.pkey);
1898 else
1899 m = n;
1900
1901 /* Copy from operand beginning */
1902 for (i = 0; i < m; i++, p1++)
1903 {
1904 regs->CR_L((r1 + i) & 0xF) = fetch_fw (p1);
1905 updated |= BIT((r1 + i) & 0xF);
1906 }
1907
1908 /* Copy from next page */
1909 for ( ; i < n; i++, p2++)
1910 {
1911 regs->CR_L((r1 + i) & 0xF) = fetch_fw (p2);
1912 updated |= BIT((r1 + i) & 0xF);
1913 }
1914
1915 /* Actions based on updated control regs */
1916 SET_IC_MASK(regs);
1917 #if __GEN_ARCH == 370
1918 if (updated & BIT(1))
1919 {
1920 SET_AEA_COMMON(regs);
1921 INVALIDATE_AIA(regs);
1922 }
1923 #else
1924 if (updated & (BIT(1) | BIT(7) | BIT(13)))
1925 SET_AEA_COMMON(regs);
1926 if (updated & BIT(regs->aea_ar[USE_INST_SPACE]))
1927 INVALIDATE_AIA(regs);
1928 #endif
1929 if (updated & BIT(9))
1930 {
1931 OBTAIN_INTLOCK(regs);
1932 SET_IC_PER(regs);
1933 RELEASE_INTLOCK(regs);
1934 if (EN_IC_PER_SA(regs))
1935 ARCH_DEP(invalidate_tlb)(regs,~(ACC_WRITE|ACC_CHECK));
1936 }
1937
1938 RETURN_INTCHECK(regs);
1939
1940 } /* end DEF_INST(load_control) */
1941
1942
1943 /*-------------------------------------------------------------------*/
1944 /* 82 LPSW - Load Program Status Word [S] */
1945 /*-------------------------------------------------------------------*/
DEF_INST(load_program_status_word)1946 DEF_INST(load_program_status_word)
1947 {
1948 int b2; /* Base of effective addr */
1949 VADR effective_addr2; /* Effective address */
1950 DBLWRD dword;
1951 int rc;
1952 #if defined(FEATURE_ESAME)
1953 int amode64;
1954 #endif /*defined(FEATURE_ESAME)*/
1955
1956 S(inst, regs, b2, effective_addr2);
1957 #if defined(FEATURE_ECPSVM)
1958 if(ecpsvm_dolpsw(regs,b2,effective_addr2)==0)
1959 {
1960 return;
1961 }
1962 #endif
1963
1964 PRIV_CHECK(regs);
1965
1966 DW_CHECK(effective_addr2, regs);
1967
1968 #if defined(_FEATURE_SIE)
1969 if(SIE_STATB(regs, IC1, LPSW))
1970 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
1971 #endif /*defined(_FEATURE_SIE)*/
1972
1973 /* Perform serialization and checkpoint synchronization */
1974 PERFORM_SERIALIZATION (regs);
1975 PERFORM_CHKPT_SYNC (regs);
1976
1977 /* Fetch new PSW from operand address */
1978 STORE_DW ( dword, ARCH_DEP(vfetch8) ( effective_addr2, b2, regs ) );
1979
1980 /* Set the breaking event address register */
1981 SET_BEAR_REG(regs, regs->ip - 4);
1982
1983 /* Load updated PSW (ESA/390 Format in ESAME mode) */
1984 #if !defined(FEATURE_ESAME)
1985 if ((rc = ARCH_DEP(load_psw) ( regs, dword )))
1986 ARCH_DEP(program_interrupt) (regs, rc);
1987 #else /*defined(FEATURE_ESAME)*/
1988
1989 /* Make the PSW valid for ESA/390 mode
1990 after first saving our amode64 flag */
1991 amode64 = dword[3] & 0x01;
1992 dword[3] &= ~0x01;
1993
1994 /* Now call 's390_load_psw' to load our ESA/390 PSW for us */
1995 rc = s390_load_psw ( regs, dword );
1996
1997 /* PROGRAMMING NOTE: z/Arch (ESAME) only supports the loading
1998 of ESA/390 mode (Extended Control mode (i.e. EC mode)) PSWs
1999 via the LPSW instruction. Thus the above 's390_load_psw' call
2000 has already checked to make sure bit 12 -- the EC mode bit
2001 (otherwise also known as the 'NOTESAME' bit) -- was set when
2002 the PSW was loaded (otherwise it would not have even returned
2003 and instead would have thrown a PGM_SPECIFICATION_EXCEPTION).
2004
2005 Since we're actually executing in z/Arch (ESAME) mode though
2006 we now need to turn that bit off (since it's not supposed to
2007 be on for z/Arch (ESAME) mode) as explained in the Principles
2008 of Operations manual for the LPSW instruction.
2009 */
2010 regs->psw.states &= ~BIT(PSW_NOTESAME_BIT);
2011
2012 /* Restore the amode64 flag setting and set the actual correct
2013 AMASK value according to it (if we need to) since we had to
2014 force non-amode64 further above to get the 's390_load_psw'
2015 function to work right without erroneously program-checking.
2016 */
2017 if((regs->psw.amode64 = amode64))
2018 {
2019 regs->psw.AMASK = AMASK64;
2020
2021 /* amode31 bit must be set when amode64 is set */
2022 if(!regs->psw.amode)
2023 {
2024 regs->psw.zeroilc = 1;
2025 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
2026 }
2027 }
2028 else
2029 /* Clear the high word of the address mask since
2030 the 's390_load_psw' function didn't do that for us */
2031 regs->psw.AMASK_H = 0;
2032
2033 /* Check for Load PSW success/failure */
2034 if (rc)
2035 ARCH_DEP(program_interrupt) (regs, rc);
2036
2037 /* Clear the high word of the instruction address since
2038 the 's390_load_psw' function didn't do that for us */
2039 regs->psw.IA_H = 0;
2040
2041 #endif /*defined(FEATURE_ESAME)*/
2042
2043 /* Perform serialization and checkpoint synchronization */
2044 PERFORM_SERIALIZATION (regs);
2045 PERFORM_CHKPT_SYNC (regs);
2046
2047 RETURN_INTCHECK(regs);
2048
2049 } /* end DEF_INST(load_program_status_word) */
2050
2051
2052 /*-------------------------------------------------------------------*/
2053 /* B1 LRA - Load Real Address [RX] */
2054 /*-------------------------------------------------------------------*/
DEF_INST(load_real_address)2055 DEF_INST(load_real_address)
2056 {
2057 int r1; /* Register number */
2058 int b2; /* Base of effective addr */
2059 VADR effective_addr2; /* Effective address */
2060
2061 RX(inst, regs, r1, b2, effective_addr2);
2062
2063 ARCH_DEP(load_real_address_proc) (regs, r1, b2, effective_addr2);
2064
2065 } /* end DEF_INST(load_real_address) */
2066
2067
2068 /*-------------------------------------------------------------------*/
2069 /* Common processing routine for the LRA and LRAY instructions */
2070 /*-------------------------------------------------------------------*/
ARCH_DEP(load_real_address_proc)2071 void ARCH_DEP(load_real_address_proc) (REGS *regs,
2072 int r1, int b2, VADR effective_addr2)
2073 {
2074 int cc; /* Condition code */
2075
2076 SIE_XC_INTERCEPT(regs);
2077
2078 PRIV_CHECK(regs);
2079
2080 /* Translate the effective address to a real address */
2081 cc = ARCH_DEP(translate_addr) (effective_addr2, b2, regs, ACCTYPE_LRA);
2082
2083 /* If ALET exception or ASCE-type or region translation
2084 exception, set exception code in R1 bits 48-63, set
2085 bit 32 of R1, and set condition code 3 */
2086 if (cc > 3) {
2087 regs->GR_L(r1) = 0x80000000 | regs->dat.xcode;
2088 cc = 3;
2089 }
2090 else
2091 {
2092 /* Set r1 and condition code as returned by translate_addr */
2093 #if defined(FEATURE_ESAME)
2094 if (regs->psw.amode64 && cc != 3)
2095 {
2096 regs->GR_G(r1) = regs->dat.raddr;
2097 }
2098 else
2099 {
2100 if (regs->dat.raddr <= 0x7FFFFFFF)
2101 {
2102 regs->GR_L(r1) = regs->dat.raddr;
2103 }
2104 else
2105 {
2106 /* Special handling if in 24-bit or 31-bit mode
2107 and the returned address exceeds 2GB, or if
2108 cc=3 and the returned address exceeds 2GB */
2109 if (cc == 0)
2110 {
2111 /* Real address exceeds 2GB */
2112 ARCH_DEP(program_interrupt) (regs,
2113 PGM_SPECIAL_OPERATION_EXCEPTION);
2114 }
2115
2116 /* Condition code is 1, 2, or 3, and the returned
2117 table entry address exceeds 2GB. Convert to
2118 condition code 3 and return the exception code
2119 which will be X'0010' or X'0011' */
2120 regs->GR_L(r1) = 0x80000000 | regs->dat.xcode;
2121 cc = 3;
2122 } /* end else(regs->dat.raddr) */
2123 } /* end else(amode) */
2124 #else /*!defined(FEATURE_ESAME)*/
2125 regs->GR_L(r1) = regs->dat.raddr;
2126 #endif /*!defined(FEATURE_ESAME)*/
2127 } /* end else(cc) */
2128
2129 regs->psw.cc = cc;
2130
2131 } /* end ARCH_DEP(load_real_address_proc) */
2132
2133
2134 /*-------------------------------------------------------------------*/
2135 /* B24B LURA - Load Using Real Address [RRE] */
2136 /*-------------------------------------------------------------------*/
DEF_INST(load_using_real_address)2137 DEF_INST(load_using_real_address)
2138 {
2139 int r1, r2; /* Values of R fields */
2140 RADR n; /* Unsigned work */
2141
2142 RRE(inst, regs, r1, r2);
2143
2144 PRIV_CHECK(regs);
2145
2146 /* R2 register contains operand real storage address */
2147 n = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
2148
2149 /* Program check if operand not on fullword boundary */
2150 FW_CHECK(n, regs);
2151
2152 /* Load R1 register from second operand */
2153 regs->GR_L(r1) = ARCH_DEP(vfetch4) ( n, USE_REAL_ADDR, regs );
2154
2155 }
2156
2157
2158 #if defined(FEATURE_LOCK_PAGE)
2159 /*-------------------------------------------------------------------*/
2160 /* B262 LKPG - Lock Page [RRE] */
2161 /*-------------------------------------------------------------------*/
DEF_INST(lock_page)2162 DEF_INST(lock_page)
2163 {
2164 int r1, r2; /* Values of R fields */
2165 VADR n2; /* effective addr of r2 */
2166 RADR rpte; /* PTE real address */
2167 CREG pte; /* Page Table Entry */
2168
2169 RRE(inst, regs, r1, r2);
2170
2171 PRIV_CHECK(regs);
2172
2173 if(REAL_MODE(&(regs->psw)))
2174 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2175
2176 if(regs->GR_L(0) & LKPG_GPR0_RESV)
2177 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
2178
2179 n2 = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
2180
2181 /* Access to PTE must be serialized */
2182 OBTAIN_MAINLOCK(regs);
2183
2184 /* Return condition code 3 if translation exception */
2185 if (ARCH_DEP(translate_addr) (n2, r2, regs, ACCTYPE_PTE) == 0)
2186 {
2187 rpte = APPLY_PREFIXING (regs->dat.raddr, regs->PX);
2188
2189 pte =
2190 #if defined(FEATURE_ESAME)
2191 ARCH_DEP(fetch_doubleword_absolute) (rpte, regs);
2192 #else /*!defined(FEATURE_ESAME)*/
2193 ARCH_DEP(fetch_fullword_absolute) (rpte, regs);
2194 #endif /*!defined(FEATURE_ESAME)*/
2195
2196 if(regs->GR_L(0) & LKPG_GPR0_LOCKBIT)
2197 {
2198 /* Lock request */
2199 if(!(pte & PAGETAB_PGLOCK))
2200 {
2201 /* Return condition code 3 if translation exception */
2202 if(ARCH_DEP(translate_addr) (n2, r2, regs, ACCTYPE_LRA))
2203 {
2204 regs->psw.cc = 3;
2205 RELEASE_MAINLOCK(regs);
2206 return;
2207 }
2208
2209 pte |= PAGETAB_PGLOCK;
2210 #if defined(FEATURE_ESAME)
2211 ARCH_DEP(store_doubleword_absolute) (pte, rpte, regs);
2212 #else /*!defined(FEATURE_ESAME)*/
2213 ARCH_DEP(store_fullword_absolute) (pte, rpte, regs);
2214 #endif /*!defined(FEATURE_ESAME)*/
2215 regs->GR(r1) = regs->dat.raddr;
2216 regs->psw.cc = 0;
2217 }
2218 else
2219 regs->psw.cc = 1;
2220 }
2221 else
2222 {
2223 /* Unlock reguest */
2224 if(pte & PAGETAB_PGLOCK)
2225 {
2226 pte &= ~((U64)PAGETAB_PGLOCK);
2227 #if defined(FEATURE_ESAME)
2228 ARCH_DEP(store_doubleword_absolute) (pte, rpte, regs);
2229 #else /*!defined(FEATURE_ESAME)*/
2230 ARCH_DEP(store_fullword_absolute) (pte, rpte, regs);
2231 #endif /*!defined(FEATURE_ESAME)*/
2232 regs->psw.cc = 0;
2233 }
2234 else
2235 regs->psw.cc = 1;
2236 }
2237
2238 }
2239 else
2240 regs->psw.cc = 3;
2241
2242 RELEASE_MAINLOCK(regs);
2243
2244 } /* end DEF_INST(lock_page) */
2245 #endif /*defined(FEATURE_LOCK_PAGE)*/
2246
2247
2248 #if defined(FEATURE_LINKAGE_STACK)
2249 /*-------------------------------------------------------------------*/
2250 /* B247 MSTA - Modify Stacked State [RRE] */
2251 /*-------------------------------------------------------------------*/
DEF_INST(modify_stacked_state)2252 DEF_INST(modify_stacked_state)
2253 {
2254 int r1, unused; /* Values of R fields */
2255 U32 m1, m2; /* Modify values */
2256 LSED lsed; /* Linkage stack entry desc. */
2257 VADR lsea; /* Linkage stack entry addr */
2258
2259 RRE(inst, regs, r1, unused);
2260
2261 SIE_XC_INTERCEPT(regs);
2262
2263 if (REAL_MODE(®s->psw)
2264 || SECONDARY_SPACE_MODE(®s->psw)
2265 || !ASF_ENABLED(regs))
2266 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2267
2268 ODD_CHECK(r1, regs);
2269
2270 /* Find the virtual address of the entry descriptor
2271 of the current state entry in the linkage stack */
2272 lsea = ARCH_DEP(locate_stack_entry) (0, &lsed, regs);
2273
2274 /* Load values from rightmost 32 bits of R1 and R1+1 registers */
2275 m1 = regs->GR_L(r1);
2276 m2 = regs->GR_L(r1+1);
2277
2278 /* Store two 32-bit values into modifiable area of state entry */
2279 ARCH_DEP(stack_modify) (lsea, m1, m2, regs);
2280 }
2281 #endif /*defined(FEATURE_LINKAGE_STACK)*/
2282
2283
2284 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
2285 /*-------------------------------------------------------------------*/
2286 /* DA MVCP - Move to Primary [SS] */
2287 /*-------------------------------------------------------------------*/
DEF_INST(move_to_primary)2288 DEF_INST(move_to_primary)
2289 {
2290 int r1, r3; /* Register numbers */
2291 int b1, b2; /* Values of base registers */
2292 VADR effective_addr1,
2293 effective_addr2; /* Effective addresses */
2294 int cc; /* Condition code */
2295 int k; /* Integer workarea */
2296 GREG l; /* Unsigned workarea */
2297
2298 SS(inst, regs, r1, r3, b1, effective_addr1,
2299 b2, effective_addr2);
2300
2301 SIE_XC_INTERCEPT(regs);
2302
2303 /* Program check if secondary space control (CR0 bit 5) is 0,
2304 or if DAT is off, or if in AR mode or home-space mode */
2305 if ((regs->CR(0) & CR0_SEC_SPACE) == 0
2306 || REAL_MODE(®s->psw)
2307 || AR_BIT(®s->psw))
2308 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2309
2310 /* Load true length from R1 register */
2311 l = GR_A(r1,regs);
2312
2313 /* If the true length does not exceed 256, set condition code
2314 zero, otherwise set cc=3 and use effective length of 256 */
2315 if (l <= 256)
2316 cc = 0;
2317 else {
2318 cc = 3;
2319 l = 256;
2320 }
2321
2322 /* Load secondary space key from R3 register bits 24-27 */
2323 k = regs->GR_L(r3) & 0xF0;
2324
2325 /* Program check if in problem state and key mask in
2326 CR3 bits 0-15 is not 1 for the specified key */
2327 if ( PROBSTATE(®s->psw)
2328 && ((regs->CR(3) << (k >> 4)) & 0x80000000) == 0 )
2329 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
2330
2331 /* Move characters from secondary address space to primary
2332 address space using secondary key for second operand */
2333 if (l > 0)
2334 ARCH_DEP(move_chars) (effective_addr1, USE_PRIMARY_SPACE,
2335 regs->psw.pkey,
2336 effective_addr2, USE_SECONDARY_SPACE,
2337 k, l-1, regs);
2338
2339 /* Set condition code */
2340 regs->psw.cc = cc;
2341
2342 }
2343 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
2344
2345
2346 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
2347 /*-------------------------------------------------------------------*/
2348 /* DB MVCS - Move to Secondary [SS] */
2349 /*-------------------------------------------------------------------*/
DEF_INST(move_to_secondary)2350 DEF_INST(move_to_secondary)
2351 {
2352 int r1, r3; /* Register numbers */
2353 int b1, b2; /* Values of base registers */
2354 VADR effective_addr1,
2355 effective_addr2; /* Effective addresses */
2356 int cc; /* Condition code */
2357 int k; /* Integer workarea */
2358 GREG l; /* Unsigned workarea */
2359
2360 SS(inst, regs, r1, r3, b1, effective_addr1,
2361 b2, effective_addr2);
2362
2363 SIE_XC_INTERCEPT(regs);
2364
2365 /* Program check if secondary space control (CR0 bit 5) is 0,
2366 or if DAT is off, or if in AR mode or home-space mode */
2367 if ((regs->CR(0) & CR0_SEC_SPACE) == 0
2368 || REAL_MODE(®s->psw)
2369 || AR_BIT(®s->psw))
2370 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2371
2372 /* Load true length from R1 register */
2373 l = GR_A(r1,regs);
2374
2375 /* If the true length does not exceed 256, set condition code
2376 zero, otherwise set cc=3 and use effective length of 256 */
2377 if (l <= 256)
2378 cc = 0;
2379 else {
2380 cc = 3;
2381 l = 256;
2382 }
2383
2384 /* Load secondary space key from R3 register bits 24-27 */
2385 k = regs->GR_L(r3) & 0xF0;
2386
2387 /* Program check if in problem state and key mask in
2388 CR3 bits 0-15 is not 1 for the specified key */
2389 if ( PROBSTATE(®s->psw)
2390 && ((regs->CR(3) << (k >> 4)) & 0x80000000) == 0 )
2391 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
2392
2393 /* Move characters from primary address space to secondary
2394 address space using secondary key for first operand */
2395 if (l > 0)
2396 ARCH_DEP(move_chars) (effective_addr1, USE_SECONDARY_SPACE, k,
2397 effective_addr2, USE_PRIMARY_SPACE,
2398 regs->psw.pkey, l-1, regs);
2399
2400 /* Set condition code */
2401 regs->psw.cc = cc;
2402
2403 }
2404 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
2405
2406
2407 /*-------------------------------------------------------------------*/
2408 /* E50F MVCDK - Move with Destination Key [SSE] */
2409 /*-------------------------------------------------------------------*/
DEF_INST(move_with_destination_key)2410 DEF_INST(move_with_destination_key)
2411 {
2412 int b1, b2; /* Values of base registers */
2413 VADR effective_addr1,
2414 effective_addr2; /* Effective addresses */
2415 int k, l; /* Integer workarea */
2416
2417 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
2418
2419 /* Load operand length-1 from register 0 bits 24-31 */
2420 l = regs->GR_L(0) & 0xFF;
2421
2422 /* Load destination key from register 1 bits 24-27 */
2423 k = regs->GR_L(1) & 0xF0;
2424
2425 /* Program check if in problem state and key mask in
2426 CR3 bits 0-15 is not 1 for the specified key */
2427 if ( PROBSTATE(®s->psw)
2428 && ((regs->CR(3) << (k >> 4)) & 0x80000000) == 0 )
2429 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
2430
2431 /* Move characters using destination key for operand 1 */
2432 ARCH_DEP(move_chars) (effective_addr1, b1, k,
2433 effective_addr2, b2, regs->psw.pkey,
2434 l, regs);
2435
2436 }
2437
2438
2439 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
2440 /*-------------------------------------------------------------------*/
2441 /* D9 MVCK - Move with Key [SS] */
2442 /*-------------------------------------------------------------------*/
DEF_INST(move_with_key)2443 DEF_INST(move_with_key)
2444 {
2445 int r1, r3; /* Register numbers */
2446 int b1, b2; /* Values of base registers */
2447 VADR effective_addr1,
2448 effective_addr2; /* Effective addresses */
2449 int cc; /* Condition code */
2450 int k; /* Integer workarea */
2451 GREG l; /* Unsigned workarea */
2452
2453 SS(inst, regs, r1, r3, b1, effective_addr1,
2454 b2, effective_addr2);
2455
2456 /* Load true length from R1 register */
2457 l = GR_A(r1,regs);
2458
2459 /* If the true length does not exceed 256, set condition code
2460 zero, otherwise set cc=3 and use effective length of 256 */
2461 if (l <= 256)
2462 cc = 0;
2463 else {
2464 cc = 3;
2465 l = 256;
2466 }
2467
2468 /* Load source key from R3 register bits 24-27 */
2469 k = regs->GR_L(r3) & 0xF0;
2470
2471 /* Program check if in problem state and key mask in
2472 CR3 bits 0-15 is not 1 for the specified key */
2473 if ( PROBSTATE(®s->psw)
2474 && ((regs->CR(3) << (k >> 4)) & 0x80000000) == 0 )
2475 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
2476
2477 /* Move characters using source key for second operand */
2478 if (l > 0)
2479 ARCH_DEP(move_chars) (effective_addr1, b1, regs->psw.pkey,
2480 effective_addr2, b2, k, l-1, regs);
2481
2482 /* Set condition code */
2483 regs->psw.cc = cc;
2484
2485 }
2486 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
2487
2488
2489 #if defined(FEATURE_MOVE_WITH_OPTIONAL_SPECIFICATIONS)
2490 /*-------------------------------------------------------------------*/
2491 /* C8x0 MVCOS - Move with Optional Specifications [SSF] */
2492 /*-------------------------------------------------------------------*/
DEF_INST(move_with_optional_specifications)2493 DEF_INST(move_with_optional_specifications)
2494 {
2495 int r3; /* Register number */
2496 int b1, b2; /* Base register numbers */
2497 VADR effective_addr1,
2498 effective_addr2; /* Effective addresses */
2499 int kbit1, kbit2, abit1, abit2; /* Key and AS validity bits */
2500 int key1, key2; /* Access keys in bits 0-3 */
2501 int asc1, asc2; /* AS controls (same as PSW) */
2502 int cc; /* Condition code */
2503 GREG len; /* Effective length */
2504 int space1, space2; /* Address space modifiers */
2505
2506 SSF(inst, regs, b1, effective_addr1, b2, effective_addr2, r3);
2507
2508 SIE_XC_INTERCEPT(regs);
2509
2510 /* Program check if DAT is off */
2511 if (REAL_MODE(®s->psw))
2512 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2513
2514 /* Extract the access key and address-space control for operand 1 */
2515 abit1 = regs->GR_LHH(0) & 0x0001;
2516 kbit1 = (regs->GR_LHH(0) & 0x0002) >> 1;
2517 asc1 = regs->GR_LHH(0) & 0x00C0;
2518 key1 = (regs->GR_LHH(0) & 0xF000) >> 8;
2519
2520 /* Extract the access key and address-space control for operand 2 */
2521 abit2 = regs->GR_LHL(0) & 0x0001;
2522 kbit2 = (regs->GR_LHL(0) & 0x0002) >> 1;
2523 asc2 = regs->GR_LHL(0) & 0x00C0;
2524 key2 = (regs->GR_LHL(0) & 0xF000) >> 8;
2525
2526 /* Use PSW address-space control for operand 1 if A bit is zero */
2527 if (abit1 == 0)
2528 asc1 = regs->psw.asc;
2529
2530 /* Use PSW address-space control for operand 2 if A bit is zero */
2531 if (abit2 == 0)
2532 asc2 = regs->psw.asc;
2533
2534 /* Use PSW key for operand 1 if K bit is zero */
2535 if (kbit1 == 0)
2536 key1 = regs->psw.pkey;
2537
2538 /* Use PSW key for operand 2 if K bit is zero */
2539 if (kbit2 == 0)
2540 key2 = regs->psw.pkey;
2541
2542 /* Program check if home-space mode is specified for operand 1
2543 and PSW indicates problem state */
2544 if (abit1 && asc1 == PSW_HOME_SPACE_MODE
2545 && PROBSTATE(®s->psw))
2546 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2547
2548 /* Program check if secondary space control (CR0 bit 5/37) is 0, and
2549 secondary space mode is specified or implied for either operand */
2550 if ((regs->CR(0) & CR0_SEC_SPACE) == 0
2551 && (asc1 == PSW_SECONDARY_SPACE_MODE
2552 || asc2 == PSW_SECONDARY_SPACE_MODE))
2553 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2554
2555 /* Program check if in problem state and the key mask in CR3 is zero
2556 for the specified or implied access key for either operand */
2557 if (PROBSTATE(®s->psw)
2558 && ( ((regs->CR(3) << (key1 >> 4)) & 0x80000000) == 0
2559 || ((regs->CR(3) << (key2 >> 4)) & 0x80000000) == 0 ))
2560 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
2561
2562 /* Load true length from R3 register */
2563 len = GR_A(r3,regs);
2564
2565 /* If the true length does not exceed 4096, set condition code
2566 zero, otherwise set cc=3 and use effective length of 4096 */
2567 if (len <= 4096)
2568 cc = 0;
2569 else {
2570 cc = 3;
2571 len = 4096;
2572 }
2573
2574 /* Set the address space modifier for operand 1 */
2575 space1 = (asc1 == PSW_PRIMARY_SPACE_MODE) ? USE_PRIMARY_SPACE :
2576 (asc1 == PSW_SECONDARY_SPACE_MODE) ? USE_SECONDARY_SPACE :
2577 (asc1 == PSW_ACCESS_REGISTER_MODE) ? USE_ARMODE | b1 :
2578 (asc1 == PSW_HOME_SPACE_MODE) ? USE_HOME_SPACE : 0;
2579
2580 /* Set the address space modifier for operand 2 */
2581 space2 = (asc2 == PSW_PRIMARY_SPACE_MODE) ? USE_PRIMARY_SPACE :
2582 (asc2 == PSW_SECONDARY_SPACE_MODE) ? USE_SECONDARY_SPACE :
2583 (asc2 == PSW_ACCESS_REGISTER_MODE) ? USE_ARMODE | b2 :
2584 (asc2 == PSW_HOME_SPACE_MODE) ? USE_HOME_SPACE : 0;
2585
2586 /* Perform the move */
2587 ARCH_DEP(move_charx) (effective_addr1, space1, key1,
2588 effective_addr2, space2, key2, len, regs);
2589
2590 /* Set the condition code */
2591 regs->psw.cc = cc;
2592
2593 } /* end DEF_INST(move_with_optional_specifications) */
2594 #endif /*defined(FEATURE_MOVE_WITH_OPTIONAL_SPECIFICATIONS)*/
2595
2596
2597 /*-------------------------------------------------------------------*/
2598 /* E50E MVCSK - Move with Source Key [SSE] */
2599 /*-------------------------------------------------------------------*/
DEF_INST(move_with_source_key)2600 DEF_INST(move_with_source_key)
2601 {
2602 int b1, b2; /* Values of base registers */
2603 VADR effective_addr1,
2604 effective_addr2; /* Effective addresses */
2605 int k, l; /* Integer workarea */
2606
2607 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
2608
2609 /* Load operand length-1 from register 0 bits 24-31 */
2610 l = regs->GR_L(0) & 0xFF;
2611
2612 /* Load source key from register 1 bits 24-27 */
2613 k = regs->GR_L(1) & 0xF0;
2614
2615 /* Program check if in problem state and key mask in
2616 CR3 bits 0-15 is not 1 for the specified key */
2617 if ( PROBSTATE(®s->psw)
2618 && ((regs->CR(3) << (k >> 4)) & 0x80000000) == 0 )
2619 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
2620
2621 /* Move characters using source key for second operand */
2622 ARCH_DEP(move_chars) (effective_addr1, b1, regs->psw.pkey,
2623 effective_addr2, b2, k, l, regs);
2624
2625 }
2626
2627
2628 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
2629 /*-------------------------------------------------------------------*/
2630 /* B218 PC - Program Call [S] */
2631 /*-------------------------------------------------------------------*/
DEF_INST(program_call)2632 DEF_INST(program_call)
2633 {
2634 int b2; /* Base of effective addr */
2635 U32 pcnum; /* Program call number */
2636 U32 pctea; /* TEA in case of program chk*/
2637 VADR effective_addr2; /* Effective address */
2638 RADR abs; /* Absolute address */
2639 BYTE *mn; /* Mainstor address */
2640 RADR pstd; /* Primary STD or ASCE */
2641 U32 oldpstd; /* Old Primary STD or ASCE */
2642 U32 ltdesig; /* Linkage table designation
2643 (LTD or LFTD) */
2644 U32 pasteo=0; /* Primary ASTE origin */
2645 RADR lto; /* Linkage table origin */
2646 U32 ltl; /* Linkage table length */
2647 U32 lte; /* Linkage table entry */
2648 RADR lfto; /* Linkage first table origin*/
2649 U32 lftl; /* Linkage first table length*/
2650 U32 lfte; /* Linkage first table entry */
2651 RADR lsto; /* Linkage second table orig */
2652 U32 lste[2]; /* Linkage second table entry*/
2653 RADR eto; /* Entry table origin */
2654 U32 etl; /* Entry table length */
2655 U32 ete[8]; /* Entry table entry */
2656 int numwords; /* ETE size (4 or 8 words) */
2657 int i; /* Array subscript */
2658 int ssevent = 0; /* 1=space switch event */
2659 U32 aste[16]; /* ASN second table entry */
2660 U32 akm; /* Bits 0-15=AKM, 16-31=zero */
2661 U16 xcode; /* Exception code */
2662 U16 pasn; /* Primary ASN */
2663 U16 oldpasn; /* Old Primary ASN */
2664 #if defined(FEATURE_LINKAGE_STACK)
2665 U32 csi; /* Called-space identifier */
2666 VADR retn; /* Return address and amode */
2667 #endif /*defined(FEATURE_LINKAGE_STACK)*/
2668 #ifdef FEATURE_TRACING
2669 CREG newcr12 = 0; /* CR12 upon completion */
2670 #endif /*FEATURE_TRACING*/
2671 #if defined(FEATURE_ESAME)
2672 CREG savecr12 = 0; /* CR12 save */
2673 #endif /*FEATURE_ESAME*/
2674
2675 S(inst, regs, b2, effective_addr2);
2676
2677 SIE_XC_INTERCEPT(regs);
2678
2679 #if defined(_FEATURE_SIE)
2680 if(SIE_STATB(regs, IC2, PC))
2681 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
2682 #endif /*defined(_FEATURE_SIE)*/
2683
2684 /* Perform serialization and checkpoint-synchronization */
2685 PERFORM_SERIALIZATION (regs);
2686 PERFORM_CHKPT_SYNC (regs);
2687
2688 /* Load the PC number from the operand address */
2689 if (!ASN_AND_LX_REUSE_ENABLED(regs))
2690 {
2691 /* When ASN-and-LX-reuse is not installed or not enabled, the
2692 PC number is the low-order 20 bits of the operand address
2693 and the translation exception identification is the 20-bit
2694 PC number with 12 high order zeroes appended to the left */
2695 pcnum = effective_addr2 & (PC_LX | PC_EX);
2696 pctea = pcnum;
2697 }
2698 else /* ASN_AND_LX_REUSE_ENABLED */
2699 {
2700 /* When ASN-and-LX-reuse is installed and enabled by CR0,
2701 the PC number is loaded from the low-order 20 bits of the
2702 operand address (bits 44-63) if bit 44 is zero, otherwise
2703 a 31-bit PC number is constructed using bits 32-43 (LFX1)
2704 of the operand address concatenated with bits 45-63 (LFX2,
2705 LSX,EX) of the operand address. The translation exception
2706 identification is either the 20 bit PC number with 12 high
2707 order zeroes, or, if bit 44 is one, is the entire 32 bits
2708 of the effective address including the 1 in bit 44 */
2709 if ((effective_addr2 & PC_BIT44) == 0)
2710 {
2711 pcnum = effective_addr2 & (PC_LFX2 | PC_LSX | PC_EX);
2712 pctea = pcnum;
2713 }
2714 else
2715 {
2716 pcnum = ((effective_addr2 & PC_LFX1) >> 1)
2717 | (effective_addr2 & (PC_LFX2 | PC_LSX | PC_EX));
2718 pctea = effective_addr2 & 0xFFFFFFFF;
2719 }
2720 } /* end ASN_AND_LX_REUSE_ENABLED */
2721
2722 /* Special operation exception if DAT is off, or if
2723 in secondary space mode or home space mode */
2724 if (REAL_MODE(&(regs->psw)) || SPACE_BIT(®s->psw))
2725 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2726
2727 /* Save CR4 and CR1 in case of space switch */
2728 oldpasn = regs->CR(4) & CR4_PASN;
2729 oldpstd = regs->CR(1);
2730
2731 /* [5.5.3.1] Load the linkage table designation */
2732 if (!ASF_ENABLED(regs))
2733 {
2734 /* Special operation exception if in AR mode */
2735 if (ACCESS_REGISTER_MODE(&(regs->psw)))
2736 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2737
2738 /* Obtain the LTD from control register 5 */
2739 ltdesig = regs->CR_L(5);
2740 }
2741 else
2742 {
2743 /* Obtain the primary ASTE origin from control register 5 */
2744 pasteo = regs->CR_L(5) & CR5_PASTEO;
2745
2746 /* Convert the PASTE origin to an absolute address */
2747 abs = APPLY_PREFIXING (pasteo, regs->PX);
2748
2749 /* Program check if PASTE is outside main storage */
2750 if (abs > regs->mainlim)
2751 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
2752
2753 /* Fetch primary ASTE words 3 or 6 from absolute storage
2754 (note: the ASTE cannot cross a page boundary) */
2755 #if !defined(FEATURE_ESAME)
2756 aste[3] = ARCH_DEP(fetch_fullword_absolute) (abs+12, regs);
2757 #else /*defined(FEATURE_ESAME)*/
2758 aste[6] = ARCH_DEP(fetch_fullword_absolute) (abs+24, regs);
2759 #endif /*defined(FEATURE_ESAME)*/
2760
2761 /* Load LTD or LFTD from primary ASTE word 3 or 6 */
2762 ltdesig = ASTE_LT_DESIGNATOR(aste);
2763 }
2764
2765 /* Note: When ASN-and-LX-reuse is installed and enabled
2766 by CR0, ltdesig is an LFTD, otherwise it is an LTD */
2767
2768 /* Special operation exception if subsystem linkage
2769 control bit in linkage table designation is zero */
2770 if ((ltdesig & LTD_SSLINK) == 0)
2771 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2772
2773 #ifdef FEATURE_TRACING
2774 /* Form trace entry if ASN tracing is active */
2775 if (regs->CR(12) & CR12_ASNTRACE)
2776 newcr12 = ARCH_DEP(trace_pc) (pctea, regs);
2777 #endif /*FEATURE_TRACING*/
2778
2779 /* [5.5.3.2] Linkage table lookup */
2780 if (!ASN_AND_LX_REUSE_ENABLED(regs))
2781 {
2782 /* Extract the linkage table origin and length from the LTD */
2783 lto = ltdesig & LTD_LTO;
2784 ltl = ltdesig & LTD_LTL;
2785
2786 /* Program check if linkage index outside the linkage table */
2787 if (ltl < ((pcnum & PC_LX) >> 13))
2788 {
2789 regs->TEA = pctea;
2790 ARCH_DEP(program_interrupt) (regs, PGM_LX_TRANSLATION_EXCEPTION);
2791 }
2792
2793 /* Calculate the address of the linkage table entry */
2794 lto += (pcnum & PC_LX) >> 6;
2795 lto &= 0x7FFFFFFF;
2796
2797 /* Program check if linkage table entry outside real storage */
2798 if (lto > regs->mainlim)
2799 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
2800
2801 /* Fetch linkage table entry from real storage. All bytes
2802 must be fetched concurrently as observed by other CPUs */
2803 lto = APPLY_PREFIXING (lto, regs->PX);
2804 lte = ARCH_DEP(fetch_fullword_absolute)(lto, regs);
2805
2806 /* Program check if the LX invalid bit is set */
2807 if (lte & LTE_INVALID)
2808 {
2809 regs->TEA = pctea;
2810 ARCH_DEP(program_interrupt) (regs, PGM_LX_TRANSLATION_EXCEPTION);
2811 }
2812
2813 /* Extract the entry table origin and length from the LTE */
2814 eto = lte & LTE_ETO;
2815 etl = lte & LTE_ETL;
2816
2817 }
2818 else /* ASN_AND_LX_REUSE_ENABLED */
2819 {
2820 /* Extract linkage first table origin and length from LFTD */
2821 lfto = ltdesig & LFTD_LFTO;
2822 lftl = ltdesig & LFTD_LFTL;
2823
2824 /* If the linkage first index exceeds the length of the
2825 linkage first table, then generate a program check.
2826 The index exceeds the table length if the LFX1 (which
2827 is now in bits 1-12 of the 32-bit PC number) exceeds the
2828 LFTL. Since the LFTL is only 8 bits, this also implies
2829 that the first 4 bits of the LFX1 (originally bits 32-35
2830 of the operand address) must always be 0. The LFX1 was
2831 loaded from bits 32-43 of the operand address if bit 44
2832 of the operand address was 1, otherwise LFX1 is zero.
2833 However, when bit 44 of the effective address is zero,
2834 the LFTL (Linkage-First-Table Length) is ignored. */
2835 if ((effective_addr2 & PC_BIT44) && lftl < (pcnum >> 19))
2836 {
2837 regs->TEA = pctea;
2838 ARCH_DEP(program_interrupt) (regs, PGM_LFX_TRANSLATION_EXCEPTION);
2839 }
2840
2841 /* Calculate the address of the linkage first table entry
2842 (it is always a 31-bit address even in ESAME) */
2843 lfto += (pcnum & ((PC_LFX1>>1)|PC_LFX2)) >> (13-2);
2844 lfto &= 0x7FFFFFFF;
2845
2846 /* Program check if the LFTE address is outside real storage */
2847 if (lfto > regs->mainlim)
2848 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
2849
2850 /* Fetch linkage first table entry from real storage. All bytes
2851 must be fetched concurrently as observed by other CPUs */
2852 lfto = APPLY_PREFIXING (lfto, regs->PX);
2853 lfte = ARCH_DEP(fetch_fullword_absolute)(lfto, regs);
2854
2855 /* Program check if the LFX invalid bit is set */
2856 if (lfte & LFTE_INVALID)
2857 {
2858 regs->TEA = pctea;
2859 ARCH_DEP(program_interrupt) (regs, PGM_LFX_TRANSLATION_EXCEPTION);
2860 }
2861
2862 /* Extract the linkage second table origin from the LFTE */
2863 lsto = lfte & LFTE_LSTO;
2864
2865 /* Calculate the address of the linkage second table entry
2866 (it is always a 31-bit address even in ESAME) */
2867 lsto += (pcnum & PC_LSX) >> (8-3);
2868 lsto &= 0x7FFFFFFF;
2869
2870 /* Program check if the LSTE address is outside real storage */
2871 if (lsto > regs->mainlim)
2872 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
2873
2874 /* Fetch the linkage second table entry from real storage.
2875 The LSTE is 2 fullwords and cannot cross a page boundary.
2876 All 8 bytes of the LSTE must be fetched concurrently as
2877 observed by other CPUs */
2878 abs = APPLY_PREFIXING (lsto, regs->PX);
2879 mn = FETCH_MAIN_ABSOLUTE (abs, regs, 2 * 4);
2880 lste[0] = fetch_fw (mn);
2881 lste[1] = fetch_fw (mn + 4);
2882
2883 /* Program check if the LSX invalid bit is set */
2884 if (lste[0] & LSTE0_INVALID)
2885 {
2886 regs->TEA = pctea;
2887 ARCH_DEP(program_interrupt) (regs, PGM_LSX_TRANSLATION_EXCEPTION);
2888 }
2889
2890 /* Program check if the LSTESN in word 1 of the LSTE is
2891 non-zero and not equal to bits 0-31 of register 15 */
2892 if (lste[1] != 0 && regs->GR_H(15) != lste[1])
2893 {
2894 regs->TEA = pctea;
2895 ARCH_DEP(program_interrupt) (regs, PGM_LSTE_SEQUENCE_EXCEPTION);
2896 }
2897
2898 /* Extract the entry table origin and length from the LSTE */
2899 eto = lste[0] & LSTE0_ETO;
2900 etl = lste[0] & LSTE0_ETL;
2901
2902 } /* end ASN_AND_LX_REUSE_ENABLED */
2903
2904 /* [5.5.3.3] Entry table lookup */
2905
2906 /* Program check if entry index is outside the entry table */
2907 if (etl < ((pcnum & PC_EX) >> (8-6)))
2908 {
2909 regs->TEA = pctea;
2910 ARCH_DEP(program_interrupt) (regs, PGM_EX_TRANSLATION_EXCEPTION);
2911 }
2912
2913 /* Calculate the starting address of the entry table entry
2914 (it is always a 31-bit address even in ESAME) */
2915 eto += (pcnum & PC_EX) << (ASF_ENABLED(regs) ? 5 : 4);
2916 eto &= 0x7FFFFFFF;
2917
2918 /* Determine the size of the entry table entry */
2919 numwords = ASF_ENABLED(regs) ? 8 : 4;
2920
2921 /* Program check if entry table entry is outside main storage */
2922 abs = APPLY_PREFIXING (eto, regs->PX);
2923 if (abs > regs->mainlim - (numwords * 4))
2924 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
2925
2926 /* Fetch the 4- or 8-word entry table entry from real
2927 storage. Each fullword of the ETE must be fetched
2928 concurrently as observed by other CPUs. The entry
2929 table entry cannot cross a page boundary. */
2930 mn = FETCH_MAIN_ABSOLUTE (abs, regs, numwords * 4);
2931 for (i = 0; i < numwords; i++)
2932 {
2933 ete[i] = fetch_fw (mn);
2934 mn += 4;
2935 }
2936
2937 /* Clear remaining words if fewer than 8 words were loaded */
2938 while (i < 8) ete[i++] = 0;
2939
2940 /* Program check if basic program call in AR mode */
2941 if ((ete[4] & ETE4_T) == 0 && AR_BIT(®s->psw))
2942 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2943
2944 #if defined(FEATURE_ESAME)
2945 /* Program check if basic program call is attempting
2946 to switch into or out of 64-bit addressing mode */
2947 if ((ete[4] & ETE4_T) == 0
2948 && ((ete[4] & ETE4_G) ? 1 : 0) != regs->psw.amode64)
2949 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2950 #endif /*defined(FEATURE_ESAME)*/
2951
2952 /* Program check if resulting addressing mode is 24 and the
2953 entry instruction address is not a 24-bit address */
2954 if ((ete[1] & ETE1_AMODE) == 0
2955 #if defined(FEATURE_ESAME)
2956 && (ete[4] & ETE4_G) == 0
2957 #endif /*defined(FEATURE_ESAME)*/
2958 && (ete[1] & ETE1_EIA) > 0x00FFFFFF)
2959 ARCH_DEP(program_interrupt) (regs, PGM_PC_TRANSLATION_SPECIFICATION_EXCEPTION);
2960
2961 /* Obtain the authorization key mask from the entry table */
2962 #if defined(FEATURE_ESAME)
2963 akm = ete[2] & ETE2_AKM;
2964 #else /*!defined(FEATURE_ESAME)*/
2965 akm = ete[0] & ETE0_AKM;
2966 #endif /*!defined(FEATURE_ESAME)*/
2967
2968 /* Program check if in problem state and the PKM in control
2969 register 3 produces zero when ANDed with the AKM in the ETE */
2970 if (PROBSTATE(®s->psw)
2971 && ((regs->CR(3) & CR3_KEYMASK) & akm) == 0)
2972 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
2973
2974 /* Obtain the new primary ASN from the entry table */
2975 #if defined(FEATURE_ESAME)
2976 pasn = ete[2] & ETE2_ASN;
2977 #else /*!defined(FEATURE_ESAME)*/
2978 pasn = ete[0] & ETE0_ASN;
2979 #endif /*!defined(FEATURE_ESAME)*/
2980
2981 /* Obtain the ASTE if ASN is non-zero */
2982 if (pasn != 0)
2983 {
2984 /* Program check if ASN translation control is zero */
2985 if ((regs->CR(14) & CR14_ASN_TRAN) == 0)
2986 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
2987
2988 /* For ESA/390 when ASF control is not enabled, the ASTE
2989 is obtained by ASN translation. For ESAME, and for
2990 ESA/390 when ASF control is enabled, the ASTE is loaded
2991 using the ASTE real address from the entry table */
2992 if (!ASF_ENABLED(regs))
2993 {
2994 /* Perform ASN translation to obtain ASTE */
2995 xcode = ARCH_DEP(translate_asn) (pasn, regs, &pasteo, aste);
2996
2997 /* Program check if ASN translation exception */
2998 if (xcode != 0)
2999 ARCH_DEP(program_interrupt) (regs, xcode);
3000 }
3001 else
3002 {
3003 /* Load the ASTE origin from the entry table */
3004 pasteo = ete[5] & ETE5_ASTE;
3005
3006 /* Convert the ASTE origin to an absolute address */
3007 abs = APPLY_PREFIXING (pasteo, regs->PX);
3008
3009 /* Program check if ASTE origin address is invalid */
3010 if (abs > regs->mainlim)
3011 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
3012
3013 /* Fetch the 16-word ASTE from absolute storage
3014 (note: the ASTE cannot cross a page boundary) */
3015 mn = FETCH_MAIN_ABSOLUTE (abs, regs, 64);
3016 for (i = 0; i < 16; i++)
3017 {
3018 aste[i] = fetch_fw (mn);
3019 mn += 4;
3020 }
3021
3022 /* ASX translation exception if ASTE invalid bit is one */
3023 if (aste[0] & ASTE0_INVALID)
3024 {
3025 regs->TEA = pasn;
3026 ARCH_DEP(program_interrupt) (regs, PGM_ASX_TRANSLATION_EXCEPTION);
3027 }
3028 }
3029
3030 /* Obtain the new PSTD or PASCE from the ASTE */
3031 pstd = ASTE_AS_DESIGNATOR(aste);
3032
3033 #ifdef FEATURE_SUBSPACE_GROUP
3034 /* Perform subspace replacement on new PSTD */
3035 pstd = ARCH_DEP(subspace_replace) (pstd, pasteo, NULL, regs);
3036 #endif /*FEATURE_SUBSPACE_GROUP*/
3037
3038 } /* end if(PC-ss) */
3039 else
3040 { /* PC-cp */
3041
3042 /* For PC to current primary, load current primary STD */
3043 pstd = regs->CR(1);
3044
3045 } /* end if(PC-cp) */
3046
3047 /* Perform basic or stacking program call */
3048 if ((ete[4] & ETE4_T) == 0)
3049 {
3050 /* For basic PC, load linkage info into general register 14 */
3051 #if defined(FEATURE_ESAME)
3052 if (regs->psw.amode64)
3053 regs->GR_G(14) = PSW_IA(regs, 0) | PROBSTATE(®s->psw);
3054 else
3055 regs->GR_L(14) = (regs->psw.amode ? 0x80000000 : 0)
3056 | PSW_IA(regs, 0) | PROBSTATE(®s->psw);
3057 #else /*!defined(FEATURE_ESAME)*/
3058 regs->GR_L(14) = (regs->psw.amode ? 0x80000000 : 0)
3059 | PSW_IA(regs, 0) | PROBSTATE(®s->psw);
3060 #endif /*!defined(FEATURE_ESAME)*/
3061
3062 /* Set the breaking event address register */
3063 SET_BEAR_REG(regs, regs->ip - 4);
3064
3065 /* Update the PSW from the entry table */
3066 #if defined(FEATURE_ESAME)
3067 if (regs->psw.amode64)
3068 UPD_PSW_IA(regs , ((U64)(ete[0]) << 32)
3069 | (U64)(ete[1] & 0xFFFFFFFE));
3070 else
3071 {
3072 regs->psw.amode = (ete[1] & ETE1_AMODE) ? 1 : 0;
3073 regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
3074 UPD_PSW_IA(regs, ete[1] & ETE1_EIA);
3075 }
3076 #else /*!defined(FEATURE_ESAME)*/
3077 regs->psw.amode = (ete[1] & ETE1_AMODE) ? 1 : 0;
3078 regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
3079 UPD_PSW_IA(regs, ete[1] & ETE1_EIA);
3080 #endif /*!defined(FEATURE_ESAME)*/
3081 if (ete[1] & ETE1_PROB)
3082 regs->psw.states |= BIT(PSW_PROB_BIT);
3083 else
3084 regs->psw.states &= ~BIT(PSW_PROB_BIT);
3085
3086 /* Load the current PKM and PASN into general register 3 */
3087 regs->GR_L(3) = (regs->CR(3) & CR3_KEYMASK)
3088 | (regs->CR(4) & CR4_PASN);
3089
3090 /* OR the EKM into the current PKM */
3091 regs->CR(3) |= (ete[3] & ETE3_EKM);
3092
3093 /* Load the entry parameter into general register 4 */
3094 #if defined(FEATURE_ESAME)
3095 if (regs->psw.amode64)
3096 regs->GR_H(4) = ete[6];
3097 regs->GR_L(4) = ete[7];
3098 #else /*!defined(FEATURE_ESAME)*/
3099 regs->GR_L(4) = ete[2];
3100 #endif /*!defined(FEATURE_ESAME)*/
3101
3102 } /* end if(basic PC) */
3103 else
3104 #if defined(FEATURE_LINKAGE_STACK)
3105 { /* stacking PC */
3106
3107 /* ESA/390 POP Fig 10-17 8.B.11 */
3108 if (!ASF_ENABLED(regs))
3109 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
3110
3111 #ifdef FEATURE_TRACING
3112 #if defined(FEATURE_ESAME)
3113 /* Add a mode trace entry when switching in/out of 64 bit mode */
3114 if((regs->CR(12) & CR12_MTRACE) && (regs->psw.amode64 != ((ete[4] & ETE4_G) ? 1 : 0)))
3115 {
3116 /* since ASN trace might be made already, need to save
3117 current CR12 and use newcr12 for this second entry */
3118 if (!newcr12)
3119 newcr12 = regs->CR(12);
3120 savecr12 = regs->CR(12);
3121 regs->CR(12) = newcr12;
3122 newcr12 = ARCH_DEP(trace_ms) (0, 0, regs);
3123 regs->CR(12) = savecr12;
3124 }
3125 #endif /*defined(FEATURE_ESAME)*/
3126 #endif /*FEATURE_TRACING*/
3127
3128 /* Set the called-space identification */
3129 if (pasn == 0)
3130 csi = 0;
3131 else if (ASN_AND_LX_REUSE_ENABLED(regs))
3132 csi = pasn << 16 | (aste[11] & 0x0000FFFF);
3133 else
3134 csi = pasn << 16 | (aste[5] & 0x0000FFFF);
3135
3136 /* Set the addressing mode bits in the return address */
3137 retn = PSW_IA(regs, 0);
3138 #if defined(FEATURE_ESAME)
3139 if ( regs->psw.amode64 )
3140 retn |= 0x01;
3141 else
3142 #endif /*defined(FEATURE_ESAME)*/
3143 if ( regs->psw.amode )
3144 retn |= 0x80000000;
3145
3146 #if defined(FEATURE_ESAME)
3147 /* Set the high-order bit of the PC number if
3148 the resulting addressing mode is 64-bit */
3149 if (ete[4] & ETE4_G)
3150 pcnum |= 0x80000000;
3151 #endif /*defined(FEATURE_ESAME)*/
3152
3153 /* Perform the stacking process */
3154 ARCH_DEP(form_stack_entry) (LSED_UET_PC, retn, 0, csi,
3155 pcnum, regs);
3156
3157 /* Set the breaking event address register */
3158 SET_BEAR_REG(regs, regs->ip - 4);
3159
3160 /* Update the PSW from the entry table */
3161 #if defined(FEATURE_ESAME)
3162 if (ete[4] & ETE4_G)
3163 {
3164 regs->psw.amode64 = 1;
3165 regs->psw.amode = 1;
3166 regs->psw.AMASK = AMASK64;
3167 UPD_PSW_IA(regs, ((U64)(ete[0]) << 32)
3168 | (U64)(ete[1] & 0xFFFFFFFE));
3169 }
3170 else
3171 {
3172 regs->psw.amode64 = 0;
3173 regs->psw.amode = (ete[1] & ETE1_AMODE) ? 1 : 0;
3174 regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
3175 UPD_PSW_IA(regs, ete[1] & ETE1_EIA);
3176 }
3177 #else /*!defined(FEATURE_ESAME)*/
3178 regs->psw.amode = (ete[1] & ETE1_AMODE) ? 1 : 0;
3179 regs->psw.AMASK = regs->psw.amode ? AMASK31 : AMASK24;
3180 UPD_PSW_IA(regs, ete[1] & ETE1_EIA);
3181 #endif /*!defined(FEATURE_ESAME)*/
3182 if (ete[1] & ETE1_PROB)
3183 regs->psw.states |= BIT(PSW_PROB_BIT);
3184 else
3185 regs->psw.states &= ~BIT(PSW_PROB_BIT);
3186
3187 /* Replace the PSW key by the entry key if the K bit is set */
3188 if (ete[4] & ETE4_K)
3189 {
3190 regs->psw.pkey = (ete[4] & ETE4_EK) >> 16;
3191 }
3192
3193 /* Replace the PSW key mask by the EKM if the M bit is set,
3194 otherwise OR the EKM into the current PSW key mask */
3195 if (ete[4] & ETE4_M)
3196 regs->CR_LHH(3) = 0;
3197 regs->CR(3) |= (ete[3] & ETE3_EKM);
3198
3199 /* Replace the EAX key by the EEAX if the E bit is set */
3200 if (ete[4] & ETE4_E)
3201 {
3202 regs->CR_LHH(8) = (ete[4] & ETE4_EEAX);
3203 }
3204
3205 /* Set the access mode according to the C bit */
3206 if (ete[4] & ETE4_C)
3207 regs->psw.asc |= BIT(PSW_AR_BIT);
3208 else
3209 regs->psw.asc &= ~BIT(PSW_AR_BIT);
3210
3211 /* Load the entry parameter into general register 4 */
3212 #if defined(FEATURE_ESAME)
3213 if (regs->psw.amode64)
3214 regs->GR_H(4) = ete[6];
3215 regs->GR_L(4) = ete[7];
3216 #else /*!defined(FEATURE_ESAME)*/
3217 regs->GR_L(4) = ete[2];
3218 #endif /*!defined(FEATURE_ESAME)*/
3219
3220 } /* end if(stacking PC) */
3221 #else /*!defined(FEATURE_LINKAGE_STACK)*/
3222 ARCH_DEP(program_interrupt) (regs, PGM_PC_TRANSLATION_SPECIFICATION_EXCEPTION);
3223 #endif /*!defined(FEATURE_LINKAGE_STACK)*/
3224
3225 /* If new ASN is zero, perform program call to current primary */
3226 if (pasn == 0)
3227 {
3228 /* Set SASN equal to PASN */
3229 regs->CR_LHL(3) = regs->CR_LHL(4);
3230
3231 /* Set SSTD equal to PSTD */
3232 regs->CR(7) = regs->CR(1);
3233
3234 /* When ASN-and-LX-reuse is installed and enabled,
3235 set the SASTEIN equal to the PASTEIN */
3236 if (ASN_AND_LX_REUSE_ENABLED(regs))
3237 regs->CR_H(3) = regs->CR_H(4);
3238
3239 } /* end if(PC-cp) */
3240 else
3241 { /* Program call with space switching */
3242
3243 /* Set SASN and SSTD equal to current PASN and PSTD */
3244 regs->CR_LHL(3) = regs->CR_LHL(4);
3245 regs->CR(7) = regs->CR(1);
3246
3247 /* When ASN-and-LX-reuse is installed and enabled,
3248 set the SASTEIN equal to the current PASTEIN */
3249 if (ASN_AND_LX_REUSE_ENABLED(regs))
3250 regs->CR_H(3) = regs->CR_H(4);
3251
3252 /* Set flag if either the current or new PSTD indicates
3253 a space switch event */
3254 if ((regs->CR(1) & SSEVENT_BIT)
3255 || (pstd & SSEVENT_BIT) )
3256 {
3257 /* Indicate space-switch event required */
3258 ssevent = 1;
3259 }
3260
3261 /* Obtain new AX from the ASTE and new PASN from the ET */
3262 regs->CR_L(4) = (aste[1] & ASTE1_AX) | pasn;
3263
3264 /* When ASN-and-LX-reuse is installed and enabled,
3265 obtain the new PASTEIN from the new primary ASTE */
3266 if (ASN_AND_LX_REUSE_ENABLED(regs))
3267 regs->CR_H(4) = aste[11];
3268
3269 /* Load the new primary STD or ASCE */
3270 regs->CR(1) = pstd;
3271
3272 /* Update control register 5 with the new PASTEO or LTD */
3273 regs->CR_L(5) = ASF_ENABLED(regs) ?
3274 pasteo : ASTE_LT_DESIGNATOR(aste);
3275
3276 #if defined(FEATURE_LINKAGE_STACK)
3277 /* For stacking PC when the S-bit in the entry table is
3278 one, set SASN and SSTD equal to new PASN and PSTD */
3279 if ((ete[4] & ETE4_T) && (ete[4] & ETE4_S))
3280 {
3281 regs->CR_LHL(3) = regs->CR_LHL(4);
3282 regs->CR(7) = regs->CR(1);
3283
3284 /* When ASN-and-LX-reuse is installed and enabled,
3285 also set the SASTEIN equal to the new PASTEIN */
3286 if (ASN_AND_LX_REUSE_ENABLED(regs))
3287 regs->CR_H(3) = regs->CR_H(4);
3288 }
3289 #endif /*defined(FEATURE_LINKAGE_STACK)*/
3290
3291 } /* end if(PC-ss) */
3292
3293 #ifdef FEATURE_TRACING
3294 /* Update trace table address if ASN or Mode switch made trace entry */
3295 if (newcr12)
3296 regs->CR(12) = newcr12;
3297 #endif /*FEATURE_TRACING*/
3298
3299 /* Update cpu states */
3300 SET_IC_MASK(regs);
3301 SET_AEA_MODE(regs); // psw.asc may be updated
3302 SET_AEA_COMMON(regs); // cr[1], cr[7] may be updated
3303 INVALIDATE_AIA(regs);
3304
3305 /* Check for Successful Branch PER event */
3306 PER_SB(regs, regs->psw.IA);
3307
3308 /* Generate space switch event if required */
3309 if ( ssevent || (pasn != 0 && IS_IC_PER(regs)) )
3310 {
3311 /* [6.5.2.34] Set the translation exception address equal
3312 to the old primary ASN, with the high-order bit set if
3313 the old primary space-switch-event control bit is one */
3314 regs->TEA = oldpasn;
3315 if (oldpstd & SSEVENT_BIT)
3316 regs->TEA |= TEA_SSEVENT;
3317
3318 ARCH_DEP(program_interrupt) (regs, PGM_SPACE_SWITCH_EVENT);
3319 }
3320
3321 /* Perform serialization and checkpoint-synchronization */
3322 PERFORM_SERIALIZATION (regs);
3323 PERFORM_CHKPT_SYNC (regs);
3324
3325 } /* end DEF_INST(program_call) */
3326 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
3327
3328
3329 #if defined(FEATURE_LINKAGE_STACK)
3330 /*-------------------------------------------------------------------*/
3331 /* 0101 PR - Program Return [E] */
3332 /*-------------------------------------------------------------------*/
DEF_INST(program_return)3333 DEF_INST(program_return)
3334 {
3335 REGS newregs; /* Copy of CPU registers */
3336 int etype; /* Entry type unstacked */
3337 int ssevent = 0; /* 1=space switch event */
3338 RADR alsed; /* Absolute addr of LSED of
3339 previous stack entry */
3340 LSED *lsedp; /* -> LSED in main storage */
3341 U32 aste[16]; /* ASN second table entry */
3342 U32 pasteo=0; /* Primary ASTE origin */
3343 U32 sasteo=0; /* Secondary ASTE origin */
3344 U16 oldpasn; /* Original primary ASN */
3345 U32 oldpstd; /* Original primary STD */
3346 U16 pasn = 0; /* New primary ASN */
3347 U16 sasn; /* New secondary ASN */
3348 U16 ax; /* Authorization index */
3349 U16 xcode; /* Exception code */
3350 int rc; /* return code from load_psw */
3351
3352 E(inst, regs);
3353
3354 SIE_XC_INTERCEPT(regs);
3355
3356 #if defined(_FEATURE_SIE)
3357 if(SIE_STATB(regs, IC3, PR))
3358 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
3359 #endif /*defined(_FEATURE_SIE)*/
3360
3361 /* Perform serialization and checkpoint-synchronization */
3362 PERFORM_SERIALIZATION (regs);
3363 PERFORM_CHKPT_SYNC (regs);
3364
3365 INVALIDATE_AIA(regs);
3366
3367 /* Create a working copy of the CPU registers... */
3368 memcpy( &newregs, regs, sysblk.regs_copy_len );
3369
3370 /* Now INVALIDATE ALL TLB ENTRIES in our working copy.. */
3371 memset( &newregs.tlb.vaddr, 0, TLBN * sizeof(DW) );
3372 newregs.tlbID = 1;
3373
3374 /* Set the breaking event address register in the copy */
3375 SET_BEAR_REG(&newregs, newregs.ip - (newregs.execflag ?
3376 newregs.exrl ? 6 : 4 : 2));
3377
3378 /* Save the primary ASN (CR4) and primary STD (CR1) */
3379 oldpasn = regs->CR_LHL(4);
3380 oldpstd = regs->CR(1);
3381
3382 /* Perform the unstacking process */
3383 etype = ARCH_DEP(program_return_unstack) (&newregs, &alsed, &rc);
3384
3385 #ifdef FEATURE_TRACING
3386 #if defined(FEATURE_ESAME)
3387 /* If unstacked entry was a BAKR: */
3388 /* Add a mode trace entry when switching in/out of 64 bit mode */
3389 if((etype == LSED_UET_BAKR)
3390 && (regs->CR(12) & CR12_MTRACE)
3391 && (regs->psw.amode64 != newregs.psw.amode64))
3392 newregs.CR(12) = ARCH_DEP(trace_ms) (0, 0, regs);
3393 #endif /*defined(FEATURE_ESAME)*/
3394 #endif /*FEATURE_TRACING*/
3395
3396 /* Perform PR-cp or PR-ss if unstacked entry was a program call */
3397 if (etype == LSED_UET_PC)
3398 {
3399 /* Extract the new primary ASN from CR4 bits 16-31 */
3400 pasn = newregs.CR_LHL(4);
3401
3402 #ifdef FEATURE_TRACING
3403 /* Perform tracing if ASN tracing is on */
3404 if (regs->CR(12) & CR12_ASNTRACE)
3405 newregs.CR(12) = ARCH_DEP(trace_pr) (&newregs, regs);
3406
3407 #if defined(FEATURE_ESAME)
3408 else
3409 /* Add a mode trace entry when switching in/out of 64 bit mode */
3410 if((regs->CR(12) & CR12_MTRACE) && (regs->psw.amode64 != newregs.psw.amode64))
3411 newregs.CR(12) = ARCH_DEP(trace_ms) (0, 0, regs);
3412 #endif /*defined(FEATURE_ESAME)*/
3413
3414 #endif /*FEATURE_TRACING*/
3415
3416 /* Perform PASN translation if new PASN not equal old PASN */
3417 if (pasn != oldpasn)
3418 {
3419 /* Special operation exception if ASN translation
3420 control (control register 14 bit 12) is zero */
3421 if ((regs->CR(14) & CR14_ASN_TRAN) == 0)
3422 ARCH_DEP(program_interrupt) (&newregs, PGM_SPECIAL_OPERATION_EXCEPTION);
3423
3424 /* Translate new primary ASN to obtain ASTE */
3425 xcode = ARCH_DEP(translate_asn) (pasn, &newregs, &pasteo, aste);
3426
3427 /* Program check if ASN translation exception */
3428 if (xcode != 0)
3429 ARCH_DEP(program_interrupt) (&newregs, xcode);
3430
3431 /* When ASN-and-LX-reuse is installed and enabled by CR0,
3432 the PASTEIN previously loaded from the state entry (by
3433 the program_return_unstack procedure) into the high word
3434 of CR4 must equal the ASTEIN in word 11 of the ASTE */
3435 if (ASN_AND_LX_REUSE_ENABLED(regs))
3436 {
3437 if (newregs.CR_H(4) != aste[11])
3438 {
3439 /* Set bit 2 of the exception access identification
3440 to indicate that the program check occurred
3441 during PASN translation in a PR instruction */
3442 newregs.excarid = 0x20;
3443 ARCH_DEP(program_interrupt) (&newregs, PGM_ASTE_INSTANCE_EXCEPTION);
3444 }
3445 } /* end if(ASN_AND_LX_REUSE_ENABLED) */
3446
3447 /* Obtain new PSTD (or PASCE) and AX from the ASTE */
3448 newregs.CR(1) = ASTE_AS_DESIGNATOR(aste);
3449 newregs.CR_LHH(4) = 0;
3450 newregs.CR_L(4) |= aste[1] & ASTE1_AX;
3451
3452 /* Load CR5 with the primary ASTE origin address */
3453 newregs.CR_L(5) = pasteo;
3454
3455 #ifdef FEATURE_SUBSPACE_GROUP
3456 /* Perform subspace replacement on new PSTD */
3457 newregs.CR(1) = ARCH_DEP(subspace_replace) (newregs.CR(1),
3458 pasteo, NULL, &newregs);
3459 #endif /*FEATURE_SUBSPACE_GROUP*/
3460
3461 /* Space switch if either current PSTD or new PSTD
3462 space-switch-event control bit is set to 1 */
3463 if ((regs->CR(1) & SSEVENT_BIT)
3464 || (newregs.CR(1) & SSEVENT_BIT))
3465 {
3466 /* Indicate space-switch event required */
3467 ssevent = 1;
3468 }
3469 else
3470 {
3471 /* space-switch event maybe - if PER event */
3472 ssevent = 2;
3473 }
3474
3475 } /* end if(pasn!=oldpasn) */
3476
3477 /* Extract the new secondary ASN from CR3 bits 16-31 */
3478 sasn = newregs.CR_LHL(3);
3479
3480 /* Set SSTD = PSTD if new SASN is equal to new PASN */
3481 if (sasn == pasn)
3482 {
3483 newregs.CR(7) = newregs.CR(1);
3484 }
3485 else /* sasn != pasn */
3486 {
3487 /* Perform SASN translation */
3488
3489 /* Special operation exception if ASN translation
3490 control (control register 14 bit 12) is zero */
3491 if ((regs->CR(14) & CR14_ASN_TRAN) == 0)
3492 ARCH_DEP(program_interrupt) (&newregs, PGM_SPECIAL_OPERATION_EXCEPTION);
3493
3494 /* Translate new secondary ASN to obtain ASTE */
3495 xcode = ARCH_DEP(translate_asn) (sasn, &newregs, &sasteo, aste);
3496
3497 /* Program check if ASN translation exception */
3498 if (xcode != 0)
3499 ARCH_DEP(program_interrupt) (&newregs, xcode);
3500
3501 /* When ASN-and-LX-reuse is installed and enabled by CR0,
3502 the SASTEIN previously loaded from the state entry (by
3503 the program_return_unstack procedure) into the high word
3504 of CR3 must equal the ASTEIN in word 11 of the ASTE */
3505 if (ASN_AND_LX_REUSE_ENABLED(regs))
3506 {
3507 if (newregs.CR_H(3) != aste[11])
3508 {
3509 /* Set bit 3 of the exception access identification
3510 to indicate that the program check occurred
3511 during SASN translation in a PR instruction */
3512 newregs.excarid = 0x10;
3513 ARCH_DEP(program_interrupt) (&newregs, PGM_ASTE_INSTANCE_EXCEPTION);
3514 }
3515 } /* end if(ASN_AND_LX_REUSE_ENABLED) */
3516
3517 /* Obtain new SSTD or SASCE from secondary ASTE */
3518 newregs.CR(7) = ASTE_AS_DESIGNATOR(aste);
3519
3520 /* Perform SASN authorization using new AX */
3521 ax = newregs.CR_LHH(4);
3522 if (ARCH_DEP(authorize_asn) (ax, aste, ATE_SECONDARY, &newregs))
3523 {
3524 newregs.TEA = sasn;
3525 ARCH_DEP(program_interrupt) (&newregs, PGM_SECONDARY_AUTHORITY_EXCEPTION);
3526 }
3527
3528 #ifdef FEATURE_SUBSPACE_GROUP
3529 /* Perform subspace replacement on new SSTD */
3530 newregs.CR(7) = ARCH_DEP(subspace_replace) (newregs.CR(7),
3531 sasteo, NULL, &newregs);
3532 #endif /*FEATURE_SUBSPACE_GROUP*/
3533
3534 } /* end else(sasn!=pasn) */
3535
3536 } /* end if(LSED_UET_PC) */
3537
3538 /* Update the updated CPU registers from the working copy */
3539 memcpy(&(regs->psw), &(newregs.psw), sizeof(newregs.psw));
3540 memcpy(regs->gr, newregs.gr, sizeof(newregs.gr));
3541 memcpy(regs->cr, newregs.cr, sizeof(newregs.cr));
3542 memcpy(regs->ar, newregs.ar, sizeof(newregs.ar));
3543 regs->bear = newregs.bear;
3544
3545 /* Set the main storage reference and change bits */
3546 STORAGE_KEY(alsed, regs) |= (STORKEY_REF | STORKEY_CHANGE);
3547
3548 /* [5.12.4.4] Clear the next entry size field of the linkage
3549 stack entry now pointed to by control register 15 */
3550 lsedp = (LSED*)(regs->mainstor + alsed);
3551 lsedp->nes[0] = 0;
3552 lsedp->nes[1] = 0;
3553
3554 #if defined(FEATURE_PER)
3555
3556 /* Copy PER info from working copy to real copy of registers */
3557 if (IS_IC_PER_SA(&newregs))
3558 {
3559 ON_IC_PER_SA(regs);
3560 regs->perc = newregs.perc;
3561 }
3562
3563 PER_SB(regs, regs->psw.IA);
3564
3565 #endif /*defined(FEATURE_PER)*/
3566
3567 /* Update cpu states */
3568 SET_IC_MASK(regs);
3569 SET_AEA_MODE(regs); // psw has been updated
3570 SET_AEA_COMMON(regs); // control regs been updated
3571
3572 /* Generate space switch event if required */
3573 if ( ssevent == 1 || (ssevent == 2 && IS_IC_PER(regs)) )
3574 {
3575 /* [6.5.2.34] Set translation exception address equal
3576 to old primary ASN, and set high-order bit if old
3577 primary space-switch-event control bit is one */
3578 regs->TEA = oldpasn;
3579 if (oldpstd & SSEVENT_BIT)
3580 regs->TEA |= TEA_SSEVENT;
3581
3582 ARCH_DEP(program_interrupt) (regs, PGM_SPACE_SWITCH_EVENT);
3583 }
3584
3585 if (rc) /* if new psw has bad format */
3586 {
3587 ARCH_DEP(program_interrupt) (regs, rc);
3588 }
3589
3590 /* Perform serialization and checkpoint-synchronization */
3591 PERFORM_SERIALIZATION (regs);
3592 PERFORM_CHKPT_SYNC (regs);
3593
3594 RETURN_INTCHECK(regs);
3595
3596 } /* end DEF_INST(program_return) */
3597 #endif /*defined(FEATURE_LINKAGE_STACK)*/
3598
3599
3600 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
3601 /*-------------------------------------------------------------------*/
3602 /* Common processing routine for the PT and PTI instructions */
3603 /*-------------------------------------------------------------------*/
ARCH_DEP(program_transfer_proc)3604 void ARCH_DEP(program_transfer_proc) (REGS *regs,
3605 int r1, int r2, int pti_instruction)
3606 {
3607 U16 pkm; /* New program key mask */
3608 U16 pasn; /* New primary ASN */
3609 U16 oldpasn; /* Old primary ASN */
3610 int amode; /* New amode */
3611 VADR ia; /* New instruction address */
3612 int prob; /* New problem state bit */
3613 RADR abs; /* Absolute address */
3614 U32 ltd; /* Linkage table designation */
3615 U32 pasteo=0; /* Primary ASTE origin */
3616 U32 aste[16]; /* ASN second table entry */
3617 CREG pstd; /* Primary STD */
3618 U32 oldpstd; /* Old Primary STD */
3619 U16 ax; /* Authorization index */
3620 U16 xcode; /* Exception code */
3621 int ssevent = 0; /* 1=space switch event */
3622 #ifdef FEATURE_TRACING
3623 CREG newcr12 = 0; /* CR12 upon completion */
3624 #endif /*FEATURE_TRACING*/
3625
3626 SIE_XC_INTERCEPT(regs);
3627
3628 #if defined(_FEATURE_SIE)
3629 if(SIE_STATB(regs, IC2, PT))
3630 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
3631 #endif /*defined(_FEATURE_SIE)*/
3632
3633 /* Perform serialization and checkpoint-synchronization */
3634 PERFORM_SERIALIZATION (regs);
3635 PERFORM_CHKPT_SYNC (regs);
3636
3637 /* Special operation exception if DAT is off, or
3638 not in primary space mode */
3639 if (REAL_MODE(&(regs->psw))
3640 || !PRIMARY_SPACE_MODE(&(regs->psw)))
3641 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
3642
3643 /* Special operation exception if subsystem linkage
3644 control bit in CR5 is zero (when ASF is off)*/
3645 if (!ASF_ENABLED(regs) && !(regs->CR_L(5) & LTD_SSLINK))
3646 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
3647
3648 /* Save the primary ASN (CR4) and primary STD (CR1) */
3649 oldpasn = regs->CR_LHL(4);
3650 oldpstd = regs->CR(1);
3651
3652 /* Extract the PSW key mask from R1 register bits 0-15 */
3653 pkm = regs->GR_LHH(r1);
3654
3655 /* Extract the ASN from R1 register bits 16-31 */
3656 pasn = regs->GR_LHL(r1);
3657
3658 #ifdef FEATURE_TRACING
3659 /* Build trace entry if ASN tracing is on */
3660 if (regs->CR(12) & CR12_ASNTRACE)
3661 newcr12 = ARCH_DEP(trace_pt) (pti_instruction, pasn, regs->GR(r2), regs);
3662 #endif /*FEATURE_TRACING*/
3663
3664 /* Determine instruction address, amode, and problem state */
3665 #if defined(FEATURE_ESAME)
3666 if (regs->psw.amode64)
3667 {
3668 /* In 64-bit address mode, extract instruction address from
3669 R2 register bits 0-62, and leave address mode unchanged */
3670 ia = regs->GR_G(r2) & 0xFFFFFFFFFFFFFFFEULL;
3671 amode = regs->psw.amode;
3672 }
3673 else
3674 #endif /*defined(FEATURE_ESAME)*/
3675 {
3676 /* In 31- or 24-bit mode, extract new amode from R2 bit 0 */
3677 amode = (regs->GR_L(r2) & 0x80000000) ? 1 : 0;
3678
3679 /* Extract the instruction address from R2 bits 1-30 */
3680 ia = regs->GR_L(r2) & 0x7FFFFFFE;
3681 }
3682
3683 /* Extract the problem state bit from R2 register bit 31 */
3684 prob = regs->GR_L(r2) & 0x00000001;
3685
3686 /* [5.5.3.1] Load the linkage table designation */
3687 if (!ASF_ENABLED(regs))
3688 {
3689 /* Obtain the LTD from control register 5 */
3690 ltd = regs->CR_L(5);
3691 }
3692 else
3693 {
3694 /* Obtain the primary ASTE origin from control register 5 */
3695 pasteo = regs->CR_L(5) & CR5_PASTEO;
3696
3697 /* Convert the PASTE origin to an absolute address */
3698 abs = APPLY_PREFIXING (pasteo, regs->PX);
3699
3700 /* Program check if PASTE is outside main storage */
3701 if (abs > regs->mainlim)
3702 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
3703
3704 /* Fetch primary ASTE words 3 and 6 from absolute storage
3705 (note: the ASTE cannot cross a page boundary) */
3706 #if !defined(FEATURE_ESAME)
3707 aste[3] = ARCH_DEP(fetch_fullword_absolute) (abs+12, regs);
3708 #else /*defined(FEATURE_ESAME)*/
3709 aste[6] = ARCH_DEP(fetch_fullword_absolute) (abs+24, regs);
3710 #endif /*defined(FEATURE_ESAME)*/
3711
3712 /* Load LTD from primary ASTE word 3 or 6 */
3713 ltd = ASTE_LT_DESIGNATOR(aste);
3714 }
3715
3716 /* Special operation exception if subsystem linkage
3717 control bit in linkage table designation is zero */
3718 if ((ltd & LTD_SSLINK) == 0)
3719 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
3720
3721 /* Privileged operation exception if in problem state and
3722 problem bit indicates a change to supervisor state */
3723 if (PROBSTATE(®s->psw) && prob == 0)
3724 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
3725
3726 /* Specification exception if new amode is 24-bit and
3727 new instruction address is not a 24-bit address */
3728 if (amode == 0 && ia > 0x00FFFFFF)
3729 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
3730
3731 /* Space switch if ASN not equal to current PASN */
3732 if ( pasn != regs->CR_LHL(4) )
3733 {
3734 /* Special operation exception if ASN translation
3735 control (control register 14 bit 12) is zero */
3736 if ((regs->CR(14) & CR14_ASN_TRAN) == 0)
3737 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
3738
3739 /* Translate ASN and generate program check if
3740 AFX- or ASX-translation exception condition */
3741 xcode = ARCH_DEP(translate_asn) (pasn, regs, &pasteo, aste);
3742 if (xcode != 0)
3743 ARCH_DEP(program_interrupt) (regs, xcode);
3744
3745 /* For PT-ss only, generate a special operation exception
3746 if ASN-and-LX-reuse is enabled and the reusable-ASN bit
3747 in the ASTE is one */
3748 if (pti_instruction == 0 && ASN_AND_LX_REUSE_ENABLED(regs)
3749 && (aste[1] & ASTE1_RA) != 0)
3750 {
3751 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
3752 } /* end if (PT && ASN_AND_LX_REUSE_ENABLED && ASTE1_RA) */
3753
3754 /* For PTI-ss only, generate a special operation exception
3755 if the controlled-ASN bit in the ASTE is one and the CPU
3756 was in problem state at the beginning of the operation */
3757 if (pti_instruction && (aste[1] & ASTE1_CA) != 0
3758 && PROBSTATE(®s->psw))
3759 {
3760 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
3761 } /* end if (PT && ASTE1_CA && PROBSTATE) */
3762
3763 /* For PTI-ss only, generate an ASTE instance exception
3764 if the ASTEIN in bits 0-31 of the R1 register does
3765 not equal the ASTEIN in the ASTE*/
3766 if (pti_instruction && aste[11] != regs->GR_H(r1))
3767 {
3768 /* Set bit 2 of the exception access identification
3769 to indicate that the program check occurred
3770 during PASN translation in a PTI instruction */
3771 regs->excarid = 0x20;
3772 ARCH_DEP(program_interrupt) (regs, PGM_ASTE_INSTANCE_EXCEPTION);
3773 } /* end if (PT && ASTE11_ASTEIN != GR_H(r1)) */
3774
3775 /* Perform primary address space authorization
3776 using current authorization index */
3777 ax = regs->CR_LHH(4);
3778 if (ARCH_DEP(authorize_asn) (ax, aste, ATE_PRIMARY, regs))
3779 {
3780 regs->TEA = pasn;
3781 ARCH_DEP(program_interrupt) (regs, PGM_PRIMARY_AUTHORITY_EXCEPTION);
3782 }
3783
3784 /* Obtain new primary STD or ASCE from the ASTE */
3785 pstd = ASTE_AS_DESIGNATOR(aste);
3786
3787 #ifdef FEATURE_SUBSPACE_GROUP
3788 /* Perform subspace replacement on new PSTD */
3789 pstd = ARCH_DEP(subspace_replace) (pstd, pasteo, NULL, regs);
3790 #endif /*FEATURE_SUBSPACE_GROUP*/
3791
3792 /* Space switch if either current PSTD or new PSTD
3793 space-switch-event control bit is set to 1 */
3794 if ((regs->CR(1) & SSEVENT_BIT) || (pstd & SSEVENT_BIT))
3795 {
3796 /* Indicate space-switch event required */
3797 ssevent = 1;
3798 }
3799 else
3800 {
3801 ssevent = 2; /* maybe, if PER is pending */
3802 }
3803
3804 /* Load new primary STD or ASCE into control register 1 */
3805 regs->CR(1) = pstd;
3806
3807 /* Load new AX and PASN into control register 4 */
3808 regs->CR_L(4) = (aste[1] & ASTE1_AX) | pasn;
3809
3810 /* Load new PASTEO or LTD into control register 5 */
3811 regs->CR_L(5) = ASF_ENABLED(regs) ?
3812 pasteo : ASTE_LT_DESIGNATOR(aste);
3813
3814 /* For PTI-ss, and for PT-ss when ASN-and-LX-reuse is enabled,
3815 load the new PASTEIN into CR4 from ASTE11_ASTEIN */
3816 if (pti_instruction || ASN_AND_LX_REUSE_ENABLED(regs))
3817 {
3818 regs->CR_H(4) = aste[11];
3819 } /* end if (PTI || ASN_AND_LX_REUSE_ENABLED) */
3820
3821 } /* end if(PT-ss or PTI-ss) */
3822 else
3823 {
3824 /* For PT-cp or PTI-cp use current primary STD or ASCE */
3825 pstd = regs->CR(1);
3826 }
3827
3828 #ifdef FEATURE_TRACING
3829 /* Update trace table address if ASN tracing is on */
3830 if (regs->CR(12) & CR12_ASNTRACE)
3831 regs->CR(12) = newcr12;
3832 #endif /*FEATURE_TRACING*/
3833
3834 /* Check for Successful Branch PER event */
3835 PER_SB(regs, ia);
3836
3837 /* Set the breaking event address register */
3838 SET_BEAR_REG(regs, regs->ip - 4);
3839
3840 /* Replace PSW amode, instruction address, and problem state bit */
3841 regs->psw.amode = amode;
3842 UPD_PSW_IA(regs, ia);
3843 if (prob)
3844 regs->psw.states |= BIT(PSW_PROB_BIT);
3845 else
3846 regs->psw.states &= ~BIT(PSW_PROB_BIT);
3847
3848 regs->psw.AMASK =
3849 #if defined(FEATURE_ESAME)
3850 regs->psw.amode64 ? AMASK64 :
3851 #endif /*defined(FEATURE_ESAME)*/
3852 regs->psw.amode ? AMASK31 : AMASK24;
3853
3854 /* AND control register 3 bits 0-15 with the supplied PKM value
3855 and replace the SASN in CR3 bits 16-31 with new PASN */
3856 regs->CR_LHH(3) &= pkm;
3857 regs->CR_LHL(3) = pasn;
3858
3859 /* For PTI, and also for PT when ASN-and-LX-reuse is enabled,
3860 set the SASTEIN in CR3 equal to the new PASTEIN in CR4 */
3861 if (pti_instruction || ASN_AND_LX_REUSE_ENABLED(regs))
3862 {
3863 regs->CR_H(3) = regs->CR_H(4);
3864 } /* end if (PTI || ASN_AND_LX_REUSE_ENABLED) */
3865
3866 /* Set secondary STD or ASCE equal to new primary STD or ASCE */
3867 regs->CR(7) = pstd;
3868
3869 /* Update cpu states */
3870 SET_IC_MASK(regs);
3871 SET_AEA_COMMON(regs);
3872 INVALIDATE_AIA(regs);
3873
3874 /* Generate space switch event if required */
3875 if ( ssevent == 1 || (ssevent == 2 && IS_IC_PER(regs)) )
3876 {
3877 /* [6.5.2.34] Set the translation exception address equal
3878 to the old primary ASN, with the high-order bit set if
3879 the old primary space-switch-event control bit is one */
3880 regs->TEA = oldpasn;
3881 if (oldpstd & SSEVENT_BIT)
3882 regs->TEA |= TEA_SSEVENT;
3883
3884 ARCH_DEP(program_interrupt) (regs, PGM_SPACE_SWITCH_EVENT);
3885 }
3886
3887 /* Perform serialization and checkpoint-synchronization */
3888 PERFORM_SERIALIZATION (regs);
3889 PERFORM_CHKPT_SYNC (regs);
3890
3891 } /* end ARCH_DEP(program_transfer_proc) */
3892
3893
3894 /*-------------------------------------------------------------------*/
3895 /* B228 PT - Program Transfer [RRE] */
3896 /*-------------------------------------------------------------------*/
DEF_INST(program_transfer)3897 DEF_INST(program_transfer)
3898 {
3899 int r1, r2; /* Values of R fields */
3900
3901 RRE(inst, regs, r1, r2);
3902 ARCH_DEP(program_transfer_proc) (regs, r1, r2, 0);
3903
3904 } /* end DEF_INST(program_transfer) */
3905 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
3906
3907
3908 #if defined(FEATURE_ASN_AND_LX_REUSE)
3909 /*-------------------------------------------------------------------*/
3910 /* B99E PTI - Program Transfer with Instance [RRE] */
3911 /*-------------------------------------------------------------------*/
DEF_INST(program_transfer_with_instance)3912 DEF_INST(program_transfer_with_instance)
3913 {
3914 int r1, r2; /* Values of R fields */
3915
3916 if(!sysblk.asnandlxreuse)
3917 {
3918 ARCH_DEP(operation_exception)(inst,regs);
3919 }
3920
3921 RRE(inst, regs, r1, r2);
3922 ARCH_DEP(program_transfer_proc) (regs, r1, r2, 1);
3923
3924 } /* end DEF_INST(program_transfer_with_instance) */
3925 #endif /*defined(FEATURE_ASN_AND_LX_REUSE)*/
3926
3927
3928 #if defined(FEATURE_ACCESS_REGISTERS)
3929 /*-------------------------------------------------------------------*/
3930 /* B248 PALB - Purge ALB [RRE] */
3931 /*-------------------------------------------------------------------*/
DEF_INST(purge_accesslist_lookaside_buffer)3932 DEF_INST(purge_accesslist_lookaside_buffer)
3933 {
3934 int r1, r2; /* Register values (unused) */
3935
3936 RRE(inst, regs, r1, r2);
3937
3938 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
3939 /* This instruction is executed as a no-operation in XC mode */
3940 if(SIE_STATB(regs, MX, XC))
3941 return;
3942 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
3943
3944 PRIV_CHECK(regs);
3945
3946 #if defined(_FEATURE_SIE)
3947 if(SIE_STATB(regs, IC1, PXLB))
3948 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
3949 #endif /*defined(_FEATURE_SIE)*/
3950
3951 /* Purge the ART lookaside buffer for this CPU */
3952 ARCH_DEP(purge_alb) (regs);
3953
3954 }
3955 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
3956
3957
3958 /*-------------------------------------------------------------------*/
3959 /* B20D PTLB - Purge TLB [S] */
3960 /*-------------------------------------------------------------------*/
DEF_INST(purge_translation_lookaside_buffer)3961 DEF_INST(purge_translation_lookaside_buffer)
3962 {
3963 int b2; /* Base of effective addr */
3964 VADR effective_addr2; /* Effective address */
3965
3966 S(inst, regs, b2, effective_addr2);
3967
3968 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
3969 /* This instruction is executed as a no-operation in XC mode */
3970 if(SIE_STATB(regs, MX, XC))
3971 return;
3972 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
3973
3974 PRIV_CHECK(regs);
3975
3976 #if defined(_FEATURE_SIE)
3977 if(SIE_STATB(regs, IC1, PXLB))
3978 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
3979 #endif /*defined(_FEATURE_SIE)*/
3980
3981 /* Purge the translation lookaside buffer for this CPU */
3982 ARCH_DEP(purge_tlb) (regs);
3983
3984 }
3985
3986
3987 #if defined(FEATURE_BASIC_STORAGE_KEYS)
3988 /*-------------------------------------------------------------------*/
3989 /* B213 RRB - Reset Reference Bit [S] */
3990 /*-------------------------------------------------------------------*/
DEF_INST(reset_reference_bit)3991 DEF_INST(reset_reference_bit)
3992 {
3993 int b2; /* Base of effective addr */
3994 VADR effective_addr2; /* Effective address */
3995 RADR n; /* Absolute storage addr */
3996 BYTE storkey; /* Storage key */
3997
3998 S(inst, regs, b2, effective_addr2);
3999
4000 #if defined(FEATURE_4K_STORAGE_KEYS) || defined(_FEATURE_SIE)
4001 if(
4002 #if defined(_FEATURE_SIE) && !defined(FEATURE_4K_STORAGE_KEYS)
4003 SIE_MODE(regs) &&
4004 #endif
4005 !(regs->CR(0) & CR0_STORKEY_4K) )
4006 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
4007 #endif
4008
4009 PRIV_CHECK(regs);
4010
4011 /* Load 2K block real address from operand address */
4012 n = effective_addr2 & 0x00FFF800;
4013
4014 /* Convert real address to absolute address */
4015 n = APPLY_PREFIXING (n, regs->PX);
4016
4017 /* Addressing exception if block is outside main storage */
4018 if ( n > regs->mainlim )
4019 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
4020
4021 #if defined(_FEATURE_SIE)
4022 if(SIE_MODE(regs))
4023 {
4024 if(SIE_STATB(regs, IC2, RRBE))
4025 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4026
4027 if(!regs->sie_pref)
4028 {
4029 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4030 if(SIE_STATB(regs, RCPO0, SKA)
4031 && SIE_STATB(regs, RCPO2, RCPBY))
4032 {
4033 SIE_TRANSLATE(&n, ACCTYPE_SIE, regs);
4034 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4035 storkey = STORAGE_KEY(n, regs);
4036 #else
4037 storkey = STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs);
4038 #endif
4039
4040 /* Reset the reference bit in the storage key */
4041 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4042 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
4043 #else
4044 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
4045 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
4046 #endif
4047 }
4048 else
4049 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4050 {
4051 BYTE rcpkey, realkey;
4052 RADR ra;
4053 RADR rcpa;
4054
4055 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4056 if(SIE_STATB(regs, RCPO0, SKA))
4057 {
4058 /* guest absolute to host PTE addr */
4059 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
4060 regs->hostregs, ACCTYPE_PTE))
4061 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4062
4063 /* Convert real address to absolute address */
4064 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
4065
4066 /* The reference and change byte is located directly
4067 beyond the page table and is located at offset 1 in
4068 the entry. S/370 mode cannot be emulated in ESAME
4069 mode, so no provision is made for ESAME mode tables */
4070 rcpa += 1025;
4071 }
4072 else
4073 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4074 {
4075 /* Obtain address of the RCP area from the state desc */
4076 rcpa = regs->sie_rcpo &= 0x7FFFF000;
4077
4078 /* frame index as byte offset to 4K keys in RCP area */
4079 rcpa += n >> 12;
4080
4081 /* host primary to host absolute */
4082 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
4083 regs->hostregs, ACCTYPE_SIE, 0);
4084 }
4085
4086 /* fetch the RCP key */
4087 rcpkey = regs->mainstor[rcpa];
4088 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
4089
4090 if (!SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
4091 regs->hostregs, ACCTYPE_SIE))
4092 {
4093 ra = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
4094 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4095 realkey = STORAGE_KEY(ra, regs)
4096 #else
4097 realkey = (STORAGE_KEY1(ra, regs) | STORAGE_KEY2(ra, regs))
4098 #endif
4099 & (STORKEY_REF | STORKEY_CHANGE);
4100
4101 /* Reset reference and change bits in storage key */
4102 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4103 STORAGE_KEY(ra, regs) &= ~(STORKEY_REF | STORKEY_CHANGE);
4104 #else
4105 STORAGE_KEY1(ra, regs) &= ~(STORKEY_REF | STORKEY_CHANGE);
4106 STORAGE_KEY2(ra, regs) &= ~(STORKEY_REF | STORKEY_CHANGE);
4107 #endif
4108 }
4109 else
4110 realkey = 0;
4111
4112 /* The storage key is obtained by logical or
4113 or the real and guest RC bits */
4114 storkey = realkey | (rcpkey & (STORKEY_REF | STORKEY_CHANGE));
4115 /* or with host set */
4116 rcpkey |= realkey << 4;
4117 /* Put storage key in guest set */
4118 rcpkey |= storkey;
4119 /* reset the reference bit */
4120 rcpkey &= ~(STORKEY_REF);
4121 regs->mainstor[rcpa] = rcpkey;
4122 STORAGE_KEY(rcpa, regs) |= (STORKEY_REF|STORKEY_CHANGE);
4123 }
4124 }
4125 else /* regs->sie_perf */
4126 {
4127 #if defined(_FEATURE_2K_STORAGE_KEYS)
4128 storkey = STORAGE_KEY(n, regs);
4129 #else
4130 storkey = STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs);
4131 #endif
4132 /* Reset the reference bit in the storage key */
4133 #if defined(_FEATURE_2K_STORAGE_KEYS)
4134 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
4135 #else
4136 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
4137 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
4138 #endif
4139 }
4140 }
4141 else
4142 #endif /*defined(_FEATURE_SIE)*/
4143 {
4144 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4145 storkey = STORAGE_KEY(n, regs);
4146 #else
4147 storkey = STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs);
4148 #endif
4149 /* Reset the reference bit in the storage key */
4150 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4151 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
4152 #else
4153 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
4154 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
4155 #endif
4156 }
4157
4158 /* Set the condition code according to the original state
4159 of the reference and change bits in the storage key */
4160 regs->psw.cc =
4161 ((storkey & STORKEY_REF) ? 2 : 0)
4162 | ((storkey & STORKEY_CHANGE) ? 1 : 0);
4163
4164 /* If the storage key had the REF bit on then perform
4165 * accelerated lookup invalidations on all CPUs
4166 * so that the REF bit will be set when referenced next.
4167 */
4168 if (storkey & STORKEY_REF)
4169 STORKEY_INVALIDATE(regs, n);
4170
4171 }
4172 #endif /*defined(FEATURE_BASIC_STORAGE_KEYS)*/
4173
4174
4175 #if defined(FEATURE_EXTENDED_STORAGE_KEYS)
4176 /*-------------------------------------------------------------------*/
4177 /* B22A RRBE - Reset Reference Bit Extended [RRE] */
4178 /*-------------------------------------------------------------------*/
DEF_INST(reset_reference_bit_extended)4179 DEF_INST(reset_reference_bit_extended)
4180 {
4181 int r1, r2; /* Register values */
4182 RADR n; /* Abs frame addr stor key */
4183 BYTE storkey; /* Storage key */
4184
4185 RRE(inst, regs, r1, r2);
4186
4187 PRIV_CHECK(regs);
4188
4189 /* Load 4K block address from R2 register */
4190 n = regs->GR(r2) & ADDRESS_MAXWRAP_E(regs);
4191
4192 /* Convert real address to absolute address */
4193 n = APPLY_PREFIXING (n, regs->PX);
4194
4195 /* Addressing exception if block is outside main storage */
4196 if ( n > regs->mainlim )
4197 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
4198
4199 #if defined(_FEATURE_SIE)
4200 if(SIE_MODE(regs))
4201 {
4202 if(SIE_STATB(regs, IC2, RRBE))
4203 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4204
4205 if(!regs->sie_pref)
4206 {
4207 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4208 if((SIE_STATB(regs, RCPO0, SKA)
4209 #if defined(_FEATURE_ZSIE)
4210 || (regs->hostregs->arch_mode == ARCH_900)
4211 #endif /*defined(_FEATURE_ZSIE)*/
4212 ) && SIE_STATB(regs, RCPO2, RCPBY))
4213 {
4214 SIE_TRANSLATE(&n, ACCTYPE_SIE, regs);
4215 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4216 storkey = STORAGE_KEY(n, regs);
4217 #else
4218 storkey = STORAGE_KEY1(n, regs)
4219 | (STORAGE_KEY2(n, regs) & (STORKEY_REF|STORKEY_CHANGE))
4220 #endif
4221 ;
4222 /* Reset the reference bit in the storage key */
4223 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4224 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
4225 #else
4226 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
4227 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
4228 #endif
4229 }
4230 else
4231 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4232 {
4233 BYTE rcpkey, realkey;
4234 RADR ra;
4235 RADR rcpa;
4236
4237 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4238 if(SIE_STATB(regs, RCPO0, SKA)
4239 #if defined(_FEATURE_ZSIE)
4240 || (regs->hostregs->arch_mode == ARCH_900)
4241 #endif /*defined(_FEATURE_ZSIE)*/
4242 )
4243 {
4244 /* guest absolute to host PTE addr */
4245 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
4246 regs->hostregs, ACCTYPE_PTE))
4247 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4248
4249 /* Convert real address to absolute address */
4250 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
4251
4252 /* For ESA/390 the RCP byte entry is at offset 1 in a
4253 four byte entry directly beyond the page table,
4254 for ESAME mode, this entry is eight bytes long */
4255 rcpa += regs->hostregs->arch_mode == ARCH_900 ? 2049 : 1025;
4256 }
4257 else
4258 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4259 {
4260 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
4261 if(SIE_STATB(regs, MX, XC))
4262 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4263 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
4264
4265 /* Obtain address of the RCP area from the state desc */
4266 rcpa = regs->sie_rcpo &= 0x7FFFF000;
4267
4268 /* frame index as byte offset to 4K keys in RCP area */
4269 rcpa += n >> 12;
4270
4271 /* host primary to host absolute */
4272 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
4273 regs->hostregs, ACCTYPE_SIE, 0);
4274 }
4275
4276 /* fetch the RCP key */
4277 rcpkey = regs->mainstor[rcpa];
4278 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
4279
4280 if (!SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
4281 regs->hostregs, ACCTYPE_SIE))
4282 {
4283 ra = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
4284 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4285 realkey = STORAGE_KEY(ra, regs) & (STORKEY_REF | STORKEY_CHANGE);
4286 #else
4287 realkey = (STORAGE_KEY1(ra, regs) | STORAGE_KEY2(ra, regs))
4288 & (STORKEY_REF | STORKEY_CHANGE);
4289 #endif
4290 /* Reset the reference and change bits in
4291 the real machine storage key */
4292 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4293 STORAGE_KEY(ra, regs) &= ~(STORKEY_REF | STORKEY_CHANGE);
4294 #else
4295 STORAGE_KEY1(ra, regs) &= ~(STORKEY_REF | STORKEY_CHANGE);
4296 STORAGE_KEY2(ra, regs) &= ~(STORKEY_REF | STORKEY_CHANGE);
4297 #endif
4298 }
4299 else
4300 realkey = 0;
4301
4302 /* The storage key is obtained by logical or
4303 or the real and guest RC bits */
4304 storkey = realkey | (rcpkey & (STORKEY_REF | STORKEY_CHANGE));
4305 /* or with host set */
4306 rcpkey |= realkey << 4;
4307 /* Put storage key in guest set */
4308 rcpkey |= storkey;
4309 /* reset the reference bit */
4310 rcpkey &= ~(STORKEY_REF);
4311 regs->mainstor[rcpa] = rcpkey;
4312 STORAGE_KEY(rcpa, regs) |= (STORKEY_REF|STORKEY_CHANGE);
4313 }
4314 }
4315 else
4316 {
4317 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4318 storkey = STORAGE_KEY(n, regs);
4319 #else
4320 storkey = STORAGE_KEY1(n, regs)
4321 | (STORAGE_KEY2(n, regs) & (STORKEY_REF|STORKEY_CHANGE))
4322 #endif
4323 ;
4324 /* Reset the reference bit in the storage key */
4325 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4326 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
4327 #else
4328 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
4329 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
4330 #endif
4331 }
4332 }
4333 else
4334 #endif /*defined(_FEATURE_SIE)*/
4335 {
4336 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4337 storkey = STORAGE_KEY(n, regs);
4338 #else
4339 storkey = STORAGE_KEY1(n, regs)
4340 | (STORAGE_KEY2(n, regs) & (STORKEY_REF|STORKEY_CHANGE))
4341 #endif
4342 ;
4343 /* Reset the reference bit in the storage key */
4344 #if !defined(_FEATURE_2K_STORAGE_KEYS)
4345 STORAGE_KEY(n, regs) &= ~(STORKEY_REF);
4346 #else
4347 STORAGE_KEY1(n, regs) &= ~(STORKEY_REF);
4348 STORAGE_KEY2(n, regs) &= ~(STORKEY_REF);
4349 #endif
4350 }
4351
4352 /* Set the condition code according to the original state
4353 of the reference and change bits in the storage key */
4354 regs->psw.cc =
4355 ((storkey & STORKEY_REF) ? 2 : 0)
4356 | ((storkey & STORKEY_CHANGE) ? 1 : 0);
4357
4358 /* If the storage key had the REF bit on then perform
4359 * accelerated looup invalidations on all CPUs
4360 * so that the REF bit will be set when referenced next.
4361 */
4362 if (storkey & STORKEY_REF)
4363 STORKEY_INVALIDATE(regs, n);
4364
4365 } /* end DEF_INST(reset_reference_bit_extended) */
4366 #endif /*defined(FEATURE_EXTENDED_STORAGE_KEYS)*/
4367
4368
4369 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
4370 /*-------------------------------------------------------------------*/
4371 /* B219 SAC - Set Address Space Control [S] */
4372 /* B279 SACF - Set Address Space Control Fast [S] */
4373 /*-------------------------------------------------------------------*/
DEF_INST(set_address_space_control)4374 DEF_INST(set_address_space_control)
4375 {
4376 int b2; /* Base of effective addr */
4377 VADR effective_addr2; /* Effective address */
4378 BYTE mode; /* New addressing mode */
4379 BYTE oldmode; /* Current addressing mode */
4380 int ssevent = 0; /* 1=space switch event */
4381
4382 S(inst, regs, b2, effective_addr2);
4383
4384 #if defined(FEATURE_SET_ADDRESS_SPACE_CONTROL_FAST)
4385 if(inst[1] == 0x19) // SAC only
4386 #endif /*defined(FEATURE_SET_ADDRESS_SPACE_CONTROL_FAST)*/
4387 {
4388 /* Perform serialization and checkpoint-synchronization */
4389 PERFORM_SERIALIZATION (regs);
4390 PERFORM_CHKPT_SYNC (regs);
4391 }
4392
4393 /* Isolate bits 20-23 of effective address */
4394 mode = (effective_addr2 & 0x00000F00) >> 8;
4395
4396 /* Special operation exception if DAT is off or
4397 secondary-space control bit is zero */
4398 if ((REAL_MODE(&(regs->psw))
4399 || (regs->CR(0) & CR0_SEC_SPACE) == 0)
4400 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
4401 && !SIE_STATB(regs, MX, XC)
4402 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
4403 )
4404 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
4405
4406 /* Privileged operation exception if setting home-space
4407 mode while in problem state */
4408 if (mode == 3 && PROBSTATE(®s->psw))
4409 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
4410
4411 /* Special operation exception if setting AR mode
4412 and address-space function control bit is zero */
4413 if (mode == 2 && !ASF_ENABLED(regs))
4414 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
4415
4416 /* Specification exception if mode is invalid */
4417 if (mode > 3
4418 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
4419 /* Secondary and Home space mode are not supported in XC mode */
4420 || ( SIE_STATB(regs, MX, XC)
4421 && (mode == 1 || mode == 3) )
4422 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
4423 )
4424 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
4425
4426 /* Save the current address-space control bits */
4427 oldmode = (AR_BIT(®s->psw) << 1) | SPACE_BIT(®s->psw);
4428
4429 /* Reset the address-space control bits in the PSW */
4430 if (mode & 1)
4431 regs->psw.asc |= BIT(PSW_SPACE_BIT);
4432 else
4433 regs->psw.asc &= ~BIT(PSW_SPACE_BIT);
4434 if (mode & 2)
4435 regs->psw.asc |= BIT(PSW_AR_BIT);
4436 else
4437 regs->psw.asc &= ~BIT(PSW_AR_BIT);
4438
4439 TEST_SET_AEA_MODE(regs);
4440
4441 /* If switching into or out of home-space mode, and also:
4442 primary space-switch-event control bit is set; or
4443 home space-switch-event control bit is set; or
4444 PER event is to be indicated
4445 then indicate a space-switch-event */
4446 if (((oldmode != 3 && mode == 3) || (oldmode == 3 && mode != 3))
4447 && (regs->CR(1) & SSEVENT_BIT
4448 || regs->CR(13) & SSEVENT_BIT
4449 || OPEN_IC_PER(regs) ))
4450 {
4451 /* Indicate space-switch event required */
4452 ssevent = 1;
4453
4454 /* [6.5.2.34] Set the translation exception address */
4455 if (mode == 3)
4456 {
4457 /* When switching into home-space mode, set the
4458 translation exception address equal to the primary
4459 ASN, with the high-order bit set equal to the value
4460 of the primary space-switch-event control bit */
4461 regs->TEA = regs->CR_LHL(4);
4462 if (regs->CR(1) & SSEVENT_BIT)
4463 regs->TEA |= TEA_SSEVENT;
4464 }
4465 else
4466 {
4467 /* When switching out of home-space mode, set the
4468 translation exception address equal to zero, with
4469 the high-order bit set equal to the value of the
4470 home space-switch-event control bit */
4471 regs->TEA = 0;
4472 if (regs->CR(13) & SSEVENT_BIT)
4473 regs->TEA |= TEA_SSEVENT;
4474 }
4475 }
4476
4477 /* Generate a space-switch-event if indicated */
4478 if (ssevent)
4479 ARCH_DEP(program_interrupt) (regs, PGM_SPACE_SWITCH_EVENT);
4480
4481 #if defined(FEATURE_SET_ADDRESS_SPACE_CONTROL_FAST)
4482 if(inst[1] == 0x19) // SAC only
4483 #endif /*defined(FEATURE_SET_ADDRESS_SPACE_CONTROL_FAST)*/
4484 {
4485 /* Perform serialization and checkpoint-synchronization */
4486 PERFORM_SERIALIZATION (regs);
4487 PERFORM_CHKPT_SYNC (regs);
4488 }
4489 }
4490 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
4491
4492
4493 /*-------------------------------------------------------------------*/
4494 /* B204 SCK - Set Clock [S] */
4495 /*-------------------------------------------------------------------*/
DEF_INST(set_clock)4496 DEF_INST(set_clock)
4497 {
4498 int b2; /* Base of effective addr */
4499 VADR effective_addr2; /* Effective address */
4500 U64 dreg; /* Clock value */
4501
4502 S(inst, regs, b2, effective_addr2);
4503
4504 SIE_INTERCEPT(regs);
4505
4506 PRIV_CHECK(regs);
4507
4508 DW_CHECK(effective_addr2, regs);
4509
4510 /* Fetch new TOD clock value from operand address */
4511 dreg = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs);
4512
4513 /* Set the clock epoch register */
4514 set_tod_clock(dreg >> 8);
4515
4516 /* reset the clock comparator pending flag according to
4517 the setting of the tod clock */
4518 OBTAIN_INTLOCK(regs);
4519
4520 if( tod_clock(regs) > regs->clkc )
4521 ON_IC_CLKC(regs);
4522 else
4523 OFF_IC_CLKC(regs);
4524
4525 RELEASE_INTLOCK(regs);
4526
4527 /* Return condition code zero */
4528 regs->psw.cc = 0;
4529
4530 RETURN_INTCHECK(regs);
4531
4532 // /*debug*/logmsg("Set TOD clock=%16.16" I64_FMT "X\n", dreg);
4533
4534 }
4535
4536
4537 /*-------------------------------------------------------------------*/
4538 /* B206 SCKC - Set Clock Comparator [S] */
4539 /*-------------------------------------------------------------------*/
DEF_INST(set_clock_comparator)4540 DEF_INST(set_clock_comparator)
4541 {
4542 int b2; /* Base of effective addr */
4543 VADR effective_addr2; /* Effective address */
4544 U64 dreg; /* Clock value */
4545
4546
4547 S(inst, regs, b2, effective_addr2);
4548
4549 PRIV_CHECK(regs);
4550
4551 DW_CHECK(effective_addr2, regs);
4552
4553 #if defined(_FEATURE_SIE)
4554 if(SIE_STATB(regs, IC3, SCKC))
4555 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4556 #endif /*defined(_FEATURE_SIE)*/
4557
4558 /* Fetch clock comparator value from operand location */
4559 dreg = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
4560
4561 // /*debug*/logmsg("Set clock comparator=%16.16" I64_FMT "X\n", dreg);
4562
4563 dreg >>= 8;
4564
4565 OBTAIN_INTLOCK(regs);
4566
4567 regs->clkc = dreg;
4568
4569 /* reset the clock comparator pending flag according to
4570 the setting of the tod clock */
4571 if( tod_clock(regs) > dreg )
4572 ON_IC_CLKC(regs);
4573 else
4574 OFF_IC_CLKC(regs);
4575
4576 RELEASE_INTLOCK(regs);
4577
4578 RETURN_INTCHECK(regs);
4579 }
4580
4581
4582 #if defined(FEATURE_EXTENDED_TOD_CLOCK)
4583 /*-------------------------------------------------------------------*/
4584 /* 0107 SCKPF - Set Clock Programmable Field [E] */
4585 /*-------------------------------------------------------------------*/
DEF_INST(set_clock_programmable_field)4586 DEF_INST(set_clock_programmable_field)
4587 {
4588 E(inst, regs);
4589
4590 PRIV_CHECK(regs);
4591
4592 /* Program check if register 0 bits 0-15 are not zeroes */
4593 if ( regs->GR_LHH(0) )
4594 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
4595
4596 /* Set TOD programmable register from register 0 */
4597 regs->todpr = regs->GR_LHL(0);
4598
4599 } /* end DEF_INST(set_clock_programmable_field) */
4600 #endif /*defined(FEATURE_EXTENDED_TOD_CLOCK)*/
4601
4602
4603 /*-------------------------------------------------------------------*/
4604 /* B208 SPT - Set CPU Timer [S] */
4605 /*-------------------------------------------------------------------*/
DEF_INST(set_cpu_timer)4606 DEF_INST(set_cpu_timer)
4607 {
4608 int b2; /* Base of effective addr */
4609 VADR effective_addr2; /* Effective address */
4610 S64 dreg; /* Timer value */
4611
4612 S(inst, regs, b2, effective_addr2);
4613
4614 PRIV_CHECK(regs);
4615
4616 DW_CHECK(effective_addr2, regs);
4617
4618 #if defined(_FEATURE_SIE)
4619 if(SIE_STATB(regs, IC3, SPT))
4620 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4621 #endif /*defined(_FEATURE_SIE)*/
4622
4623 /* Fetch the CPU timer value from operand location */
4624 dreg = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
4625
4626 OBTAIN_INTLOCK(regs);
4627
4628 set_cpu_timer(regs, dreg);
4629
4630 /* reset the cpu timer pending flag according to its value */
4631 if( CPU_TIMER(regs) < 0 )
4632 ON_IC_PTIMER(regs);
4633 else
4634 OFF_IC_PTIMER(regs);
4635
4636 RELEASE_INTLOCK(regs);
4637
4638 // /*debug*/logmsg("Set CPU timer=%16.16" I64_FMT "X\n", dreg);
4639
4640 RETURN_INTCHECK(regs);
4641 }
4642
4643
4644 /*-------------------------------------------------------------------*/
4645 /* B210 SPX - Set Prefix [S] */
4646 /*-------------------------------------------------------------------*/
DEF_INST(set_prefix)4647 DEF_INST(set_prefix)
4648 {
4649 int b2; /* Base of effective addr */
4650 VADR effective_addr2; /* Effective address */
4651 RADR n; /* Prefix value */
4652
4653 S(inst, regs, b2, effective_addr2);
4654
4655 PRIV_CHECK(regs);
4656
4657 SIE_INTERCEPT(regs);
4658
4659 FW_CHECK(effective_addr2, regs);
4660
4661 /* Perform serialization before fetching the operand */
4662 PERFORM_SERIALIZATION (regs);
4663
4664 /* Load new prefix value from operand address */
4665 n = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
4666
4667 /* Isolate bits 1-19 for ESA/390 or 1-18 for ESAME of new prefix value */
4668 n &= PX_MASK;
4669
4670 /* Program check if prefix is invalid absolute address */
4671 if ( n > regs->mainlim )
4672 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
4673
4674 /* Load new value into prefix register */
4675 regs->PX = n;
4676
4677 /* Set pointer to active PSA structure */
4678 regs->psa = (PSA_3XX*)(regs->mainstor + regs->PX);
4679
4680 /* Invalidate the ALB and TLB */
4681 ARCH_DEP(purge_tlb) (regs);
4682 #if defined(FEATURE_ACCESS_REGISTERS)
4683 ARCH_DEP(purge_alb) (regs);
4684 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
4685
4686 /* Perform serialization after completing the operation */
4687 PERFORM_SERIALIZATION (regs);
4688
4689 }
4690
4691
4692 /*-------------------------------------------------------------------*/
4693 /* B20A SPKA - Set PSW Key from Address [S] */
4694 /*-------------------------------------------------------------------*/
DEF_INST(set_psw_key_from_address)4695 DEF_INST(set_psw_key_from_address)
4696 {
4697 int b2; /* Base of effective addr */
4698 VADR effective_addr2; /* Effective address */
4699 int n; /* Storage key workarea */
4700 BYTE pkey; /* Original key */
4701
4702 S(inst, regs, b2, effective_addr2);
4703
4704 pkey = regs->psw.pkey;
4705
4706 /* Isolate the key from bits 24-27 of effective address */
4707 n = effective_addr2 & 0x000000F0;
4708
4709 /* Privileged operation exception if in problem state
4710 and the corresponding PSW key mask bit is zero */
4711 if ( PROBSTATE(®s->psw)
4712 && ((regs->CR(3) << (n >> 4)) & 0x80000000) == 0 )
4713 ARCH_DEP(program_interrupt) (regs, PGM_PRIVILEGED_OPERATION_EXCEPTION);
4714
4715 /* Set PSW key */
4716 regs->psw.pkey = n;
4717 INVALIDATE_AIA(regs);
4718 }
4719
4720
4721 #if defined(FEATURE_DUAL_ADDRESS_SPACE)
4722 /*-------------------------------------------------------------------*/
4723 /* Common processing routine for the SSAR and SSAIR instructions */
4724 /*-------------------------------------------------------------------*/
ARCH_DEP(set_secondary_asn_proc)4725 void ARCH_DEP(set_secondary_asn_proc) (REGS *regs,
4726 int r1, int r2, int ssair_instruction)
4727 {
4728 U16 sasn; /* New Secondary ASN */
4729 RADR sstd; /* Secondary STD */
4730 U32 sasteo=0; /* Secondary ASTE origin */
4731 U32 aste[16]; /* ASN second table entry */
4732 U32 sastein; /* New Secondary ASTEIN */
4733 U16 xcode; /* Exception code */
4734 U16 ax; /* Authorization index */
4735 #ifdef FEATURE_TRACING
4736 CREG newcr12 = 0; /* CR12 upon completion */
4737 #endif /*FEATURE_TRACING*/
4738
4739 UNREFERENCED(r2);
4740
4741 SIE_XC_INTERCEPT(regs);
4742
4743 /* Perform serialization and checkpoint-synchronization */
4744 PERFORM_SERIALIZATION (regs);
4745 PERFORM_CHKPT_SYNC (regs);
4746
4747 /* Special operation exception if ASN translation control
4748 (bit 12 of control register 14) is zero or DAT is off */
4749 if ((regs->CR(14) & CR14_ASN_TRAN) == 0
4750 || REAL_MODE(&(regs->psw)))
4751 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
4752
4753 /* Load the new ASN from R1 register bits 16-31 */
4754 sasn = regs->GR_LHL(r1);
4755
4756 #ifdef FEATURE_TRACING
4757 /* Form trace entry if ASN tracing is on */
4758 if (regs->CR(12) & CR12_ASNTRACE)
4759 newcr12 = ARCH_DEP(trace_ssar) (ssair_instruction, sasn, regs);
4760 #endif /*FEATURE_TRACING*/
4761
4762 /* Test for SSAR/SSAIR to current primary */
4763 if ( sasn == regs->CR_LHL(4) )
4764 {
4765 /* Set new secondary STD equal to primary STD */
4766 sstd = regs->CR(1);
4767
4768 /* Set new secondary ASTEIN equal to primary ASTEIN */
4769 sastein = regs->CR_H(4);
4770
4771 } /* end if(SSAR-cp or SSAIR-cp) */
4772 else
4773 { /* SSAR/SSAIR with space-switch */
4774
4775 /* Perform ASN translation to obtain ASTE */
4776 xcode = ARCH_DEP(translate_asn) (sasn, regs, &sasteo, aste);
4777
4778 /* Program check if ASN translation exception */
4779 if (xcode != 0)
4780 ARCH_DEP(program_interrupt) (regs, xcode);
4781
4782 /* For SSAR-ss only, generate a special operation exception
4783 if ASN-and-LX-reuse is enabled and the reusable-ASN bit
4784 in the ASTE is one */
4785 if (ssair_instruction == 0 && ASN_AND_LX_REUSE_ENABLED(regs)
4786 && (aste[1] & ASTE1_RA) != 0)
4787 {
4788 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
4789 } /* end if (SSAR && ASN_AND_LX_REUSE_ENABLED && ASTE1_RA) */
4790
4791 /* For SSAIR-ss only, generate a special operation exception
4792 if the controlled-ASN bit in the ASTE is one and the CPU
4793 is in problem state */
4794 if (ssair_instruction && (aste[1] & ASTE1_CA) != 0
4795 && PROBSTATE(®s->psw))
4796 {
4797 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
4798 } /* end if (SSAIR && ASTE1_CA && PROBSTATE) */
4799
4800 /* For SSAIR-ss only, generate an ASTE instance exception
4801 if the ASTEIN in bits 0-31 of the R1 register does
4802 not equal the ASTEIN in the ASTE */
4803 if (ssair_instruction && aste[11] != regs->GR_H(r1))
4804 {
4805 /* Set bit 3 of the exception access identification
4806 to indicate that the program check occurred
4807 during SASN translation in a SSAIR instruction */
4808 regs->excarid = 0x10;
4809 ARCH_DEP(program_interrupt) (regs, PGM_ASTE_INSTANCE_EXCEPTION);
4810 } /* end if (SSAIR && ASTE11_ASTEIN != GR_H(r1)) */
4811
4812 /* Perform ASN authorization using current AX */
4813 ax = regs->CR_LHH(4);
4814 if (ARCH_DEP(authorize_asn) (ax, aste, ATE_SECONDARY, regs))
4815 {
4816 regs->TEA = sasn;
4817 ARCH_DEP(program_interrupt) (regs, PGM_SECONDARY_AUTHORITY_EXCEPTION);
4818 }
4819
4820 /* Load new secondary STD or ASCE from the ASTE */
4821 sstd = ASTE_AS_DESIGNATOR(aste);
4822
4823 /* Load new secondary ASTEIN from the ASTE */
4824 sastein = aste[11];
4825
4826 #ifdef FEATURE_SUBSPACE_GROUP
4827 /* Perform subspace replacement on new SSTD */
4828 sstd = ARCH_DEP(subspace_replace) (sstd, sasteo, NULL, regs);
4829 #endif /*FEATURE_SUBSPACE_GROUP*/
4830
4831 } /* end if(SSAR-ss or SSAIR-ss) */
4832
4833 #ifdef FEATURE_TRACING
4834 /* Update trace table address if ASN tracing is on */
4835 if (regs->CR(12) & CR12_ASNTRACE)
4836 regs->CR(12) = newcr12;
4837 #endif /*FEATURE_TRACING*/
4838
4839 /* Load the new secondary ASN into control register 3 */
4840 regs->CR_LHL(3) = sasn;
4841
4842 /* Load the new secondary STD into control register 7 */
4843 regs->CR(7) = sstd;
4844
4845 /* For SSAIR, and for SSAR when ASN-and-LX-reuse is enabled,
4846 load the new secondary ASTEIN into control register 3 */
4847 if (ssair_instruction || ASN_AND_LX_REUSE_ENABLED(regs))
4848 {
4849 regs->CR_H(3) = sastein;
4850 } /* end if (SSAIR || ASN_AND_LX_REUSE_ENABLED) */
4851
4852 /* Perform serialization and checkpoint-synchronization */
4853 PERFORM_SERIALIZATION (regs);
4854 PERFORM_CHKPT_SYNC (regs);
4855
4856 } /* end ARCH_DEP(set_secondary_asn_proc) */
4857
4858
4859 /*-------------------------------------------------------------------*/
4860 /* B225 SSAR - Set Secondary ASN [RRE] */
4861 /*-------------------------------------------------------------------*/
DEF_INST(set_secondary_asn)4862 DEF_INST(set_secondary_asn)
4863 {
4864 int r1, r2; /* Values of R fields */
4865
4866 RRE(inst, regs, r1, r2);
4867 ARCH_DEP(set_secondary_asn_proc) (regs, r1, r2, 0);
4868
4869 } /* end DEF_INST(set_secondary_asn) */
4870 #endif /*defined(FEATURE_DUAL_ADDRESS_SPACE)*/
4871
4872
4873 #if defined(FEATURE_ASN_AND_LX_REUSE)
4874 /*-------------------------------------------------------------------*/
4875 /* B99F SSAIR - Set Secondary ASN with Instance [RRE] */
4876 /*-------------------------------------------------------------------*/
DEF_INST(set_secondary_asn_with_instance)4877 DEF_INST(set_secondary_asn_with_instance)
4878 {
4879 int r1, r2; /* Values of R fields */
4880
4881 if(!sysblk.asnandlxreuse)
4882 {
4883 ARCH_DEP(operation_exception)(inst,regs);
4884 }
4885
4886 RRE(inst, regs, r1, r2);
4887 ARCH_DEP(set_secondary_asn_proc) (regs, r1, r2, 1);
4888
4889 } /* end DEF_INST(set_secondary_asn_with_instance) */
4890 #endif /*defined(FEATURE_ASN_AND_LX_REUSE)*/
4891
4892
4893 #if defined(FEATURE_BASIC_STORAGE_KEYS)
4894 /*-------------------------------------------------------------------*/
4895 /* 08 SSK - Set Storage Key [RR] */
4896 /*-------------------------------------------------------------------*/
DEF_INST(set_storage_key)4897 DEF_INST(set_storage_key)
4898 {
4899 int r1, r2; /* Values of R fields */
4900 RADR n; /* Absolute storage addr */
4901
4902 RR(inst, regs, r1, r2);
4903
4904 PRIV_CHECK(regs);
4905
4906 #if defined(FEATURE_4K_STORAGE_KEYS) || defined(_FEATURE_SIE)
4907 if(
4908 #if defined(_FEATURE_SIE) && !defined(FEATURE_4K_STORAGE_KEYS)
4909 SIE_MODE(regs) &&
4910 #endif
4911 !(regs->CR(0) & CR0_STORKEY_4K) )
4912 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
4913 #endif
4914
4915 /* Program check if R2 bits 28-31 are not zeroes */
4916 if ( regs->GR_L(r2) & 0x0000000F )
4917 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
4918
4919 /* Load 2K block address from R2 register */
4920 n = regs->GR_L(r2) & 0x00FFF800;
4921
4922 /* Convert real address to absolute address */
4923 n = APPLY_PREFIXING (n, regs->PX);
4924
4925 /* Addressing exception if block is outside main storage */
4926 if ( n > regs->mainlim )
4927 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
4928
4929 #if defined(_FEATURE_SIE)
4930 if(SIE_MODE(regs))
4931 {
4932 if(SIE_STATB(regs, IC2, SSKE))
4933 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4934
4935 if(!regs->sie_pref)
4936 {
4937 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4938 if(SIE_STATB(regs, RCPO0, SKA)
4939 && SIE_STATB(regs, RCPO2, RCPBY))
4940 { SIE_TRANSLATE(&n, ACCTYPE_SIE, regs); }
4941 else
4942 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4943 {
4944 int sr;
4945 BYTE realkey,
4946 rcpkey;
4947 RADR rcpa;
4948
4949 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4950 if(SIE_STATB(regs, RCPO0, SKA))
4951 {
4952 /* guest absolute to host PTE addr */
4953 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
4954 regs->hostregs, ACCTYPE_PTE))
4955 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4956
4957 /* Convert real address to absolute address */
4958 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
4959
4960 /* The reference and change byte is located directly
4961 beyond the page table and is located at offset 1 in
4962 the entry. S/370 mode cannot be emulated in ESAME
4963 mode, so no provision is made for ESAME mode tables */
4964 rcpa += 1025;
4965 }
4966 else
4967 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4968 {
4969 /* Obtain address of the RCP area from the state desc */
4970 rcpa = regs->sie_rcpo &= 0x7FFFF000;
4971
4972 /* frame index as byte offset to 4K keys in RCP area */
4973 rcpa += n >> 12;
4974
4975 /* host primary to host absolute */
4976 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
4977 regs->hostregs, ACCTYPE_SIE, 0);
4978 }
4979
4980 /* guest absolute to host real */
4981 sr = SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
4982 regs->hostregs, ACCTYPE_SIE);
4983
4984 if (sr
4985 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4986 && !SIE_FEATB(regs, RCPO0, SKA)
4987 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4988 )
4989 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
4990
4991 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
4992 if (sr)
4993 realkey = 0;
4994 else
4995 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
4996 {
4997 /* host real to host absolute */
4998 n = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
4999
5000 realkey =
5001 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5002 STORAGE_KEY(n, regs)
5003 #else
5004 (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs))
5005 #endif
5006 & (STORKEY_REF | STORKEY_CHANGE);
5007 }
5008
5009 /* fetch the RCP key */
5010 rcpkey = regs->mainstor[rcpa];
5011 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
5012 /* or with host set */
5013 rcpkey |= realkey << 4;
5014 /* or new settings with guest set */
5015 rcpkey &= ~(STORKEY_REF | STORKEY_CHANGE);
5016 rcpkey |= regs->GR_L(r1) & (STORKEY_REF | STORKEY_CHANGE);
5017 regs->mainstor[rcpa] = rcpkey;
5018 STORAGE_KEY(rcpa, regs) |= (STORKEY_REF|STORKEY_CHANGE);
5019 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5020 /* Insert key in new storage key */
5021 if(SIE_STATB(regs, RCPO0, SKA))
5022 regs->mainstor[rcpa-1] = regs->GR_LHLCL(r1)
5023 & (STORKEY_KEY | STORKEY_FETCH);
5024 if(!sr)
5025 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5026 {
5027 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5028 STORAGE_KEY(n, regs) &= STORKEY_BADFRM;
5029 STORAGE_KEY(n, regs) |= regs->GR_LHLCL(r1)
5030 & (STORKEY_KEY | STORKEY_FETCH);
5031 #else
5032 STORAGE_KEY1(n, regs) &= STORKEY_BADFRM;
5033 STORAGE_KEY1(n, regs) |= regs->GR_LHLCL(r1)
5034 & (STORKEY_KEY | STORKEY_FETCH);
5035 STORAGE_KEY2(n, regs) &= STORKEY_BADFRM;
5036 STORAGE_KEY2(n, regs) |= regs->GR_LHLCL(r1)
5037 & (STORKEY_KEY | STORKEY_FETCH);
5038 #endif
5039 }
5040 }
5041 }
5042 else
5043 {
5044 /* Update the storage key from R1 register bits 24-30 */
5045 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5046 STORAGE_KEY(n, regs) &= STORKEY_BADFRM;
5047 STORAGE_KEY(n, regs) |= regs->GR_LHLCL(r1) & ~(STORKEY_BADFRM);
5048 #else
5049 STORAGE_KEY1(n, regs) &= STORKEY_BADFRM;
5050 STORAGE_KEY1(n, regs) |= regs->GR_LHLCL(r1) & ~(STORKEY_BADFRM);
5051 STORAGE_KEY2(n, regs) &= STORKEY_BADFRM;
5052 STORAGE_KEY2(n, regs) |= regs->GR_LHLCL(r1) & ~(STORKEY_BADFRM);
5053 #endif
5054 }
5055 }
5056 else
5057 #endif /*defined(_FEATURE_SIE)*/
5058 {
5059 /* Update the storage key from R1 register bits 24-30 */
5060 #if defined(_FEATURE_2K_STORAGE_KEYS)
5061 STORAGE_KEY(n, regs) &= STORKEY_BADFRM;
5062 STORAGE_KEY(n, regs) |= regs->GR_LHLCL(r1) & ~(STORKEY_BADFRM);
5063 #else
5064 STORAGE_KEY1(n, regs) &= STORKEY_BADFRM;
5065 STORAGE_KEY1(n, regs) |= regs->GR_LHLCL(r1) & ~(STORKEY_BADFRM);
5066 STORAGE_KEY2(n, regs) &= STORKEY_BADFRM;
5067 STORAGE_KEY2(n, regs) |= regs->GR_LHLCL(r1) & ~(STORKEY_BADFRM);
5068 #endif
5069 }
5070
5071 STORKEY_INVALIDATE(regs, n);
5072
5073 // /*debug*/logmsg("SSK storage block %8.8X key %2.2X\n",
5074 // /*debug*/ regs->GR_L(r2), regs->GR_LHLCL(r1) & 0xFE);
5075
5076 } /* end DEF_INST(set_storage_key) */
5077 #endif /*defined(FEATURE_BASIC_STORAGE_KEYS)*/
5078
5079
5080 #if defined(FEATURE_EXTENDED_STORAGE_KEYS)
5081 #if defined(FEATURE_CONDITIONAL_SSKE)
5082 /*-------------------------------------------------------------------*/
5083 /* SUBROUTINE TO PERFORM CONDITIONAL SSKE PROCESSING */
5084 /* Input: */
5085 /* regs Register context */
5086 /* r1 Register number field from SSKE instruction */
5087 /* m3 Mask field from SSKE instruction */
5088 /* skey Contents of storage key before modification */
5089 /* r1key New storage key to be set (R1 bits 56-63) */
5090 /* Output (when conditional SSKE is not indicated): */
5091 /* r1 register and condition code remain unchanged; */
5092 /* The function return value is 0. */
5093 /* Output (when conditional SSKE is indicated): */
5094 /* r1 register bits 48-55 contain original storage key; */
5095 /* - if storage key is to be updated, the condition code */
5096 /* is set to 1 and the function return value is 0; */
5097 /* - if storage key update is to be bypassed, the condition */
5098 /* code is set to 0 and the function return value is 1; */
5099 /*-------------------------------------------------------------------*/
ARCH_DEP(conditional_sske_procedure)5100 static inline int ARCH_DEP(conditional_sske_procedure)
5101 (REGS *regs, int r1, int m3, BYTE skey, BYTE r1key)
5102 {
5103 /* Perform normal SSKE if MR and MC bits are both zero */
5104 if ((m3 & (SSKE_MASK_MR | SSKE_MASK_MC)) == 0)
5105 return 0;
5106
5107 /* Perform conditional SSKE if either MR or MC bits are set */
5108
5109 /* Ignore Bad Frame indicator */
5110 skey &= ~(STORKEY_BADFRM);
5111
5112 /* Insert storage key into R1 register bits 48-55 */
5113 regs->GR_LHLCH(r1) = skey;
5114
5115 /* If storage key and fetch bit do not equal new values
5116 in R1 register bits 56-60 then set condition code 1
5117 and return to SSKE to update storage key */
5118 if ((skey & (STORKEY_KEY | STORKEY_FETCH))
5119 != (r1key & (STORKEY_KEY | STORKEY_FETCH)))
5120 {
5121 regs->psw.cc = 1;
5122 return 0;
5123 }
5124
5125 /* If both MR and MC mask bits are one then set
5126 condition code 0 and leave storage key unchanged */
5127 if ((m3 & (SSKE_MASK_MR | SSKE_MASK_MC))
5128 == (SSKE_MASK_MR | SSKE_MASK_MC))
5129 {
5130 regs->psw.cc = 0;
5131 return 1;
5132 }
5133
5134 /* If MR bit is zero and reference bit is equal to
5135 bit 61 of R1 register then set condition code 0
5136 and leave storage key unchanged */
5137 if ((m3 & SSKE_MASK_MR) == 0
5138 && ((skey & STORKEY_REF)
5139 == (r1key & STORKEY_REF)))
5140 {
5141 regs->psw.cc = 0;
5142 return 1;
5143 }
5144
5145 /* If MC bit is zero and the change bit is equal to
5146 bit 62 of R1 register then set condition code 0
5147 and leave storage key unchanged */
5148 if ((m3 & SSKE_MASK_MC) == 0
5149 && ((skey & STORKEY_CHANGE)
5150 == (r1key & STORKEY_CHANGE)))
5151 {
5152 regs->psw.cc = 0;
5153 return 1;
5154 }
5155
5156 /* Set condition code 1 and let SSKE update storage key */
5157 regs->psw.cc = 1;
5158 return 0;
5159
5160 } /* end function conditional_sske_procedure */
5161 #endif /*defined(FEATURE_CONDITIONAL_SSKE)*/
5162 #endif /*defined(FEATURE_EXTENDED_STORAGE_KEYS)*/
5163
5164
5165 #if defined(FEATURE_EXTENDED_STORAGE_KEYS)
5166 /*-------------------------------------------------------------------*/
5167 /* B22B SSKE - Set Storage Key extended [RRF] */
5168 /*-------------------------------------------------------------------*/
DEF_INST(set_storage_key_extended)5169 DEF_INST(set_storage_key_extended)
5170 {
5171 int r1, r2; /* Register numbers */
5172 int m3; /* Mask field */
5173 RADR a,n; /* Abs frame addr stor key */
5174 #if defined(FEATURE_ENHANCED_DAT_FACILITY)
5175 int fc; /* Frame Count */
5176 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY)*/
5177 BYTE r1key; /* New key (R1 bits 56-63) */
5178
5179 RRF_M(inst, regs, r1, r2, m3);
5180
5181 PRIV_CHECK(regs);
5182
5183 /* Load 4K block address from R2 register */
5184 a = regs->GR(r2) & ADDRESS_MAXWRAP_E(regs);
5185
5186 /* Key to be applied */
5187 r1key = regs->GR_LHLCL(r1);
5188
5189 /* Perform serialization and checkpoint-synchronization */
5190 PERFORM_SERIALIZATION (regs);
5191 PERFORM_CHKPT_SYNC (regs);
5192
5193 #if defined(FEATURE_ENHANCED_DAT_FACILITY)
5194 if ((m3 & SSKE_MASK_MB))
5195 fc = 0x100 - ((a & 0xFF000) >> PAGEFRAME_PAGESHIFT);
5196 else
5197 fc = 1;
5198
5199 for( ; fc--; )
5200 {
5201
5202 if ((m3 & SSKE_MASK_MB))
5203 /* r2 contains an absolute address when
5204 multiple block control is one */
5205 n = a;
5206 else
5207 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY)*/
5208 /* Convert real address to absolute address */
5209 n = APPLY_PREFIXING (a, regs->PX);
5210
5211 /* Addressing exception if block is outside main storage */
5212 if ( n > regs->mainlim )
5213 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
5214
5215 #if defined(_FEATURE_SIE)
5216 if(SIE_MODE(regs))
5217 {
5218 if(SIE_STATB(regs, IC2, SSKE))
5219 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5220
5221 if(!regs->sie_pref)
5222 {
5223 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5224 if ((SIE_STATB(regs, RCPO0, SKA)
5225 #if defined(_FEATURE_ZSIE)
5226 || (regs->hostregs->arch_mode == ARCH_900)
5227 #endif /*defined(_FEATURE_ZSIE)*/
5228 ) && SIE_STATB(regs, RCPO2, RCPBY))
5229 { SIE_TRANSLATE(&n, ACCTYPE_SIE, regs); }
5230 else
5231 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5232 {
5233 int sr;
5234 BYTE realkey,
5235 rcpkey,
5236 protkey;
5237 RADR rcpa;
5238
5239 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5240 if(SIE_STATB(regs, RCPO0, SKA)
5241 #if defined(_FEATURE_ZSIE)
5242 || (regs->hostregs->arch_mode == ARCH_900)
5243 #endif /*defined(_FEATURE_ZSIE)*/
5244 )
5245 {
5246 /* guest absolute to host PTE addr */
5247 if (SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
5248 regs->hostregs, ACCTYPE_PTE))
5249 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5250
5251 /* Convert real address to absolute address */
5252 rcpa = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
5253
5254 /* For ESA/390 the RCP byte entry is at offset 1 in a
5255 four byte entry directly beyond the page table,
5256 for ESAME mode, this entry is eight bytes long */
5257 rcpa += regs->hostregs->arch_mode == ARCH_900 ? 2049 : 1025;
5258 }
5259 else
5260 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5261 {
5262 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
5263 if(SIE_STATB(regs, MX, XC))
5264 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5265 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
5266
5267 /* Obtain address of the RCP area from the state desc */
5268 rcpa = regs->sie_rcpo &= 0x7FFFF000;
5269
5270 /* frame index as byte offset to 4K keys in RCP area */
5271 rcpa += n >> 12;
5272
5273 /* host primary to host absolute */
5274 rcpa = SIE_LOGICAL_TO_ABS (rcpa, USE_PRIMARY_SPACE,
5275 regs->hostregs, ACCTYPE_SIE, 0);
5276 }
5277
5278 /* guest absolute to host real */
5279 sr = SIE_TRANSLATE_ADDR (regs->sie_mso + n, USE_PRIMARY_SPACE,
5280 regs->hostregs, ACCTYPE_SIE);
5281
5282 if (sr
5283 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5284 && !(SIE_FEATB(regs, RCPO0, SKA)
5285 #if defined(_FEATURE_ZSIE)
5286 || (regs->hostregs->arch_mode == ARCH_900)
5287 #endif /*defined(_FEATURE_ZSIE)*/
5288 )
5289 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5290 )
5291 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5292
5293 /* fetch the RCP key */
5294 rcpkey = regs->mainstor[rcpa];
5295 /* set the reference bit in the RCP key */
5296 STORAGE_KEY(rcpa, regs) |= STORKEY_REF;
5297 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5298 if(sr)
5299 {
5300 realkey = 0;
5301 protkey = rcpkey & (STORKEY_REF | STORKEY_CHANGE);
5302 /* rcpa-1 is correct here - would have been SIE Intercepted otherwise */
5303 protkey |= regs->mainstor[rcpa-1] & (STORKEY_KEY | STORKEY_FETCH);
5304 }
5305 else
5306 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5307 {
5308 /* host real to host absolute */
5309 n = APPLY_PREFIXING(regs->hostregs->dat.raddr, regs->hostregs->PX);
5310
5311 protkey =
5312 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5313 STORAGE_KEY(n, regs)
5314 #else
5315 (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs))
5316 #endif
5317 ;
5318 realkey = protkey & (STORKEY_REF | STORKEY_CHANGE);
5319 }
5320
5321 #if defined(FEATURE_CONDITIONAL_SSKE)
5322 /* Perform conditional SSKE procedure */
5323 if (ARCH_DEP(conditional_sske_procedure)(regs, r1, m3, protkey, r1key))
5324 return;
5325 #endif /*defined(FEATURE_CONDITIONAL_SSKE)*/
5326 /* or with host set */
5327 rcpkey |= realkey << 4;
5328 /* insert new settings of the guest set */
5329 rcpkey &= ~(STORKEY_REF | STORKEY_CHANGE);
5330 rcpkey |= r1key & (STORKEY_REF | STORKEY_CHANGE);
5331 regs->mainstor[rcpa] = rcpkey;
5332 STORAGE_KEY(rcpa, regs) |= (STORKEY_REF|STORKEY_CHANGE);
5333 #if defined(_FEATURE_STORAGE_KEY_ASSIST)
5334 /* Insert key in new storage key */
5335 if(SIE_STATB(regs, RCPO0, SKA)
5336 #if defined(_FEATURE_ZSIE)
5337 || (regs->hostregs->arch_mode == ARCH_900)
5338 #endif /*defined(_FEATURE_ZSIE)*/
5339 )
5340 regs->mainstor[rcpa-1] = r1key
5341 & (STORKEY_KEY | STORKEY_FETCH);
5342 if(!sr)
5343 #endif /*defined(_FEATURE_STORAGE_KEY_ASSIST)*/
5344 {
5345 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5346 STORAGE_KEY(n, regs) &= STORKEY_BADFRM;
5347 STORAGE_KEY(n, regs) |= r1key
5348 & (STORKEY_KEY | STORKEY_FETCH);
5349 #else
5350 STORAGE_KEY1(n, regs) &= STORKEY_BADFRM;
5351 STORAGE_KEY1(n, regs) |= r1key
5352 & (STORKEY_KEY | STORKEY_FETCH);
5353 STORAGE_KEY2(n, regs) &= STORKEY_BADFRM;
5354 STORAGE_KEY2(n, regs) |= r1key
5355 & (STORKEY_KEY | STORKEY_FETCH);
5356 #endif
5357 }
5358 }
5359 }
5360 else
5361 {
5362 #if defined(FEATURE_CONDITIONAL_SSKE)
5363 /* Perform conditional SSKE procedure */
5364 if (ARCH_DEP(conditional_sske_procedure)(regs, r1, m3,
5365 #if defined(FEATURE_4K_STORAGE_KEYS) && !defined(_FEATURE_2K_STORAGE_KEYS)
5366 STORAGE_KEY(n, regs),
5367 #else
5368 (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)),
5369 #endif
5370 r1key))
5371 return;
5372 #endif /*defined(FEATURE_CONDITIONAL_SSKE)*/
5373 /* Update the storage key from R1 register bits 24-30 */
5374 #if !defined(_FEATURE_2K_STORAGE_KEYS)
5375 STORAGE_KEY(n, regs) &= STORKEY_BADFRM;
5376 STORAGE_KEY(n, regs) |= r1key & ~(STORKEY_BADFRM);
5377 #else
5378 STORAGE_KEY1(n, regs) &= STORKEY_BADFRM;
5379 STORAGE_KEY1(n, regs) |= r1key & ~(STORKEY_BADFRM);
5380 STORAGE_KEY2(n, regs) &= STORKEY_BADFRM;
5381 STORAGE_KEY2(n, regs) |= r1key & ~(STORKEY_BADFRM);
5382 #endif
5383 }
5384 }
5385 else
5386 #endif /*defined(_FEATURE_SIE)*/
5387 {
5388 #if defined(FEATURE_CONDITIONAL_SSKE)
5389 /* Perform conditional SSKE procedure */
5390 if (ARCH_DEP(conditional_sske_procedure)(regs, r1, m3,
5391 #if defined(FEATURE_4K_STORAGE_KEYS) && !defined(_FEATURE_2K_STORAGE_KEYS)
5392 STORAGE_KEY(n, regs),
5393 #else
5394 (STORAGE_KEY1(n, regs) | STORAGE_KEY2(n, regs)),
5395 #endif
5396 r1key))
5397 return;
5398 #endif /*defined(FEATURE_CONDITIONAL_SSKE)*/
5399
5400 /* Update the storage key from R1 register bits 24-30 */
5401 #if defined(FEATURE_4K_STORAGE_KEYS) && !defined(_FEATURE_2K_STORAGE_KEYS)
5402 STORAGE_KEY(n, regs) &= STORKEY_BADFRM;
5403 STORAGE_KEY(n, regs) |= r1key & ~(STORKEY_BADFRM);
5404 #else
5405 STORAGE_KEY1(n, regs) &= STORKEY_BADFRM;
5406 STORAGE_KEY1(n, regs) |= r1key & ~(STORKEY_BADFRM);
5407 STORAGE_KEY2(n, regs) &= STORKEY_BADFRM;
5408 STORAGE_KEY2(n, regs) |= r1key & ~(STORKEY_BADFRM);
5409 #endif
5410 }
5411
5412 /* Invalidate AIA/AEA so that the REF and CHANGE bits will be set
5413 when referenced next */
5414 STORKEY_INVALIDATE(regs, n);
5415
5416 #if defined(FEATURE_ENHANCED_DAT_FACILITY)
5417 /* Update r2 in the case of a multiple page update */
5418 if ((m3 & SSKE_MASK_MB))
5419 {
5420 /* Advance r2 to the next page */
5421 a += PAGEFRAME_PAGESIZE;
5422
5423 if(regs->psw.amode64)
5424 regs->GR_G(r2) = a & ADDRESS_MAXWRAP(regs);
5425 else
5426 regs->GR_L(r2) = a & ADDRESS_MAXWRAP(regs);
5427 }
5428
5429 }
5430 #endif /*defined(FEATURE_ENHANCED_DAT_FACILITY)*/
5431
5432 /* Perform serialization and checkpoint-synchronization */
5433 PERFORM_SERIALIZATION (regs);
5434 PERFORM_CHKPT_SYNC (regs);
5435
5436 } /* end DEF_INST(set_storage_key_extended) */
5437 #endif /*defined(FEATURE_EXTENDED_STORAGE_KEYS)*/
5438
5439
5440 /*-------------------------------------------------------------------*/
5441 /* 80 SSM - Set System Mask [S] */
5442 /*-------------------------------------------------------------------*/
DEF_INST(set_system_mask)5443 DEF_INST(set_system_mask)
5444 {
5445 int b2; /* Base of effective addr */
5446 VADR effective_addr2; /* Effective address */
5447
5448 S(inst, regs, b2, effective_addr2);
5449 /*
5450 * ECPS:VM - Before checking for prob/priv
5451 * Check CR6 to see if S-ASSIST is requested
5452 *
5453 * If we can process it, then do it
5454 */
5455 #if defined(FEATURE_ECPSVM)
5456 if(ecpsvm_dossm(regs,b2,effective_addr2)==0)
5457 {
5458 return;
5459 }
5460 #endif
5461
5462 PRIV_CHECK(regs);
5463
5464 /* Special operation exception if SSM-suppression is active */
5465 if ( (regs->CR(0) & CR0_SSM_SUPP)
5466 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
5467 /* SSM-suppression is ignored in XC mode */
5468 && !SIE_STATB(regs, MX, XC)
5469 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
5470 )
5471 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
5472
5473 #if defined(_FEATURE_SIE)
5474 if(SIE_STATB(regs, IC1, SSM))
5475 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
5476 #endif /*defined(_FEATURE_SIE)*/
5477
5478 /* Load new system mask value from operand address */
5479 regs->psw.sysmask = ARCH_DEP(vfetchb) ( effective_addr2, b2, regs );
5480
5481 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
5482 /* DAT must be off in XC mode */
5483 if(SIE_STATB(regs, MX, XC)
5484 && (regs->psw.sysmask & PSW_DATMODE) )
5485 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
5486 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
5487
5488 /* For ECMODE, bits 0 and 2-4 of system mask must be zero */
5489 if ((regs->psw.sysmask & 0xB8) != 0
5490 #if defined(FEATURE_BCMODE)
5491 && ECMODE(®s->psw)
5492 #endif /*defined(FEATURE_BCMODE)*/
5493 )
5494 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
5495
5496 SET_IC_MASK(regs);
5497 TEST_SET_AEA_MODE(regs);
5498
5499 RETURN_INTCHECK(regs);
5500
5501 } /* end DEF_INST(set_system_mask) */
5502
5503
5504 /*-------------------------------------------------------------------*/
5505 /* AE SIGP - Signal Processor [RS] */
5506 /*-------------------------------------------------------------------*/
DEF_INST(signal_processor)5507 DEF_INST(signal_processor)
5508 {
5509 int r1, r3; /* Register numbers */
5510 int b2; /* effective address base */
5511 VADR effective_addr2; /* effective address */
5512 REGS *tregs; /* -> Target CPU registers */
5513 GREG parm; /* Signal parameter */
5514 GREG status = 0; /* Signal status */
5515 RADR abs; /* Absolute address */
5516 U16 cpad; /* Target CPU address */
5517 BYTE order; /* SIGP order code */
5518 #if defined(_900) || defined(FEATURE_ESAME) || defined(FEATURE_HERCULES_DIAGCALLS)
5519 int cpu; /* cpu number */
5520 int set_arch = 0; /* Need to switch mode */
5521 #endif /*defined(_900) || defined(FEATURE_ESAME)*/
5522 size_t log_sigp = 0; /* Log SIGP instruction flag */
5523 char log_buf[128]; /* Log buffer */
5524 static char *ordername[] = {
5525 /* 0x00 */ "Unassigned",
5526 /* 0x01 SIGP_SENSE */ "Sense",
5527 /* 0x02 SIGP_EXTCALL */ "External call",
5528 /* 0x03 SIGP_EMERGENCY */ "Emergency signal",
5529 /* 0x04 SIGP_START */ "Start",
5530 /* 0x05 SIGP_STOP */ "Stop",
5531 /* 0x06 SIGP_RESTART */ "Restart",
5532 /* 0x07 SIGP_IPR */ "Initial program reset",
5533 /* 0x08 SIGP_PR */ "Program reset",
5534 /* 0x09 SIGP_STOPSTORE */ "Stop and store status",
5535 /* 0x0A SIGP_IMPL */ "Initial microprogram load",
5536 /* 0x0B SIGP_INITRESET */ "Initial CPU reset",
5537 /* 0x0C SIGP_RESET */ "CPU reset",
5538 /* 0x0D SIGP_SETPREFIX */ "Set prefix",
5539 /* 0x0E SIGP_STORE */ "Store status",
5540 /* 0x0F */ "Unassigned",
5541 /* 0x10 */ "Unassigned",
5542 /* 0x11 SIGP_STOREX */ "Store extended status at address",
5543 /* 0x12 SIGP_SETARCH */ "Set architecture mode",
5544 /* 0x13 SIGP_COND_EMERGENCY */ "Conditional emergency",
5545 /* 0x14 */ "Unassigned",
5546 /* 0x15 SIGP_SENSE_RUNNING_STATE */ "Sense running state"
5547 };
5548
5549 RS(inst, regs, r1, r3, b2, effective_addr2);
5550
5551 PRIV_CHECK(regs);
5552
5553 SIE_INTERCEPT(regs);
5554
5555 PTT(PTT_CL_SIG,"SIGP",regs->GR_L(r1),regs->GR_L(r3),(U32)(effective_addr2 & 0xffffffff));
5556
5557 /* Perform serialization before starting operation */
5558 PERFORM_SERIALIZATION (regs);
5559
5560 /* Load the order code from operand address bits 24-31 */
5561 order = effective_addr2 & 0xFF;
5562
5563 /* Load the target CPU address from R3 bits 16-31 */
5564 cpad = (order != SIGP_SETARCH) ? regs->GR_LHL(r3) : regs->cpuad;
5565
5566 /* Load the parameter from R1 (if R1 odd), or R1+1 (if even) */
5567 parm = (r1 & 1) ? regs->GR_L(r1) : regs->GR_L(r1+1);
5568
5569 /* Return condition code 3 if target CPU does not exist */
5570 if (cpad >= MAX_CPU)
5571 {
5572 PTT(PTT_CL_ERR,"*SIGP",regs->GR_L(r1),regs->GR_L(r3),(U32)(effective_addr2 & 0xffffffff));
5573 regs->psw.cc = 3;
5574 return;
5575 }
5576
5577 /* Issuing Sense to an offline CPU that is >= numcpu or
5578 HI_CPU is not now considered unusual especially since
5579 we have increased the default max CPU number to 8 */
5580 if (order == SIGP_SENSE && !IS_CPU_ONLINE(cpad)
5581 && cpad >= sysblk.numcpu && cpad >= HI_CPU)
5582 {
5583 PTT(PTT_CL_ERR,"*SIGP",regs->GR_L(r1),regs->GR_L(r3),(U32)(effective_addr2 & 0xffffffff));
5584 regs->psw.cc = 3;
5585 return;
5586 }
5587
5588 /* Trace SIGP unless Sense, External Call, Emergency Signal,
5589 Sense Running State,
5590 or the target CPU is configured offline */
5591 if ((order > LOG_SIGPORDER && order != SIGP_SENSE_RUNNING_STATE)
5592 || !IS_CPU_ONLINE(cpad))
5593 {
5594 log_sigp = snprintf ( log_buf, sizeof(log_buf),
5595 "CPU%4.4X: SIGP %s (%2.2X) CPU%4.4X, PARM "F_GREG,
5596 regs->cpuad,
5597 order >= sizeof(ordername) / sizeof(ordername[0]) ?
5598 "Unassigned" : ordername[order],
5599 order,
5600 cpad,
5601 parm);
5602 }
5603
5604 /* [4.9.2.1] Claim the use of the CPU signaling and response
5605 facility, and return condition code 2 if the facility is
5606 busy. The sigplock is held while the facility is in
5607 use by any CPU. */
5608 if(try_obtain_lock (&sysblk.sigplock))
5609 {
5610 regs->psw.cc = 2;
5611 if (log_sigp)
5612 logmsg("%s: CC 2\n",log_buf);
5613 return;
5614 }
5615
5616 /* Obtain the interrupt lock */
5617 OBTAIN_INTLOCK(regs);
5618
5619 /* If the cpu is not part of the configuration then return cc3
5620 Initial CPU reset may IML a processor that is currently not
5621 part of the configuration, ie configure the cpu implicitly
5622 online */
5623 if (order != SIGP_INITRESET
5624 #if defined(FEATURE_S370_CHANNEL)
5625 && order != SIGP_IMPL
5626 #endif /*defined(FEATURE_S370_CHANNEL)*/
5627 && !IS_CPU_ONLINE(cpad))
5628 {
5629 RELEASE_INTLOCK(regs);
5630 release_lock(&sysblk.sigplock);
5631 regs->psw.cc = 3;
5632 if (log_sigp)
5633 logmsg("%s: CC 3\n",log_buf);
5634 return;
5635 }
5636
5637 /* Point to the target CPU -- may be NULL if INITRESET or IMPL */
5638 tregs = sysblk.regs[cpad];
5639
5640 /* Except for the reset orders, return condition code 2 if the
5641 target CPU is executing a previous start, stop, restart,
5642 stop and store status, set prefix, or store status order */
5643 if ((order != SIGP_RESET
5644 #if defined(FEATURE_S370_CHANNEL)
5645 && order != SIGP_IMPL
5646 && order != SIGP_IPR
5647 #endif /*defined(FEATURE_S370_CHANNEL)*/
5648 && order != SIGP_INITRESET)
5649 && (tregs) && (tregs->cpustate == CPUSTATE_STOPPING
5650 || IS_IC_RESTART(tregs)))
5651 {
5652 RELEASE_INTLOCK(regs);
5653 release_lock(&sysblk.sigplock);
5654 regs->psw.cc = 2;
5655 if (log_sigp)
5656 logmsg("%s: CC 2\n",log_buf);
5657 sched_yield();
5658 return;
5659 }
5660
5661 /* The operator-intervening condition, when present, can be indicated
5662 in response to all orders, and is indicated in response to sense if
5663 it precludes the acceptance of any of the installed orders (which
5664 is always true in our case), but cannot arise as a result of a SIGP
5665 instruction executed by a CPU addressing itself.
5666 */
5667 if (1
5668 && order != SIGP_SENSE // if this isn't a sense,
5669 && cpad != regs->cpuad // and we're not addressing ourselves,
5670 && (tregs) && tregs->opinterv // and operator intervening condition...
5671 )
5672 {
5673 // ...then we cannot proceed
5674 status |= SIGP_STATUS_OPERATOR_INTERVENING;
5675 }
5676 else /* (order == SIGP_SENSE || cpad == regs->cpuad || ((tregs) && !tregs->opinterv)) */
5677 /* Process signal according to order code */
5678 switch (order)
5679 {
5680 case SIGP_SENSE:
5681 /* Set status bit 24 if external call interrupt pending */
5682 if (IS_IC_EXTCALL(tregs))
5683 status |= SIGP_STATUS_EXTERNAL_CALL_PENDING;
5684
5685 /* Set status bit 25 if target CPU is stopped */
5686 if (tregs->cpustate != CPUSTATE_STARTED)
5687 status |= SIGP_STATUS_STOPPED;
5688
5689 /* Test for checkstop state */
5690 if(tregs->checkstop)
5691 status |= SIGP_STATUS_CHECK_STOP;
5692
5693 /* Test for operator intervening state */
5694 if(cpad != regs->cpuad && tregs->opinterv)
5695 status |= SIGP_STATUS_OPERATOR_INTERVENING;
5696
5697 break;
5698
5699 case SIGP_EXTCALL:
5700 /* Test for checkstop state */
5701 if(tregs->checkstop)
5702 {
5703 status |= SIGP_STATUS_CHECK_STOP;
5704 break;
5705 }
5706
5707 /* Exit with status bit 24 set if a previous external
5708 call interrupt is still pending in the target CPU */
5709 if (IS_IC_EXTCALL(tregs))
5710 {
5711 status |= SIGP_STATUS_EXTERNAL_CALL_PENDING;
5712 break;
5713 }
5714
5715 /* Raise an external call interrupt pending condition */
5716 ON_IC_EXTCALL(tregs);
5717 tregs->extccpu = regs->cpuad;
5718
5719 break;
5720
5721 #if defined(_900) || defined(FEATURE_ESAME)
5722
5723 case SIGP_COND_EMERGENCY:
5724
5725 /* Test for checkstop state */
5726 if(tregs->checkstop)
5727 status |= SIGP_STATUS_CHECK_STOP;
5728 else
5729 {
5730 U16 check_asn = (parm & 0xFFFF);
5731
5732 SET_PSW_IA(tregs);
5733
5734 if (0
5735
5736 /* PSW disabled for external interruptions,
5737 I/O interruptions, or both */
5738 || (!(tregs->psw.sysmask & PSW_EXTMASK) ||
5739 !(tregs->psw.sysmask & PSW_IOMASK))
5740
5741 /* CPU in wait state and the PSW instruction
5742 address not zero */
5743 || ( WAITSTATE( &tregs->psw ) && tregs->psw.IA )
5744
5745 /* CPU not in wait state and check_asn value
5746 equals an ASN of the CPU (primary, secondary
5747 or both) -- regardless of the setting of PSW
5748 bits 16-17 */
5749 || (1
5750 && !WAITSTATE( &tregs->psw )
5751 && (check_asn == tregs->CR_LHL(3) ||
5752 check_asn == tregs->CR_LHL(4))
5753 )
5754 )
5755 {
5756 /* Raise an emergency signal interrupt pending condition */
5757 tregs->emercpu[regs->cpuad] = 1;
5758 ON_IC_EMERSIG(tregs);
5759 }
5760 else
5761 status |= SIGP_STATUS_INCORRECT_STATE;
5762 }
5763 break;
5764
5765 #endif /* defined(_900) || defined(FEATURE_ESAME) */
5766
5767 case SIGP_EMERGENCY:
5768 /* Test for checkstop state */
5769 if(tregs->checkstop)
5770 {
5771 status |= SIGP_STATUS_CHECK_STOP;
5772 break;
5773 }
5774
5775 /* Raise an emergency signal interrupt pending condition */
5776 ON_IC_EMERSIG(tregs);
5777 tregs->emercpu[regs->cpuad] = 1;
5778
5779 break;
5780
5781 case SIGP_START:
5782 /* Test for checkstop state */
5783 if(tregs->checkstop)
5784 {
5785 status |= SIGP_STATUS_CHECK_STOP;
5786 break;
5787 }
5788
5789 /* Restart the target CPU if it is in the stopped state */
5790 tregs->cpustate = CPUSTATE_STARTED;
5791
5792 break;
5793
5794 case SIGP_STOP:
5795 /* Test for checkstop state */
5796 if(tregs->checkstop)
5797 {
5798 status |= SIGP_STATUS_CHECK_STOP;
5799 break;
5800 }
5801
5802 /* Put the the target CPU into the stopping state */
5803 tregs->cpustate = CPUSTATE_STOPPING;
5804 ON_IC_INTERRUPT(tregs);
5805
5806 break;
5807
5808 case SIGP_RESTART:
5809 /* Test for checkstop state */
5810 if(tregs->checkstop)
5811 {
5812 status |= SIGP_STATUS_CHECK_STOP;
5813 break;
5814 }
5815
5816 /* Make restart interrupt pending in the target CPU */
5817 ON_IC_RESTART(tregs);
5818 /* Set cpustate to stopping. If the restart is successful,
5819 then the cpustate will be set to started in cpu.c */
5820 if(tregs->cpustate == CPUSTATE_STOPPED)
5821 tregs->cpustate = CPUSTATE_STOPPING;
5822
5823 break;
5824
5825 case SIGP_STOPSTORE:
5826 /* Test for checkstop state */
5827 if(tregs->checkstop)
5828 {
5829 status |= SIGP_STATUS_CHECK_STOP;
5830 break;
5831 }
5832
5833 /* Indicate store status is required when stopped */
5834 ON_IC_STORSTAT(tregs);
5835
5836 /* Put the the target CPU into the stopping state */
5837 tregs->cpustate = CPUSTATE_STOPPING;
5838 ON_IC_INTERRUPT(tregs);
5839
5840 break;
5841
5842 #if defined(FEATURE_S370_CHANNEL)
5843 case SIGP_IMPL:
5844 case SIGP_IPR:
5845 #endif /* defined(FEATURE_S370_CHANNEL) */
5846 case SIGP_INITRESET:
5847 if (!IS_CPU_ONLINE(cpad))
5848 {
5849 configure_cpu(cpad);
5850 if (!IS_CPU_ONLINE(cpad))
5851 {
5852 status |= SIGP_STATUS_OPERATOR_INTERVENING;
5853 break;
5854 }
5855 tregs = sysblk.regs[cpad];
5856 }
5857
5858 #if defined(FEATURE_S370_CHANNEL)
5859 if (order == SIGP_IMPL || order == SIGP_IPR)
5860 channelset_reset(tregs);
5861 #endif /* defined(FEATURE_S370_CHANNEL) */
5862
5863 /* Signal initial CPU reset function */
5864 tregs->sigpireset = 1;
5865 tregs->cpustate = CPUSTATE_STOPPING;
5866 ON_IC_INTERRUPT(tregs);
5867
5868 break;
5869
5870 #if defined(FEATURE_S370_CHANNEL)
5871 case SIGP_PR:
5872 channelset_reset(tregs);
5873 /* fallthrough*/
5874 #endif /* defined(FEATURE_S370_CHANNEL) */
5875 case SIGP_RESET:
5876 /* Signal CPU reset function */
5877 tregs->sigpreset = 1;
5878 tregs->cpustate = CPUSTATE_STOPPING;
5879 ON_IC_INTERRUPT(tregs);
5880
5881 break;
5882
5883 case SIGP_SETPREFIX:
5884 /* Test for checkstop state */
5885 if(tregs->checkstop)
5886 {
5887 status |= SIGP_STATUS_CHECK_STOP;
5888 break;
5889 }
5890
5891 /* Exit with operator intervening if the status is
5892 stopping, such that a retry can be attempted */
5893 if(tregs->cpustate == CPUSTATE_STOPPING)
5894 {
5895 status |= SIGP_STATUS_OPERATOR_INTERVENING;
5896 break;
5897 }
5898
5899 /* Exit with status bit 22 set if CPU is not stopped */
5900 if (tregs->cpustate != CPUSTATE_STOPPED)
5901 {
5902 status |= SIGP_STATUS_INCORRECT_STATE;
5903 break;
5904 }
5905
5906 /* Obtain new prefix from parameter register bits 1-19
5907 or bits 1-18 in ESAME mode */
5908 abs = parm & PX_MASK;
5909
5910 /* Exit with status bit 23 set if new prefix is invalid */
5911 if (abs > regs->mainlim)
5912 {
5913 status |= SIGP_STATUS_INVALID_PARAMETER;
5914 break;
5915 }
5916
5917 /* Load new value into prefix register of target CPU */
5918 tregs->PX = abs;
5919
5920 /* Set pointer to active PSA structure */
5921 tregs->psa = (PSA_3XX*)(tregs->mainstor + tregs->PX);
5922
5923 /* Invalidate the ALB and TLB of the target CPU */
5924 ARCH_DEP(purge_tlb) (tregs);
5925 #if defined(FEATURE_ACCESS_REGISTERS)
5926 ARCH_DEP(purge_alb) (tregs);
5927 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
5928
5929 /* Perform serialization and checkpoint-sync on target CPU */
5930 // perform_serialization (tregs);
5931 // perform_chkpt_sync (tregs);
5932
5933 break;
5934
5935 case SIGP_STORE:
5936 /* Test for checkstop state */
5937 if(tregs->checkstop)
5938 {
5939 status |= SIGP_STATUS_CHECK_STOP;
5940 break;
5941 }
5942
5943 /* Exit with operator intervening if the status is
5944 stopping, such that a retry can be attempted */
5945 if(tregs->cpustate == CPUSTATE_STOPPING)
5946 {
5947 status |= SIGP_STATUS_OPERATOR_INTERVENING;
5948 break;
5949 }
5950
5951 /* Exit with status bit 22 set if CPU is not stopped */
5952 if (tregs->cpustate != CPUSTATE_STOPPED)
5953 {
5954 status |= SIGP_STATUS_INCORRECT_STATE;
5955 break;
5956 }
5957
5958 /* Obtain status address from parameter register bits 1-22 */
5959 abs = parm & 0x7FFFFE00;
5960
5961 /* Exit with status bit 23 set if status address invalid */
5962 if (abs > regs->mainlim)
5963 {
5964 status |= SIGP_STATUS_INVALID_PARAMETER;
5965 break;
5966 }
5967
5968 /* Store status at specified main storage address */
5969 ARCH_DEP(store_status) (tregs, abs);
5970
5971 /* Perform serialization and checkpoint-sync on target CPU */
5972 // perform_serialization (tregs);
5973
5974 // perform_chkpt_sync (tregs);
5975
5976 break;
5977
5978 #if defined(_390)
5979 case SIGP_STOREX:
5980 {
5981 #if !defined(FEATURE_BASIC_FP_EXTENSIONS)
5982 status |= SIGP_STATUS_INVALID_ORDER;
5983 #else /* defined(FEATURE_BASIC_FP_EXTENSIONS) */
5984 RADR absx; /* abs addr of extended save area */
5985
5986 /* Test for checkstop state */
5987 if(tregs->checkstop)
5988 status |= SIGP_STATUS_CHECK_STOP;
5989
5990 /* Check if CPU is not stopped */
5991 if (tregs->cpustate != CPUSTATE_STOPPED)
5992 status |= SIGP_STATUS_INCORRECT_STATE;
5993
5994 /* Only proceed if no conditions exist to preclude
5995 the acceptance of this signal-processor order */
5996 if (!status)
5997 {
5998 /* Obtain status address from parameter register bits 1-22 */
5999 abs = parm & 0x7FFFFE00;
6000
6001 /* Exit with status bit 23 set if status address invalid */
6002 if (abs > regs->mainlim)
6003 status |= SIGP_STATUS_INVALID_PARAMETER;
6004 else
6005 {
6006 /* Fetch the address of the extended save area */
6007 absx = ARCH_DEP(fetch_fullword_absolute) (abs+212, tregs);
6008 absx &= 0x7FFFF000;
6009
6010 /* Invalid parameter if extended save area address invalid */
6011 if (absx > regs->mainlim)
6012 status |= SIGP_STATUS_INVALID_PARAMETER;
6013 else
6014 { int i; // (work)
6015
6016 /* Store status at specified main storage address */
6017 ARCH_DEP(store_status) (tregs, abs );
6018
6019 /* Store extended status at specified main storage address */
6020 for (i = 0; i < 32; i++)
6021 STORE_FW( tregs->mainstor + absx + (i*4), tregs->fpr[i] );
6022 STORE_FW( tregs->mainstor + absx + 128, tregs->fpc );
6023 STORE_FW( tregs->mainstor + absx + 132, 0 );
6024 STORE_FW( tregs->mainstor + absx + 136, 0 );
6025 STORE_FW( tregs->mainstor + absx + 140, 0 );
6026
6027 /* Perform serialization and checkpoint-sync on target CPU */
6028 // perform_serialization (tregs);
6029 // perform_chkpt_sync (tregs);
6030 }
6031 }
6032 }
6033
6034 #endif /* defined(FEATURE_BASIC_FP_EXTENSIONS) */
6035 }
6036 break;
6037 #endif /* defined(_390) */
6038
6039 #if defined(_900) || defined(FEATURE_ESAME) || defined(FEATURE_HERCULES_DIAGCALLS)
6040 case SIGP_SETARCH:
6041
6042 /* CPU must have ESAME support */
6043 if(!sysblk.arch_z900)
6044 status = SIGP_STATUS_INVALID_ORDER;
6045
6046 PERFORM_SERIALIZATION (regs);
6047 PERFORM_CHKPT_SYNC (regs);
6048
6049 for (cpu = 0; cpu < MAX_CPU; cpu++)
6050 if (IS_CPU_ONLINE(cpu)
6051 && sysblk.regs[cpu]->cpustate != CPUSTATE_STOPPED
6052 && sysblk.regs[cpu]->cpuad != regs->cpuad)
6053 status |= SIGP_STATUS_INCORRECT_STATE;
6054
6055 if(!status) {
6056 switch(parm & 0xFF) {
6057
6058 #if defined(_900) || defined(FEATURE_ESAME)
6059
6060 case 0: // from: -- z/Arch --to--> 390
6061
6062 if(sysblk.arch_mode == ARCH_390)
6063 status = SIGP_STATUS_INVALID_PARAMETER;
6064 else
6065 {
6066 sysblk.arch_mode = ARCH_390;
6067 set_arch = 1;
6068
6069 INVALIDATE_AIA(regs);
6070 regs->captured_zpsw = regs->psw;
6071 regs->psw.states |= BIT(PSW_NOTESAME_BIT);
6072 regs->PX_L &= 0x7FFFE000;
6073
6074 for (cpu = 0; cpu < MAX_CPU; cpu++)
6075 {
6076 if (IS_CPU_ONLINE(cpu) &&
6077 sysblk.regs[cpu]->cpuad != regs->cpuad)
6078 {
6079 INVALIDATE_AIA(sysblk.regs[cpu]);
6080 sysblk.regs[cpu]->captured_zpsw = sysblk.regs[cpu]->psw;
6081 sysblk.regs[cpu]->psw.states |= BIT(PSW_NOTESAME_BIT);
6082 sysblk.regs[cpu]->PX_L &= 0x7FFFE000;
6083 }
6084 }
6085 }
6086 break;
6087
6088 case 1: // from: -- 390 --to--> z/Arch
6089
6090 if(sysblk.arch_mode == ARCH_900)
6091 status = SIGP_STATUS_INVALID_PARAMETER;
6092 else
6093 {
6094 sysblk.arch_mode = ARCH_900;
6095 set_arch = 1;
6096
6097 INVALIDATE_AIA(regs);
6098 regs->psw.states &= ~BIT(PSW_NOTESAME_BIT);
6099 regs->psw.IA_H = 0;
6100 regs->PX_G &= 0x7FFFE000;
6101
6102 for (cpu = 0; cpu < MAX_CPU; cpu++)
6103 {
6104 if (IS_CPU_ONLINE(cpu) &&
6105 sysblk.regs[cpu]->cpuad != regs->cpuad)
6106 {
6107 INVALIDATE_AIA(sysblk.regs[cpu]);
6108 sysblk.regs[cpu]->psw.states &= ~BIT(PSW_NOTESAME_BIT);
6109 sysblk.regs[cpu]->psw.IA_H = 0;
6110 sysblk.regs[cpu]->PX_G &= 0x7FFFE000;
6111 }
6112 }
6113 }
6114 break;
6115
6116 case 2: // restore CAPTURED z/Arch PSW...
6117
6118 if(sysblk.arch_mode == ARCH_900)
6119 status = SIGP_STATUS_INVALID_PARAMETER;
6120 else
6121 {
6122 sysblk.arch_mode = ARCH_900;
6123 set_arch = 1;
6124
6125 INVALIDATE_AIA(regs);
6126 regs->psw.states &= ~BIT(PSW_NOTESAME_BIT);
6127 regs->psw.IA_H = 0;
6128 regs->PX_G &= 0x7FFFE000;
6129
6130 for (cpu = 0; cpu < MAX_CPU; cpu++)
6131 {
6132 if (IS_CPU_ONLINE(cpu) &&
6133 sysblk.regs[cpu]->cpuad != regs->cpuad)
6134 {
6135 INVALIDATE_AIA(sysblk.regs[cpu]);
6136 sysblk.regs[cpu]->psw = sysblk.regs[cpu]->captured_zpsw;
6137 sysblk.regs[cpu]->PX_G &= 0x7FFFE000;
6138 }
6139 }
6140 }
6141 break;
6142
6143 #endif // defined(_900) || defined(FEATURE_ESAME)
6144
6145 #if defined(FEATURE_HERCULES_DIAGCALLS)
6146
6147 case 37:
6148
6149 if(sysblk.arch_mode == ARCH_370)
6150 status = SIGP_STATUS_INVALID_PARAMETER;
6151 else
6152 {
6153 sysblk.arch_mode = ARCH_370;
6154 set_arch = 1;
6155 }
6156 break;
6157
6158 #endif /*defined(FEATURE_HERCULES_DIAGCALLS)*/
6159
6160 default:
6161 PTT(PTT_CL_ERR,"*SIGP",regs->GR_L(r1),regs->GR_L(r3),(U32)(effective_addr2 & 0xffffffff));
6162 status |= SIGP_STATUS_INVALID_PARAMETER;
6163 } /* end switch(parm & 0xFF) */
6164 } /* end if(!status) */
6165
6166 sysblk.dummyregs.arch_mode = sysblk.arch_mode;
6167 #if defined(OPTION_FISHIO)
6168 ios_arch_mode = sysblk.arch_mode;
6169 #endif // defined(OPTION_FISHIO)
6170
6171 /* Invalidate the ALB and TLB */
6172 ARCH_DEP(purge_tlb) (regs);
6173 #if defined(FEATURE_ACCESS_REGISTERS)
6174 ARCH_DEP(purge_alb) (tregs);
6175 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
6176
6177 PERFORM_SERIALIZATION (regs);
6178 PERFORM_CHKPT_SYNC (regs);
6179
6180 break;
6181 #endif /*defined(_900) || defined(FEATURE_ESAME) || defined(FEATURE_HERCULES_DIAGCALLS)*/
6182
6183 #if defined(FEATURE_SENSE_RUNNING_STATUS)
6184
6185 case SIGP_SENSE_RUNNING_STATE:
6186
6187 if (tregs->cpustate != CPUSTATE_STARTED)
6188 status = SIGP_STATUS_NOT_RUNNING;
6189
6190 break;
6191
6192 #endif /*defined(FEATURE_SENSE_RUNNING_STATUS)*/
6193
6194 default:
6195 PTT(PTT_CL_ERR,"*SIGP",regs->GR_L(r1),regs->GR_L(r3),(U32)(effective_addr2 & 0xffffffff));
6196 status = SIGP_STATUS_INVALID_ORDER;
6197 } /* end switch(order) */
6198
6199 /* Release the use of the signalling and response facility */
6200 release_lock(&sysblk.sigplock);
6201
6202 /* Wake up the target CPU */
6203 if (IS_CPU_ONLINE(cpad))
6204 WAKEUP_CPU (sysblk.regs[cpad]);
6205
6206 /* Release the interrupt lock */
6207 RELEASE_INTLOCK(regs);
6208
6209 /* If status is non-zero, load the status word into
6210 the R1 register and return condition code 1 */
6211 if (status != 0)
6212 {
6213 regs->GR_L(r1) = status;
6214 regs->psw.cc = 1;
6215 }
6216 else
6217 regs->psw.cc = 0;
6218
6219 /* Log the results if we're interested in this particular SIGP */
6220 if (log_sigp)
6221 {
6222 if (regs->psw.cc == 0)
6223 logmsg("%s: CC 0\n",log_buf);
6224 else
6225 logmsg("%s: CC 1 STATUS %8.8X\n",log_buf, (U32)status);
6226 }
6227
6228 /* Perform serialization after completing operation */
6229 PERFORM_SERIALIZATION (regs);
6230
6231 #if defined(_900) || defined(FEATURE_ESAME) || defined(FEATURE_HERCULES_DIAGCALLS)
6232 if(set_arch)
6233 {
6234 OBTAIN_INTLOCK(regs);
6235 longjmp(regs->archjmp, 0);
6236 }
6237 #endif /*defined(_900) || defined(FEATURE_ESAME)*/
6238
6239 RETURN_INTCHECK(regs);
6240
6241 }
6242
6243
6244 /*-------------------------------------------------------------------*/
6245 /* B207 STCKC - Store Clock Comparator [S] */
6246 /*-------------------------------------------------------------------*/
DEF_INST(store_clock_comparator)6247 DEF_INST(store_clock_comparator)
6248 {
6249 int b2; /* Base of effective addr */
6250 VADR effective_addr2; /* Effective address */
6251 U64 dreg; /* Clock value */
6252
6253 S(inst, regs, b2, effective_addr2);
6254
6255 PRIV_CHECK(regs);
6256
6257 DW_CHECK(effective_addr2, regs);
6258
6259 #if defined(_FEATURE_SIE)
6260 if(SIE_STATB(regs, IC3, SCKC))
6261 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
6262 #endif /*defined(_FEATURE_SIE)*/
6263
6264 /* Obtain the interrupt lock */
6265 OBTAIN_INTLOCK(regs);
6266
6267 /* Save clock comparator value */
6268 dreg = regs->clkc;
6269
6270 /* reset the clock comparator pending flag according to
6271 the setting of the tod clock */
6272 if( tod_clock(regs) > dreg )
6273 {
6274 ON_IC_CLKC(regs);
6275
6276 /* Roll back the instruction and take the
6277 timer interrupt if we have a pending CPU timer
6278 and we are enabled for such interrupts *JJ */
6279 if( OPEN_IC_CLKC(regs) )
6280 {
6281 RELEASE_INTLOCK(regs);
6282 UPD_PSW_IA(regs, PSW_IA(regs, -4));
6283 RETURN_INTCHECK(regs);
6284 }
6285 }
6286 else
6287 OFF_IC_CLKC(regs);
6288
6289 RELEASE_INTLOCK(regs);
6290
6291 /* Store clock comparator value at operand location */
6292 ARCH_DEP(vstore8) ((dreg << 8), effective_addr2, b2, regs );
6293
6294 // /*debug*/logmsg("Store clock comparator=%16.16" I64_FMT "X\n", dreg);
6295
6296 RETURN_INTCHECK(regs);
6297 }
6298
6299
6300 /*-------------------------------------------------------------------*/
6301 /* B6 STCTL - Store Control [RS] */
6302 /*-------------------------------------------------------------------*/
DEF_INST(store_control)6303 DEF_INST(store_control)
6304 {
6305 int r1, r3; /* Register numbers */
6306 int b2; /* Base of effective addr */
6307 VADR effective_addr2; /* Effective address */
6308 int i, m, n; /* Integer work areas */
6309 U32 *p1, *p2 = NULL; /* Mainstor pointers */
6310
6311 RS(inst, regs, r1, r3, b2, effective_addr2);
6312 #if defined(FEATURE_ECPSVM)
6313 if(ecpsvm_dostctl(regs,r1,r3,b2,effective_addr2)==0)
6314 {
6315 return;
6316 }
6317 #endif
6318
6319 PRIV_CHECK(regs);
6320
6321 FW_CHECK(effective_addr2, regs);
6322
6323 #if defined(_FEATURE_SIE)
6324 if(SIE_STATB(regs, IC1, STCTL))
6325 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
6326 #endif /*defined(_FEATURE_SIE)*/
6327
6328 /* Calculate number of regs to store */
6329 n = ((r3 - r1) & 0xF) + 1;
6330
6331 /* Calculate number of words to next boundary */
6332 m = (0x800 - (effective_addr2 & 0x7ff)) >> 2;
6333
6334 /* Address of operand beginning */
6335 p1 = (U32*)MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
6336
6337 /* Get address of next page if boundary crossed */
6338 if (unlikely (m < n))
6339 p2 = (U32*)MADDR(effective_addr2 + (m*4), b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
6340 else
6341 m = n;
6342
6343 /* Store at operand beginning */
6344 for (i = 0; i < m; i++)
6345 store_fw (p1++, regs->CR_L((r1 + i) & 0xF));
6346
6347 /* Store on next page */
6348 for ( ; i < n; i++)
6349 store_fw (p2++, regs->CR_L((r1 + i) & 0xF));
6350
6351 ITIMER_UPDATE(effective_addr2,(n*4)-1,regs);
6352
6353 } /* end DEF_INST(store_control) */
6354
6355
6356 /*-------------------------------------------------------------------*/
6357 /* B212 STAP - Store CPU Address [S] */
6358 /*-------------------------------------------------------------------*/
DEF_INST(store_cpu_address)6359 DEF_INST(store_cpu_address)
6360 {
6361 int b2; /* Base of effective addr */
6362 VADR effective_addr2; /* Effective address */
6363
6364 S(inst, regs, b2, effective_addr2);
6365
6366 PRIV_CHECK(regs);
6367
6368 SIE_INTERCEPT(regs);
6369
6370 ODD_CHECK(effective_addr2, regs);
6371
6372 /* Store CPU address at operand address */
6373 ARCH_DEP(vstore2) ( regs->cpuad, effective_addr2, b2, regs );
6374
6375 }
6376
6377
6378 /*-------------------------------------------------------------------*/
6379 /* B202 STIDP - Store CPU ID [S] */
6380 /*-------------------------------------------------------------------*/
DEF_INST(store_cpu_id)6381 DEF_INST(store_cpu_id)
6382 {
6383 int b2; /* Base of effective addr */
6384 VADR effective_addr2; /* Effective address */
6385 U64 dreg; /* Double word workarea */
6386
6387 S(inst, regs, b2, effective_addr2);
6388
6389 PRIV_CHECK(regs);
6390
6391 SIE_INTERCEPT(regs);
6392
6393 DW_CHECK(effective_addr2, regs);
6394
6395 /* Load the CPU ID */
6396 dreg = sysblk.cpuid;
6397
6398 /* If LPARNUM is two digits, build a format 1 CPU ID */
6399 if (sysblk.lparnuml == 2)
6400 {
6401 /* Overlay first two digits of CPU ID by LPARNUM */
6402 dreg &= 0xFF00FFFFFFFFFFFFULL;
6403 dreg |= ((U64)(sysblk.lparnum & 0xFF) << 48);
6404
6405 /* Indicate format 1 CPU ID */
6406 dreg |= 0x8000ULL;
6407 }
6408 /* If LPARNUM is one digit, build a format 0 CPU ID */
6409 else if (sysblk.lparnuml == 1)
6410 {
6411 /* Overlay first digit of CPU ID by processor id
6412 and overlay second digit of CPU ID by LPARNUM */
6413 dreg &= 0xFF00FFFFFFFFFFFFULL;
6414 dreg |= ((U64)(regs->cpuad & 0x0F) << 52)
6415 | ((U64)(sysblk.lparnum & 0x0F) << 48);
6416 }
6417 /* If LPARNUM is not specified, build basic mode CPU ID */
6418 else
6419 {
6420 /* If first digit of serial is zero, insert processor id */
6421 if ((dreg & 0x00F0000000000000ULL) == 0)
6422 dreg |= (U64)(regs->cpuad & 0x0F) << 52;
6423 }
6424
6425 #if defined(FEATURE_ESAME)
6426 /* For ESAME, set version code in CPU ID bits 0-7 to zero */
6427 dreg &= 0x00FFFFFFFFFFFFFFULL;
6428 #endif /*defined(FEATURE_ESAME)*/
6429
6430 /* Store CPU ID at operand address */
6431 ARCH_DEP(vstore8) ( dreg, effective_addr2, b2, regs );
6432
6433 }
6434
6435
6436 /*-------------------------------------------------------------------*/
6437 /* B209 STPT - Store CPU Timer [S] */
6438 /*-------------------------------------------------------------------*/
DEF_INST(store_cpu_timer)6439 DEF_INST(store_cpu_timer)
6440 {
6441 int b2; /* Base of effective addr */
6442 VADR effective_addr2; /* Effective address */
6443 S64 dreg; /* Double word workarea */
6444
6445 S(inst, regs, b2, effective_addr2);
6446
6447 PRIV_CHECK(regs);
6448
6449 DW_CHECK(effective_addr2, regs);
6450
6451 #if defined(_FEATURE_SIE)
6452 if(SIE_STATB(regs, IC3, SPT))
6453 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
6454 #endif /*defined(_FEATURE_SIE)*/
6455
6456 OBTAIN_INTLOCK(regs);
6457
6458 /* Save the CPU timer value */
6459 dreg = cpu_timer(regs);
6460
6461 /* reset the cpu timer pending flag according to its value */
6462 if( CPU_TIMER(regs) < 0 )
6463 {
6464 ON_IC_PTIMER(regs);
6465
6466 /* Roll back the instruction and take the
6467 timer interrupt if we have a pending CPU timer
6468 and we are enabled for such interrupts *JJ */
6469 if( OPEN_IC_PTIMER(regs) )
6470 {
6471 RELEASE_INTLOCK(regs);
6472 UPD_PSW_IA(regs, PSW_IA(regs, -4));
6473 RETURN_INTCHECK(regs);
6474 }
6475 }
6476 else
6477 OFF_IC_PTIMER(regs);
6478
6479 RELEASE_INTLOCK(regs);
6480
6481 /* Store CPU timer value at operand location */
6482 ARCH_DEP(vstore8) ( dreg, effective_addr2, b2, regs );
6483
6484 // /*debug*/logmsg("Store CPU timer=%16.16" I64_FMT "X\n", dreg);
6485
6486 RETURN_INTCHECK(regs);
6487 }
6488
6489
6490 /*-------------------------------------------------------------------*/
6491 /* B211 STPX - Store Prefix [S] */
6492 /*-------------------------------------------------------------------*/
DEF_INST(store_prefix)6493 DEF_INST(store_prefix)
6494 {
6495 int b2; /* Base of effective addr */
6496 VADR effective_addr2; /* Effective address */
6497
6498 S(inst, regs, b2, effective_addr2);
6499
6500 PRIV_CHECK(regs);
6501
6502 SIE_INTERCEPT(regs);
6503
6504 FW_CHECK(effective_addr2, regs);
6505
6506 /* Store prefix register at operand address */
6507 ARCH_DEP(vstore4) ( regs->PX, effective_addr2, b2, regs );
6508
6509 }
6510
6511
6512 /*-------------------------------------------------------------------*/
6513 /* Calculate CPU capability indicator for STSI instruction */
6514 /* */
6515 /* The CPU capability indicator is 32-bit value which is calculated */
6516 /* dynamically. A lower value indicates a faster CPU. The value may */
6517 /* be either an unsigned binary integer or a floating point number. */
6518 /* If bits 0-8 are zero, it is an integer in the range 0 to 2**23-1. */
6519 /* If bits 0-8 are nonzero, is is a 32-bit short BFP number. */
6520 /*-------------------------------------------------------------------*/
6521 #if !defined(_STSI_CAPABILITY)
6522 #define _STSI_CAPABILITY
stsi_capability(REGS * regs)6523 static inline U32 stsi_capability (REGS *regs)
6524 {
6525 U64 dreg; /* work doubleword */
6526 struct rusage usage; /* RMF type data */
6527
6528 #define SUSEC_PER_MIPS 48 /* One MIPS eq 48 SU */
6529
6530 getrusage(RUSAGE_SELF,&usage);
6531 dreg = (U64)(usage.ru_utime.tv_sec + usage.ru_stime.tv_sec);
6532 dreg = (dreg * 1000000) + (usage.ru_utime.tv_usec + usage.ru_stime.tv_usec);
6533 dreg = INSTCOUNT(regs) / (dreg ? dreg : 1);
6534 dreg *= SUSEC_PER_MIPS;
6535 return 0x800000 / (dreg ? dreg : 1);
6536
6537 } /* end function stsi_capability */
6538 #endif /*!defined(_STSI_CAPABILITY)*/
6539
6540
6541 #ifdef FEATURE_STORE_SYSTEM_INFORMATION
6542 /*-------------------------------------------------------------------*/
6543 /* B27D STSI - Store System Information [S] */
6544 /*-------------------------------------------------------------------*/
DEF_INST(store_system_information)6545 DEF_INST(store_system_information)
6546 {
6547 int b2; /* Base of effective addr */
6548 VADR effective_addr2; /* Effective address */
6549 BYTE *m; /* Mainstor address */
6550 int i;
6551 U16 offset; /* Offset into control block */
6552 SYSIB111 *sysib111; /* Basic machine conf */
6553 SYSIB121 *sysib121; /* Basic machine CPU */
6554 SYSIB122 *sysib122; /* Basic machine CPUs */
6555 SYSIB221 *sysib221; /* LPAR CPU */
6556 SYSIB222 *sysib222; /* LPAR CPUs */
6557 #if 0
6558 SYSIB322 *sysib322; /* VM CPUs */
6559 SYSIBVMDB *sysib322; /* VM description block */
6560 #endif
6561 #if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
6562 SYSIB1512 *sysib1512; /* Configuration Topology */
6563 BYTE *tle; /* Pointer to next TLE */
6564 TLECNTNR *tlecntnr; /* Container TLE pointer */
6565 TLECPU *tlecpu; /* CPU TLE Type */
6566 U64 cpumask; /* work */
6567 int cputype; /* work */
6568 U16 cpuad; /* CPU address */
6569 BYTE cntnrid; /* Container ID */
6570 #endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
6571
6572 /* "0 1 2 3 4 5 6 7" */
6573 static BYTE hexebcdic[16] = { 0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,
6574 /* "8 9 A B C D E F" */
6575 0xF8,0xF9,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6 };
6576
6577 #define STSI_CAPABILITY stsi_capability(regs)
6578
6579 S(inst, regs, b2, effective_addr2);
6580
6581 PRIV_CHECK(regs);
6582
6583 SIE_INTERCEPT(regs);
6584
6585 PTT(PTT_CL_INF,"STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6586
6587 #if defined(DEBUG_STSI)
6588 logmsg("control.c: STSI %d.%d.%d ia="F_VADR" sysib="F_VADR"\n",
6589 (regs->GR_L(0) & STSI_GPR0_FC_MASK) >> 28,
6590 regs->GR_L(0) & STSI_GPR0_SEL1_MASK,
6591 regs->GR_L(1) & STSI_GPR1_SEL2_MASK,
6592 PSW_IA(regs,-4),
6593 effective_addr2);
6594 #endif /*DEBUG_STSI*/
6595
6596 /* Check function code */
6597 if((regs->GR_L(0) & STSI_GPR0_FC_MASK) > STSI_GPR0_FC_LPAR
6598 #if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
6599 && (regs->GR_L(0) & STSI_GPR0_FC_MASK) != STSI_GPR0_FC_CURRINFO
6600 #endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
6601 )
6602 {
6603 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6604 #ifdef DEBUG_STSI
6605 logmsg("control.c: STSI cc=3 function code invalid\n");
6606 #endif /*DEBUG_STSI*/
6607 regs->psw.cc = 3;
6608 return;
6609 }
6610
6611 /* Program check if reserved bits not zero */
6612 if(regs->GR_L(0) & STSI_GPR0_RESERVED
6613 || regs->GR_L(1) & STSI_GPR1_RESERVED)
6614 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
6615
6616 /* Return current level if function code is zero */
6617 if((regs->GR_L(0) & STSI_GPR0_FC_MASK) == STSI_GPR0_FC_CURRNUM)
6618 {
6619 regs->GR_L(0) |= STSI_GPR0_FC_LPAR;
6620 #ifdef DEBUG_STSI
6621 logmsg("control.c: STSI cc=0 R0=%8.8X\n", regs->GR_L(0));
6622 #endif /*DEBUG_STSI*/
6623 regs->psw.cc = 0;
6624 return;
6625 }
6626
6627 /* Program check if operand not on a page boundary */
6628 if ( effective_addr2 & 0x00000FFF )
6629 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
6630
6631 /* Return with cc3 if selector codes invalid */
6632 /*
6633 Func-
6634 tion Selec- Selec-
6635 Code tor 1 tor 2 Information Requested about
6636 ---- ----- ----- ----------------------------
6637
6638 1 1 1 Basic-machine configuration
6639 1 2 1 Basic-machine CPU
6640 1 2 2 Basic-machine CPUs
6641
6642 2 2 1 Logical-partition CPU
6643 2 2 2 Logical-partition CPUs
6644
6645 3 2 2 Virtual-machine CPUs
6646
6647 15 1 2 Topology information of current configuration
6648 */
6649 if (0
6650 || ((regs->GR_L(0) & STSI_GPR0_FC_MASK) == STSI_GPR0_FC_BASIC
6651 && (0
6652 || (regs->GR_L(0) & STSI_GPR0_SEL1_MASK) == 0
6653 || (regs->GR_L(0) & STSI_GPR0_SEL1_MASK) > 2
6654 || (regs->GR_L(1) & STSI_GPR1_SEL2_MASK) == 0
6655 || (regs->GR_L(1) & STSI_GPR1_SEL2_MASK) > 2
6656 )
6657 )
6658 || ((regs->GR_L(0) & STSI_GPR0_FC_MASK) == STSI_GPR0_FC_LPAR
6659 && (0
6660 || (regs->GR_L(0) & STSI_GPR0_SEL1_MASK) != 2
6661 || (regs->GR_L(1) & STSI_GPR1_SEL2_MASK) == 0
6662 || (regs->GR_L(1) & STSI_GPR1_SEL2_MASK) > 2
6663 )
6664 )
6665 || ((regs->GR_L(0) & STSI_GPR0_FC_MASK) == STSI_GPR0_FC_VM
6666 && (0
6667 || (regs->GR_L(0) & STSI_GPR0_SEL1_MASK) != 2
6668 || (regs->GR_L(1) & STSI_GPR1_SEL2_MASK) != 2
6669 )
6670 )
6671 #if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
6672 || ((regs->GR_L(0) & STSI_GPR0_FC_MASK) == STSI_GPR0_FC_CURRINFO
6673 && (0
6674 || (regs->GR_L(0) & STSI_GPR0_SEL1_MASK) != 1
6675 || (regs->GR_L(1) & STSI_GPR1_SEL2_MASK) != 2
6676 )
6677 )
6678 #endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
6679 )
6680 {
6681 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6682 #ifdef DEBUG_STSI
6683 logmsg("control.c: STSI cc=3 selector codes invalid\n");
6684 #endif /*DEBUG_STSI*/
6685 regs->psw.cc = 3;
6686 return;
6687 }
6688
6689 switch(regs->GR_L(0) & STSI_GPR0_FC_MASK) {
6690
6691 case STSI_GPR0_FC_BASIC:
6692
6693 /* The statement below was relocated from immediately @PJJ */
6694 /* prior to the switch statement above, and copied to @PJJ */
6695 /* become the 1st statement in each of the 3 cases in @PJJ */
6696 /* this switch, in order to avoid a possible access @PJJ */
6697 /* exception on the system information block addres @PJJ */
6698 /* (e.g. non-page boundary) in case CC=3 results from @PJJ */
6699 /* the switch default statement. The IBM Principles @PJJ */
6700 /* of Operation explicitly state CC=3 has the higher @PJJ */
6701 /* priority than such exception. @PJJ */
6702 /* (Such access exception actually did occur for SUSE @PJJ */
6703 /* SLES 12 under z/VM, causing a disabled wait very @PJJ */
6704 /* early on in its IPL process.) @PJJ */
6705 /* (Hercules 4.00 was subsequently discovered to have @PJJ */
6706 /* this fix already implemented.) @PJJ */
6707 /* (P.J.Jansen, October 2015) @PJJ */
6708
6709 /* Obtain absolute address of main storage block,
6710 check protection, and set reference and change bits */
6711 m = MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
6712
6713 switch(regs->GR_L(0) & STSI_GPR0_SEL1_MASK) {
6714
6715 case 1:
6716
6717 switch(regs->GR_L(1) & STSI_GPR1_SEL2_MASK) {
6718
6719 case 1:
6720 /* Basic-machine configuration */
6721 sysib111 = (SYSIB111*)(m);
6722 memset(sysib111, 0x00, MAX(sizeof(SYSIB111),64*4));
6723 sysib111->flag1 |= SYSIB111_PFLAG;
6724 get_manufacturer(sysib111->manufact);
6725 get_model(sysib111->model);
6726 for(i = 0; i < 4; i++)
6727 sysib111->type[i] =
6728 hexebcdic[(sysblk.cpuid >> (28 - (i*4))) & 0x0F];
6729 get_modelcapa(sysib111->modcapaid);
6730 if (sysib111->modcapaid[0] == '\0')
6731 memcpy(sysib111->modcapaid, sysib111->model, sizeof(sysib111->model));
6732 get_modelperm(sysib111->mpci);
6733 get_modeltemp(sysib111->mtci);
6734 memset(sysib111->seqc,0xF0,sizeof(sysib111->seqc));
6735 for(i = 0; i < 6; i++)
6736 sysib111->seqc[(sizeof(sysib111->seqc) - 6) + i] =
6737 hexebcdic[(sysblk.cpuid >> (52 - (i*4))) & 0x0F];
6738 get_plant(sysib111->plant);
6739 STORE_FW(sysib111->mcaprating, STSI_CAPABILITY);
6740 STORE_FW(sysib111->mpcaprating, STSI_CAPABILITY);
6741 STORE_FW(sysib111->mtcaprating, STSI_CAPABILITY);
6742 for(i=0;i<5;i++)
6743 {
6744 sysib111->typepct[i] = 100;
6745 }
6746 regs->psw.cc = 0;
6747 break;
6748
6749 default:
6750 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6751 regs->psw.cc = 3;
6752 } /* selector 2 */
6753 break;
6754
6755 case 2:
6756
6757 switch(regs->GR_L(1) & STSI_GPR1_SEL2_MASK) {
6758
6759 case 1:
6760 /* Basic-machine Current CPU */
6761 sysib121 = (SYSIB121*)(m);
6762 memset(sysib121, 0x00, MAX(sizeof(SYSIB121),64*4));
6763 memset(sysib121->seqc,0xF0,sizeof(sysib121->seqc));
6764 for(i = 0; i < 6; i++)
6765 sysib121->seqc[(sizeof(sysib121->seqc) - 6) + i] =
6766 hexebcdic[sysblk.cpuid >> (52 - (i*4)) & 0x0F];
6767 get_plant(sysib121->plant);
6768 STORE_HW(sysib121->cpuad,regs->cpuad);
6769 regs->psw.cc = 0;
6770 break;
6771
6772 case 2:
6773 /* Basic-machine All CPUs */
6774 sysib122 = (SYSIB122*)(m);
6775 memset(sysib122, 0x00, MAX(sizeof(SYSIB122),64*4));
6776 sysib122->format = 1;
6777 offset = (U16)(sysib122->accap - (BYTE*)sysib122);
6778 STORE_HW(sysib122->accoff, offset);
6779 STORE_FW(sysib122->sccap, STSI_CAPABILITY);
6780 STORE_FW(sysib122->cap, STSI_CAPABILITY);
6781 STORE_HW(sysib122->totcpu, MAX_CPU);
6782 STORE_HW(sysib122->confcpu, sysblk.cpus);
6783 STORE_HW(sysib122->sbcpu, MAX_CPU - sysblk.cpus);
6784 get_mpfactors((BYTE*)sysib122->mpfact);
6785 STORE_FW(sysib122->accap, STSI_CAPABILITY);
6786 get_mpfactors((BYTE*)sysib122->ampfact);
6787 regs->psw.cc = 0;
6788 break;
6789
6790 default:
6791 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6792 regs->psw.cc = 3;
6793 } /* selector 2 */
6794 break;
6795
6796 default:
6797 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6798 regs->psw.cc = 3;
6799 } /* selector 1 */
6800 break;
6801
6802 case STSI_GPR0_FC_LPAR:
6803
6804 /* Obtain absolute address of main storage block,
6805 check protection, and set reference and change bits */
6806 m = MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
6807
6808 switch(regs->GR_L(0) & STSI_GPR0_SEL1_MASK) {
6809
6810 case 2:
6811
6812 switch(regs->GR_L(1) & STSI_GPR1_SEL2_MASK) {
6813
6814 case 1:
6815 /* Logical-partition Current CPU */
6816 sysib221 = (SYSIB221 *)(m);
6817 memset(sysib221, 0x00, MAX(sizeof(SYSIB221),64*4));
6818 memset(sysib221->seqc,0xF0,sizeof(sysib111->seqc));
6819 for(i = 0; i < 6; i++)
6820 sysib221->seqc[(sizeof(sysib221->seqc) - 6) + i] =
6821 hexebcdic[(sysblk.cpuid >> (52 - (i*4))) & 0x0F];
6822 get_plant(sysib221->plant);
6823 STORE_HW(sysib221->lcpuid,regs->cpuad);
6824 STORE_HW(sysib221->cpuad,regs->cpuad);
6825 regs->psw.cc = 0;
6826 break;
6827
6828 case 2:
6829 /* Logical-partition All CPUs */
6830 sysib222 = (SYSIB222 *)(m);
6831 memset(sysib222, 0x00, MAX(sizeof(SYSIB222),64*4));
6832 STORE_HW(sysib222->lparnum,1);
6833 sysib222->lcpuc = SYSIB222_LCPUC_SHARED;
6834 STORE_HW(sysib222->totcpu,MAX_CPU);
6835 STORE_HW(sysib222->confcpu,sysblk.cpus);
6836 STORE_HW(sysib222->sbcpu,MAX_CPU - sysblk.cpus);
6837 get_lparname(sysib222->lparname);
6838 STORE_FW(sysib222->lparcaf,1000); /* Full capability factor */
6839 STORE_FW(sysib222->mdep[0],1000); /* ZZ nonzero value */
6840 STORE_FW(sysib222->mdep[1],1000); /* ZZ nonzero value */
6841 STORE_HW(sysib222->shrcpu,sysblk.cpus);
6842 regs->psw.cc = 0;
6843 break;
6844
6845 default:
6846 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6847 regs->psw.cc = 3;
6848 } /* selector 2 */
6849 break;
6850
6851 default:
6852 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6853 regs->psw.cc = 3;
6854 } /* selector 1 */
6855 break;
6856
6857 #if defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)
6858 case STSI_GPR0_FC_CURRINFO:
6859
6860 /* Obtain absolute address of main storage block,
6861 check protection, and set reference and change bits */
6862 m = MADDR(effective_addr2, b2, regs, ACCTYPE_WRITE, regs->psw.pkey);
6863
6864 switch(regs->GR_L(0) & STSI_GPR0_SEL1_MASK) {
6865
6866 case 1:
6867
6868 switch(regs->GR_L(1) & STSI_GPR1_SEL2_MASK) {
6869
6870 case 2:
6871 /* Topology information of current configuration */
6872 sysib1512 = (SYSIB1512 *)(m);
6873 memset(sysib1512, 0x00, sizeof(SYSIB1512));
6874
6875 sysib1512->mnest = 2;
6876 sysib1512->mag[4] = 1; /*added by PaoloG 25-10-13*/
6877 sysib1512->mag[5] = MAX_CPU;
6878
6879 tle = sysib1512->tles;
6880 cntnrid = 1;
6881 cpuad = 0;
6882
6883 /* Build a container TLE */
6884 tlecntnr = (TLECNTNR *)tle;
6885 memset(tlecntnr, 0x00, sizeof(TLECNTNR));
6886 tlecntnr->nl = 1;
6887 tlecntnr->cntnrid = cntnrid;
6888 tle += sizeof(TLECNTNR);
6889
6890 /* For each type of CPU */
6891 for (cputype = 0; cputype <= SCCB_PTYP_MAX; cputype++)
6892 {
6893 tlecpu = (TLECPU *)tle;
6894
6895 /* For each CPU of this type */
6896 cpumask = 0;
6897 for (i=0; i < sysblk.hicpu; i++)
6898 {
6899 if (1
6900 && sysblk.regs[i]
6901 && sysblk.regs[i]->configured
6902 && sysblk.ptyp[i] == cputype
6903 )
6904 {
6905 /* Initialize new TLE for this type */
6906 if (!cpumask)
6907 {
6908 memset(tlecpu, 0x00, sizeof(TLECPU));
6909 tlecpu->nl = 0;
6910 if (sysblk.topology == TOPOLOGY_VERT) {
6911 tlecpu->flags = CPUTLE_FLAG_VERTMED;
6912 } else {
6913 tlecpu->flags = CPUTLE_FLAG_HORIZ;
6914 }
6915 tlecpu->cpuadorg = cpuad;
6916 tlecpu->cputype = cputype;
6917 }
6918 /* Update CPU mask field for this type */
6919 cpumask |= 0x8000000000000000ULL >> sysblk.regs[i]->cpuad;
6920 }
6921 }
6922 /* Bump to next TLE */
6923 if (cpumask)
6924 {
6925 STORE_DW( &tlecpu->cpumask, cpumask );
6926 tle += sizeof(TLECPU);
6927 }
6928 }
6929
6930 /* Save the length of this System Information Block */
6931 STORE_HW(sysib1512->len,(U16)(tle - (BYTE*)sysib1512));
6932
6933 /* Successful completion */
6934 regs->psw.cc = 0;
6935
6936 /* Clear topology-change-report-pending condition */
6937 OBTAIN_INTLOCK(regs);
6938 sysblk.topchnge = 0;
6939 RELEASE_INTLOCK(regs);
6940 break;
6941
6942 default:
6943 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6944 regs->psw.cc = 3;
6945 } /* selector 2 */
6946 break;
6947
6948 default:
6949 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6950 regs->psw.cc = 3;
6951 } /* selector 1 */
6952 break;
6953 #endif /*defined(FEATURE_CONFIGURATION_TOPOLOGY_FACILITY)*/
6954
6955 default:
6956 PTT(PTT_CL_ERR,"*STSI",regs->GR_L(0),regs->GR_L(1),(U32)(effective_addr2 & 0xffffffff));
6957 regs->psw.cc = 3;
6958 } /* function code */
6959
6960 #ifdef DEBUG_STSI
6961 /* Display results of STSI */
6962 logmsg("control.c: STSI cc=%d\n", regs->psw.cc);
6963 for (i=0; i<256; i+=16, m+=16) {
6964 BYTE c, s[17]; int j;
6965 for (j=0; j<16; j++) {
6966 c = guest_to_host(m[j]);
6967 s[j] = isprint(c) ? c : '.';
6968 }
6969 s[j] = '\0';
6970 logmsg("+%2.2X %2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X "
6971 "%2.2X%2.2X%2.2X%2.2X %2.2X%2.2X%2.2X%2.2X *%s*\n",
6972 i,m[0],m[1],m[2],m[3],m[4],m[5],m[6],m[7],
6973 m[8],m[9],m[10],m[11],m[12],m[13],m[14],m[15],s);
6974 }
6975 #endif /*DEBUG_STSI*/
6976
6977 } /* end DEF_INST(store_system_information) */
6978 #endif /*FEATURE_STORE_SYSTEM_INFORMATION*/
6979
6980
6981 /*-------------------------------------------------------------------*/
6982 /* AC STNSM - Store Then And Systen Mask [SI] */
6983 /*-------------------------------------------------------------------*/
DEF_INST(store_then_and_system_mask)6984 DEF_INST(store_then_and_system_mask)
6985 {
6986 BYTE i2; /* Immediate byte of opcode */
6987 int b1; /* Base of effective addr */
6988 VADR effective_addr1; /* Effective address */
6989
6990 SI(inst, regs, i2, b1, effective_addr1);
6991 #ifdef FEATURE_ECPSVM
6992 if(ecpsvm_dostnsm(regs,b1,effective_addr1,i2)==0)
6993 {
6994 return;
6995 }
6996 #endif
6997
6998 PRIV_CHECK(regs);
6999
7000 #if defined(_FEATURE_SIE)
7001 if(SIE_STATB(regs, IC1, STNSM))
7002 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
7003 #endif /*defined(_FEATURE_SIE)*/
7004
7005 /* Store current system mask value into storage operand */
7006 ARCH_DEP(vstoreb) ( regs->psw.sysmask, effective_addr1, b1, regs );
7007
7008 /* AND system mask with immediate operand */
7009 regs->psw.sysmask &= i2;
7010
7011 SET_IC_MASK(regs);
7012 TEST_SET_AEA_MODE(regs);
7013
7014 RETURN_INTCHECK(regs);
7015
7016 } /* end DEF_INST(store_then_and_system_mask) */
7017
7018
7019 /*-------------------------------------------------------------------*/
7020 /* AD STOSM - Store Then Or Systen Mask [SI] */
7021 /*-------------------------------------------------------------------*/
DEF_INST(store_then_or_system_mask)7022 DEF_INST(store_then_or_system_mask)
7023 {
7024 BYTE i2; /* Immediate byte of opcode */
7025 int b1; /* Base of effective addr */
7026 VADR effective_addr1; /* Effective address */
7027
7028 SI(inst, regs, i2, b1, effective_addr1);
7029
7030 #ifdef FEATURE_ECPSVM
7031 if(ecpsvm_dostosm(regs,b1,effective_addr1,i2)==0)
7032 {
7033 return;
7034 }
7035 #endif
7036
7037 PRIV_CHECK(regs);
7038
7039 #if defined(_FEATURE_SIE)
7040 if(SIE_STATB(regs, IC1, STOSM))
7041 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
7042 #endif /*defined(_FEATURE_SIE)*/
7043
7044 /* Store current system mask value into storage operand */
7045 ARCH_DEP(vstoreb) ( regs->psw.sysmask, effective_addr1, b1, regs );
7046
7047 /* OR system mask with immediate operand */
7048 regs->psw.sysmask |= i2;
7049
7050 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
7051 /* DAT must be off in XC mode */
7052 if(SIE_STATB(regs, MX, XC)
7053 && (regs->psw.sysmask & PSW_DATMODE) )
7054 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
7055 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
7056
7057 /* For ECMODE, bits 0 and 2-4 of system mask must be zero */
7058 if (
7059 #if defined(FEATURE_BCMODE)
7060 ECMODE(®s->psw) &&
7061 #endif /*defined(FEATURE_BCMODE)*/
7062 (regs->psw.sysmask & 0xB8) != 0)
7063 ARCH_DEP(program_interrupt) (regs, PGM_SPECIFICATION_EXCEPTION);
7064
7065 SET_IC_MASK(regs);
7066 TEST_SET_AEA_MODE(regs);
7067
7068 RETURN_INTCHECK(regs);
7069
7070 } /* end DEF_INST(store_then_or_system_mask) */
7071
7072
7073 /*-------------------------------------------------------------------*/
7074 /* B246 STURA - Store Using Real Address [RRE] */
7075 /*-------------------------------------------------------------------*/
DEF_INST(store_using_real_address)7076 DEF_INST(store_using_real_address)
7077 {
7078 int r1, r2; /* Values of R fields */
7079 RADR n; /* Unsigned work */
7080
7081 RRE(inst, regs, r1, r2);
7082
7083 PRIV_CHECK(regs);
7084
7085 /* R2 register contains operand real storage address */
7086 n = regs->GR(r2) & ADDRESS_MAXWRAP(regs);
7087
7088 /* Program check if operand not on fullword boundary */
7089 FW_CHECK(n, regs);
7090
7091 /* Store R1 register at second operand location */
7092 ARCH_DEP(vstore4) (regs->GR_L(r1), n, USE_REAL_ADDR, regs );
7093
7094 #if defined(FEATURE_PER2)
7095 /* Storage alteration must be enabled for STURA to be recognised */
7096 if( EN_IC_PER_SA(regs) && EN_IC_PER_STURA(regs) )
7097 {
7098 ON_IC_PER_SA(regs) ;
7099 ON_IC_PER_STURA(regs) ;
7100 regs->perc &= 0xFFFC; /* zero STD ID part of PER code */
7101 }
7102 #endif /*defined(FEATURE_PER2)*/
7103
7104 } /* end DEF_INST(store_using_real_address) */
7105
7106
7107 #if defined(FEATURE_ACCESS_REGISTERS)
7108 /*-------------------------------------------------------------------*/
7109 /* B24C TAR - Test Access [RRE] */
7110 /*-------------------------------------------------------------------*/
DEF_INST(test_access)7111 DEF_INST(test_access)
7112 {
7113 int r1, r2; /* Values of R fields */
7114 U32 asteo; /* Real address of ASTE */
7115 U32 aste[16]; /* ASN second table entry */
7116
7117 RRE(inst, regs, r1, r2);
7118
7119 /* Program check if ASF control bit is zero */
7120 if (!ASF_ENABLED(regs))
7121 ARCH_DEP(program_interrupt) (regs, PGM_SPECIAL_OPERATION_EXCEPTION);
7122
7123 /* Set condition code 0 if ALET value is 0 */
7124 if (regs->AR(r1) == ALET_PRIMARY)
7125 {
7126 regs->psw.cc = 0;
7127 return;
7128 }
7129
7130 /* Set condition code 3 if ALET value is 1 */
7131 if (regs->AR(r1) == ALET_SECONDARY)
7132 {
7133 regs->psw.cc = 3;
7134 return;
7135 }
7136
7137 /* Perform ALET translation using EAX value from register
7138 R2 bits 0-15, and set condition code 3 if exception */
7139 if (ARCH_DEP(translate_alet) (regs->AR(r1), regs->GR_LHH(r2),
7140 ACCTYPE_TAR,
7141 #if defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)
7142 SIE_STATB(regs, MX, XC) ? regs->hostregs :
7143 #endif /*defined(FEATURE_MULTIPLE_CONTROLLED_DATA_SPACE)*/
7144 regs,
7145 &asteo, aste))
7146 {
7147 regs->psw.cc = 3;
7148 return;
7149 }
7150
7151 /* Set condition code 1 or 2 according to whether
7152 the ALET designates the DUCT or the PASTE */
7153 regs->psw.cc = (regs->AR(r1) & ALET_PRI_LIST) ? 2 : 1;
7154
7155 }
7156 #endif /*defined(FEATURE_ACCESS_REGISTERS)*/
7157
7158
7159 #if defined(FEATURE_TEST_BLOCK)
7160 /*-------------------------------------------------------------------*/
7161 /* B22C TB - Test Block [RRE] */
7162 /*-------------------------------------------------------------------*/
DEF_INST(test_block)7163 DEF_INST(test_block)
7164 {
7165 int r1, r2; /* Values of R fields */
7166 RADR n; /* Real address */
7167
7168 RRE(inst, regs, r1, r2);
7169
7170 PRIV_CHECK(regs);
7171
7172 #if defined(FEATURE_REGION_RELOCATE)
7173 if(SIE_STATNB(regs, MX, RRF) && !regs->sie_pref)
7174 #endif
7175 SIE_INTERCEPT(regs);
7176
7177 /* Load 4K block address from R2 register */
7178 n = regs->GR(r2) & ADDRESS_MAXWRAP_E(regs);
7179 n &= XSTORE_PAGEMASK; /* 4K boundary */
7180
7181 /* Perform serialization */
7182 PERFORM_SERIALIZATION (regs);
7183
7184 /* Addressing exception if block is outside main storage */
7185 if ( n > regs->mainlim )
7186 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
7187
7188 /* Protection exception if low-address protection is set */
7189 if (ARCH_DEP(is_low_address_protected) (n, regs))
7190 {
7191 #ifdef FEATURE_SUPPRESSION_ON_PROTECTION
7192 regs->TEA = (n & STORAGE_KEY_PAGEMASK);
7193 regs->excarid = 0;
7194 #endif /*FEATURE_SUPPRESSION_ON_PROTECTION*/
7195 ARCH_DEP(program_interrupt) (regs, PGM_PROTECTION_EXCEPTION);
7196 }
7197
7198 /* Convert real address to absolute address */
7199 n = APPLY_PREFIXING (n, regs->PX);
7200
7201 /* Clear the 4K block to zeroes */
7202 memset (regs->mainstor + n, 0x00, PAGEFRAME_PAGESIZE);
7203
7204 /* Set condition code 0 if storage usable, 1 if unusable */
7205 if (STORAGE_KEY(n, regs) & STORKEY_BADFRM)
7206 regs->psw.cc = 1;
7207 else
7208 regs->psw.cc = 0;
7209
7210 /* Perform serialization */
7211 PERFORM_SERIALIZATION (regs);
7212
7213 /* Clear general register 0 */
7214 SET_GR_A(0, regs, 0);
7215
7216 }
7217 #endif /*defined(FEATURE_TEST_BLOCK)*/
7218
7219
7220 /*-------------------------------------------------------------------*/
7221 /* E501 TPROT - Test Protection [SSE] */
7222 /*-------------------------------------------------------------------*/
DEF_INST(test_protection)7223 DEF_INST(test_protection)
7224 {
7225 int b1, b2; /* Values of base registers */
7226 VADR effective_addr1,
7227 effective_addr2; /* Effective addresses */
7228 RADR aaddr; /* Absolute address */
7229 BYTE skey; /* Storage key */
7230 BYTE akey; /* Access key */
7231
7232 SSE(inst, regs, b1, effective_addr1, b2, effective_addr2);
7233
7234 PRIV_CHECK(regs);
7235
7236 #if defined(_FEATURE_SIE)
7237 if(SIE_STATB(regs, IC2, TPROT))
7238 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
7239 #endif /*defined(_FEATURE_SIE)*/
7240
7241 /* Convert logical address to real address */
7242 if (REAL_MODE(®s->psw))
7243 {
7244 regs->dat.protect = 0;
7245 regs->dat.raddr = effective_addr1;
7246 }
7247 else
7248 {
7249 /* Return condition code 3 if translation exception */
7250 if (ARCH_DEP(translate_addr) (effective_addr1, b1, regs, ACCTYPE_TPROT))
7251 {
7252 regs->psw.cc = 3;
7253 return;
7254 }
7255 }
7256
7257 /* Convert real address to absolute address */
7258 aaddr = APPLY_PREFIXING (regs->dat.raddr, regs->PX);
7259
7260 /* Program check if absolute address is outside main storage */
7261 if (aaddr > regs->mainlim)
7262 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
7263
7264 #if defined(_FEATURE_SIE)
7265 if(SIE_MODE(regs) && !regs->sie_pref)
7266 {
7267 /* Under SIE TPROT also indicates if the host is using
7268 page protection */
7269 /* Translate to real address - eventually using an access
7270 register if the guest is in XC mode */
7271 if (SIE_TRANSLATE_ADDR (regs->sie_mso + aaddr,
7272 b1>0 &&
7273 MULTIPLE_CONTROLLED_DATA_SPACE(regs) ?
7274 b1 : USE_PRIMARY_SPACE,
7275 regs->hostregs, ACCTYPE_SIE))
7276 longjmp(regs->progjmp, SIE_INTERCEPT_INST);
7277
7278 /* Convert host real address to host absolute address */
7279 aaddr = APPLY_PREFIXING (regs->hostregs->dat.raddr, regs->hostregs->PX);
7280
7281 if (aaddr > regs->hostregs->mainlim)
7282 ARCH_DEP(program_interrupt) (regs, PGM_ADDRESSING_EXCEPTION);
7283 }
7284 #endif /*defined(_FEATURE_SIE)*/
7285
7286 /* Load access key from operand 2 address bits 24-27 */
7287 akey = effective_addr2 & 0xF0;
7288
7289 /* Load the storage key for the absolute address */
7290 skey = STORAGE_KEY(aaddr, regs);
7291
7292 /* Return condition code 2 if location is fetch protected */
7293 if (ARCH_DEP(is_fetch_protected) (effective_addr1, skey, akey, regs))
7294 regs->psw.cc = 2;
7295 else
7296 /* Return condition code 1 if location is store protected */
7297 if (ARCH_DEP(is_store_protected) (effective_addr1, skey, akey, regs))
7298 regs->psw.cc = 1;
7299 else
7300 /* Return condition code 0 if location is not protected */
7301 regs->psw.cc = 0;
7302
7303 }
7304
7305
7306 #if defined(FEATURE_TRACING)
7307 /*-------------------------------------------------------------------*/
7308 /* 99 TRACE - Trace [RS] */
7309 /*-------------------------------------------------------------------*/
DEF_INST(trace)7310 DEF_INST(trace)
7311 {
7312 int r1, r3; /* Register numbers */
7313 int b2; /* effective address base */
7314 VADR effective_addr2; /* effective address */
7315 #if defined(FEATURE_TRACING)
7316 U32 op; /* Operand */
7317 #endif /*defined(FEATURE_TRACING)*/
7318
7319 RS(inst, regs, r1, r3, b2, effective_addr2);
7320
7321 PRIV_CHECK(regs);
7322
7323 FW_CHECK(effective_addr2, regs);
7324
7325 #if defined(FEATURE_TRACING)
7326 /* Exit if explicit tracing (control reg 12 bit 31) is off */
7327 if ( (regs->CR(12) & CR12_EXTRACE) == 0 )
7328 return;
7329
7330 /* Fetch the trace operand */
7331 op = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
7332
7333 /* Exit if bit zero of the trace operand is one */
7334 if ( (op & 0x80000000) )
7335 return;
7336
7337 /* Perform serialization and checkpoint-synchronization */
7338 PERFORM_SERIALIZATION (regs);
7339 PERFORM_CHKPT_SYNC (regs);
7340
7341 regs->CR(12) = ARCH_DEP(trace_tr) (r1, r3, op, regs);
7342
7343 #endif /*defined(FEATURE_TRACING)*/
7344
7345 /* Perform serialization and checkpoint-synchronization */
7346 PERFORM_SERIALIZATION (regs);
7347 PERFORM_CHKPT_SYNC (regs);
7348
7349 }
7350 #endif /*defined(FEATURE_TRACING)*/
7351
7352
7353 #if !defined(_GEN_ARCH)
7354
7355 #if defined(_ARCHMODE2)
7356 #define _GEN_ARCH _ARCHMODE2
7357 #include "control.c"
7358 #endif
7359
7360 #if defined(_ARCHMODE3)
7361 #undef _GEN_ARCH
7362 #define _GEN_ARCH _ARCHMODE3
7363 #include "control.c"
7364 #endif
7365
7366 #endif /*!defined(_GEN_ARCH)*/
7367