1 /* FEATURE.H (c) Copyright Jan Jaeger, 2000-2009 */ 2 /* Architecture-dependent macro definitions */ 3 4 #ifdef HAVE_CONFIG_H 5 #include <config.h> // Hercules build configuration options/settings 6 #endif 7 8 #if !defined(FEATCHK_CHECK_DONE) 9 #include "featall.h" 10 #include "feat370.h" 11 #include "feat390.h" 12 #include "feat900.h" 13 #define FEATCHK_CHECK_ALL 14 #include "featchk.h" 15 #undef FEATCHK_CHECK_ALL 16 #define FEATCHK_CHECK_DONE 17 #endif /*!defined(FEATCHK_CHECK_DONE)*/ 18 19 #undef __GEN_ARCH 20 #if defined(_GEN_ARCH) 21 #define __GEN_ARCH _GEN_ARCH 22 #else 23 #define __GEN_ARCH _ARCHMODE1 24 #endif 25 26 #include "featall.h" 27 28 #if __GEN_ARCH == 370 29 #include "feat370.h" 30 #elif __GEN_ARCH == 390 31 #include "feat390.h" 32 #elif __GEN_ARCH == 900 33 #include "feat900.h" 34 #else 35 #error Unable to determine Architecture Mode 36 #endif 37 38 #include "featchk.h" 39 40 #undef ARCH_MODE 41 #undef APPLY_PREFIXING 42 #undef AMASK 43 #undef ADDRESS_MAXWRAP 44 #undef ADDRESS_MAXWRAP_E 45 #undef REAL_MODE 46 #undef PER_MODE 47 #undef ASF_ENABLED 48 #undef ASN_AND_LX_REUSE_ENABLED 49 #undef ASTE_AS_DESIGNATOR 50 #undef ASTE_LT_DESIGNATOR 51 #undef SAEVENT_BIT 52 #undef SSEVENT_BIT 53 #undef SSGROUP_BIT 54 #undef LSED_UET_HDR 55 #undef LSED_UET_TLR 56 #undef LSED_UET_BAKR 57 #undef LSED_UET_PC 58 #undef CR12_BRTRACE 59 #undef CR12_TRACEEA 60 #undef CHM_GPR2_RESV 61 #undef DEF_INST 62 #undef ARCH_DEP 63 #undef PSA 64 #undef PSA_SIZE 65 #undef IA 66 #undef PX 67 #undef CR 68 #undef GR 69 #undef GR_A 70 #undef SET_GR_A 71 #undef MONCODE 72 #undef TEA 73 #undef DXC 74 #undef ET 75 #undef PX_MASK 76 #undef RSTOLD 77 #undef RSTNEW 78 #undef RADR 79 #undef F_RADR 80 #undef VADR 81 #undef VADR_L 82 #undef F_VADR 83 #undef GREG 84 #undef F_GREG 85 #undef CREG 86 #undef F_CREG 87 #undef AREG 88 #undef F_AREG 89 #undef STORE_W 90 #undef FETCH_W 91 #undef AIV 92 #undef AIE 93 #undef VIE 94 #undef SIEBK 95 #undef ZPB 96 #undef TLB_REAL_ASD 97 #undef TLB_ASD 98 #undef TLB_VADDR 99 #undef TLB_PTE 100 #undef TLB_PAGEMASK 101 #undef TLB_BYTEMASK 102 #undef TLB_PAGESHIFT 103 #undef TLBID_PAGEMASK 104 #undef TLBID_BYTEMASK 105 #undef ASD_PRIVATE 106 #undef PER_SB 107 108 #if __GEN_ARCH == 370 109 110 #define ARCH_MODE ARCH_370 111 112 #define DEF_INST(_name) \ 113 void (ATTR_REGPARM(2) s370_ ## _name) (BYTE inst[], REGS *regs) 114 115 #define ARCH_DEP(_name) \ 116 s370_ ## _name 117 118 #define APPLY_PREFIXING(addr,pfx) \ 119 ( ((U32)(addr) & 0x7FFFF000) == 0 || ((U32)(addr) & 0x7FFFF000) == (pfx) \ 120 ? (U32)(addr) ^ (pfx) \ 121 : (addr) \ 122 ) 123 124 #define AMASK AMASK_L 125 126 #define ADDRESS_MAXWRAP(_register_context) \ 127 (AMASK24) 128 129 #define ADDRESS_MAXWRAP_E(_register_context) \ 130 (AMASK31) 131 132 #define REAL_MODE(p) \ 133 (!ECMODE(p) || ((p)->sysmask & PSW_DATMODE)==0) 134 135 #if defined(_FEATURE_SIE) 136 #define PER_MODE(_regs) \ 137 ( (ECMODE(&(_regs)->psw) && ((_regs)->psw.sysmask & PSW_PERMODE)) \ 138 || (SIE_MODE((_regs)) && ((_regs)->siebk->m & SIE_M_GPE)) ) 139 #else 140 #define PER_MODE(_regs) \ 141 (ECMODE(&(_regs)->psw) && ((_regs)->psw.sysmask & PSW_PERMODE)) 142 #endif 143 144 #define ASF_ENABLED(_regs) 0 /* ASF is never enabled for S/370 */ 145 146 #define ASN_AND_LX_REUSE_ENABLED(_regs) 0 /* never enabled for S/370 */ 147 148 #define ASTE_AS_DESIGNATOR(_aste) \ 149 ((_aste)[2]) 150 151 #define ASTE_LT_DESIGNATOR(_aste) \ 152 ((_aste)[3]) 153 154 #define SAEVENT_BIT STD_SAEVENT 155 #define SSEVENT_BIT STD_SSEVENT 156 #define SSGROUP_BIT STD_GROUP 157 158 #define PSA PSA_3XX 159 #define PSA_SIZE 4096 160 #define IA IA_L 161 #define PX PX_L 162 #define CR(_r) CR_L(_r) 163 #define GR(_r) GR_L(_r) 164 #define GR_A(_r, _regs) ((_regs)->GR_L((_r))) 165 #define SET_GR_A(_r, _regs,_v) ((_regs)->GR_L((_r))=(_v)) 166 #define MONCODE MC_L 167 #define TEA EA_L 168 #define DXC tea 169 #define ET ET_L 170 #define PX_MASK 0x7FFFF000 171 #define RSTOLD iplccw1 172 #define RSTNEW iplpsw 173 #if !defined(_FEATURE_ZSIE) 174 #define RADR U32 175 #define F_RADR "%8.8"I32_FMT"X" 176 #else 177 #define RADR U64 178 #define F_RADR "%8.8"I64_FMT"X" 179 #endif 180 #define VADR U32 181 #define VADR_L VADR 182 #define F_VADR "%8.8"I32_FMT"X" 183 #define GREG U32 184 #define F_GREG "%8.8"I32_FMT"X" 185 #define CREG U32 186 #define F_CREG "%8.8"I32_FMT"X" 187 #define AREG U32 188 #define F_AREG "%8.8"I32_FMT"X" 189 #define STORE_W STORE_FW 190 #define FETCH_W FETCH_FW 191 #define AIV AIV_L 192 #define AIE AIE_L 193 #define SIEBK SIE1BK 194 #define ZPB ZPB1 195 #define TLB_REAL_ASD TLB_REAL_ASD_L 196 #define TLB_ASD(_n) TLB_ASD_L(_n) 197 #define TLB_VADDR(_n) TLB_VADDR_L(_n) 198 #define TLB_PTE(_n) TLB_PTE_L(_n) 199 #define TLB_PAGEMASK 0x00FFF800 200 #define TLB_BYTEMASK 0x000007FF 201 #define TLB_PAGESHIFT 11 202 #define TLBID_PAGEMASK 0x00E00000 203 #define TLBID_BYTEMASK 0x001FFFFF 204 #define ASD_PRIVATE SEGTAB_370_CMN 205 206 #elif __GEN_ARCH == 390 207 208 #define ARCH_MODE ARCH_390 209 210 #define DEF_INST(_name) \ 211 void (ATTR_REGPARM(2) s390_ ## _name) (BYTE inst[], REGS *regs) 212 213 #define ARCH_DEP(_name) \ 214 s390_ ## _name 215 216 #define APPLY_PREFIXING(addr,pfx) \ 217 ( ((U32)(addr) & 0x7FFFF000) == 0 || ((U32)(addr) & 0x7FFFF000) == (pfx) \ 218 ? (U32)(addr) ^ (pfx) \ 219 : (addr) \ 220 ) 221 222 #define AMASK AMASK_L 223 224 #define ADDRESS_MAXWRAP(_register_context) \ 225 ((_register_context)->psw.AMASK) 226 227 #define ADDRESS_MAXWRAP_E(_register_context) \ 228 ((_register_context)->psw.AMASK) 229 230 #define REAL_MODE(p) \ 231 (((p)->sysmask & PSW_DATMODE)==0) 232 233 #if defined(_FEATURE_SIE) 234 #define PER_MODE(_regs) \ 235 ( ((_regs)->psw.sysmask & PSW_PERMODE) \ 236 || (SIE_MODE((_regs)) && ((_regs)->siebk->m & SIE_M_GPE)) ) 237 #else 238 #define PER_MODE(_regs) \ 239 ((_regs)->psw.sysmask & PSW_PERMODE) 240 #endif 241 242 #define ASF_ENABLED(_regs) ((_regs)->CR(0) & CR0_ASF) 243 244 #define ASN_AND_LX_REUSE_ENABLED(_regs) 0 /* never enabled in ESA/390 */ 245 246 #define ASTE_AS_DESIGNATOR(_aste) \ 247 ((_aste)[2]) 248 249 #define ASTE_LT_DESIGNATOR(_aste) \ 250 ((_aste)[3]) 251 252 #define SAEVENT_BIT STD_SAEVENT 253 #define SSEVENT_BIT STD_SSEVENT 254 #define SSGROUP_BIT STD_GROUP 255 256 #define LSED_UET_HDR S_LSED_UET_HDR 257 #define LSED_UET_TLR S_LSED_UET_TLR 258 #define LSED_UET_BAKR S_LSED_UET_BAKR 259 #define LSED_UET_PC S_LSED_UET_PC 260 #define CR12_BRTRACE S_CR12_BRTRACE 261 #define CR12_TRACEEA S_CR12_TRACEEA 262 263 #define CHM_GPR2_RESV S_CHM_GPR2_RESV 264 265 #define PSA PSA_3XX 266 #define PSA_SIZE 4096 267 #define IA IA_L 268 #define PX PX_L 269 #define CR(_r) CR_L(_r) 270 #define GR(_r) GR_L(_r) 271 #define GR_A(_r, _regs) ((_regs)->GR_L((_r))) 272 #define SET_GR_A(_r, _regs,_v) ((_regs)->GR_L((_r))=(_v)) 273 #define MONCODE MC_L 274 #define TEA EA_L 275 #define DXC tea 276 #define ET ET_L 277 #define PX_MASK 0x7FFFF000 278 #define RSTNEW iplpsw 279 #define RSTOLD iplccw1 280 #if !defined(_FEATURE_ZSIE) 281 #define RADR U32 282 #define F_RADR "%8.8"I32_FMT"X" 283 #else 284 #define RADR U64 285 #define F_RADR "%8.8"I64_FMT"X" 286 #endif 287 #define VADR U32 288 #define VADR_L VADR 289 #define F_VADR "%8.8"I32_FMT"X" 290 #define GREG U32 291 #define F_GREG "%8.8"I32_FMT"X" 292 #define CREG U32 293 #define F_CREG "%8.8"I32_FMT"X" 294 #define AREG U32 295 #define F_AREG "%8.8"I32_FMT"X" 296 #define STORE_W STORE_FW 297 #define FETCH_W FETCH_FW 298 #define AIV AIV_L 299 #define AIE AIE_L 300 #define SIEBK SIE1BK 301 #define ZPB ZPB1 302 #define TLB_REAL_ASD TLB_REAL_ASD_L 303 #define TLB_ASD(_n) TLB_ASD_L(_n) 304 #define TLB_VADDR(_n) TLB_VADDR_L(_n) 305 #define TLB_PTE(_n) TLB_PTE_L(_n) 306 #define TLB_PAGEMASK 0x7FFFF000 307 #define TLB_BYTEMASK 0x00000FFF 308 #define TLB_PAGESHIFT 12 309 #define TLBID_PAGEMASK 0x7FC00000 310 #define TLBID_BYTEMASK 0x003FFFFF 311 #define ASD_PRIVATE STD_PRIVATE 312 313 #elif __GEN_ARCH == 900 314 315 #define ARCH_MODE ARCH_900 316 317 #define APPLY_PREFIXING(addr,pfx) \ 318 ( (U64)((addr) & 0xFFFFFFFFFFFFE000ULL) == (U64)0 || (U64)((addr) & 0xFFFFFFFFFFFFE000ULL) == (pfx) \ 319 ? (addr) ^ (pfx) \ 320 : (addr) \ 321 ) 322 323 #define AMASK AMASK_G 324 325 #define ADDRESS_MAXWRAP(_register_context) \ 326 ((_register_context)->psw.AMASK) 327 328 #define ADDRESS_MAXWRAP_E(_register_context) \ 329 ((_register_context)->psw.AMASK) 330 331 #define REAL_MODE(p) \ 332 (((p)->sysmask & PSW_DATMODE)==0) 333 334 #if defined(_FEATURE_SIE) 335 #define PER_MODE(_regs) \ 336 ( ((_regs)->psw.sysmask & PSW_PERMODE) \ 337 || (SIE_MODE((_regs)) && ((_regs)->siebk->m & SIE_M_GPE)) ) 338 #else 339 #define PER_MODE(_regs) \ 340 ((_regs)->psw.sysmask & PSW_PERMODE) 341 #endif 342 343 #define ASF_ENABLED(_regs) 1 /* ASF is always enabled for ESAME */ 344 345 /* ASN-and-LX-reuse is enabled if the ASN-and-LX-reuse 346 facility is installed and CR0 bit 44 is 1 */ 347 #if defined(FEATURE_ASN_AND_LX_REUSE) 348 #define ASN_AND_LX_REUSE_ENABLED(_regs) \ 349 (sysblk.asnandlxreuse && ((_regs)->CR_L(0) & CR0_ASN_LX_REUS)) 350 #else /* !defined(FEATURE_ASN_AND_LX_REUSE) */ 351 #define ASN_AND_LX_REUSE_ENABLED(_regs) 0 352 #endif /* !defined(FEATURE_ASN_AND_LX_REUSE) */ 353 354 #define ASTE_AS_DESIGNATOR(_aste) \ 355 (((U64)((_aste)[2])<<32)|(U64)((_aste)[3])) 356 357 #define ASTE_LT_DESIGNATOR(_aste) \ 358 ((_aste)[6]) 359 360 #define SAEVENT_BIT ASCE_S 361 #define SSEVENT_BIT ASCE_X 362 #define SSGROUP_BIT ASCE_G 363 364 #define LSED_UET_HDR Z_LSED_UET_HDR 365 #define LSED_UET_TLR Z_LSED_UET_TLR 366 #define LSED_UET_BAKR Z_LSED_UET_BAKR 367 #define LSED_UET_PC Z_LSED_UET_PC 368 #define CR12_BRTRACE Z_CR12_BRTRACE 369 #define CR12_TRACEEA Z_CR12_TRACEEA 370 371 #define CHM_GPR2_RESV Z_CHM_GPR2_RESV 372 373 #define DEF_INST(_name) \ 374 void (ATTR_REGPARM(2) z900_ ## _name) (BYTE inst[], REGS *regs) 375 376 #define ARCH_DEP(_name) \ 377 z900_ ## _name 378 379 #define PSA PSA_900 380 #define PSA_SIZE 8192 381 #define IA IA_G 382 #define PX PX_L 383 #define CR(_r) CR_G(_r) 384 #define GR(_r) GR_G(_r) 385 #define GR_A(_r, _regs) ((_regs)->psw.amode64 ? (_regs)->GR_G((_r)) : (_regs)->GR_L((_r))) 386 #define SET_GR_A(_r, _regs,_v) \ 387 do { \ 388 if((_regs)->psw.amode64) { \ 389 ((_regs)->GR_G((_r))=(_v)); \ 390 } else { \ 391 ((_regs)->GR_L((_r))=(_v)); \ 392 } \ 393 } while(0) 394 395 #define MONCODE MC_G 396 #define TEA EA_G 397 #define DXC dataexc 398 #define ET ET_G 399 #define PX_MASK 0x7FFFE000 400 #define RSTOLD rstold 401 #define RSTNEW rstnew 402 #if 0 403 #define RADR U32 404 #else 405 #define RADR U64 406 #endif 407 #define F_RADR "%16.16"I64_FMT"X" 408 #define VADR U64 409 #if SIZEOF_INT == 4 410 #define VADR_L U32 411 #else 412 #define VADR_L VADR 413 #endif 414 #define F_VADR "%16.16"I64_FMT"X" 415 #define GREG U64 416 #define F_GREG "%16.16"I64_FMT"X" 417 #define CREG U64 418 #define F_CREG "%16.16"I64_FMT"X" 419 #define AREG U32 420 #define F_AREG "%8.8"I32_FMT"X" 421 #define STORE_W STORE_DW 422 #define FETCH_W FETCH_DW 423 #define AIV AIV_G 424 #define AIE AIE_G 425 #define SIEBK SIE2BK 426 #define ZPB ZPB2 427 #define TLB_REAL_ASD TLB_REAL_ASD_G 428 #define TLB_ASD(_n) TLB_ASD_G(_n) 429 #define TLB_VADDR(_n) TLB_VADDR_G(_n) 430 #define TLB_PTE(_n) TLB_PTE_G(_n) 431 #define TLB_PAGEMASK 0xFFFFFFFFFFFFF000ULL 432 #define TLB_BYTEMASK 0x0000000000000FFFULL 433 #define TLB_PAGESHIFT 12 434 #define TLBID_PAGEMASK 0xFFFFFFFFFFC00000ULL 435 #define TLBID_BYTEMASK 0x00000000003FFFFFULL 436 #define ASD_PRIVATE (ASCE_P|ASCE_R) 437 438 #else 439 440 #warning __GEN_ARCH must be 370, 390, 900 or undefined 441 442 #endif 443 444 #undef PAGEFRAME_PAGESIZE 445 #undef PAGEFRAME_PAGESHIFT 446 #undef PAGEFRAME_BYTEMASK 447 #undef PAGEFRAME_PAGEMASK 448 #undef MAXADDRESS 449 #if defined(FEATURE_ESAME) 450 #define PAGEFRAME_PAGESIZE 4096 451 #define PAGEFRAME_PAGESHIFT 12 452 #define PAGEFRAME_BYTEMASK 0x00000FFF 453 #define PAGEFRAME_PAGEMASK 0xFFFFFFFFFFFFF000ULL 454 #define MAXADDRESS 0xFFFFFFFFFFFFFFFFULL 455 #elif defined(FEATURE_S390_DAT) 456 #define PAGEFRAME_PAGESIZE 4096 457 #define PAGEFRAME_PAGESHIFT 12 458 #define PAGEFRAME_BYTEMASK 0x00000FFF 459 #define PAGEFRAME_PAGEMASK 0x7FFFF000 460 #define MAXADDRESS 0x7FFFFFFF 461 #else /* S/370 */ 462 #define PAGEFRAME_PAGESIZE 2048 463 #define PAGEFRAME_PAGESHIFT 11 464 #define PAGEFRAME_BYTEMASK 0x000007FF 465 #define PAGEFRAME_PAGEMASK 0x7FFFF800 466 #if defined(FEATURE_370E_EXTENDED_ADDRESSING) 467 #define MAXADDRESS 0x03FFFFFF 468 #else 469 #define MAXADDRESS 0x00FFFFFF 470 #endif 471 #endif 472 473 474 #undef ITIMER_UPDATE 475 #undef ITIMER_SYNC 476 #if defined(FEATURE_INTERVAL_TIMER) 477 #define ITIMER_UPDATE(_addr, _len, _regs) \ 478 do { \ 479 if( ITIMER_ACCESS((_addr), (_len)) ) \ 480 ARCH_DEP(fetch_int_timer) ((_regs)); \ 481 } while(0) 482 #define ITIMER_SYNC(_addr, _len, _regs) \ 483 do { \ 484 if( ITIMER_ACCESS((_addr), (_len)) ) \ 485 ARCH_DEP(store_int_timer) ((_regs)); \ 486 } while (0) 487 #else 488 #define ITIMER_UPDATE(_addr, _len, _regs) 489 #define ITIMER_SYNC(_addr, _len, _regs) 490 #endif 491 492 493 #if !defined(_FEATURE_2K_STORAGE_KEYS) 494 #define STORAGE_KEY_UNITSIZE 4096 495 #else 496 #define STORAGE_KEY_UNITSIZE 2048 497 #endif 498 499 #undef STORAGE_KEY 500 #undef STORAGE_KEY_PAGESHIFT 501 #undef STORAGE_KEY_PAGESIZE 502 #undef STORAGE_KEY_PAGEMASK 503 #undef STORAGE_KEY_BYTEMASK 504 #ifdef FEATURE_4K_STORAGE_KEYS 505 #if defined(_FEATURE_2K_STORAGE_KEYS) 506 #define STORAGE_KEY_PAGESHIFT 11 507 #else 508 #define STORAGE_KEY_PAGESHIFT 12 509 #endif 510 #define STORAGE_KEY_PAGESIZE 4096 511 #if defined(FEATURE_ESAME) 512 #define STORAGE_KEY_PAGEMASK 0xFFFFFFFFFFFFF000ULL 513 #else 514 #define STORAGE_KEY_PAGEMASK 0x7FFFF000 515 #endif 516 #define STORAGE_KEY_BYTEMASK 0x00000FFF 517 #else 518 #define STORAGE_KEY_PAGESHIFT 11 519 #define STORAGE_KEY_PAGESIZE 2048 520 #define STORAGE_KEY_PAGEMASK 0x7FFFF800 521 #define STORAGE_KEY_BYTEMASK 0x000007FF 522 #endif 523 524 #define STORAGE_KEY(_addr, _pointer) \ 525 (_pointer)->storkeys[(_addr)>>STORAGE_KEY_PAGESHIFT] 526 527 #if defined(_FEATURE_2K_STORAGE_KEYS) 528 #define STORAGE_KEY1(_addr, _pointer) \ 529 (_pointer)->storkeys[((_addr)>>STORAGE_KEY_PAGESHIFT)&~1] 530 #define STORAGE_KEY2(_addr, _pointer) \ 531 (_pointer)->storkeys[((_addr)>>STORAGE_KEY_PAGESHIFT)|1] 532 #endif 533 534 #define XSTORE_INCREMENT_SIZE 0x00100000 535 #define XSTORE_PAGESHIFT 12 536 #define XSTORE_PAGESIZE 4096 537 #undef XSTORE_PAGEMASK 538 #if defined(FEATURE_ESAME) || defined(_FEATURE_ZSIE) 539 #define XSTORE_PAGEMASK 0xFFFFFFFFFFFFF000ULL 540 #else 541 #define XSTORE_PAGEMASK 0x7FFFF000 542 #endif 543 544 /*-------------------------------------------------------------------*/ 545 /* Macros use by Compare and Form Codeword (CFC (B21A)) instruction */ 546 /*-------------------------------------------------------------------*/ 547 548 #undef CFC_A64_OPSIZE 549 #undef CFC_DEF_OPSIZE 550 #undef CFC_MAX_OPSIZE 551 #undef CFC_OPSIZE 552 #undef CFC_GR2_SHIFT 553 #undef CFC_HIGH_BIT 554 #undef AR1 555 #define AR1 ( 1 ) /* Access Register 1 */ 556 #define CFC_A64_OPSIZE ( 6 ) /* amode-64 operand size */ 557 #define CFC_DEF_OPSIZE ( 2 ) /* non-amode-64 operand size */ 558 #define CFC_MAX_OPSIZE ( CFC_A64_OPSIZE > CFC_DEF_OPSIZE ? CFC_A64_OPSIZE : CFC_DEF_OPSIZE ) 559 #if defined(FEATURE_ESAME) 560 #define CFC_OPSIZE ( a64 ? CFC_A64_OPSIZE : CFC_DEF_OPSIZE ) 561 #define CFC_GR2_SHIFT ( a64 ? ( CFC_A64_OPSIZE * 8 ) : ( CFC_DEF_OPSIZE * 8 ) ) 562 #define CFC_HIGH_BIT ( a64 ? 0x8000000000000000ULL : 0x0000000080000000ULL ) 563 #else 564 #define CFC_OPSIZE ( CFC_DEF_OPSIZE ) 565 #define CFC_GR2_SHIFT ( CFC_DEF_OPSIZE * 8 ) 566 #define CFC_HIGH_BIT ( 0x80000000UL ) 567 #endif 568 569 /*-------------------------------------------------------------------*/ 570 /* Macros use by Update Tree (CFC (0102)) instruction */ 571 /*-------------------------------------------------------------------*/ 572 #undef UPT_ALIGN_MASK 573 #undef UPT_SHIFT_MASK 574 #undef UPT_HIGH_BIT 575 #undef AR4 576 #define AR4 (4) /* Access Register 4 */ 577 #if defined(FEATURE_ESAME) 578 #define UPT_ALIGN_MASK ( a64 ? 0x000000000000000FULL : 0x0000000000000007ULL ) 579 #define UPT_SHIFT_MASK ( a64 ? 0xFFFFFFFFFFFFFFF0ULL : 0xFFFFFFFFFFFFFFF8ULL ) 580 #define UPT_HIGH_BIT ( a64 ? 0x8000000000000000ULL : 0x0000000080000000ULL ) 581 #else 582 #define UPT_ALIGN_MASK ( 0x00000007 ) 583 #define UPT_SHIFT_MASK ( 0xFFFFFFF8 ) 584 #define UPT_HIGH_BIT ( 0x80000000 ) 585 #endif 586 587 /* Macros for accelerated lookup */ 588 #undef SPACE_BIT 589 #undef AR_BIT 590 #undef PRIMARY_SPACE_MODE 591 #undef SECONDARY_SPACE_MODE 592 #undef ACCESS_REGISTER_MODE 593 #undef HOME_SPACE_MODE 594 #undef AEA_MODE 595 #undef SET_AEA_COMMON 596 #undef SET_AEA_MODE 597 #undef _CASE_AR_SET_AEA_MODE 598 #undef _CASE_DAS_SET_AEA_MODE 599 #undef _CASE_HOME_SET_AEA_MODE 600 #undef TEST_SET_AEA_MODE 601 #undef SET_AEA_AR 602 #undef MADDR 603 604 #if defined(FEATURE_DUAL_ADDRESS_SPACE) && defined(FEATURE_LINKAGE_STACK) 605 #define SET_AEA_COMMON(_regs) \ 606 do { \ 607 (_regs)->aea_common[1] = ((_regs)->CR(1) & ASD_PRIVATE) == 0; \ 608 (_regs)->aea_common[7] = ((_regs)->CR(7) & ASD_PRIVATE) == 0; \ 609 (_regs)->aea_common[13] = ((_regs)->CR(13) & ASD_PRIVATE) == 0; \ 610 } while (0) 611 #elif defined(FEATURE_DUAL_ADDRESS_SPACE) 612 #define SET_AEA_COMMON(_regs) \ 613 do { \ 614 (_regs)->aea_common[1] = ((_regs)->CR(1) & ASD_PRIVATE) == 0; \ 615 (_regs)->aea_common[7] = ((_regs)->CR(7) & ASD_PRIVATE) == 0; \ 616 } while (0) 617 #else 618 #define SET_AEA_COMMON(_regs) \ 619 do { \ 620 (_regs)->aea_common[1] = ((_regs)->CR(1) & ASD_PRIVATE) == 0; \ 621 } while (0) 622 #endif 623 624 #if defined(FEATURE_DUAL_ADDRESS_SPACE) || defined(FEATURE_LINKAGE_STACK) 625 #define SPACE_BIT(p) \ 626 (((p)->asc & BIT(PSW_SPACE_BIT)) != 0) 627 #define AR_BIT(p) \ 628 (((p)->asc & BIT(PSW_AR_BIT)) != 0) 629 #define PRIMARY_SPACE_MODE(p) \ 630 ((p)->asc == PSW_PRIMARY_SPACE_MODE) 631 #define SECONDARY_SPACE_MODE(p) \ 632 ((p)->asc == PSW_SECONDARY_SPACE_MODE) 633 #define ACCESS_REGISTER_MODE(p) \ 634 ((p)->asc == PSW_ACCESS_REGISTER_MODE) 635 #define HOME_SPACE_MODE(p) \ 636 ((p)->asc == PSW_HOME_SPACE_MODE) 637 #define AEA_MODE(_regs) \ 638 ( ( REAL_MODE(&(_regs)->psw) ? (SIE_STATB((_regs), MX, XC) && AR_BIT(&(_regs)->psw) ? 2 : 0) : (((_regs)->psw.asc >> 6) + 1) ) \ 639 | ( PER_MODE((_regs)) ? 0x40 : 0 ) \ 640 ) 641 #else 642 #define SPACE_BIT(p) (0) 643 #define AR_BIT(p) (0) 644 #define PRIMARY_SPACE_MODE(p) (1) 645 #define SECONDARY_SPACE_MODE(p) (0) 646 #define ACCESS_REGISTER_MODE(p) (0) 647 #define HOME_SPACE_MODE(p) (0) 648 #define AEA_MODE(_regs) \ 649 ( (REAL_MODE(&(_regs)->psw) ? 0 : 1 ) | (PER_MODE((_regs)) ? 0x40 : 0 ) ) 650 #endif 651 652 #if defined(FEATURE_ACCESS_REGISTERS) 653 /* 654 * Update the aea_ar vector whenever an access register 655 * is changed and in armode 656 */ 657 #define SET_AEA_AR(_regs, _arn) \ 658 do \ 659 { \ 660 if (ACCESS_REGISTER_MODE(&(_regs)->psw) && (_arn) > 0 && (_arn) < 16) { \ 661 if ((_regs)->AR((_arn)) == ALET_PRIMARY) \ 662 (_regs)->aea_ar[(_arn)] = 1; \ 663 else if ((_regs)->AR((_arn)) == ALET_SECONDARY) \ 664 (_regs)->aea_ar[(_arn)] = 7; \ 665 else \ 666 (_regs)->aea_ar[(_arn)] = 0; \ 667 } \ 668 } while (0) 669 #else 670 #define SET_AEA_AR(_regs, _arn) 671 #endif 672 673 674 /* 675 * Conditionally reset the aea_ar vector 676 */ 677 #define TEST_SET_AEA_MODE(_regs) \ 678 do \ 679 { \ 680 if ((_regs)->aea_mode != AEA_MODE((_regs))) { \ 681 SET_AEA_MODE((_regs)); \ 682 } \ 683 } while (0) 684 685 686 /* 687 * Reset aea_ar vector to indicate the appropriate 688 * control register: 689 * 0 - unresolvable (armode and alet is not 0 or 1) 690 * 1 - primary space 691 * 7 - secondary space 692 * 13 - home space 693 * 16 - real 694 */ 695 #if defined(FEATURE_ACCESS_REGISTERS) 696 #define _CASE_AR_SET_AEA_MODE(_regs) \ 697 case 2: /* AR */ \ 698 (_regs)->aea_ar[USE_INST_SPACE] = 1; \ 699 for(i = 0; i < 16; i++) \ 700 (_regs)->aea_ar[i] = 1; \ 701 for (i = 1; i < 16; i++) { \ 702 if ((_regs)->AR(i) == ALET_SECONDARY) (_regs)->aea_ar[i] = 7; \ 703 else if ((_regs)->AR(i) != ALET_PRIMARY) (_regs)->aea_ar[i] = 0; \ 704 } \ 705 break; 706 #else 707 #define _CASE_AR_SET_AEA_MODE(_regs) 708 #endif 709 710 #if defined(FEATURE_DUAL_ADDRESS_SPACE) 711 #define _CASE_DAS_SET_AEA_MODE(_regs) \ 712 case 3: /* SEC */ \ 713 (_regs)->aea_ar[USE_INST_SPACE] = 1; \ 714 for(i = 0; i < 16; i++) \ 715 (_regs)->aea_ar[i] = 7; \ 716 break; 717 #else 718 #define _CASE_DAS_SET_AEA_MODE(_regs) 719 #endif 720 721 #if defined(FEATURE_LINKAGE_STACK) 722 #define _CASE_HOME_SET_AEA_MODE(_regs) \ 723 case 4: /* HOME */ \ 724 (_regs)->aea_ar[USE_INST_SPACE] = 13; \ 725 for(i = 0; i < 16; i++) \ 726 (_regs)->aea_ar[i] = 13; \ 727 break; 728 #else 729 #define _CASE_HOME_SET_AEA_MODE(_regs) 730 #endif 731 732 #define SET_AEA_MODE(_regs) \ 733 do { \ 734 int i; \ 735 int inst_cr = (_regs)->aea_ar[USE_INST_SPACE]; \ 736 BYTE oldmode = (_regs)->aea_mode; \ 737 (_regs)->aea_mode = AEA_MODE((_regs)); \ 738 switch ((_regs)->aea_mode & 0x0F) { \ 739 case 1: /* PRIM */ \ 740 (_regs)->aea_ar[USE_INST_SPACE] = 1; \ 741 for(i = 0; i < 16; i++) \ 742 (_regs)->aea_ar[i] = 1; \ 743 break; \ 744 _CASE_AR_SET_AEA_MODE((_regs)) \ 745 _CASE_DAS_SET_AEA_MODE((_regs)) \ 746 _CASE_HOME_SET_AEA_MODE((_regs)) \ 747 default: /* case 0: REAL */ \ 748 (_regs)->aea_ar[USE_INST_SPACE] = CR_ASD_REAL; \ 749 for(i = 0; i < 16; i++) \ 750 (_regs)->aea_ar[i] = CR_ASD_REAL; \ 751 } \ 752 if (inst_cr != (_regs)->aea_ar[USE_INST_SPACE]) \ 753 INVALIDATE_AIA((_regs)); \ 754 if ((oldmode & PSW_PERMODE) == 0 && ((_regs)->aea_mode & PSW_PERMODE) != 0) { \ 755 INVALIDATE_AIA((_regs)); \ 756 if (EN_IC_PER_SA((_regs))) \ 757 ARCH_DEP(invalidate_tlb)((_regs),~(ACC_WRITE|ACC_CHECK)); \ 758 } \ 759 } while (0) 760 761 762 /* 763 * Accelerated lookup 764 */ 765 #define MADDRL(_addr, _len, _arn, _regs, _acctype, _akey) \ 766 ( \ 767 likely((_regs)->aea_ar[(_arn)]) \ 768 && likely( \ 769 ((_regs)->CR((_regs)->aea_ar[(_arn)]) == (_regs)->tlb.TLB_ASD(TLBIX(_addr))) \ 770 || ((_regs)->aea_common[(_regs)->aea_ar[(_arn)]] & (_regs)->tlb.common[TLBIX(_addr)]) \ 771 ) \ 772 && likely((_akey) == 0 || (_akey) == (_regs)->tlb.skey[TLBIX(_addr)]) \ 773 && likely((((_addr) & TLBID_PAGEMASK) | (_regs)->tlbID) == (_regs)->tlb.TLB_VADDR(TLBIX(_addr))) \ 774 && likely((_acctype) & (_regs)->tlb.acc[TLBIX(_addr)]) \ 775 ? ( \ 776 ((_acctype) & ACC_CHECK) ? \ 777 (_regs)->dat.storkey = (_regs)->tlb.storkey[TLBIX(_addr)], \ 778 MAINADDR((_regs)->tlb.main[TLBIX(_addr)], (_addr)) : \ 779 MAINADDR((_regs)->tlb.main[TLBIX(_addr)], (_addr)) \ 780 ) \ 781 : ( \ 782 ARCH_DEP(logical_to_main_l) ((_addr), (_arn), (_regs), (_acctype), (_akey), (_len)) \ 783 ) \ 784 ) 785 786 /* Old style accelerated lookup (without length) */ 787 #define MADDR(_addr, _arn, _regs, _acctype, _akey) \ 788 MADDRL( (_addr), 1, (_arn), (_regs), (_acctype), (_akey)) 789 790 /* 791 * PER Successful Branch 792 */ 793 #if defined(FEATURE_PER) 794 #if defined(FEATURE_PER2) 795 #define PER_SB(_regs, _addr) \ 796 do { \ 797 if (unlikely(EN_IC_PER_SB((_regs))) \ 798 && (!((_regs)->CR(9) & CR9_BAC) \ 799 || PER_RANGE_CHECK((_addr) & ADDRESS_MAXWRAP((_regs)), \ 800 (_regs)->CR(10), (_regs)->CR(11)) \ 801 ) \ 802 ) \ 803 ON_IC_PER_SB((_regs)); \ 804 } while (0) 805 #else /*!defined(FEATURE_PER2)*/ 806 #define PER_SB(_regs, _addr) \ 807 do { \ 808 if (unlikely(EN_IC_PER_SB((_regs)))) \ 809 ON_IC_PER_SB((_regs)); \ 810 } while (0) 811 #endif /*!defined(FEATURE_PER2)*/ 812 #else /*!defined(FEATURE_PER)*/ 813 #define PER_SB(_regs,_addr) 814 #endif /*!defined(FEATURE_PER)*/ 815 816 /* end of FEATURES.H */ 817