1 /* PLO.C (c) Copyright Jan Jaeger, 2000-2009 */
2 /* Perform Locked Operation functions codes */
3
4 /* Interpretive Execution - (c) Copyright Jan Jaeger, 1999-2009 */
5 /* z/Architecture support - (c) Copyright Jan Jaeger, 1999-2009 */
6
7 #include "hstdinc.h"
8
9 #if !defined(_HENGINE_DLL_)
10 #define _HENGINE_DLL_
11 #endif
12
13 #if !defined(_PLO_C_)
14 #define _PLO_C_
15 #endif
16
17 #include "hercules.h"
18
19 #include "opcode.h"
20
21 #include "inline.h"
22
23
24 #if defined(FEATURE_PERFORM_LOCKED_OPERATION)
ARCH_DEP(plo_cl)25 int ARCH_DEP(plo_cl) (int r1, int r3, VADR effective_addr2, int b2,
26 VADR effective_addr4, int b4, REGS *regs)
27 {
28 U32 op2,
29 op4;
30
31 FW_CHECK(effective_addr2, regs);
32 FW_CHECK(effective_addr4, regs);
33
34 /* Load second operand from operand address */
35 op2 = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
36
37 if(regs->GR_L(r1) == op2)
38 {
39
40 op4 = ARCH_DEP(vfetch4) ( effective_addr4, b4, regs );
41 regs->GR_L(r3) = op4;
42
43 return 0;
44 }
45 else
46 {
47 regs->GR_L(r1) = op2;
48
49 return 1;
50 }
51
52 }
53
54
ARCH_DEP(plo_clg)55 int ARCH_DEP(plo_clg) (int r1, int r3, VADR effective_addr2, int b2,
56 VADR effective_addr4, int b4, REGS *regs)
57 {
58 U64 op1c,
59 op2,
60 op4;
61 U32 op4alet = 0;
62 VADR op4addr;
63
64 UNREFERENCED(r1);
65
66 DW_CHECK(effective_addr4, regs);
67 DW_CHECK(effective_addr2, regs);
68
69 /* load second operand */
70 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
71
72 /* load 1st op. compare value */
73 op1c = ARCH_DEP(wfetch8)(effective_addr4 + 8, b4, regs);
74
75 if(op1c == op2)
76 {
77 /* When in ar mode, ar3 is used to access the
78 operand. The alet is fetched from the pl */
79 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
80 {
81 if(r3 == 0)
82 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
83 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
84 regs->AR(r3) = op4alet;
85 SET_AEA_AR(regs, r3);
86 }
87
88 /* Load address of operand 4 */
89 #if defined(FEATURE_ESAME)
90 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
91 #else
92 op4addr = ARCH_DEP(wfetch4)(effective_addr4 + 76, b4, regs);
93 #endif
94 op4addr &= ADDRESS_MAXWRAP(regs);
95 DW_CHECK(op4addr, regs);
96
97 /* Load operand 4, using ar3 when in ar mode */
98 op4 = ARCH_DEP(vfetch8)(op4addr, r3, regs);
99
100 /* replace the 3rd operand with the 4th operand */
101 ARCH_DEP(wstore8)(op4, effective_addr4 + 40, b4, regs);
102
103 return 0;
104 }
105 else
106 {
107 /* replace the first op compare value with 2nd op */
108 ARCH_DEP(wstore8)(op2, effective_addr4 + 8, b4, regs);
109
110 return 1;
111 }
112 }
113
114
115 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_clgr)116 int ARCH_DEP(plo_clgr) (int r1, int r3, VADR effective_addr2, int b2,
117 VADR effective_addr4, int b4, REGS *regs)
118 {
119 U64 op2,
120 op4;
121
122 DW_CHECK(effective_addr2, regs);
123 DW_CHECK(effective_addr4, regs);
124
125 /* Load second operand from operand address */
126 op2 = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
127
128 if(regs->GR_G(r1) == op2)
129 {
130
131 op4 = ARCH_DEP(vfetch8) ( effective_addr4, b4, regs );
132 regs->GR_G(r3) = op4;
133
134 return 0;
135 }
136 else
137 {
138 regs->GR_G(r1) = op2;
139
140 return 1;
141 }
142
143 }
144 #endif /*defined(FEATURE_ESAME)*/
145
146
147 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_clx)148 int ARCH_DEP(plo_clx) (int r1, int r3, VADR effective_addr2, int b2,
149 VADR effective_addr4, int b4, REGS *regs)
150 {
151 BYTE op1c[16],
152 op2[16],
153 op4[16];
154 U32 op4alet = 0;
155 VADR op4addr;
156
157 UNREFERENCED(r1);
158
159 DW_CHECK(effective_addr4, regs);
160 QW_CHECK(effective_addr2, regs);
161
162 /* load second operand */
163 ARCH_DEP(vfetchc) ( op2, 16-1, effective_addr2, b2, regs );
164
165 /* load 1st op. compare value */
166 ARCH_DEP(vfetchc) ( op1c, 16-1, effective_addr4 + 0, b4, regs );
167
168 if(memcmp(op1c,op2,16) == 0)
169 {
170 /* When in ar mode, ar3 is used to access the
171 operand. The alet is fetched from the pl */
172 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
173 {
174 if(r3 == 0)
175 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
176 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
177 regs->AR(r3) = op4alet;
178 SET_AEA_AR(regs, r3);
179 }
180
181 /* Load address of operand 4 */
182 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
183 op4addr &= ADDRESS_MAXWRAP(regs);
184 QW_CHECK(op4addr, regs);
185
186 /* Load operand 4, using ar3 when in ar mode */
187 ARCH_DEP(vfetchc) ( op4, 16-1, op4addr, r3, regs );
188
189 /* replace the 3rd operand with the 4th operand */
190 ARCH_DEP(wstorec) ( op4, 16-1, effective_addr4 + 32, b4, regs );
191
192 return 0;
193 }
194 else
195 {
196 /* replace the first op compare value with 2nd op */
197 ARCH_DEP(vstorec) ( op2, 16-1, effective_addr4 + 0, b4, regs );
198
199 return 1;
200 }
201 }
202 #endif /*defined(FEATURE_ESAME)*/
203
204
ARCH_DEP(plo_cs)205 int ARCH_DEP(plo_cs) (int r1, int r3, VADR effective_addr2, int b2,
206 VADR effective_addr4, int b4, REGS *regs)
207 {
208 U32 op2;
209
210 UNREFERENCED(r3);
211 UNREFERENCED(effective_addr4);
212 UNREFERENCED(b4);
213
214 ODD_CHECK(r1, regs);
215 FW_CHECK(effective_addr2, regs);
216
217 /* Load second operand from operand address */
218 op2 = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
219
220 /* Compare operand with R1 register contents */
221 if ( regs->GR_L(r1) == op2 )
222 {
223 /* If equal, store R1+1 at operand loc and set cc=0 */
224 ARCH_DEP(vstore4) ( regs->GR_L(r1+1), effective_addr2, b2, regs );
225
226 return 0;
227 }
228 else
229 {
230 /* If unequal, load R1 from operand and set cc=1 */
231 regs->GR_L(r1) = op2;
232
233 return 1;
234 }
235
236 }
237
238
ARCH_DEP(plo_csg)239 int ARCH_DEP(plo_csg) (int r1, int r3, VADR effective_addr2, int b2,
240 VADR effective_addr4, int b4, REGS *regs)
241 {
242 U64 op1c,
243 op1r,
244 op2;
245
246 UNREFERENCED(r1);
247 UNREFERENCED(r3);
248
249 DW_CHECK(effective_addr4, regs);
250 DW_CHECK(effective_addr2, regs);
251
252 /* Load first op compare value */
253 op1c = ARCH_DEP(wfetch8)(effective_addr4 + 8, b4, regs);
254
255 /* Load 2nd operand */
256 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
257
258 if(op1c == op2)
259 {
260 /* Load 1st op replacement value */
261 op1r = ARCH_DEP(wfetch8)(effective_addr4 + 24, b4, regs);
262
263 /* Store at 2nd operand location */
264 ARCH_DEP(vstore8)(op1r, effective_addr2, b2, regs);
265
266 return 0;
267 }
268 else
269 {
270 /* Replace 1st op comp value by 2nd op */
271 ARCH_DEP(wstore8)(op2, effective_addr4 + 8, b4, regs);
272
273 return 1;
274 }
275 }
276
277
278 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_csgr)279 int ARCH_DEP(plo_csgr) (int r1, int r3, VADR effective_addr2, int b2,
280 VADR effective_addr4, int b4, REGS *regs)
281 {
282 U64 op2;
283
284 UNREFERENCED(r3);
285 UNREFERENCED(effective_addr4);
286 UNREFERENCED(b4);
287
288 ODD_CHECK(r1, regs);
289 DW_CHECK(effective_addr2, regs);
290
291 /* Load second operand from operand address */
292 op2 = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
293
294 /* Compare operand with R1 register contents */
295 if ( regs->GR_G(r1) == op2 )
296 {
297 /* If equal, store R1+1 at operand loc and set cc=0 */
298 ARCH_DEP(vstore8) ( regs->GR_G(r1+1), effective_addr2, b2, regs );
299
300 return 0;
301 }
302 else
303 {
304 /* If unequal, load R1 from operand and set cc=1 */
305 regs->GR_G(r1) = op2;
306
307 return 1;
308 }
309
310 }
311 #endif /*defined(FEATURE_ESAME)*/
312
313
314 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_csx)315 int ARCH_DEP(plo_csx) (int r1, int r3, VADR effective_addr2, int b2,
316 VADR effective_addr4, int b4, REGS *regs)
317 {
318 BYTE op1c[16],
319 op1r[16],
320 op2[16];
321
322 UNREFERENCED(r1);
323 UNREFERENCED(r3);
324
325 DW_CHECK(effective_addr4, regs);
326 QW_CHECK(effective_addr2, regs);
327
328 /* Load first op compare value */
329 ARCH_DEP(vfetchc) ( op1c, 16-1, effective_addr4 + 0, b4, regs );
330
331 /* Load 2nd operand */
332 ARCH_DEP(vfetchc) ( op2, 16-1, effective_addr2, b2, regs );
333
334 if(memcmp(op1c,op2,16) == 0)
335 {
336 /* Load 1st op replacement value */
337 ARCH_DEP(wfetchc) ( op1r, 16-1, effective_addr4 + 16, b4, regs );
338
339 /* Store at 2nd operand location */
340 ARCH_DEP(vstorec) ( op1r, 16-1, effective_addr2, b2, regs );
341
342 return 0;
343 }
344 else
345 {
346 /* Replace 1st op comp value by 2nd op */
347 ARCH_DEP(vstorec) ( op2, 16-1, effective_addr4 + 0, b4, regs );
348
349 return 1;
350 }
351 }
352 #endif /*defined(FEATURE_ESAME)*/
353
354
ARCH_DEP(plo_dcs)355 int ARCH_DEP(plo_dcs) (int r1, int r3, VADR effective_addr2, int b2,
356 VADR effective_addr4, int b4, REGS *regs)
357 {
358 U32 op2,
359 op4;
360
361 ODD2_CHECK(r1, r3, regs);
362 FW_CHECK(effective_addr2, regs);
363 FW_CHECK(effective_addr4, regs);
364
365 /* Load second operands from operand addresses */
366 op2 = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
367
368 if(regs->GR_L(r1) != op2)
369 {
370 regs->GR_L(r1) = op2;
371
372 return 1;
373 }
374 else
375 {
376 op4 = ARCH_DEP(vfetch4) ( effective_addr4, b4, regs );
377
378 /* Compare operand with register contents */
379 if (regs->GR_L(r3) != op4)
380 {
381 /* If unequal, load r3 from op and set cc=2 */
382 regs->GR_L(r3) = op4;
383
384 return 2;
385 }
386 else
387 {
388 /* Verify access to 2nd operand */
389 ARCH_DEP(validate_operand) (effective_addr2, b2, 4-1,
390 ACCTYPE_WRITE_SKP, regs);
391
392 /* If equal, store replacement and set cc=0 */
393 ARCH_DEP(vstore4) ( regs->GR_L(r3+1), effective_addr4, b4, regs );
394 ARCH_DEP(vstore4) ( regs->GR_L(r1+1), effective_addr2, b2, regs );
395
396 return 0;
397 }
398 }
399
400 }
401
402
ARCH_DEP(plo_dcsg)403 int ARCH_DEP(plo_dcsg) (int r1, int r3, VADR effective_addr2, int b2,
404 VADR effective_addr4, int b4, REGS *regs)
405 {
406 U64 op1c,
407 op1r,
408 op2,
409 op3c,
410 op3r,
411 op4;
412 U32 op4alet = 0;
413 VADR op4addr;
414
415 UNREFERENCED(r1);
416
417 DW_CHECK(effective_addr2, regs);
418 DW_CHECK(effective_addr4, regs);
419
420 /* load 1st op compare value from the pl */
421 op1c = ARCH_DEP(wfetch8)(effective_addr4 + 8, b4, regs);
422
423 /* load 2nd operand */
424 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
425
426 if(op1c != op2)
427 {
428 /* replace the 1st op compare value with 2nd op */
429 ARCH_DEP(wstore8)(op2, effective_addr4 + 8, b4, regs);
430
431 return 1;
432 }
433 else
434 {
435 /* Load 3rd op compare value */
436 op3c = ARCH_DEP(wfetch8)(effective_addr4 + 40, b4, regs);
437
438 /* When in ar mode, ar3 is used to access the
439 operand. The alet is fetched from the pl */
440 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
441 {
442 if(r3 == 0)
443 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
444 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
445 regs->AR(r3) = op4alet;
446 SET_AEA_AR(regs, r3);
447 }
448
449 /* Load address of operand 4 */
450 #if defined(FEATURE_ESAME)
451 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
452 #else
453 op4addr = ARCH_DEP(wfetch4)(effective_addr4 + 76, b4, regs);
454 #endif
455 op4addr &= ADDRESS_MAXWRAP(regs);
456 DW_CHECK(op4addr, regs);
457
458 /* Load operand 4, using ar3 when in ar mode */
459 op4 = ARCH_DEP(vfetch8)(op4addr, r3, regs);
460
461 if(op3c != op4)
462 {
463 ARCH_DEP(wstore8)(op4, effective_addr4 + 40, b4, regs);
464
465 return 2;
466 }
467 else
468 {
469 /* load replacement values */
470 op1r = ARCH_DEP(wfetch8)(effective_addr4 + 24, b4, regs);
471 op3r = ARCH_DEP(wfetch8)(effective_addr4 + 56, b4, regs);
472
473 /* Verify access to 2nd operand */
474 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
475 ACCTYPE_WRITE_SKP, regs);
476
477 /* Store 3rd op replacement at 4th op */
478 ARCH_DEP(vstore8)(op3r, op4addr, r3, regs);
479
480 /* Store 1st op replacement at 2nd op */
481 ARCH_DEP(vstore8)(op1r, effective_addr2, b2, regs);
482
483 return 0;
484 }
485 }
486
487 }
488
489
490 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_dcsgr)491 int ARCH_DEP(plo_dcsgr) (int r1, int r3, VADR effective_addr2, int b2,
492 VADR effective_addr4, int b4, REGS *regs)
493 {
494 U64 op2,
495 op4;
496
497 ODD2_CHECK(r1, r3, regs);
498 DW_CHECK(effective_addr2, regs);
499 DW_CHECK(effective_addr4, regs);
500
501 /* Load second operands from operand addresses */
502 op2 = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
503
504 if(regs->GR_G(r1) != op2)
505 {
506 regs->GR_G(r1) = op2;
507
508 return 1;
509 }
510 else
511 {
512 op4 = ARCH_DEP(vfetch8) ( effective_addr4, b4, regs );
513
514 /* Compare operand with register contents */
515 if (regs->GR_G(r3) != op4)
516 {
517 /* If unequal, load r3 from op and set cc=2 */
518 regs->GR_G(r3) = op4;
519
520 return 2;
521 }
522 else
523 {
524 /* Verify access to 2nd operand */
525 ARCH_DEP(validate_operand) (effective_addr2, b2, 4-1,
526 ACCTYPE_WRITE_SKP, regs);
527
528 /* If equal, store replacement and set cc=0 */
529 ARCH_DEP(vstore8) ( regs->GR_G(r3+1), effective_addr4, b4, regs );
530 ARCH_DEP(vstore8) ( regs->GR_G(r1+1), effective_addr2, b2, regs );
531
532 return 0;
533 }
534 }
535
536 }
537 #endif /*defined(FEATURE_ESAME)*/
538
539
540 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_dcsx)541 int ARCH_DEP(plo_dcsx) (int r1, int r3, VADR effective_addr2, int b2,
542 VADR effective_addr4, int b4, REGS *regs)
543 {
544 BYTE op1c[16],
545 op1r[16],
546 op2[16],
547 op3c[16],
548 op3r[16],
549 op4[16];
550 U32 op4alet = 0;
551 VADR op4addr;
552
553 UNREFERENCED(r1);
554
555 QW_CHECK(effective_addr2, regs);
556 DW_CHECK(effective_addr4, regs);
557
558 /* load 1st op compare value from the pl */
559 ARCH_DEP(vfetchc) ( op1c, 16-1, effective_addr4 + 0, b4, regs );
560
561 /* load 2nd operand */
562 ARCH_DEP(vfetchc) ( op2, 16-1, effective_addr2, b2, regs );
563
564 if(memcmp(op1c,op2,16) != 0)
565 {
566 /* replace the 1st op compare value with 2nd op */
567 ARCH_DEP(vstorec) ( op2, 16-1, effective_addr4 + 0, b4, regs );
568
569 return 1;
570 }
571 else
572 {
573 /* Load 3rd op compare value */
574 ARCH_DEP(wfetchc) ( op3c, 16-1, effective_addr4 + 32, b4, regs );
575
576 /* When in ar mode, ar3 is used to access the
577 operand. The alet is fetched from the pl */
578 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
579 {
580 if(r3 == 0)
581 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
582 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
583 regs->AR(r3) = op4alet;
584 SET_AEA_AR(regs, r3);
585 }
586
587 /* Load address of operand 4 */
588 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
589 op4addr &= ADDRESS_MAXWRAP(regs);
590 QW_CHECK(op4addr, regs);
591
592 /* Load operand 4, using ar3 when in ar mode */
593 ARCH_DEP(vfetchc) ( op4, 16-1, op4addr, r3, regs );
594
595 if(memcmp(op3c,op4,16) != 0)
596 {
597 ARCH_DEP(wstorec) ( op4, 16-1, effective_addr4 + 32, b4, regs );
598
599 return 2;
600 }
601 else
602 {
603 /* load replacement values */
604 ARCH_DEP(wfetchc) ( op1r, 16-1, effective_addr4 + 16, b4, regs );
605 ARCH_DEP(wfetchc) ( op3r, 16-1, effective_addr4 + 48, b4, regs );
606
607 /* Verify access to 2nd operand */
608 ARCH_DEP(validate_operand) (effective_addr2, b2, 16-1,
609 ACCTYPE_WRITE_SKP, regs);
610
611 /* Store 3rd op replacement at 4th op */
612 ARCH_DEP(vstorec) ( op3r, 16-1, op4addr, r3, regs);
613
614 /* Store 1st op replacement at 2nd op */
615 ARCH_DEP(vstorec) ( op1r, 16-1, effective_addr2, b2, regs);
616
617 return 0;
618 }
619 }
620
621 }
622 #endif /*defined(FEATURE_ESAME)*/
623
624
ARCH_DEP(plo_csst)625 int ARCH_DEP(plo_csst) (int r1, int r3, VADR effective_addr2, int b2,
626 VADR effective_addr4, int b4, REGS *regs)
627 {
628 U32 op2;
629
630 ODD_CHECK(r1, regs);
631 FW_CHECK(effective_addr2, regs);
632 FW_CHECK(effective_addr4, regs);
633
634 /* Load second operand from operand address */
635 op2 = ARCH_DEP(vfetch4) ( effective_addr2, b2, regs );
636
637 /* Compare operand with register contents */
638 if ( regs->GR_L(r1) == op2)
639 {
640 /* Verify access to 2nd operand */
641 ARCH_DEP(validate_operand) (effective_addr2, b2, 4-1,
642 ACCTYPE_WRITE_SKP, regs);
643
644 /* If equal, store replacement and set cc=0 */
645 ARCH_DEP(vstore4) ( regs->GR_L(r3), effective_addr4, b4, regs );
646 ARCH_DEP(vstore4) ( regs->GR_L(r1+1), effective_addr2, b2, regs );
647
648 return 0;
649 }
650 else
651 {
652 regs->GR_L(r1) = op2;
653
654 return 1;
655 }
656
657 }
658
659
ARCH_DEP(plo_csstg)660 int ARCH_DEP(plo_csstg) (int r1, int r3, VADR effective_addr2, int b2,
661 VADR effective_addr4, int b4, REGS *regs)
662 {
663 U64 op1c,
664 op1r,
665 op2,
666 op3;
667 U32 op4alet = 0;
668 VADR op4addr;
669
670 UNREFERENCED(r1);
671
672 DW_CHECK(effective_addr2, regs);
673 DW_CHECK(effective_addr4, regs);
674
675 op1c = ARCH_DEP(wfetch8)(effective_addr4 + 8, b4, regs);
676 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
677
678 if(op1c == op2)
679 {
680 op1r = ARCH_DEP(wfetch8)(effective_addr4 + 24, b4, regs);
681 op3 = ARCH_DEP(wfetch8)(effective_addr4 + 56, b4, regs);
682
683 /* Verify access to 2nd operand */
684 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
685 ACCTYPE_WRITE_SKP, regs);
686
687 /* When in ar mode, ar3 is used to access the
688 operand. The alet is fetched from the pl */
689 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
690 {
691 if(r3 == 0)
692 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
693 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
694 regs->AR(r3) = op4alet;
695 SET_AEA_AR(regs, r3);
696 }
697
698 /* Load address of operand 4 */
699 #if defined(FEATURE_ESAME)
700 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
701 #else
702 op4addr = ARCH_DEP(wfetch4)(effective_addr4 + 76, b4, regs);
703 #endif
704 op4addr &= ADDRESS_MAXWRAP(regs);
705 DW_CHECK(op4addr, regs);
706
707 ARCH_DEP(vstore8)(op3, op4addr, r3, regs);
708 ARCH_DEP(vstore8)(op1r, effective_addr2, b2, regs);
709
710 return 0;
711 }
712 else
713 {
714 /* Store 2nd op at 1st op comare value */
715 ARCH_DEP(wstore8)(op2, effective_addr4 + 8, b4, regs);
716
717 return 1;
718 }
719
720 }
721
722
723 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_csstgr)724 int ARCH_DEP(plo_csstgr) (int r1, int r3, VADR effective_addr2, int b2,
725 VADR effective_addr4, int b4, REGS *regs)
726 {
727 U64 op2;
728
729 ODD_CHECK(r1, regs);
730 DW_CHECK(effective_addr2, regs);
731 DW_CHECK(effective_addr4, regs);
732
733 /* Load second operand from operand address */
734 op2 = ARCH_DEP(vfetch8) ( effective_addr2, b2, regs );
735
736 /* Compare operand with register contents */
737 if ( regs->GR_G(r1) == op2)
738 {
739 /* Verify access to 2nd operand */
740 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
741 ACCTYPE_WRITE_SKP, regs);
742
743 /* If equal, store replacement and set cc=0 */
744 ARCH_DEP(vstore8) ( regs->GR_G(r3), effective_addr4, b4, regs );
745 ARCH_DEP(vstore8) ( regs->GR_G(r1+1), effective_addr2, b2, regs );
746
747 return 0;
748 }
749 else
750 {
751 regs->GR_G(r1) = op2;
752
753 return 1;
754 }
755
756 }
757 #endif /*defined(FEATURE_ESAME)*/
758
759
760 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_csstx)761 int ARCH_DEP(plo_csstx) (int r1, int r3, VADR effective_addr2, int b2,
762 VADR effective_addr4, int b4, REGS *regs)
763 {
764 BYTE op1c[16],
765 op1r[16],
766 op2[16],
767 op3[16];
768 U32 op4alet = 0;
769 VADR op4addr;
770
771 UNREFERENCED(r1);
772
773 QW_CHECK(effective_addr2, regs);
774 DW_CHECK(effective_addr4, regs);
775
776 ARCH_DEP(vfetchc) ( op1c, 16-1, effective_addr4 + 0, b4, regs );
777 ARCH_DEP(vfetchc) ( op2, 16-1, effective_addr2, b2, regs );
778
779 if(memcmp(op1c,op2,16) == 0)
780 {
781 ARCH_DEP(wfetchc) ( op1r, 16-1, effective_addr4 + 16, b4, regs );
782 ARCH_DEP(wfetchc) ( op3, 16-1, effective_addr4 + 48, b4, regs );
783
784 /* Verify access to 2nd operand */
785 ARCH_DEP(validate_operand) (effective_addr2, b2, 16-1,
786 ACCTYPE_WRITE_SKP, regs);
787
788 /* When in ar mode, ar3 is used to access the
789 operand. The alet is fetched from the pl */
790 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
791 {
792 if(r3 == 0)
793 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
794 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
795 regs->AR(r3) = op4alet;
796 SET_AEA_AR(regs, r3);
797 }
798
799 /* Load address of operand 4 */
800 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
801 op4addr &= ADDRESS_MAXWRAP(regs);
802 QW_CHECK(op4addr, regs);
803
804 ARCH_DEP(vstorec)(op3, 16-1, op4addr, r3, regs);
805 ARCH_DEP(vstorec)(op1r, 16-1, effective_addr2, b2, regs);
806
807 return 0;
808 }
809 else
810 {
811 /* Store 2nd op at 1st op comare value */
812 ARCH_DEP(vstorec)(op2, 16-1, effective_addr4 + 0, b4, regs);
813
814 return 1;
815 }
816
817 }
818 #endif /*defined(FEATURE_ESAME)*/
819
820
ARCH_DEP(plo_csdst)821 int ARCH_DEP(plo_csdst) (int r1, int r3, VADR effective_addr2, int b2,
822 VADR effective_addr4, int b4, REGS *regs)
823 {
824 U32 op2,
825 op3,
826 op4alet = 0,
827 op5,
828 op6alet = 0;
829 VADR op4addr,
830 op6addr;
831
832 ODD_CHECK(r1, regs);
833 FW_CHECK(effective_addr2, regs);
834 FW_CHECK(effective_addr4, regs);
835
836 op2 = ARCH_DEP(vfetch4)(effective_addr2, b2, regs);
837 op3 = ARCH_DEP(wfetch4)(effective_addr4 + 60, b4, regs);
838 op5 = ARCH_DEP(wfetch4)(effective_addr4 + 92, b4, regs);
839
840 if(regs->GR_L(r1) == op2)
841 {
842
843 /* Verify access to 2nd operand */
844 ARCH_DEP(validate_operand) (effective_addr2, b2, 4-1,
845 ACCTYPE_WRITE_SKP, regs);
846
847 /* When in ar mode, ar3 is used to access the
848 operand. The alet is fetched from the pl */
849 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
850 {
851 if(r3 == 0)
852 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
853 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
854 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
855 regs->AR(r3) = op6alet;
856 SET_AEA_AR(regs, r3);
857 }
858
859 /* Load address of operand 4 */
860 #if defined(FEATURE_ESAME)
861 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
862 #else
863 op4addr = ARCH_DEP(wfetch4)(effective_addr4 + 76, b4, regs);
864 #endif
865 op4addr &= ADDRESS_MAXWRAP(regs);
866 FW_CHECK(op4addr, regs);
867
868 /* Load address of operand 6 */
869 #if defined(FEATURE_ESAME)
870 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
871 #else
872 op6addr = ARCH_DEP(wfetch4)(effective_addr4 + 108, b4, regs);
873 #endif
874 op6addr &= ADDRESS_MAXWRAP(regs);
875 FW_CHECK(op6addr, regs);
876
877 /* Verify access to 6th operand */
878 ARCH_DEP(validate_operand) (op6addr, r3, 4-1,ACCTYPE_WRITE_SKP, regs);
879
880 /* Store 3th op at 4th op */
881 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
882 {
883 regs->AR(r3) = op4alet;
884 SET_AEA_AR(regs, r3);
885 }
886 ARCH_DEP(vstore4)(op3, op4addr, r3, regs);
887
888 /* Store 5th op at 6th op */
889 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
890 {
891 regs->AR(r3) = op6alet;
892 SET_AEA_AR(regs, r3);
893 }
894 ARCH_DEP(vstore4)(op5, op6addr, r3, regs);
895
896 /* Store 1st op at 2nd op */
897 ARCH_DEP(vstore4)(regs->GR_L(r1+1), effective_addr2, b2, regs);
898
899 return 0;
900 }
901 else
902 {
903 regs->GR_L(r1) = op2;
904
905 return 1;
906 }
907 }
908
909
ARCH_DEP(plo_csdstg)910 int ARCH_DEP(plo_csdstg) (int r1, int r3, VADR effective_addr2, int b2,
911 VADR effective_addr4, int b4, REGS *regs)
912 {
913 U64 op1c,
914 op1r,
915 op2,
916 op3,
917 op5;
918 U32 op4alet = 0,
919 op6alet = 0;
920 VADR op4addr,
921 op6addr;
922
923 UNREFERENCED(r1);
924
925 DW_CHECK(effective_addr2, regs);
926 DW_CHECK(effective_addr4, regs);
927
928 op1c = ARCH_DEP(wfetch8)(effective_addr4 + 8, b4, regs);
929 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
930
931 if(op1c == op2)
932 {
933 op1r = ARCH_DEP(wfetch8)(effective_addr4 + 24, b4, regs);
934 op3 = ARCH_DEP(wfetch8)(effective_addr4 + 56, b4, regs);
935 op5 = ARCH_DEP(wfetch8)(effective_addr4 + 88, b4, regs);
936
937 /* Verify access to 2nd operand */
938 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
939 ACCTYPE_WRITE_SKP, regs);
940
941 /* When in ar mode, ar3 is used to access the
942 operand. The alet is fetched from the pl */
943 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
944 {
945 if(r3 == 0)
946 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
947 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
948 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
949 regs->AR(r3) = op6alet;
950 SET_AEA_AR(regs, r3);
951 }
952
953 /* Load address of operand 4 */
954 #if defined(FEATURE_ESAME)
955 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
956 #else
957 op4addr = ARCH_DEP(wfetch4)(effective_addr4 + 76, b4, regs);
958 #endif
959 op4addr &= ADDRESS_MAXWRAP(regs);
960 DW_CHECK(op4addr, regs);
961
962 /* Load address of operand 6 */
963 #if defined(FEATURE_ESAME)
964 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
965 #else
966 op6addr = ARCH_DEP(wfetch4)(effective_addr4 + 108, b4, regs);
967 #endif
968 op6addr &= ADDRESS_MAXWRAP(regs);
969 DW_CHECK(op6addr, regs);
970
971 /* Verify access to 6th operand */
972 ARCH_DEP(validate_operand) (op6addr, r3, 8-1, ACCTYPE_WRITE_SKP, regs);
973
974 /* Store 3th op at 4th op */
975 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
976 {
977 regs->AR(r3) = op4alet;
978 SET_AEA_AR(regs, r3);
979 }
980 ARCH_DEP(vstore8)(op3, op4addr, r3, regs);
981
982 /* Store 5th op at 6th op */
983 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
984 {
985 regs->AR(r3) = op6alet;
986 SET_AEA_AR(regs, r3);
987 }
988 ARCH_DEP(vstore8)(op5, op6addr, r3, regs);
989
990 /* Store 1st op replacement at 2nd op */
991 ARCH_DEP(vstore8)(op1r, effective_addr2, b2, regs);
992
993 return 0;
994 }
995 else
996 {
997 ARCH_DEP(wstore8)(op2, effective_addr4 + 8, b4, regs);
998
999 return 1;
1000 }
1001 }
1002
1003
1004 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_csdstgr)1005 int ARCH_DEP(plo_csdstgr) (int r1, int r3, VADR effective_addr2, int b2,
1006 VADR effective_addr4, int b4, REGS *regs)
1007 {
1008 U64 op2,
1009 op3,
1010 op5;
1011 U32 op4alet = 0,
1012 op6alet = 0;
1013 VADR op4addr,
1014 op6addr;
1015
1016 ODD_CHECK(r1, regs);
1017 DW_CHECK(effective_addr2, regs);
1018 DW_CHECK(effective_addr4, regs);
1019
1020 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
1021
1022 if(regs->GR_G(r1) == op2)
1023 {
1024 op3 = ARCH_DEP(wfetch8)(effective_addr4 + 56, b4, regs);
1025 op5 = ARCH_DEP(wfetch8)(effective_addr4 + 88, b4, regs);
1026
1027 /* Verify access to 2nd operand */
1028 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
1029 ACCTYPE_WRITE_SKP, regs);
1030
1031 /* When in ar mode, ar3 is used to access the
1032 operand. The alet is fetched from the pl */
1033 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1034 {
1035 if(r3 == 0)
1036 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
1037 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
1038 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
1039 regs->AR(r3) = op6alet;
1040 SET_AEA_AR(regs, r3);
1041 }
1042
1043 /* Load address of operand 4 */
1044 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
1045 op4addr &= ADDRESS_MAXWRAP(regs);
1046 DW_CHECK(op4addr, regs);
1047
1048 /* Load address of operand 6 */
1049 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
1050 op6addr &= ADDRESS_MAXWRAP(regs);
1051 DW_CHECK(op6addr, regs);
1052
1053 /* Verify access to 6th operand */
1054 ARCH_DEP(validate_operand) (op6addr, r3, 8-1,ACCTYPE_WRITE_SKP, regs);
1055
1056 /* Store 3th op at 4th op */
1057 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1058 {
1059 regs->AR(r3) = op4alet;
1060 SET_AEA_AR(regs, r3);
1061 }
1062 ARCH_DEP(vstore8)(op3, op4addr, r3, regs);
1063
1064 /* Store 5th op at 6th op */
1065 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1066 {
1067 regs->AR(r3) = op6alet;
1068 SET_AEA_AR(regs, r3);
1069 }
1070 ARCH_DEP(vstore8)(op5, op6addr, r3, regs);
1071
1072 /* Store 1st op at 2nd op */
1073 ARCH_DEP(vstore8)(regs->GR_G(r1+1), effective_addr2, b2, regs);
1074
1075 return 0;
1076 }
1077 else
1078 {
1079 regs->GR_G(r1) = op2;
1080
1081 return 1;
1082 }
1083 }
1084 #endif /*defined(FEATURE_ESAME)*/
1085
1086
1087 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_csdstx)1088 int ARCH_DEP(plo_csdstx) (int r1, int r3, VADR effective_addr2, int b2,
1089 VADR effective_addr4, int b4, REGS *regs)
1090 {
1091 BYTE op1c[16],
1092 op1r[16],
1093 op2[16],
1094 op3[16],
1095 op5[16];
1096 U32 op4alet = 0,
1097 op6alet = 0;
1098 VADR op4addr,
1099 op6addr;
1100
1101 UNREFERENCED(r1);
1102
1103 QW_CHECK(effective_addr2, regs);
1104 DW_CHECK(effective_addr4, regs);
1105
1106 ARCH_DEP(vfetchc)(op1c, 16-1, effective_addr4 + 0, b4, regs);
1107 ARCH_DEP(vfetchc)(op2, 16-1, effective_addr2, b2, regs);
1108
1109 if(memcmp(op1c,op2,16) == 0)
1110 {
1111 ARCH_DEP(wfetchc)(op1r, 16-1, effective_addr4 + 16, b4, regs);
1112 ARCH_DEP(wfetchc)(op3, 16-1, effective_addr4 + 48, b4, regs);
1113 ARCH_DEP(wfetchc)(op5, 16-1, effective_addr4 + 80, b4, regs);
1114
1115 /* Verify access to 2nd operand */
1116 ARCH_DEP(validate_operand) (effective_addr2, b2, 16-1,
1117 ACCTYPE_WRITE_SKP, regs);
1118
1119 /* When in ar mode, ar3 is used to access the
1120 operand. The alet is fetched from the pl */
1121 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1122 {
1123 if(r3 == 0)
1124 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
1125 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
1126 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
1127 regs->AR(r3) = op6alet;
1128 SET_AEA_AR(regs, r3);
1129 }
1130
1131 /* Load address of operand 4 */
1132 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
1133 op4addr &= ADDRESS_MAXWRAP(regs);
1134 QW_CHECK(op4addr, regs);
1135
1136 /* Load address of operand 6 */
1137 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
1138 op6addr &= ADDRESS_MAXWRAP(regs);
1139 QW_CHECK(op6addr, regs);
1140
1141 /* Verify access to 6th operand */
1142 ARCH_DEP(validate_operand) (op6addr, r3, 16-1,ACCTYPE_WRITE_SKP, regs);
1143
1144 /* Store 3th op at 4th op */
1145 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1146 {
1147 regs->AR(r3) = op4alet;
1148 SET_AEA_AR(regs, r3);
1149 }
1150 ARCH_DEP(vstorec)(op3, 16-1, op4addr, r3, regs);
1151
1152 /* Store 5th op at 6th op */
1153 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1154 {
1155 regs->AR(r3) = op6alet;
1156 SET_AEA_AR(regs, r3);
1157 }
1158 ARCH_DEP(vstorec)(op5, 16-1, op6addr, r3, regs);
1159
1160 /* Store 1st op replacement at 2nd op */
1161 ARCH_DEP(vstorec)(op1r, 16-1, effective_addr2, b2, regs);
1162
1163 return 0;
1164 }
1165 else
1166 {
1167 ARCH_DEP(vstorec)(op2, 16-1, effective_addr4 + 0, b4, regs);
1168
1169 return 1;
1170 }
1171 }
1172 #endif /*defined(FEATURE_ESAME)*/
1173
1174
ARCH_DEP(plo_cstst)1175 int ARCH_DEP(plo_cstst) (int r1, int r3, VADR effective_addr2, int b2,
1176 VADR effective_addr4, int b4, REGS *regs)
1177 {
1178 U32 op2,
1179 op3,
1180 op4alet = 0,
1181 op5,
1182 op6alet = 0,
1183 op7,
1184 op8alet = 0;
1185 VADR op4addr,
1186 op6addr,
1187 op8addr;
1188
1189 ODD_CHECK(r1, regs);
1190 FW_CHECK(effective_addr2, regs);
1191 FW_CHECK(effective_addr4, regs);
1192
1193 op2 = ARCH_DEP(vfetch4)(effective_addr2, b2, regs);
1194 op3 = ARCH_DEP(wfetch4)(effective_addr4 + 60, b4, regs);
1195 op5 = ARCH_DEP(wfetch4)(effective_addr4 + 92, b4, regs);
1196 op7 = ARCH_DEP(wfetch4)(effective_addr4 + 124, b4, regs);
1197
1198 if(regs->GR_L(r1) == op2)
1199 {
1200 /* Verify access to 2nd operand */
1201 ARCH_DEP(validate_operand) (effective_addr2, b2, 4-1,
1202 ACCTYPE_WRITE_SKP, regs);
1203
1204 /* When in ar mode, ar3 is used to access the
1205 operand. The alet is fetched from the pl */
1206 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1207 {
1208 if(r3 == 0)
1209 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
1210 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
1211 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
1212 op8alet = ARCH_DEP(wfetch4)(effective_addr4 + 132, b4, regs);
1213 regs->AR(r3) = op8alet;
1214 SET_AEA_AR(regs, r3);
1215 }
1216
1217 /* Load address of operand 4 */
1218 #if defined(FEATURE_ESAME)
1219 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
1220 #else
1221 op4addr = ARCH_DEP(wfetch4)(effective_addr4 + 76, b4, regs);
1222 #endif
1223 op4addr &= ADDRESS_MAXWRAP(regs);
1224 FW_CHECK(op4addr, regs);
1225
1226 /* Load address of operand 6 */
1227 #if defined(FEATURE_ESAME)
1228 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
1229 #else
1230 op6addr = ARCH_DEP(wfetch4)(effective_addr4 + 108, b4, regs);
1231 #endif
1232 op6addr &= ADDRESS_MAXWRAP(regs);
1233 FW_CHECK(op6addr, regs);
1234
1235 /* Load address of operand 8 */
1236 #if defined(FEATURE_ESAME)
1237 op8addr = ARCH_DEP(wfetch8)(effective_addr4 + 136, b4, regs);
1238 #else
1239 op8addr = ARCH_DEP(wfetch4)(effective_addr4 + 140, b4, regs);
1240 #endif
1241 op8addr &= ADDRESS_MAXWRAP(regs);
1242 FW_CHECK(op8addr, regs);
1243
1244 /* Verify access to 8th operand */
1245 ARCH_DEP(validate_operand) (op8addr, r3, 4-1,ACCTYPE_WRITE_SKP, regs);
1246
1247 /* Verify access to 6th operand */
1248 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1249 {
1250 regs->AR(r3) = op6alet;
1251 SET_AEA_AR(regs, r3);
1252 }
1253 ARCH_DEP(validate_operand) (op6addr, r3, 4-1, ACCTYPE_WRITE_SKP, regs);
1254
1255 /* Store 3rd op at 4th op */
1256 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1257 {
1258 regs->AR(r3) = op4alet;
1259 SET_AEA_AR(regs, r3);
1260 }
1261 ARCH_DEP(vstore4)(op3, op4addr, r3, regs);
1262
1263 /* Store 5th op at 6th op */
1264 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1265 {
1266 regs->AR(r3) = op6alet;
1267 SET_AEA_AR(regs, r3);
1268 }
1269 ARCH_DEP(vstore4)(op5, op6addr, r3, regs);
1270
1271 /* Store 7th op at 8th op */
1272 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1273 {
1274 regs->AR(r3) = op8alet;
1275 SET_AEA_AR(regs, r3);
1276 }
1277 ARCH_DEP(vstore4)(op7, op8addr, r3, regs);
1278
1279 /* Store 1st op replacement at 2nd op */
1280 ARCH_DEP(vstore4)(regs->GR_L(r1+1), effective_addr2, b2, regs);
1281
1282 return 0;
1283 }
1284 else
1285 {
1286 regs->GR_L(r1) = op2;
1287
1288 return 1;
1289 }
1290 }
1291
1292
ARCH_DEP(plo_cststg)1293 int ARCH_DEP(plo_cststg) (int r1, int r3, VADR effective_addr2, int b2,
1294 VADR effective_addr4, int b4, REGS *regs)
1295 {
1296 U64 op1c,
1297 op1r,
1298 op2,
1299 op3,
1300 op5,
1301 op7;
1302 U32 op4alet = 0,
1303 op6alet = 0,
1304 op8alet = 0;
1305 VADR op4addr,
1306 op6addr,
1307 op8addr;
1308
1309 UNREFERENCED(r1);
1310
1311 DW_CHECK(effective_addr2, regs);
1312 DW_CHECK(effective_addr4, regs);
1313
1314 op1c = ARCH_DEP(wfetch8)(effective_addr4 + 8, b4, regs);
1315 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
1316
1317 if(op1c == op2)
1318 {
1319 op1r = ARCH_DEP(wfetch8)(effective_addr4 + 24, b4, regs);
1320 op3 = ARCH_DEP(wfetch8)(effective_addr4 + 56, b4, regs);
1321 op5 = ARCH_DEP(wfetch8)(effective_addr4 + 88, b4, regs);
1322 op7 = ARCH_DEP(wfetch8)(effective_addr4 + 120, b4, regs);
1323
1324 /* Verify access to 2nd operand */
1325 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
1326 ACCTYPE_WRITE_SKP, regs);
1327
1328 /* When in ar mode, ar3 is used to access the
1329 operand. The alet is fetched from the pl */
1330 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1331 {
1332 if(r3 == 0)
1333 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
1334 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
1335 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
1336 op8alet = ARCH_DEP(wfetch4)(effective_addr4 + 132, b4, regs);
1337 regs->AR(r3) = op8alet;
1338 SET_AEA_AR(regs, r3);
1339 }
1340
1341 /* Load address of operand 4 */
1342 #if defined(FEATURE_ESAME)
1343 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
1344 #else
1345 op4addr = ARCH_DEP(wfetch4)(effective_addr4 + 76, b4, regs);
1346 #endif
1347 op4addr &= ADDRESS_MAXWRAP(regs);
1348 DW_CHECK(op4addr, regs);
1349
1350 /* Load address of operand 6 */
1351 #if defined(FEATURE_ESAME)
1352 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
1353 #else
1354 op6addr = ARCH_DEP(wfetch4)(effective_addr4 + 108, b4, regs);
1355 #endif
1356 op6addr &= ADDRESS_MAXWRAP(regs);
1357 DW_CHECK(op6addr, regs);
1358
1359 /* Load address of operand 8 */
1360 #if defined(FEATURE_ESAME)
1361 op8addr = ARCH_DEP(wfetch8)(effective_addr4 + 136, b4, regs);
1362 #else
1363 op8addr = ARCH_DEP(wfetch4)(effective_addr4 + 140, b4, regs);
1364 #endif
1365 op8addr &= ADDRESS_MAXWRAP(regs);
1366 DW_CHECK(op8addr, regs);
1367
1368 /* Verify access to 8th operand */
1369 ARCH_DEP(validate_operand) (op8addr, r3, 8-1,ACCTYPE_WRITE_SKP, regs);
1370
1371 /* Verify access to 6th operand */
1372 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1373 {
1374 regs->AR(r3) = op6alet;
1375 SET_AEA_AR(regs, r3);
1376 }
1377 ARCH_DEP(validate_operand) (op6addr, r3, 8-1,ACCTYPE_WRITE_SKP, regs);
1378
1379 /* Store 3th op at 4th op */
1380 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1381 {
1382 regs->AR(r3) = op4alet;
1383 SET_AEA_AR(regs, r3);
1384 }
1385 ARCH_DEP(vstore8)(op3, op4addr, r3, regs);
1386
1387 /* Store 5th op at 6th op */
1388 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1389 {
1390 regs->AR(r3) = op6alet;
1391 SET_AEA_AR(regs, r3);
1392 }
1393 ARCH_DEP(vstore8)(op5, op6addr, r3, regs);
1394
1395 /* Store 7th op at 8th op */
1396 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1397 {
1398 regs->AR(r3) = op8alet;
1399 SET_AEA_AR(regs, r3);
1400 }
1401 ARCH_DEP(vstore8)(op7, op8addr, r3, regs);
1402
1403 /* Store 1st op replacement value at 2nd op */
1404 ARCH_DEP(vstore8)(op1r, effective_addr2, b2, regs);
1405
1406 return 0;
1407 }
1408 else
1409 {
1410 ARCH_DEP(wstore8)(op2, effective_addr4 + 8, b4, regs);
1411
1412 return 1;
1413 }
1414 }
1415
1416
1417 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_cststgr)1418 int ARCH_DEP(plo_cststgr) (int r1, int r3, VADR effective_addr2, int b2,
1419 VADR effective_addr4, int b4, REGS *regs)
1420 {
1421 U64 op2,
1422 op3,
1423 op5,
1424 op7;
1425 U32 op4alet = 0,
1426 op6alet = 0,
1427 op8alet = 0;
1428 VADR op4addr,
1429 op6addr,
1430 op8addr;
1431
1432 ODD_CHECK(r1, regs);
1433 DW_CHECK(effective_addr2, regs);
1434 DW_CHECK(effective_addr4, regs);
1435
1436 op2 = ARCH_DEP(vfetch8)(effective_addr2, b2, regs);
1437
1438 if(regs->GR_G(r1) == op2)
1439 {
1440 op3 = ARCH_DEP(wfetch8)(effective_addr4 + 56, b4, regs);
1441 op5 = ARCH_DEP(wfetch8)(effective_addr4 + 88, b4, regs);
1442 op7 = ARCH_DEP(wfetch8)(effective_addr4 + 120, b4, regs);
1443
1444 /* Verify access to 2nd operand */
1445 ARCH_DEP(validate_operand) (effective_addr2, b2, 8-1,
1446 ACCTYPE_WRITE_SKP, regs);
1447
1448 /* When in ar mode, ar3 is used to access the
1449 operand. The alet is fetched from the pl */
1450 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1451 {
1452 if(r3 == 0)
1453 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
1454 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
1455 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
1456 op8alet = ARCH_DEP(wfetch4)(effective_addr4 + 132, b4, regs);
1457 regs->AR(r3) = op8alet;
1458 SET_AEA_AR(regs, r3);
1459 }
1460
1461 /* Load address of operand 4 */
1462 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
1463 op4addr &= ADDRESS_MAXWRAP(regs);
1464 DW_CHECK(op4addr, regs);
1465
1466 /* Load address of operand 6 */
1467 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
1468 op6addr &= ADDRESS_MAXWRAP(regs);
1469 DW_CHECK(op6addr, regs);
1470
1471 /* Load address of operand 8 */
1472 op8addr = ARCH_DEP(wfetch8)(effective_addr4 + 136, b4, regs);
1473 op8addr &= ADDRESS_MAXWRAP(regs);
1474 DW_CHECK(op8addr, regs);
1475
1476 /* Verify access to 8th operand */
1477 ARCH_DEP(validate_operand) (op8addr, r3, 8-1,ACCTYPE_WRITE_SKP, regs);
1478
1479 /* Verify access to 6th operand */
1480 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1481 {
1482 regs->AR(r3) = op6alet;
1483 SET_AEA_AR(regs, r3);
1484 }
1485 ARCH_DEP(validate_operand) (op6addr, r3, 8-1,ACCTYPE_WRITE_SKP, regs);
1486
1487 /* Store 3rd op at 4th op */
1488 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1489 {
1490 regs->AR(r3) = op4alet;
1491 SET_AEA_AR(regs, r3);
1492 }
1493 ARCH_DEP(vstore8)(op3, op4addr, r3, regs);
1494
1495 /* Store 5th op at 6th op */
1496 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1497 {
1498 regs->AR(r3) = op6alet;
1499 SET_AEA_AR(regs, r3);
1500 }
1501 ARCH_DEP(vstore8)(op5, op6addr, r3, regs);
1502
1503 /* Store 7th op at 8th op */
1504 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1505 {
1506 regs->AR(r3) = op8alet;
1507 SET_AEA_AR(regs, r3);
1508 }
1509 ARCH_DEP(vstore8)(op7, op8addr, r3, regs);
1510
1511 /* Store 1st op replacement at 2nd op */
1512 ARCH_DEP(vstore8)(regs->GR_G(r1+1), effective_addr2, b2, regs);
1513
1514 return 0;
1515 }
1516 else
1517 {
1518 regs->GR_G(r1) = op2;
1519
1520 return 1;
1521 }
1522 }
1523 #endif /*defined(FEATURE_ESAME)*/
1524
1525
1526 #if defined(FEATURE_ESAME)
ARCH_DEP(plo_cststx)1527 int ARCH_DEP(plo_cststx) (int r1, int r3, VADR effective_addr2, int b2,
1528 VADR effective_addr4, int b4, REGS *regs)
1529 {
1530 BYTE op1c[16],
1531 op1r[16],
1532 op2[16],
1533 op3[16],
1534 op5[16],
1535 op7[16];
1536 U32 op4alet = 0,
1537 op6alet = 0,
1538 op8alet = 0;
1539 VADR op4addr,
1540 op6addr,
1541 op8addr;
1542
1543 UNREFERENCED(r1);
1544
1545 QW_CHECK(effective_addr2, regs);
1546 DW_CHECK(effective_addr4, regs);
1547
1548 ARCH_DEP(vfetchc)(op1c, 16-1, effective_addr4 + 0, b4, regs);
1549 ARCH_DEP(vfetchc)(op2, 16-1, effective_addr2, b2, regs);
1550
1551 if(memcmp(op1c,op2,16) == 0)
1552 {
1553 ARCH_DEP(wfetchc)(op1r, 16-1, effective_addr4 + 16, b4, regs);
1554 ARCH_DEP(wfetchc)(op3, 16-1, effective_addr4 + 48, b4, regs);
1555 ARCH_DEP(wfetchc)(op5, 16-1, effective_addr4 + 80, b4, regs);
1556 ARCH_DEP(wfetchc)(op7, 16-1, effective_addr4 + 112, b4, regs);
1557
1558 /* Verify access to 2nd operand */
1559 ARCH_DEP(validate_operand) (effective_addr2, b2, 16-1,
1560 ACCTYPE_WRITE_SKP, regs);
1561
1562 /* When in ar mode, ar3 is used to access the
1563 operand. The alet is fetched from the pl */
1564 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1565 {
1566 if(r3 == 0)
1567 ARCH_DEP(program_interrupt)(regs, PGM_SPECIFICATION_EXCEPTION);
1568 op4alet = ARCH_DEP(wfetch4)(effective_addr4 + 68, b4, regs);
1569 op6alet = ARCH_DEP(wfetch4)(effective_addr4 + 100, b4, regs);
1570 op8alet = ARCH_DEP(wfetch4)(effective_addr4 + 132, b4, regs);
1571 regs->AR(r3) = op8alet;
1572 SET_AEA_AR(regs, r3);
1573 }
1574
1575 /* Load address of operand 4 */
1576 op4addr = ARCH_DEP(wfetch8)(effective_addr4 + 72, b4, regs);
1577 op4addr &= ADDRESS_MAXWRAP(regs);
1578 QW_CHECK(op4addr, regs);
1579
1580 /* Load address of operand 6 */
1581 op6addr = ARCH_DEP(wfetch8)(effective_addr4 + 104, b4, regs);
1582 op6addr &= ADDRESS_MAXWRAP(regs);
1583 QW_CHECK(op6addr, regs);
1584
1585 /* Load address of operand 8 */
1586 op8addr = ARCH_DEP(wfetch8)(effective_addr4 + 136, b4, regs);
1587 op8addr &= ADDRESS_MAXWRAP(regs);
1588 QW_CHECK(op8addr, regs);
1589
1590 /* Verify access to 8th operand */
1591 ARCH_DEP(validate_operand) (op8addr, r3, 16-1,ACCTYPE_WRITE_SKP, regs);
1592
1593 /* Verify access to 6th operand */
1594 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1595 {
1596 regs->AR(r3) = op6alet;
1597 SET_AEA_AR(regs, r3);
1598 }
1599 ARCH_DEP(validate_operand) (op6addr, r3, 16-1, ACCTYPE_WRITE_SKP, regs);
1600
1601 /* Store 3th op at 4th op */
1602 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1603 {
1604 regs->AR(r3) = op4alet;
1605 SET_AEA_AR(regs, r3);
1606 }
1607 ARCH_DEP(vstorec)(op3, 16-1, op4addr, r3, regs);
1608
1609 /* Store 5th op at 6th op */
1610 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1611 {
1612 regs->AR(r3) = op6alet;
1613 SET_AEA_AR(regs, r3);
1614 }
1615 ARCH_DEP(vstorec)(op5, 16-1, op6addr, r3, regs);
1616
1617 /* Store 7th op at 8th op */
1618 if(!REAL_MODE(®s->psw) && ACCESS_REGISTER_MODE(®s->psw))
1619 {
1620 regs->AR(r3) = op8alet;
1621 SET_AEA_AR(regs, r3);
1622 }
1623 ARCH_DEP(vstorec)(op7, 16-1, op8addr, r3, regs);
1624
1625 /* Store 1st op replacement value at 2nd op */
1626 ARCH_DEP(vstorec)(op1r, 16-1, effective_addr2, b2, regs);
1627
1628 return 0;
1629 }
1630 else
1631 {
1632 ARCH_DEP(vstorec)(op2, 16-1, effective_addr4 + 0, b4, regs);
1633
1634 return 1;
1635 }
1636 }
1637 #endif /*defined(FEATURE_ESAME)*/
1638
1639
1640 #endif /*defined(FEATURE_PERFORM_LOCKED_OPERATION)*/
1641
1642
1643
1644 #if !defined(_GEN_ARCH)
1645
1646 #if defined(_ARCHMODE2)
1647 #define _GEN_ARCH _ARCHMODE2
1648 #include "plo.c"
1649 #endif
1650
1651 #if defined(_ARCHMODE3)
1652 #undef _GEN_ARCH
1653 #define _GEN_ARCH _ARCHMODE3
1654 #include "plo.c"
1655 #endif
1656
1657 #endif /*!defined(_GEN_ARCH)*/
1658