1 // Copyright (c) 2012- PPSSPP Project.
2
3 // This program is free software: you can redistribute it and/or modify
4 // it under the terms of the GNU General Public License as published by
5 // the Free Software Foundation, version 2.0 or later versions.
6
7 // This program is distributed in the hope that it will be useful,
8 // but WITHOUT ANY WARRANTY; without even the implied warranty of
9 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 // GNU General Public License 2.0 for more details.
11
12 // A copy of the GPL 2.0 should have been included with the program.
13 // If not, see http://www.gnu.org/licenses/
14
15 // Official git repository and contact information can be found at
16 // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/.
17
18 #include "ppsspp_config.h"
19 #if PPSSPP_ARCH(ARM)
20
21 #include "Common/Data/Convert/SmallDataConvert.h"
22 #include "Common/Profiler/Profiler.h"
23
24 #include "Core/Config.h"
25 #include "Core/Core.h"
26 #include "Core/Reporting.h"
27 #include "Core/MemMap.h"
28 #include "Core/HLE/HLE.h"
29 #include "Core/HLE/HLETables.h"
30
31 #include "Core/MIPS/MIPS.h"
32 #include "Core/MIPS/MIPSCodeUtils.h"
33 #include "Core/MIPS/MIPSAnalyst.h"
34 #include "Core/MIPS/MIPSTables.h"
35
36 #include "Core/MIPS/ARM/ArmJit.h"
37 #include "Core/MIPS/ARM/ArmRegCache.h"
38 #include "Core/MIPS/JitCommon/JitBlockCache.h"
39
40 #include "Common/ArmEmitter.h"
41
42 #define _RS MIPS_GET_RS(op)
43 #define _RT MIPS_GET_RT(op)
44 #define _RD MIPS_GET_RD(op)
45 #define _FS MIPS_GET_FS(op)
46 #define _FT MIPS_GET_FT(op)
47 #define _FD MIPS_GET_FD(op)
48 #define _SA MIPS_GET_SA(op)
49 #define _POS ((op>> 6) & 0x1F)
50 #define _SIZE ((op>>11) & 0x1F)
51 #define _IMM26 (op & 0x03FFFFFF)
52 #define TARGET16 ((int)(SignExtend16ToU32(op) << 2))
53 #define TARGET26 (_IMM26 << 2)
54
55 #define LOOPOPTIMIZATION 0
56
57 // We can disable nice delay slots.
58 // #define CONDITIONAL_NICE_DELAYSLOT delaySlotIsNice = false;
59 #define CONDITIONAL_NICE_DELAYSLOT ;
60
61 using namespace MIPSAnalyst;
62
63 namespace MIPSComp
64 {
65 using namespace ArmGen;
66 using namespace ArmJitConstants;
67
BranchRSRTComp(MIPSOpcode op,CCFlags cc,bool likely)68 void ArmJit::BranchRSRTComp(MIPSOpcode op, CCFlags cc, bool likely)
69 {
70 if (js.inDelaySlot) {
71 ERROR_LOG_REPORT(JIT, "Branch in RSRTComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
72 return;
73 }
74 int offset = TARGET16;
75 MIPSGPReg rt = _RT;
76 MIPSGPReg rs = _RS;
77 u32 targetAddr = GetCompilerPC() + offset + 4;
78
79 bool immBranch = false;
80 bool immBranchTaken = false;
81 if (gpr.IsImm(rs) && gpr.IsImm(rt)) {
82 // The cc flags are opposites: when NOT to take the branch.
83 bool immBranchNotTaken;
84 s32 rsImm = (s32)gpr.GetImm(rs);
85 s32 rtImm = (s32)gpr.GetImm(rt);
86
87 switch (cc)
88 {
89 case CC_EQ: immBranchNotTaken = rsImm == rtImm; break;
90 case CC_NEQ: immBranchNotTaken = rsImm != rtImm; break;
91 default: immBranchNotTaken = false; _dbg_assert_msg_(false, "Bad cc flag in BranchRSRTComp().");
92 }
93 immBranch = true;
94 immBranchTaken = !immBranchNotTaken;
95 }
96
97 if (jo.immBranches && immBranch && js.numInstructions < jo.continueMaxInstructions) {
98 if (!immBranchTaken) {
99 // Skip the delay slot if likely, otherwise it'll be the next instruction.
100 if (likely)
101 js.compilerPC += 4;
102 return;
103 }
104
105 // Branch taken. Always compile the delay slot, and then go to dest.
106 CompileDelaySlot(DELAYSLOT_NICE);
107 AddContinuedBlock(targetAddr);
108 // Account for the increment in the loop.
109 js.compilerPC = targetAddr - 4;
110 // In case the delay slot was a break or something.
111 js.compiling = true;
112 return;
113 }
114
115 MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
116 js.downcountAmount += MIPSGetInstructionCycleEstimate(delaySlotOp);
117 bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rt, rs);
118 CONDITIONAL_NICE_DELAYSLOT;
119
120 if (immBranch) {
121 // Continuing is handled above, this is just static jumping.
122 if (immBranchTaken || !likely)
123 CompileDelaySlot(DELAYSLOT_FLUSH);
124 else
125 FlushAll();
126
127 const u32 destAddr = immBranchTaken ? targetAddr : GetCompilerPC() + 8;
128 WriteExit(destAddr, js.nextExit++);
129 } else {
130 if (!likely && delaySlotIsNice)
131 CompileDelaySlot(DELAYSLOT_NICE);
132
133 // We might be able to flip the condition (EQ/NEQ are easy.)
134 const bool canFlip = cc == CC_EQ || cc == CC_NEQ;
135
136 Operand2 op2;
137 bool negated;
138 if (gpr.IsImm(rt) && TryMakeOperand2_AllowNegation(gpr.GetImm(rt), op2, &negated)) {
139 gpr.MapReg(rs);
140 if (!negated)
141 CMP(gpr.R(rs), op2);
142 else
143 CMN(gpr.R(rs), op2);
144 } else {
145 if (gpr.IsImm(rs) && TryMakeOperand2_AllowNegation(gpr.GetImm(rs), op2, &negated) && canFlip) {
146 gpr.MapReg(rt);
147 if (!negated)
148 CMP(gpr.R(rt), op2);
149 else
150 CMN(gpr.R(rt), op2);
151 } else {
152 gpr.MapInIn(rs, rt);
153 CMP(gpr.R(rs), gpr.R(rt));
154 }
155 }
156
157 ArmGen::FixupBranch ptr;
158 if (!likely) {
159 if (!delaySlotIsNice)
160 CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
161 else
162 FlushAll();
163 ptr = B_CC(cc);
164 } else {
165 FlushAll();
166 ptr = B_CC(cc);
167 CompileDelaySlot(DELAYSLOT_FLUSH);
168 }
169
170 // Take the branch
171 WriteExit(targetAddr, js.nextExit++);
172
173 SetJumpTarget(ptr);
174 // Not taken
175 WriteExit(GetCompilerPC() + 8, js.nextExit++);
176 }
177
178 js.compiling = false;
179 }
180
181
BranchRSZeroComp(MIPSOpcode op,CCFlags cc,bool andLink,bool likely)182 void ArmJit::BranchRSZeroComp(MIPSOpcode op, CCFlags cc, bool andLink, bool likely)
183 {
184 if (js.inDelaySlot) {
185 ERROR_LOG_REPORT(JIT, "Branch in RSZeroComp delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
186 return;
187 }
188 int offset = TARGET16;
189 MIPSGPReg rs = _RS;
190 u32 targetAddr = GetCompilerPC() + offset + 4;
191
192 bool immBranch = false;
193 bool immBranchTaken = false;
194 if (gpr.IsImm(rs)) {
195 // The cc flags are opposites: when NOT to take the branch.
196 bool immBranchNotTaken;
197 s32 imm = (s32)gpr.GetImm(rs);
198
199 switch (cc)
200 {
201 case CC_GT: immBranchNotTaken = imm > 0; break;
202 case CC_GE: immBranchNotTaken = imm >= 0; break;
203 case CC_LT: immBranchNotTaken = imm < 0; break;
204 case CC_LE: immBranchNotTaken = imm <= 0; break;
205 default: immBranchNotTaken = false; _dbg_assert_msg_(false, "Bad cc flag in BranchRSZeroComp().");
206 }
207 immBranch = true;
208 immBranchTaken = !immBranchNotTaken;
209 }
210
211 if (jo.immBranches && immBranch && js.numInstructions < jo.continueMaxInstructions) {
212 if (!immBranchTaken) {
213 // Skip the delay slot if likely, otherwise it'll be the next instruction.
214 if (andLink)
215 gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);
216 if (likely)
217 js.compilerPC += 4;
218 return;
219 }
220
221 // Branch taken. Always compile the delay slot, and then go to dest.
222 if (andLink)
223 gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);
224 CompileDelaySlot(DELAYSLOT_NICE);
225
226 AddContinuedBlock(targetAddr);
227 // Account for the increment in the loop.
228 js.compilerPC = targetAddr - 4;
229 // In case the delay slot was a break or something.
230 js.compiling = true;
231 return;
232 }
233
234 MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
235 js.downcountAmount += MIPSGetInstructionCycleEstimate(delaySlotOp);
236 bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
237 CONDITIONAL_NICE_DELAYSLOT;
238
239 if (immBranch) {
240 // Continuing is handled above, this is just static jumping.
241 if (andLink)
242 gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);
243 if (immBranchTaken || !likely)
244 CompileDelaySlot(DELAYSLOT_FLUSH);
245 else
246 FlushAll();
247
248 const u32 destAddr = immBranchTaken ? targetAddr : GetCompilerPC() + 8;
249 WriteExit(destAddr, js.nextExit++);
250 } else {
251 if (!likely && delaySlotIsNice)
252 CompileDelaySlot(DELAYSLOT_NICE);
253
254 gpr.MapReg(rs);
255 CMP(gpr.R(rs), Operand2(0, TYPE_IMM));
256
257 if (andLink)
258 gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);
259
260 ArmGen::FixupBranch ptr;
261 if (!likely)
262 {
263 if (!delaySlotIsNice)
264 CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
265 else
266 FlushAll();
267 ptr = B_CC(cc);
268 }
269 else
270 {
271 FlushAll();
272 ptr = B_CC(cc);
273 CompileDelaySlot(DELAYSLOT_FLUSH);
274 }
275
276 // Take the branch
277 WriteExit(targetAddr, js.nextExit++);
278
279 SetJumpTarget(ptr);
280 // Not taken
281 WriteExit(GetCompilerPC() + 8, js.nextExit++);
282 }
283 js.compiling = false;
284 }
285
286
Comp_RelBranch(MIPSOpcode op)287 void ArmJit::Comp_RelBranch(MIPSOpcode op)
288 {
289 // The CC flags here should be opposite of the actual branch becuase they skip the branching action.
290 switch (op >> 26)
291 {
292 case 4: BranchRSRTComp(op, CC_NEQ, false); break;//beq
293 case 5: BranchRSRTComp(op, CC_EQ, false); break;//bne
294
295 case 6: BranchRSZeroComp(op, CC_GT, false, false); break;//blez
296 case 7: BranchRSZeroComp(op, CC_LE, false, false); break;//bgtz
297
298 case 20: BranchRSRTComp(op, CC_NEQ, true); break;//beql
299 case 21: BranchRSRTComp(op, CC_EQ, true); break;//bnel
300
301 case 22: BranchRSZeroComp(op, CC_GT, false, true); break;//blezl
302 case 23: BranchRSZeroComp(op, CC_LE, false, true); break;//bgtzl
303
304 default:
305 _dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");
306 break;
307 }
308 }
309
Comp_RelBranchRI(MIPSOpcode op)310 void ArmJit::Comp_RelBranchRI(MIPSOpcode op)
311 {
312 switch ((op >> 16) & 0x1F)
313 {
314 case 0: BranchRSZeroComp(op, CC_GE, false, false); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltz
315 case 1: BranchRSZeroComp(op, CC_LT, false, false); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgez
316 case 2: BranchRSZeroComp(op, CC_GE, false, true); break; //if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 8; break;//bltzl
317 case 3: BranchRSZeroComp(op, CC_LT, false, true); break; //if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 8; break;//bgezl
318 case 16: BranchRSZeroComp(op, CC_GE, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else PC += 4; break;//bltzal
319 case 17: BranchRSZeroComp(op, CC_LT, true, false); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else PC += 4; break;//bgezal
320 case 18: BranchRSZeroComp(op, CC_GE, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) < 0) DelayBranchTo(addr); else SkipLikely(); break;//bltzall
321 case 19: BranchRSZeroComp(op, CC_LT, true, true); break; //R(MIPS_REG_RA) = PC + 8; if ((s32)R(rs) >= 0) DelayBranchTo(addr); else SkipLikely(); break;//bgezall
322 default:
323 _dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");
324 break;
325 }
326 }
327
328 // If likely is set, discard the branch slot if NOT taken.
BranchFPFlag(MIPSOpcode op,CCFlags cc,bool likely)329 void ArmJit::BranchFPFlag(MIPSOpcode op, CCFlags cc, bool likely)
330 {
331 if (js.inDelaySlot) {
332 ERROR_LOG_REPORT(JIT, "Branch in FPFlag delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
333 return;
334 }
335 int offset = TARGET16;
336 u32 targetAddr = GetCompilerPC() + offset + 4;
337
338 MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
339 js.downcountAmount += MIPSGetInstructionCycleEstimate(delaySlotOp);
340 bool delaySlotIsNice = IsDelaySlotNiceFPU(op, delaySlotOp);
341 CONDITIONAL_NICE_DELAYSLOT;
342 if (!likely && delaySlotIsNice)
343 CompileDelaySlot(DELAYSLOT_NICE);
344
345 gpr.MapReg(MIPS_REG_FPCOND);
346 TST(gpr.R(MIPS_REG_FPCOND), Operand2(1, TYPE_IMM));
347
348 ArmGen::FixupBranch ptr;
349 if (!likely)
350 {
351 if (!delaySlotIsNice)
352 CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
353 else
354 FlushAll();
355 ptr = B_CC(cc);
356 }
357 else
358 {
359 FlushAll();
360 ptr = B_CC(cc);
361 CompileDelaySlot(DELAYSLOT_FLUSH);
362 }
363
364 // Take the branch
365 WriteExit(targetAddr, js.nextExit++);
366
367 SetJumpTarget(ptr);
368 // Not taken
369 WriteExit(GetCompilerPC() + 8, js.nextExit++);
370 js.compiling = false;
371 }
372
Comp_FPUBranch(MIPSOpcode op)373 void ArmJit::Comp_FPUBranch(MIPSOpcode op)
374 {
375 switch((op >> 16) & 0x1f)
376 {
377 case 0: BranchFPFlag(op, CC_NEQ, false); break; // bc1f
378 case 1: BranchFPFlag(op, CC_EQ, false); break; // bc1t
379 case 2: BranchFPFlag(op, CC_NEQ, true); break; // bc1fl
380 case 3: BranchFPFlag(op, CC_EQ, true); break; // bc1tl
381 default:
382 _dbg_assert_msg_(false,"Trying to interpret instruction that can't be interpreted");
383 break;
384 }
385 }
386
387 // If likely is set, discard the branch slot if NOT taken.
BranchVFPUFlag(MIPSOpcode op,CCFlags cc,bool likely)388 void ArmJit::BranchVFPUFlag(MIPSOpcode op, CCFlags cc, bool likely)
389 {
390 if (js.inDelaySlot) {
391 ERROR_LOG_REPORT(JIT, "Branch in VFPU delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
392 return;
393 }
394 int offset = TARGET16;
395 u32 targetAddr = GetCompilerPC() + offset + 4;
396
397 MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
398 js.downcountAmount += MIPSGetInstructionCycleEstimate(delaySlotOp);
399
400 // Sometimes there's a VFPU branch in a delay slot (Disgaea 2: Dark Hero Days, Zettai Hero Project, La Pucelle)
401 // The behavior is undefined - the CPU may take the second branch even if the first one passes.
402 // However, it does consistently try each branch, which these games seem to expect.
403 bool delaySlotIsBranch = MIPSCodeUtils::IsVFPUBranch(delaySlotOp);
404 bool delaySlotIsNice = !delaySlotIsBranch && IsDelaySlotNiceVFPU(op, delaySlotOp);
405 CONDITIONAL_NICE_DELAYSLOT;
406 if (!likely && delaySlotIsNice)
407 CompileDelaySlot(DELAYSLOT_NICE);
408 if (delaySlotIsBranch && (signed short)(delaySlotOp & 0xFFFF) != (signed short)(op & 0xFFFF) - 1)
409 ERROR_LOG_REPORT(JIT, "VFPU branch in VFPU delay slot at %08x with different target", GetCompilerPC());
410
411 int imm3 = (op >> 18) & 7;
412
413 gpr.MapReg(MIPS_REG_VFPUCC);
414 TST(gpr.R(MIPS_REG_VFPUCC), Operand2(1 << imm3, TYPE_IMM));
415
416 ArmGen::FixupBranch ptr;
417 js.inDelaySlot = true;
418 if (!likely)
419 {
420 if (!delaySlotIsNice && !delaySlotIsBranch)
421 CompileDelaySlot(DELAYSLOT_SAFE_FLUSH);
422 else
423 FlushAll();
424 ptr = B_CC(cc);
425 }
426 else
427 {
428 FlushAll();
429 ptr = B_CC(cc);
430 if (!delaySlotIsBranch)
431 CompileDelaySlot(DELAYSLOT_FLUSH);
432 }
433 js.inDelaySlot = false;
434
435 // Take the branch
436 WriteExit(targetAddr, js.nextExit++);
437
438 SetJumpTarget(ptr);
439 // Not taken
440 u32 notTakenTarget = GetCompilerPC() + (delaySlotIsBranch ? 4 : 8);
441 WriteExit(notTakenTarget, js.nextExit++);
442 js.compiling = false;
443 }
444
Comp_VBranch(MIPSOpcode op)445 void ArmJit::Comp_VBranch(MIPSOpcode op)
446 {
447 switch ((op >> 16) & 3)
448 {
449 case 0: BranchVFPUFlag(op, CC_NEQ, false); break; // bvf
450 case 1: BranchVFPUFlag(op, CC_EQ, false); break; // bvt
451 case 2: BranchVFPUFlag(op, CC_NEQ, true); break; // bvfl
452 case 3: BranchVFPUFlag(op, CC_EQ, true); break; // bvtl
453 }
454 }
455
HitInvalidJump(uint32_t dest)456 static void HitInvalidJump(uint32_t dest) {
457 Core_ExecException(dest, currentMIPS->pc - 8, ExecExceptionType::JUMP);
458 }
459
Comp_Jump(MIPSOpcode op)460 void ArmJit::Comp_Jump(MIPSOpcode op) {
461 if (js.inDelaySlot) {
462 ERROR_LOG_REPORT(JIT, "Branch in Jump delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
463 return;
464 }
465 u32 off = TARGET26;
466 u32 targetAddr = (GetCompilerPC() & 0xF0000000) | off;
467
468 // Might be a stubbed address or something?
469 if (!Memory::IsValidAddress(targetAddr)) {
470 if (js.nextExit == 0) {
471 ERROR_LOG_REPORT(JIT, "Jump to invalid address: %08x", targetAddr);
472 } else {
473 js.compiling = false;
474 }
475 // TODO: Mark this block dirty or something? May be indication it will be changed by imports.
476 CompileDelaySlot(DELAYSLOT_NICE);
477 FlushAll();
478 gpr.SetRegImm(SCRATCHREG1, GetCompilerPC() + 8);
479 MovToPC(SCRATCHREG1);
480 MOVI2R(R0, targetAddr);
481 QuickCallFunction(SCRATCHREG2, &HitInvalidJump);
482 WriteSyscallExit();
483 return;
484 }
485
486 switch (op >> 26) {
487 case 2: //j
488 CompileDelaySlot(DELAYSLOT_NICE);
489 if (jo.continueJumps && js.numInstructions < jo.continueMaxInstructions) {
490 AddContinuedBlock(targetAddr);
491 // Account for the increment in the loop.
492 js.compilerPC = targetAddr - 4;
493 // In case the delay slot was a break or something.
494 js.compiling = true;
495 return;
496 }
497 FlushAll();
498 WriteExit(targetAddr, js.nextExit++);
499 break;
500
501 case 3: //jal
502 if (ReplaceJalTo(targetAddr))
503 return;
504
505 gpr.SetImm(MIPS_REG_RA, GetCompilerPC() + 8);
506 CompileDelaySlot(DELAYSLOT_NICE);
507 if (jo.continueJumps && js.numInstructions < jo.continueMaxInstructions) {
508 AddContinuedBlock(targetAddr);
509 // Account for the increment in the loop.
510 js.compilerPC = targetAddr - 4;
511 // In case the delay slot was a break or something.
512 js.compiling = true;
513 return;
514 }
515 FlushAll();
516 WriteExit(targetAddr, js.nextExit++);
517 break;
518
519 default:
520 _dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");
521 break;
522 }
523 js.compiling = false;
524 }
525
Comp_JumpReg(MIPSOpcode op)526 void ArmJit::Comp_JumpReg(MIPSOpcode op)
527 {
528 if (js.inDelaySlot) {
529 ERROR_LOG_REPORT(JIT, "Branch in JumpReg delay slot at %08x in block starting at %08x", GetCompilerPC(), js.blockStart);
530 return;
531 }
532 MIPSGPReg rs = _RS;
533 MIPSGPReg rd = _RD;
534 bool andLink = (op & 0x3f) == 9 && rd != MIPS_REG_ZERO;
535
536 MIPSOpcode delaySlotOp = GetOffsetInstruction(1);
537 js.downcountAmount += MIPSGetInstructionCycleEstimate(delaySlotOp);
538 bool delaySlotIsNice = IsDelaySlotNiceReg(op, delaySlotOp, rs);
539 if (andLink && rs == rd)
540 delaySlotIsNice = false;
541 CONDITIONAL_NICE_DELAYSLOT;
542
543 ARMReg destReg = R8;
544 if (IsSyscall(delaySlotOp)) {
545 gpr.MapReg(rs);
546 MovToPC(gpr.R(rs)); // For syscall to be able to return.
547 if (andLink)
548 gpr.SetImm(rd, GetCompilerPC() + 8);
549 CompileDelaySlot(DELAYSLOT_FLUSH);
550 return; // Syscall wrote exit code.
551 } else if (delaySlotIsNice) {
552 if (andLink)
553 gpr.SetImm(rd, GetCompilerPC() + 8);
554 CompileDelaySlot(DELAYSLOT_NICE);
555
556 if (!andLink && rs == MIPS_REG_RA && g_Config.bDiscardRegsOnJRRA) {
557 // According to the MIPS ABI, there are some regs we don't need to preserve.
558 // Let's discard them so we don't need to write them back.
559 // NOTE: Not all games follow the MIPS ABI! Tekken 6, for example, will crash
560 // with this enabled.
561 gpr.DiscardR(MIPS_REG_COMPILER_SCRATCH);
562 for (int i = MIPS_REG_A0; i <= MIPS_REG_T7; i++)
563 gpr.DiscardR((MIPSGPReg)i);
564 gpr.DiscardR(MIPS_REG_T8);
565 gpr.DiscardR(MIPS_REG_T9);
566 }
567
568 if (jo.continueJumps && gpr.IsImm(rs) && js.numInstructions < jo.continueMaxInstructions) {
569 AddContinuedBlock(gpr.GetImm(rs));
570 // Account for the increment in the loop.
571 js.compilerPC = gpr.GetImm(rs) - 4;
572 // In case the delay slot was a break or something.
573 js.compiling = true;
574 return;
575 }
576
577 gpr.MapReg(rs);
578 destReg = gpr.R(rs); // Safe because FlushAll doesn't change any regs
579 FlushAll();
580 } else {
581 // Delay slot - this case is very rare, might be able to free up R8.
582 gpr.MapReg(rs);
583 MOV(R8, gpr.R(rs));
584 if (andLink)
585 gpr.SetImm(rd, GetCompilerPC() + 8);
586 CompileDelaySlot(DELAYSLOT_NICE);
587 FlushAll();
588 }
589
590 switch (op & 0x3f)
591 {
592 case 8: //jr
593 break;
594 case 9: //jalr
595 break;
596 default:
597 _dbg_assert_msg_(false,"Trying to compile instruction that can't be compiled");
598 break;
599 }
600
601 WriteExitDestInR(destReg);
602 js.compiling = false;
603 }
604
605
Comp_Syscall(MIPSOpcode op)606 void ArmJit::Comp_Syscall(MIPSOpcode op)
607 {
608 if (op.encoding == 0x03FFFFcc) {
609 WARN_LOG(JIT, "Encountered bad syscall instruction at %08x (%08x)", js.compilerPC, op.encoding);
610 }
611
612 if (!g_Config.bSkipDeadbeefFilling)
613 {
614 // All of these will be overwritten with DEADBEEF anyway.
615 gpr.DiscardR(MIPS_REG_COMPILER_SCRATCH);
616 // We need to keep A0 - T3, which are used for args.
617 gpr.DiscardR(MIPS_REG_T4);
618 gpr.DiscardR(MIPS_REG_T5);
619 gpr.DiscardR(MIPS_REG_T6);
620 gpr.DiscardR(MIPS_REG_T7);
621 gpr.DiscardR(MIPS_REG_T8);
622 gpr.DiscardR(MIPS_REG_T9);
623
624 gpr.DiscardR(MIPS_REG_HI);
625 gpr.DiscardR(MIPS_REG_LO);
626 }
627
628 // If we're in a delay slot, this is off by one.
629 const int offset = js.inDelaySlot ? -1 : 0;
630 WriteDownCount(offset);
631 RestoreRoundingMode();
632 js.downcountAmount = -offset;
633
634 if (!js.inDelaySlot) {
635 gpr.SetRegImm(SCRATCHREG1, GetCompilerPC() + 4);
636 MovToPC(SCRATCHREG1);
637 }
638
639 FlushAll();
640
641 SaveDowncount();
642 #ifdef USE_PROFILER
643 // When profiling, we can't skip CallSyscall, since it times syscalls.
644 gpr.SetRegImm(R0, op.encoding);
645 QuickCallFunction(R1, (void *)&CallSyscall);
646 #else
647 // Skip the CallSyscall where possible.
648 void *quickFunc = GetQuickSyscallFunc(op);
649 if (quickFunc)
650 {
651 gpr.SetRegImm(R0, (u32)(intptr_t)GetSyscallFuncPointer(op));
652 // Already flushed, so R1 is safe.
653 QuickCallFunction(R1, quickFunc);
654 }
655 else
656 {
657 gpr.SetRegImm(R0, op.encoding);
658 QuickCallFunction(R1, (void *)&CallSyscall);
659 }
660 #endif
661 ApplyRoundingMode();
662 RestoreDowncount();
663
664 WriteSyscallExit();
665 js.compiling = false;
666 }
667
Comp_Break(MIPSOpcode op)668 void ArmJit::Comp_Break(MIPSOpcode op)
669 {
670 Comp_Generic(op);
671 WriteSyscallExit();
672 js.compiling = false;
673 }
674
675 } // namespace Mipscomp
676
677 #endif // PPSSPP_ARCH(ARM)
678