1 /*
2 * scpu64meminit.c -- Initialize SCPU64 memory.
3 *
4 * Written by
5 * Kajtar Zsolt <soci@c64.rulez.org>
6 *
7 * This file is part of VICE, the Versatile Commodore Emulator.
8 * See README for copyright notice.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
23 * 02111-1307 USA.
24 *
25 */
26
27 #include "vice.h"
28
29 #include <stdio.h>
30
31 #include "c64cart.h"
32 #include "c64cartmem.h"
33 #include "c64cia.h"
34 #include "scpu64mem.h"
35 #include "scpu64rom.h"
36 #include "scpu64meminit.h"
37 #include "cartio.h"
38 #include "sid.h"
39 #include "vicii-mem.h"
40
41 /*
42
43 missing: BA,CAS(not needed),RW(through tables),AEC
44
45 bit 7 - boot
46 bit 6 - dos
47 bit 5 - hw
48 bit 4 - !game
49 bit 3 - !exrom
50 bit 2 - loram
51 bit 1 - hiram
52 bit 0 - charen
53
54 */
55
56 enum {
57 R0, /* SRAM bank 0 */
58 R1, /* SRAM bank 1 */
59 RC, /* RAM */
60 UM, /* Ultimax */
61 RL, /* ROML */
62 RH, /* ROML */
63 IO, /* I/O */
64 CR, /* CHARROM */
65 F8, /* EPROM */
66 KS, /* Kernal shadow */
67 KT, /* Kernal trap */
68 CO, /* Color RAM */
69 OP, /* Internal Color RAM */
70 };
71
72 #define AREAS 10
73 static const unsigned int areas[AREAS][2] = {
74 { 0x00, 0x0f },
75 { 0x10, 0x5f },
76 { 0x60, 0x7f },
77 { 0x80, 0x9f },
78 { 0xa0, 0xbf },
79 { 0xc0, 0xcf },
80 { 0xd0, 0xd7 },
81 { 0xd8, 0xdb },
82 { 0xdc, 0xdf },
83 { 0xe0, 0xff }
84 };
85
86 static const uint8_t config[AREAS][256] =
87 {
88 { /* 0000-0fff */
89 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
90 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
91 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
92 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
93 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
94 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
95 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
96 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
97 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
98 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
99 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
100 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
101 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
102 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
103 RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC,
104 RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC },
105 { /* 1000-5fff */
106 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
107 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
108 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
109 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
110 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
111 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
112 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
113 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
114 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
115 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
116 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
117 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
118 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
119 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
120 RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC,
121 UM, UM, UM, UM, UM, UM, UM, UM, RC, RC, RC, RC, RC, RC, RC, RC },
122 { /* 6000-7fff */
123 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
124 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
125 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
126 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
127 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
128 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
129 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
130 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
131 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
132 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
133 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
134 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
135 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
136 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
137 RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC,
138 UM, UM, UM, UM, UM, UM, UM, UM, RC, RC, RC, RC, RC, RC, RC, RC },
139 { /* 8000-9fff */
140 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, RL, R0, R0, R0, RL,
141 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, RL, R0, R0, R0, RL,
142 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, RL, R0, R0, R0, RL,
143 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, RL, R0, R0, R0, RL,
144 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
145 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
146 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
147 R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1, R1,
148 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
149 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
150 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
151 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
152 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
153 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
154 RC, RC, RC, RC, RC, RC, RC, RC, RL, RL, RL, RL, RL, RL, RL, RL,
155 UM, UM, UM, UM, UM, UM, UM, UM, RL, RL, RL, RL, RL, RL, RL, RL },
156 { /* a000-bfff */
157 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1,
158 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, RH, RH, R0, R0, RH, RH,
159 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1,
160 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, RH, RH, R0, R0, RH, RH,
161 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1,
162 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, RH, RH, R0, R0, RH, RH,
163 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, R0, R1,
164 R0, R0, R0, R1, R0, R0, R0, R1, R0, R0, RH, RH, R0, R0, RH, RH,
165 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
166 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
167 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
168 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
169 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
170 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
171 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
172 UM, UM, UM, UM, UM, UM, UM, UM, RH, RH, RH, RH, RH, RH, RH, RH },
173 { /* c000-cfff */
174 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
175 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
176 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
177 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
178 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
179 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
180 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
181 R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0, R0,
182 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
183 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
184 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
185 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
186 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
187 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
188 RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC, RC,
189 UM, UM, UM, UM, UM, UM, UM, UM, RC, RC, RC, RC, RC, RC, RC, RC },
190 { /* d000-d7ff */
191 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
192 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
193 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
194 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
195 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
196 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
197 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
198 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
199 F8, CR, CR, CR, F8, IO, IO, IO, F8, CR, CR, CR, F8, IO, IO, IO,
200 F8, CR, CR, CR, F8, IO, IO, IO, F8, F8, CR, CR, F8, IO, IO, IO,
201 F8, CR, CR, CR, F8, IO, IO, IO, F8, CR, CR, CR, F8, IO, IO, IO,
202 F8, CR, CR, CR, F8, IO, IO, IO, F8, F8, CR, CR, F8, IO, IO, IO,
203 F8, CR, CR, CR, F8, IO, IO, IO, F8, CR, CR, CR, F8, IO, IO, IO,
204 F8, CR, CR, CR, F8, IO, IO, IO, F8, F8, CR, CR, F8, IO, IO, IO,
205 CR, CR, CR, CR, CR, IO, IO, IO, CR, CR, CR, CR, CR, IO, IO, IO,
206 CR, CR, CR, CR, CR, IO, IO, IO, CR, CR, CR, CR, CR, IO, IO, IO },
207 { /* d800-dbff */
208 R0, CR, CR, CR, R0, CO, CO, CO, R0, CR, CR, CR, R0, CO, CO, CO,
209 R0, CR, CR, CR, R0, CO, CO, CO, R0, R0, CR, CR, R0, CO, CO, CO,
210 R0, CR, CR, CR, R0, CO, CO, CO, R0, CR, CR, CR, R0, CO, CO, CO,
211 R0, CR, CR, CR, R0, CO, CO, CO, R0, R0, CR, CR, R0, CO, CO, CO,
212 R0, CR, CR, CR, R0, CO, CO, CO, R0, CR, CR, CR, R0, CO, CO, CO,
213 R0, CR, CR, CR, R0, CO, CO, CO, R0, R0, CR, CR, R0, CO, CO, CO,
214 R0, CR, CR, CR, R0, CO, CO, CO, R0, CR, CR, CR, R0, CO, CO, CO,
215 R0, CR, CR, CR, R0, CO, CO, CO, R0, R0, CR, CR, R0, CO, CO, CO,
216 F8, CR, CR, CR, F8, CO, CO, CO, F8, CR, CR, CR, F8, CO, CO, CO,
217 F8, CR, CR, CR, F8, CO, CO, CO, F8, F8, CR, CR, F8, CO, CO, CO,
218 F8, CR, CR, CR, F8, CO, CO, CO, F8, CR, CR, CR, F8, CO, CO, CO,
219 F8, CR, CR, CR, F8, CO, CO, CO, F8, F8, CR, CR, F8, CO, CO, CO,
220 F8, CR, CR, CR, F8, CO, CO, CO, F8, CR, CR, CR, F8, CO, CO, CO,
221 F8, CR, CR, CR, F8, CO, CO, CO, F8, F8, CR, CR, F8, CO, CO, CO,
222 CR, CR, CR, CR, CR, OP, OP, OP, CR, CR, CR, CR, CR, OP, OP, OP,
223 CR, CR, CR, CR, CR, OP, OP, OP, CR, CR, CR, CR, CR, OP, OP, OP },
224 { /* dc00-dfff */
225 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
226 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
227 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
228 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
229 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
230 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
231 R0, CR, CR, CR, R0, IO, IO, IO, R0, CR, CR, CR, R0, IO, IO, IO,
232 R0, CR, CR, CR, R0, IO, IO, IO, R0, R0, CR, CR, R0, IO, IO, IO,
233 F8, CR, CR, CR, F8, IO, IO, IO, F8, CR, CR, CR, F8, IO, IO, IO,
234 F8, CR, CR, CR, F8, IO, IO, IO, F8, F8, CR, CR, F8, IO, IO, IO,
235 F8, CR, CR, CR, F8, IO, IO, IO, F8, CR, CR, CR, F8, IO, IO, IO,
236 F8, CR, CR, CR, F8, IO, IO, IO, F8, F8, CR, CR, F8, IO, IO, IO,
237 F8, CR, CR, CR, F8, IO, IO, IO, F8, CR, CR, CR, F8, IO, IO, IO,
238 F8, CR, CR, CR, F8, IO, IO, IO, F8, F8, CR, CR, F8, IO, IO, IO,
239 CR, CR, CR, CR, CR, IO, IO, IO, CR, CR, CR, CR, CR, IO, IO, IO,
240 CR, CR, CR, CR, CR, IO, IO, IO, CR, CR, CR, CR, CR, IO, IO, IO },
241 { /* e000-ffff */
242 R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT,
243 R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT,
244 R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS,
245 R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS,
246 R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT,
247 R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT, R0, R0, KT, KT,
248 R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS,
249 R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS, R0, R0, KS, KS,
250 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
251 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
252 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
253 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
254 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
255 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
256 F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8, F8,
257 UM, UM, UM, UM, UM, UM, UM, UM, F8, F8, F8, F8, F8, F8, F8, F8 }
258 };
259
scpu64meminit(void)260 void scpu64meminit(void)
261 {
262 unsigned int i, j, k;
263
264 for (i = 0; i < AREAS; i++) {
265 for (j = areas[i][0]; j <= areas[i][1]; j++) {
266 for (k = 0; k < 256; k++) {
267 switch (config[i][k]) {
268 case R0:
269 mem_read_tab_set(k, j, ram_read);
270 mem_read_base_set(k, j, mem_sram);
271 /* write hook preset, ram */
272 break;
273 case R1:
274 mem_read_tab_set(k, j, ram1_read);
275 mem_read_base_set(k, j, mem_sram + 0x10000);
276 /* write hook preset, ram */
277 break;
278 case KT:
279 mem_read_tab_set(k, j, ram1_read);
280 mem_read_base_set(k, j, mem_trap_ram - 0xe000);
281 /* write hook preset, ram */
282 break;
283 case KS:
284 mem_read_tab_set(k, j, scpu64_kernalshadow_read);
285 mem_read_base_set(k, j, mem_sram + 0x8000);
286 /* write hook preset, ram */
287 break;
288 case RC:
289 mem_read_tab_set(k, j, ram_read_int);
290 mem_read_base_set(k, j, mem_ram);
291 mem_set_write_hook(k, i, ram_store_int);
292 break;
293 case UM:
294 switch (j & 0xf0) {
295 default:
296 mem_read_tab_set(k, j, scpu64_ultimax_1000_7fff_read);
297 mem_read_base_set(k, j, NULL);
298 mem_set_write_hook(k, i, scpu64_ultimax_1000_7fff_store);
299 break;
300 case 0x80:
301 case 0x90:
302 mem_read_tab_set(k, j, scpu64_roml_read);
303 mem_read_base_set(k, j, NULL);
304 mem_set_write_hook(k, j, scpu64_roml_store);
305 break;
306 case 0xa0:
307 case 0xb0:
308 mem_read_tab_set(k, j, scpu64_ultimax_a000_bfff_read);
309 mem_read_base_set(k, j, NULL);
310 mem_set_write_hook(k, i, scpu64_ultimax_a000_bfff_store);
311 break;
312 case 0xc0:
313 mem_read_tab_set(k, j, scpu64_ultimax_c000_cfff_read);
314 mem_read_base_set(k, j, NULL);
315 mem_set_write_hook(k, i, scpu64_ultimax_c000_cfff_store);
316 break;
317 case 0xe0:
318 case 0xf0:
319 mem_read_tab_set(k, j, scpu64_romh_read);
320 mem_read_base_set(k, j, NULL);
321 mem_set_write_hook(k, j, scpu64_romh_store);
322 break;
323 }
324 break;
325 case RL:
326 mem_read_tab_set(k, j, scpu64_roml_read);
327 mem_read_base_set(k, j, NULL);
328 /* write hook preset, ram */
329 break;
330 case RH:
331 mem_read_tab_set(k, j, scpu64_romh_read);
332 mem_read_base_set(k, j, NULL);
333 /* write hook preset, ram */
334 break;
335 case IO:
336 switch (j) {
337 case 0xd0:
338 mem_read_tab_set(k, j, scpu64io_d000_read);
339 mem_read_base_set(k, j, NULL);
340 mem_set_write_hook(k, j, scpu64io_d000_store);
341 break;
342 case 0xd1:
343 mem_read_tab_set(k, j, scpu64io_d100_read);
344 mem_read_base_set(k, j, NULL);
345 mem_set_write_hook(k, j, scpu64io_d100_store);
346 break;
347 case 0xd2:
348 mem_read_tab_set(k, j, scpu64io_d200_read);
349 mem_read_base_set(k, j, mem_sram + 0x10000);
350 mem_set_write_hook(k, j, scpu64io_d200_store);
351 break;
352 case 0xd3:
353 mem_read_tab_set(k, j, scpu64io_d300_read);
354 mem_read_base_set(k, j, mem_sram + 0x10000);
355 mem_set_write_hook(k, j, scpu64io_d300_store);
356 break;
357 case 0xd4:
358 mem_read_tab_set(k, j, scpu64io_d400_read);
359 mem_read_base_set(k, j, NULL);
360 mem_set_write_hook(k, j, scpu64io_d400_store);
361 break;
362 case 0xd5:
363 mem_read_tab_set(k, j, scpu64io_d500_read);
364 mem_read_base_set(k, j, NULL);
365 mem_set_write_hook(k, j, scpu64io_d500_store);
366 break;
367 case 0xd6:
368 mem_read_tab_set(k, j, scpu64io_d600_read);
369 mem_read_base_set(k, j, NULL);
370 mem_set_write_hook(k, j, scpu64io_d600_store);
371 break;
372 case 0xd7:
373 mem_read_tab_set(k, j, scpu64io_d700_read);
374 mem_read_base_set(k, j, NULL);
375 mem_set_write_hook(k, j, scpu64io_d700_store);
376 break;
377 case 0xdc:
378 mem_read_tab_set(k, j, scpu64_cia1_read);
379 mem_read_base_set(k, j, NULL);
380 mem_set_write_hook(k, j, scpu64_cia1_store);
381 break;
382 case 0xdd:
383 mem_read_tab_set(k, j, scpu64_cia2_read);
384 mem_read_base_set(k, j, NULL);
385 mem_set_write_hook(k, j, scpu64_cia2_store);
386 break;
387 case 0xde:
388 mem_read_tab_set(k, j, scpu64io_de00_read);
389 mem_read_base_set(k, j, NULL);
390 mem_set_write_hook(k, j, scpu64io_de00_store);
391 break;
392 case 0xdf:
393 mem_read_tab_set(k, j, scpu64io_df00_read);
394 mem_read_base_set(k, j, NULL);
395 mem_set_write_hook(k, j, scpu64io_df00_store);
396 break;
397 }
398 break;
399 case CO:
400 mem_read_tab_set(k, j, scpu64io_colorram_read);
401 mem_read_base_set(k, j, mem_sram + 0x10000);
402 mem_set_write_hook(k, j, scpu64io_colorram_store);
403 break;
404 case OP:
405 mem_read_tab_set(k, j, scpu64io_colorram_read_int);
406 mem_read_base_set(k, j, NULL);
407 mem_set_write_hook(k, j, scpu64io_colorram_store_int);
408 break;
409 case F8:
410 mem_read_tab_set(k, j, scpu64rom_scpu64_read);
411 mem_read_base_set(k, j, scpu64rom_scpu64_rom);
412 /* write hook preset, ram */
413 break;
414 case CR:
415 mem_read_tab_set(k, j, chargen_read);
416 mem_read_base_set(k, j, mem_chargen_rom - 0xd000);
417 /* write hook preset, ram */
418 break;
419 }
420 }
421 }
422 }
423 }
424