1 // license:BSD-3-Clause
2 // copyright-holders:Barry Rodewald
3 /*
4  *  Gravis Ultrasound ISA card
5  *
6  *  Started: 28/01/2012
7  */
8 
9 
10 #include "emu.h"
11 #include "gus.h"
12 
13 #include "bus/midi/midi.h"
14 #include "machine/clock.h"
15 #include "speaker.h"
16 
17 
18 #define IRQ_2XF           0x00
19 #define IRQ_MIDI_TRANSMIT 0x01
20 #define IRQ_MIDI_RECEIVE  0x02
21 #define IRQ_TIMER1        0x04
22 #define IRQ_TIMER2        0x08
23 #define IRQ_SB            0x10
24 #define IRQ_WAVETABLE     0x20
25 #define IRQ_VOLUME_RAMP   0x40
26 #define IRQ_DRAM_TC_DMA   0x80
27 
28 //**************************************************************************
29 //  GLOBAL VARIABLES
30 //**************************************************************************
31 
32 // uncomment this to save wave RAM content to a file
33 //#define SAVE_WAVE_RAM 1
34 //#define LOG_SOUND 1
35 
36 static const uint16_t volume_ramp_table[4] =
37 {
38 	1, 8, 64, 512
39 };
40 
41 DEFINE_DEVICE_TYPE(GGF1,      gf1_device,       "gf1",     "Gravis GF1")
42 DEFINE_DEVICE_TYPE(ISA16_GUS, isa16_gus_device, "isa_gus", "Gravis Ultrasound")
43 
44 #ifdef LOG_SOUND
45 FILE* f;
46 #endif
47 
update_irq()48 void gf1_device::update_irq()
49 {
50 	int txirq = calculate_txirq();
51 
52 	if (m_txirq != txirq)
53 	{
54 		m_txirq = txirq;
55 		m_txirq_handler(!m_txirq);
56 	}
57 
58 	int rxirq = calculate_rxirq();
59 
60 	if (m_rxirq != rxirq)
61 	{
62 		m_rxirq = rxirq;
63 		m_rxirq_handler(!m_rxirq);
64 	}
65 }
66 
67 /* only the Adlib timers are implemented in hardware */
adlib_r(offs_t offset)68 uint8_t gf1_device::adlib_r(offs_t offset)
69 {
70 	uint8_t retVal = 0xff;
71 	switch(offset)
72 	{
73 		case 0:
74 //          if(m_timer_ctrl & 0x01)
75 				return m_adlib_status;
76 //          return m_fake_adlib_status;
77 		case 1:
78 			return m_adlib_data;
79 	}
80 	return retVal;
81 }
82 
adlib_w(offs_t offset,uint8_t data)83 void gf1_device::adlib_w(offs_t offset, uint8_t data)
84 {
85 	switch(offset)
86 	{
87 		case 0:
88 			m_adlib_cmd = data;
89 			break;
90 		case 1:
91 			if(m_adlib_cmd == 0x04 && !(m_timer_ctrl & 0x01))
92 			{
93 				if(data & 0x80)
94 				{
95 					m_timer1_irq_handler(0);
96 					m_timer2_irq_handler(0);
97 					m_adlib_status &= ~0xe0;
98 					logerror("GUS: Timer flags reset\n");
99 				}
100 				else
101 				{
102 					if((data & 0x01) && !(data & 0x40))
103 					{
104 						m_adlib_timer1_enable = 1;
105 						m_timer1->adjust(attotime::zero,0,attotime::from_usec(80));
106 					}
107 					if((data & 0x02) && !(data & 0x20))
108 					{
109 						m_adlib_timer2_enable = 1;
110 						m_timer2->adjust(attotime::zero,0,attotime::from_usec(320));
111 					}
112 					if(!(data & 0x01) && !(data & 0x40))
113 					{
114 						m_adlib_timer1_enable = 0;
115 						m_timer1->reset();
116 					}
117 					if(!(data & 0x02) && !(data & 0x20))
118 					{
119 						m_adlib_timer2_enable = 0;
120 						m_timer2->reset();
121 					}
122 					logerror("GUS: Timer enable - %02x\n",data);
123 				}
124 				m_adlib_timer_cmd = data;
125 			}
126 			else
127 			{
128 				m_adlib_data = data;
129 				if(m_timer_ctrl & 0x02)
130 				{
131 					m_adlib_status |= 0x01;
132 					m_nmi_handler(1);
133 					logerror("GUS: 2X9 Timer triggered!\n");
134 				}
135 			}
136 			break;
137 	}
138 }
139 
update_volume_ramps()140 void gf1_device::update_volume_ramps()
141 {
142 	int x;
143 
144 	for(x=0;x<32;x++)
145 	{
146 		if(!(m_voice[x].vol_ramp_ctrl & 0x01))  // if ramping is enabled
147 		{
148 			m_voice[x].vol_count++;
149 			if(m_voice[x].vol_count % volume_ramp_table[(m_voice[x].vol_ramp_rate & 0xc0)>>6] == 0)
150 			{
151 				// increase/decrease volume
152 				if(m_voice[x].vol_ramp_ctrl & 0x40)
153 				{
154 					//m_voice[x].current_vol = (m_voice[x].current_vol & 0xf000) | ((m_voice[x].current_vol & 0x0ff0) + ((m_voice[x].vol_ramp_rate & 0x0f)<<8));
155 					m_voice[x].current_vol -= ((m_voice[x].vol_ramp_rate & 0x3f) << 4);
156 					if(m_voice[x].current_vol <= (m_voice[x].vol_ramp_start << 8))  // end of ramp?
157 					{
158 						if(m_voice[x].vol_ramp_ctrl & 0x08)
159 						{
160 							if(m_voice[x].vol_ramp_ctrl & 0x10)
161 							{
162 								m_voice[x].vol_ramp_ctrl &= ~0x40; // change direction and continue
163 								m_voice[x].current_vol = (m_voice[x].vol_ramp_start << 8);
164 							}
165 							else
166 								m_voice[x].current_vol = (m_voice[x].vol_ramp_end << 8);
167 						}
168 						else
169 						{
170 							m_voice[x].vol_ramp_ctrl |= 0x01;  // stop volume ramp
171 							m_voice[x].current_vol = (m_voice[x].vol_ramp_start << 8);
172 						}
173 						if(m_voice[x].vol_ramp_ctrl & 0x20)
174 							set_irq(IRQ_VOLUME_RAMP,x);
175 					}
176 				}
177 				else
178 				{
179 					//m_voice[x].current_vol = (m_voice[x].current_vol & 0xf000) | ((m_voice[x].current_vol & 0x0ff0) - ((m_voice[x].vol_ramp_rate & 0x0f)<<8));
180 					m_voice[x].current_vol += ((m_voice[x].vol_ramp_rate & 0x3f) << 4);
181 					if(m_voice[x].current_vol >= (m_voice[x].vol_ramp_end << 8))  // end of ramp?
182 					{
183 						if(m_voice[x].vol_ramp_ctrl & 0x08)
184 						{
185 							if(m_voice[x].vol_ramp_ctrl & 0x10)
186 							{
187 								m_voice[x].vol_ramp_ctrl |= 0x40; // change direction and continue
188 								m_voice[x].current_vol = (m_voice[x].vol_ramp_end << 8);
189 							}
190 							else
191 								m_voice[x].current_vol = (m_voice[x].vol_ramp_start << 8);
192 						}
193 						else
194 						{
195 							m_voice[x].vol_ramp_ctrl |= 0x01;  // stop volume ramp
196 							m_voice[x].current_vol = (m_voice[x].vol_ramp_end << 8);
197 						}
198 						if(m_voice[x].vol_ramp_ctrl & 0x20)
199 							set_irq(IRQ_VOLUME_RAMP,x);
200 					}
201 				}
202 			}
203 		}
204 	}
205 }
206 
device_timer(emu_timer & timer,device_timer_id id,int param,void * ptr)207 void gf1_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
208 {
209 	switch(id)
210 	{
211 	case ADLIB_TIMER1:
212 		if(m_adlib_timer1_enable != 0)
213 		{
214 			if(m_timer1_count == 0xff)
215 			{
216 				m_adlib_status |= 0xc0;
217 				m_timer1_count = m_timer1_value;
218 				if(m_timer_ctrl & 0x04)
219 					m_timer1_irq_handler(1);
220 			}
221 			m_timer1_count++;
222 		}
223 		break;
224 	case ADLIB_TIMER2:
225 		if(m_adlib_timer2_enable != 0)
226 		{
227 			if(m_timer2_count == 0xff)
228 			{
229 				m_adlib_status |= 0xa0;
230 				m_timer2_count = m_timer2_value;
231 				if(m_timer_ctrl & 0x08)
232 					m_timer2_irq_handler(1);
233 			}
234 			m_timer2_count++;
235 		}
236 		break;
237 	case DMA_TIMER:
238 		m_drq1_handler(1);
239 		break;
240 	case VOL_RAMP_TIMER:
241 		update_volume_ramps();
242 		break;
243 	}
244 }
245 
sound_stream_update(sound_stream & stream,std::vector<read_stream_view> const & inputs,std::vector<write_stream_view> & outputs)246 void gf1_device::sound_stream_update(sound_stream &stream, std::vector<read_stream_view> const &inputs, std::vector<write_stream_view> &outputs)
247 {
248 	int x;
249 	//uint32_t count;
250 
251 	auto &outputl = outputs[0];
252 	auto &outputr = outputs[1];
253 
254 	outputl.fill(0);
255 	outputr.fill(0);
256 
257 	for(x=0;x<32;x++)  // for each voice
258 	{
259 		uint16_t vol = (m_volume_table[(m_voice[x].current_vol & 0xfff0) >> 4]);
260 		for (int sampindex = 0; sampindex < outputl.samples(); sampindex++)
261 		{
262 			uint32_t current = m_voice[x].current_addr >> 9;
263 			// TODO: implement proper panning
264 			outputl.add_int(sampindex, m_voice[x].sample * vol, 32768 * 8192);
265 			outputr.add_int(sampindex, m_voice[x].sample * vol, 32768 * 8192);
266 			if((!(m_voice[x].voice_ctrl & 0x40)) && (m_voice[x].current_addr >= m_voice[x].end_addr) && !m_voice[x].rollover && !(m_voice[x].voice_ctrl & 0x01))
267 			{
268 				if(m_voice[x].vol_ramp_ctrl & 0x04)
269 				{
270 					m_voice[x].rollover = true;  // set roll over condition - generate IRQ, but keep voice playing
271 				}
272 
273 				if(m_voice[x].voice_ctrl & 0x20)
274 					set_irq(IRQ_WAVETABLE,x);
275 
276 				// end voice, unless looping, or rollover is active, which disables looping
277 				if(!m_voice[x].rollover)
278 				{
279 					if(!(m_voice[x].voice_ctrl & 0x08))
280 					{
281 						m_voice[x].voice_ctrl |= 0x01;
282 //                        m_voice[x].current_addr = m_voice[x].end_addr;
283 					}
284 				}
285 				// looping is not supposed to happen when rollover is active, but the Windows drivers have other ideas...
286 				if(m_voice[x].voice_ctrl & 0x08)
287 				{
288 					if(m_voice[x].voice_ctrl & 0x10)
289 						m_voice[x].voice_ctrl |= 0x40; // change direction
290 					else
291 						m_voice[x].current_addr = m_voice[x].start_addr; // start sample again
292 				}
293 			}
294 			if((m_voice[x].voice_ctrl & 0x40) && (m_voice[x].current_addr <= m_voice[x].start_addr) && !m_voice[x].rollover && !(m_voice[x].voice_ctrl & 0x01))
295 			{
296 				if(m_voice[x].vol_ramp_ctrl & 0x04)
297 				{
298 					m_voice[x].rollover = true;  // set roll over condition - generate IRQ, but keep voice playing
299 				}
300 
301 				if(m_voice[x].voice_ctrl & 0x20)
302 					set_irq(IRQ_WAVETABLE,x);
303 
304 				// end voice, unless looping, or rollover is active, which disables looping
305 				if(!m_voice[x].rollover)
306 				{
307 					// end voice, unless looping
308 					if(!(m_voice[x].voice_ctrl & 0x08))
309 					{
310 						m_voice[x].voice_ctrl |= 0x01;
311 //                          m_voice[x].current_addr = m_voice[x].start_addr;
312 					}
313 				}
314 				// looping is not supposed to happen when rollover is active, but the Windows drivers have other ideas...
315 				if(m_voice[x].voice_ctrl & 0x08)
316 				{
317 					if(m_voice[x].voice_ctrl & 0x10)
318 						m_voice[x].voice_ctrl &= ~0x40; // change direction
319 					else
320 						m_voice[x].current_addr = m_voice[x].end_addr; // start sample again
321 				}
322 			}
323 			if(!(m_voice[x].voice_ctrl & 0x01))
324 			{
325 				if(m_voice[x].voice_ctrl & 0x04)
326 				{  // 16-bit PCM
327 					current = ((m_voice[x].current_addr >> 9) & 0xc0000) + (((m_voice[x].current_addr >> 9) & 0x1ffff) << 1);
328 					m_voice[x].sample = (int16_t)((m_wave_ram[current & 0xffffe]) | ((m_wave_ram[(current & 0xffffe)+1])<<8));
329 				}
330 				else
331 				{  // 8-bit PCM
332 					m_voice[x].sample = (int16_t)(m_wave_ram[current & 0xfffff] << 8);
333 				}
334 				if(m_voice[x].voice_ctrl & 0x40)  // voice direction
335 					m_voice[x].current_addr -= (m_voice[x].freq_ctrl >> 1);
336 				else
337 					m_voice[x].current_addr += (m_voice[x].freq_ctrl >> 1);
338 			}
339 #ifdef LOG_SOUND
340 			int16_t smp = (m_voice[x].sample) * (vol / 8192.0);
341 			fwrite(&smp,4,1,f);
342 #endif
343 		}
344 	}
345 }
346 
347 //**************************************************************************
348 //  LIVE DEVICE
349 //**************************************************************************
350 
351 //-------------------------------------------------
352 //  gf1_device - constructor
353 //-------------------------------------------------
354 
gf1_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)355 gf1_device::gf1_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
356 	acia6850_device(mconfig, GGF1, tag, owner, clock),
357 	device_sound_interface(mconfig, *this),
358 	m_dma_dram_ctrl(0), m_dma_start_addr(0), m_dram_addr(0), m_timer_ctrl(0), m_timer1_count(0), m_timer2_count(0), m_timer1_value(0), m_timer2_value(0), m_sampling_freq(0), m_sampling_ctrl(0), m_joy_trim_dac(0), m_reset(0), m_active_voices(14), m_irq_source(0),
359 	m_stream(nullptr),
360 	m_timer1(nullptr), m_timer2(nullptr), m_dmatimer(nullptr), m_voltimer(nullptr),
361 	m_current_voice(0), m_current_reg(0), m_adlib_cmd(0), m_mix_ctrl(0), m_gf1_irq(0), m_midi_irq(0), m_dma_channel1(0), m_dma_channel2(0), m_irq_combine(0), m_dma_combine(0), m_adlib_timer_cmd(0), m_adlib_timer1_enable(0), m_adlib_timer2_enable(0), m_adlib_status(0), m_adlib_data(0), m_voice_irq_ptr(0), m_voice_irq_current(0), m_dma_16bit(0), m_statread(0), m_sb_data_2xc(0), m_sb_data_2xe(0), m_reg_ctrl(0), m_fake_adlib_status(0), m_dma_current(0), m_txirq(0), m_rxirq(0),
362 	m_txirq_handler(*this),
363 	m_rxirq_handler(*this),
364 	m_wave_irq_handler(*this),
365 	m_ramp_irq_handler(*this),
366 	m_timer1_irq_handler(*this),
367 	m_timer2_irq_handler(*this),
368 	m_sb_irq_handler(*this),
369 	m_dma_irq_handler(*this),
370 	m_drq1_handler(*this),
371 	m_drq2_handler(*this),
372 	m_nmi_handler(*this)
373 {
374 }
375 
376 //-------------------------------------------------
377 //  device_start - device-specific startup
378 //-------------------------------------------------
379 
device_start()380 void gf1_device::device_start()
381 {
382 	acia6850_device::device_start();
383 
384 	int i;
385 	double out = (double)(1 << 13);
386 
387 	m_txirq_handler.resolve_safe();
388 	m_rxirq_handler.resolve_safe();
389 	m_wave_irq_handler.resolve_safe();
390 	m_ramp_irq_handler.resolve_safe();
391 	m_timer1_irq_handler.resolve_safe();
392 	m_timer2_irq_handler.resolve_safe();
393 	m_sb_irq_handler.resolve_safe();
394 	m_dma_irq_handler.resolve_safe();
395 	m_drq1_handler.resolve_safe();
396 	m_drq2_handler.resolve_safe();
397 	m_nmi_handler.resolve_safe();
398 
399 	// TODO: make DRAM size configurable.  Can be 256k, 512k, 768k, or 1024k
400 	m_wave_ram.resize(1024*1024);
401 	memset(&m_wave_ram[0], 0, 1024*1024);
402 
403 	m_stream = stream_alloc(0,2,clock() / (14 * 16));
404 
405 	// init timers
406 	m_timer1 = timer_alloc(ADLIB_TIMER1);
407 	m_timer2 = timer_alloc(ADLIB_TIMER2);
408 	m_dmatimer = timer_alloc(DMA_TIMER);
409 	m_voltimer = timer_alloc(VOL_RAMP_TIMER);
410 
411 	save_item(NAME(m_wave_ram));
412 
413 	m_voice_irq_current = 0;
414 	m_voice_irq_ptr = 0;
415 	m_dma_channel1 = 0;
416 	m_dma_channel2 = 0;
417 	m_gf1_irq = 0;
418 	m_midi_irq = 0;
419 
420 	for (i=4095;i>=0;i--)
421 	{
422 		m_volume_table[i] = (int16_t)out;
423 		out /= 1.002709201; /* 0.0235 dB Steps */
424 	}
425 
426 #ifdef LOG_SOUND
427 	f = fopen("soundlog.bin","wb");
428 #endif
429 }
430 
431 //-------------------------------------------------
432 //  device_reset - device-specific reset
433 //-------------------------------------------------
434 
device_reset()435 void gf1_device::device_reset()
436 {
437 	int x;
438 
439 	memset(m_voice, 0x00, sizeof(m_voice));
440 	// init voices
441 	for(x=0;x<32;x++)
442 	{
443 		m_voice[x].voice_ctrl = 0x01;  // stop all voices
444 		m_voice[x].vol_ramp_ctrl = 0x01; // stop all volume ramps
445 		m_voice[x].current_vol = 0;  // silence all voices
446 	}
447 	m_irq_source = 0xe0;
448 	m_reg_ctrl = 0;
449 	m_active_voices = 14;
450 	m_stream->set_sample_rate(clock() / (m_active_voices * 16));
451 	m_voltimer->adjust(attotime::zero,0,attotime::from_usec(1000/(1.6*m_active_voices)));
452 }
453 
device_stop()454 void gf1_device::device_stop()
455 {
456 #ifdef SAVE_WAVE_RAM
457 	FILE* f;
458 	f=fopen("waveout.bin","wb");
459 	fwrite(m_wave_ram,1024*1024,1,f);
460 	fclose(f);
461 #endif
462 #ifdef LOG_SOUND
463 	fclose(f);
464 #endif
465 }
466 
device_clock_changed()467 void gf1_device::device_clock_changed()
468 {
469 	m_stream->set_sample_rate(clock() / (m_active_voices * 16));
470 }
471 // ------------------------------------------------
472 //   device I/O handlers
473 // ------------------------------------------------
474 
global_reg_select_r(offs_t offset)475 uint8_t gf1_device::global_reg_select_r(offs_t offset)
476 {
477 	if(offset == 0)
478 		return m_current_voice;
479 	else
480 		return m_current_reg | 0xc0;
481 }
482 
global_reg_select_w(offs_t offset,uint8_t data)483 void gf1_device::global_reg_select_w(offs_t offset, uint8_t data)
484 {
485 	if(offset == 0)
486 		m_current_voice = data & 0x1f;
487 	else
488 		m_current_reg = data;
489 }
490 
global_reg_data_r(offs_t offset)491 uint8_t gf1_device::global_reg_data_r(offs_t offset)
492 {
493 	uint16_t ret;
494 
495 	switch(m_current_reg)
496 	{
497 	case 0x41:  // DMA DRAM control
498 		if(offset == 1)
499 		{
500 			ret = m_dma_dram_ctrl;
501 			m_dma_dram_ctrl &= ~0x40;
502 			m_dma_irq_handler(0);
503 			return ret;
504 		}
505 	case 0x45:  // Timer control
506 		if(offset == 1)
507 			return m_timer_ctrl & 0x0c;
508 		break;
509 	case 0x49:  // Sampling control
510 		if(offset == 1)
511 			return m_sampling_ctrl & 0xe7;
512 	case 0x4c:  // Reset
513 		if(offset == 1)
514 			return m_reset;
515 	case 0x80: // Voice control
516 /* bit 0 - 1 if voice is stopped
517  * bit 6 - 1 if addresses are decreasing, can change when looping is enabled
518  * bit 7 - 1 if Wavetable IRQ is pending */
519 		if(offset == 1)
520 			return m_voice[m_current_voice].voice_ctrl & 0xff;
521 	case 0x81:  // Frequency Control
522 		ret = m_voice[m_current_voice].freq_ctrl;
523 		if(offset == 0)
524 			return ret & 0x00ff;
525 		else
526 			return (ret >> 8) & 0x00ff;
527 	case 0x82:  // Starting address (high 13 bits)
528 		ret = (m_voice[m_current_voice].start_addr >> 16);
529 		if(offset == 0)
530 			return ret & 0x00ff;
531 		else
532 			return (ret >> 8) & 0x00ff;
533 	case 0x83:  // Starting address (low 7 bits plus 4 bits fractional)
534 		ret = (m_voice[m_current_voice].start_addr & 0xffff);
535 		if(offset == 0)
536 			return ret & 0x00ff;
537 		else
538 			return (ret >> 8) & 0x00ff;
539 	case 0x84:  // End address (high 13 bits)
540 		ret = (m_voice[m_current_voice].end_addr >> 16);
541 		if(offset == 0)
542 			return ret & 0x00ff;
543 		else
544 			return (ret >> 8) & 0x00ff;
545 	case 0x85:  // End address (low 7 bits plus 4 bits fractional)
546 		ret = (m_voice[m_current_voice].end_addr & 0xffff);
547 		if(offset == 0)
548 			return ret & 0x00ff;
549 		else
550 			return (ret >> 8) & 0x00ff;
551 	case 0x86:  // Volume Ramp rate
552 		if(offset == 1)
553 			return m_voice[m_current_voice].vol_ramp_rate;
554 	case 0x87:  // Volume Ramp start (high 4 bits = exponent, low 4 bits = mantissa)
555 		if(offset == 1)
556 			return m_voice[m_current_voice].vol_ramp_start;
557 	case 0x88:  // Volume Ramp end (high 4 bits = exponent, low 4 bits = mantissa)
558 		if(offset == 1)
559 			return m_voice[m_current_voice].vol_ramp_end;
560 	case 0x89:  // Current Volume (high 4 bits = exponent, middle 8 bits = mantissa, low 4 bits = 0 [reserved])
561 		ret = m_voice[m_current_voice].current_vol;
562 		if(offset == 0)
563 			return ret & 0x00ff;
564 		else
565 			return (ret >> 8) & 0x00ff;
566 	case 0x8a:  // Current position (high 13 bits)
567 		ret = (m_voice[m_current_voice].current_addr >> 16);
568 		if(offset == 0)
569 			return ret & 0x00ff;
570 		else
571 			return (ret >> 8) & 0x00ff;
572 	case 0x8b:  // Current position (low 7 bits, plus 9 bit fractional)
573 		ret = (m_voice[m_current_voice].current_addr & 0xffff);
574 		if(offset == 0)
575 			return ret & 0x00ff;
576 		else
577 			return (ret >> 8) & 0x00ff;
578 	case 0x8c:  // Pan position (4 bits, 0=full left, 15=full right)
579 		if(offset == 1)
580 			return m_voice[m_current_voice].pan_position;
581 	case 0x8d:  // Volume Ramp control
582 /* bit 0 - Ramp has stopped
583  * bit 6 - Ramp direction
584  * bit 7 - Ramp IRQ pending */
585 		if(offset == 1)
586 			return m_voice[m_current_voice].vol_ramp_ctrl;
587 	case 0x8e:  // Active voices (6 bits, high 2 bits are always 1)
588 		if(offset == 1)
589 			return (m_active_voices - 1) | 0xc0;
590 	case 0x8f:  // IRQ source register
591 		if(offset == 1)
592 		{
593 			ret = m_voice_irq_fifo[m_voice_irq_current % 32];
594 			if((m_voice_irq_current % 32) != (m_voice_irq_ptr % 32))
595 				m_voice_irq_current++;
596 			else
597 				ret = 0xe0;
598 			m_wave_irq_handler(0);
599 			m_ramp_irq_handler(0);
600 			return ret;
601 		}
602 		break;
603 	default:
604 		logerror("GUS: Read from unimplemented or unknown global register %02x\n",m_current_reg);
605 		return 0xff;
606 	}
607 	return 0xff;
608 }
609 
global_reg_data_w(offs_t offset,uint8_t data)610 void gf1_device::global_reg_data_w(offs_t offset, uint8_t data)
611 {
612 	switch(m_current_reg)
613 	{
614 	case 0x00: // Voice control
615 /* bit 1 - set to 1 to stop current voice
616  * bit 2 - set to 1 for 16-bit wave data, otherwise is 8-bit
617  * bit 3 - set to 1 to loop to start address when the end address is reached
618  * bit 4 - set to 1 to enable bi-directional looping
619  * bit 5 - set to 1 to enable wavetable IRQ when end address is reached */
620 		if(offset == 1)
621 		{
622 			m_voice[m_current_voice].voice_ctrl = data & 0xff;
623 			m_voice[m_current_voice].rollover = false;
624 			if(data & 0x02)
625 				m_voice[m_current_voice].voice_ctrl |= 0x01;
626 		}
627 		logerror("GUS: Ch%i Voice control write %02x\n", m_current_voice,data);
628 		break;
629 	case 0x01: // Frequency Control
630 /* bits 15-10 - Integer portion
631  * bits 9-1   - Fractional portion
632  * bit 0      - not used */
633 		if(offset == 0)
634 			m_voice[m_current_voice].freq_ctrl = (m_voice[m_current_voice].freq_ctrl & 0xff00) | data;
635 		else
636 			m_voice[m_current_voice].freq_ctrl = (m_voice[m_current_voice].freq_ctrl & 0x00ff) | (data << 8);
637 		logerror("GUS: Ch%i Frequency control write %04x\n", m_current_voice, m_voice[m_current_voice].freq_ctrl);
638 		break;
639 	case 0x02:  // Starting address (high 13 bits)
640 		if(offset == 0)
641 			m_voice[m_current_voice].start_addr = (m_voice[m_current_voice].start_addr & 0xff00ffff) | (data << 16);
642 		else
643 			m_voice[m_current_voice].start_addr = (m_voice[m_current_voice].start_addr & 0x00ffffff) | (data << 24);
644 		logerror("GUS: Ch%i [high] Start address set to %08x\n", m_current_voice,m_voice[m_current_voice].start_addr);
645 		break;
646 	case 0x03:  // Starting address (low 7 bits plus 4 bits fractional)
647 		if(offset == 0)
648 			m_voice[m_current_voice].start_addr = (m_voice[m_current_voice].start_addr & 0xffffff00) | data;
649 		else
650 			m_voice[m_current_voice].start_addr = (m_voice[m_current_voice].start_addr & 0xffff00ff) | (data << 8);
651 		logerror("GUS: Ch%i [low] Start address set to %08x\n", m_current_voice,m_voice[m_current_voice].start_addr);
652 		break;
653 	case 0x04:  // End address (high 13 bits)
654 		if(offset == 0)
655 			m_voice[m_current_voice].end_addr = (m_voice[m_current_voice].end_addr & 0xff00ffff) | (data << 16);
656 		else
657 			m_voice[m_current_voice].end_addr = (m_voice[m_current_voice].end_addr & 0x00ffffff) | (data << 24);
658 		logerror("GUS: Ch%i [high] End address set to %08x\n", m_current_voice,m_voice[m_current_voice].end_addr);
659 		break;
660 	case 0x05:  // End address (low 7 bits plus 4 bits fractional)
661 		if(offset == 0)
662 			m_voice[m_current_voice].end_addr = (m_voice[m_current_voice].end_addr & 0xffffff00) | data;
663 		else
664 			m_voice[m_current_voice].end_addr = (m_voice[m_current_voice].end_addr & 0xffff00ff) | (data << 8);
665 		logerror("GUS: Ch%i [low] End address set to %08x\n", m_current_voice,m_voice[m_current_voice].end_addr);
666 		break;
667 	case 0x06:  // Volume Ramp rate
668 		if(offset == 1)
669 			m_voice[m_current_voice].vol_ramp_rate = data;
670 		logerror("GUS: Ch%i Volume ramp rate write %02x\n", m_current_voice,data);
671 		break;
672 	case 0x07:  // Volume Ramp start (high 4 bits = exponent, low 4 bits = mantissa)
673 		if(offset == 1)
674 			m_voice[m_current_voice].vol_ramp_start = data;
675 		logerror("GUS: Ch%i Volume ramp start write %02x\n", m_current_voice, data);
676 		break;
677 	case 0x08:  // Volume Ramp end (high 4 bits = exponent, low 4 bits = mantissa)
678 		if(offset == 1)
679 			m_voice[m_current_voice].vol_ramp_end = data;
680 		logerror("GUS: Ch%i Volume ramp end write %02x\n", m_current_voice, data);
681 		break;
682 	case 0x09:  // Current Volume (high 4 bits = exponent, middle 8 bits = mantissa, low 4 bits = 0 [reserved])
683 		if(offset == 0)
684 			m_voice[m_current_voice].current_vol = (m_voice[m_current_voice].current_vol & 0xff00) | data;
685 		else
686 			m_voice[m_current_voice].current_vol = (m_voice[m_current_voice].current_vol & 0x00ff) | (data << 8);
687 		logerror("GUS: Ch%i Current volume write %02x\n", m_current_voice, data);
688 		break;
689 	case 0x0a:  // Current position (high 13 bits)
690 		if(offset == 0)
691 			m_voice[m_current_voice].current_addr = (m_voice[m_current_voice].current_addr & 0xff00ffff) | (data << 16);
692 		else
693 			m_voice[m_current_voice].current_addr = (m_voice[m_current_voice].current_addr & 0x00ffffff) | (data << 24);
694 		logerror("GUS: Ch%i Current address write %08x\n", m_current_voice, m_voice[m_current_voice].current_addr);
695 		break;
696 	case 0x0b:  // Current position (low 7 bits, plus 9 bit fractional)
697 		if(offset == 0)
698 			m_voice[m_current_voice].current_addr = (m_voice[m_current_voice].current_addr & 0xffffff00) | data;
699 		else
700 			m_voice[m_current_voice].current_addr = (m_voice[m_current_voice].current_addr & 0xffff00ff) | (data << 8);
701 		logerror("GUS: Ch%i Current address write %08x\n", m_current_voice, m_voice[m_current_voice].current_addr);
702 		break;
703 	case 0x0c:  // Pan position (4 bits, 0=full left, 15=full right)
704 		if(offset == 1)
705 			m_voice[m_current_voice].pan_position = data & 0x0f;
706 		logerror("GUS: Ch%i Pan Position write %02x\n", m_current_voice, data);
707 		break;
708 	case 0x0d:  // Volume Ramp control
709 /* bit 1 - set to 1 to stop the ramp
710  * bit 2 - roll over condition (generate IRQ, and not stop playing voice, no looping)
711  * bit 3 - enable looping
712  * bit 4 - enable bi-directional looping
713  * bit 5 - rnable IRQ at end of ramp */
714 		if(offset == 1)
715 		{
716 			m_voice[m_current_voice].vol_ramp_ctrl = data & 0x7f;
717 			if(!(data & 0x01))
718 			{
719 				m_voice[m_current_voice].vol_count = 0;
720 				if(m_voice[m_current_voice].vol_ramp_ctrl & 0x40)
721 					m_voice[m_current_voice].current_vol = (m_voice[m_current_voice].vol_ramp_end << 8);
722 				else
723 					m_voice[m_current_voice].current_vol = (m_voice[m_current_voice].vol_ramp_start << 8);
724 			}
725 			if(data & 0x02)
726 			{
727 				m_voice[m_current_voice].vol_ramp_ctrl |= 0x01;
728 			}
729 		}
730 		logerror("GUS: Ch%i Volume Ramp control write %02x\n", m_current_voice, data);
731 		break;
732 	case 0x0e:  // Active voices (6 bits, high 2 bits are always 1)
733 		if(offset == 1)
734 		{
735 			m_active_voices = (data & 0x3f) + 1;
736 			if(m_active_voices < 14)
737 				m_active_voices = 14;
738 			if(m_active_voices > 32)
739 				m_active_voices = 32;
740 			m_stream->set_sample_rate(clock() / (m_active_voices * 16));
741 			m_voltimer->adjust(attotime::zero,0,attotime::from_usec(1000/(1.6*m_active_voices)));
742 		}
743 		logerror("GUS: Active Voices write %02x (%d voices at %u Hz)\n", data, m_active_voices, clock() / (m_active_voices * 16));
744 		break;
745 	case 0x41:
746 /* bit 0 - Enable the DMA channel.
747  * bit 1 - DMA transfer direction (1 = read from the GUS)
748  * bit 2 - DMA channel width (0=8-bit, 1=16-bit)
749  * bits 3,4 - DMA rate divider
750  * bit 5 - DMA terminal count IRQ enable
751  * bit 6 - DMA terminal count IRQ pending (read), Data size (write, 0=8bit, 1=16-bit, independent of channel size)
752  * bit 7 - Invert MSB of data
753  */
754 		if(offset == 1)
755 		{
756 			m_dma_dram_ctrl = data & 0xbf;
757 			m_dma_16bit = data & 0x40;
758 			if(data & 0x01)
759 			{
760 				m_dmatimer->adjust(attotime::zero,0,attotime::from_nsec(11489));  // based on 680Kb/sec mentioned in UltraMID docs
761 				logerror("GUS: DMA start from DRAM address 0x%05x\n",m_dma_start_addr<<4);
762 			}
763 			else
764 			{
765 				m_dmatimer->reset();  // stop transfer
766 				logerror("GUS: DMA aborted.\n");
767 			}
768 		}
769 		logerror("GUS: DMA DRAM control write %02x\n",data);
770 		break;
771 	case 0x42:  // DMA start address (high 16 bits, address lines 4-19)
772 		if(offset == 0)
773 			m_dma_start_addr = (m_dma_start_addr & 0xff00) | data;
774 		else
775 			m_dma_start_addr = (m_dma_start_addr & 0x00ff) | (data << 8);
776 		m_dma_current = m_dma_start_addr << 4;
777 		logerror("GUS: DMA start address set to %08x\n",m_dma_start_addr);
778 		break;
779 	case 0x43:  // DRAM I/O address (low 16 bits)
780 		if(offset == 0)
781 			m_dram_addr = (m_dram_addr & 0x000fff00) | data;
782 		else
783 			m_dram_addr = (m_dram_addr & 0x000f00ff) | (data << 8);
784 		//logerror("GUS: [low] DRAM I/O address set to %08x\n",m_dram_addr);
785 		break;
786 	case 0x44:  // DRAM I/O address (high 4 bits)
787 		if(offset == 1)
788 			m_dram_addr = (m_dram_addr & 0x0000ffff) | (data << 16);
789 		//logerror("GUS: [high] DRAM I/O address set to %08x\n",m_dram_addr);
790 		break;
791 	case 0x45:  // Timer control
792 /* bit 3 - Enable timer 1 IRQ
793  * bit 4 - Enable timer 2 IRQ */
794 		if(offset == 1)
795 		{
796 			m_timer_ctrl = data;
797 			if(!(data & 0x20))
798 				m_adlib_status &= ~0x18;
799 			if(!(data & 0x02))
800 				m_adlib_status &= ~0x01;
801 			if(!(m_adlib_status & 0x19))
802 				m_sb_irq_handler(0);
803 			if(!(data & 0x04))
804 			{
805 				m_adlib_status &= ~0x40;
806 				m_timer1_irq_handler(0);
807 			}
808 			if(!(data & 0x08))
809 			{
810 				m_adlib_status &= ~0x20;
811 				m_timer2_irq_handler(0);
812 			}
813 			if((m_adlib_status & 0x60) != 0)
814 				m_adlib_status &= ~0x80;
815 		}
816 		logerror("GUS: Timer control write %02x\n",data);
817 		break;
818 	case 0x46:  // Timer 1 count
819 		if(offset == 1)
820 		{
821 			m_timer1_count = data;
822 			m_timer1_value = data;
823 			logerror("GUS: Timer 1 count write %02x (%d usec)\n",data,data*80);
824 		}
825 		break;
826 	case 0x47:  // Timer 2 count
827 		if(offset == 1)
828 		{
829 			m_timer2_count = data;
830 			m_timer2_value = data;
831 			logerror("GUS: Timer 2 count write %02x (%d usec)\n",data,data*320);
832 		}
833 		break;
834 	case 0x48:  // Sampling Frequency - 9878400/(16*(FREQ+2))
835 		if(offset == 0)
836 			m_sampling_freq = (m_sampling_freq & 0xff00) | data;
837 		else
838 			m_sampling_freq = (m_sampling_freq & 0x00ff) | (data << 8);
839 		logerror("GUS: Sampling frequency write %02x\n",data);
840 		break;
841 	case 0x49: // Sampling control
842 /* bit 0 - Start sampling
843  * bit 1 - Mode (0=mono, 1=stereo)
844  * bit 2 - DMA width (0=8-bit, 1=16-bit)
845  * bit 5 - DMA IRQ enable
846  * bit 6 - DMA IRQ pending (read only)
847  * bit 7 - Invert MSB */
848 		if(offset == 1)
849 			m_sampling_ctrl = data;
850 		logerror("GUS: Sampling control write %02x\n",data);
851 		break;
852 	case 0x4b:  // Joystick trim DAC
853 		if(offset == 1)
854 			m_joy_trim_dac = data;
855 		logerror("GUS: Joystick trim DAC write %02x\n",data);
856 		break;
857 	case 0x4c:  // Reset
858 		if(offset == 1)
859 		{
860 			if(!(data & 0x01))
861 				device_reset();
862 			m_reset = data & 0xf9;
863 		}
864 		logerror("GUS: Reset write %02x\n",data);
865 		break;
866 	default:
867 		logerror("GUS: Write %02x to unimplemented or unknown global register %02x\n",data,m_current_reg);
868 	}
869 }
870 
871 /* port 0x3X7 - DRAM I/O
872  * read and write bytes directly to wavetable DRAM */
dram_r(offs_t offset)873 uint8_t gf1_device::dram_r(offs_t offset)
874 {
875 	if(offset == 1)
876 	{
877 		return m_wave_ram[m_dram_addr & 0xfffff];
878 	}
879 	else
880 		return 0xff;
881 }
882 
dram_w(offs_t offset,uint8_t data)883 void gf1_device::dram_w(offs_t offset, uint8_t data)
884 {
885 	if(offset == 1)
886 	{
887 		m_wave_ram[m_dram_addr & 0xfffff] = data;
888 	}
889 }
890 
891 /* port 2XA - read selected adlib command?
892  * the GUS driver installation writes 0x55 to port 0x388, then expects to reads the same from 0x2XA */
adlib_cmd_r(offs_t offset)893 uint8_t gf1_device::adlib_cmd_r(offs_t offset)
894 {
895 	if(offset == 0)
896 	{
897 		return m_adlib_cmd;
898 	}
899 	else
900 	{
901 		// TODO
902 		return 0xff;
903 	}
904 }
905 
906 /* port 0x2XB - set IRQ/DMA latch
907  * if IRQ (bit 6 of 0x2X0 = 1)
908  * bits 2-0 = channel 1 (GF1) IRQ selector
909  * 0 = reserved, 1 = IRQ2, 2 = IRQ5, 3 = IRQ3, 4 = IRQ7, 5 = IRQ11, 6 = IRQ12, 7 = IRQ13
910  * bits 5-3 = channel 2 (MIDI) IRQ selector
911  * 0 = No interrupt selected, rest are as for the GF1
912  * bit 6 = combine both IRQs using channel 1 IRQ
913  * if DMA (bit 6 of 0x2X0 = 0)
914  * bits 2-0 = DMA select register 1
915  * 0 = No DMA, 1 = DMA1, 2 = DMA3, 3 = DMA5, 4 = DMA6, 5 = DMA7
916  * bits 5-3 = DMA select register 2 (values same as reg 1)
917  * bit 6 = combine both on same DMA channel
918  */
adlib_cmd_w(offs_t offset,uint8_t data)919 void gf1_device::adlib_cmd_w(offs_t offset, uint8_t data)
920 {
921 	if(offset == 1)
922 	{
923 		switch(m_reg_ctrl & 0x07)
924 		{
925 		case 0x00:
926 			if(m_mix_ctrl & 0x40)
927 			{
928 				switch(data & 0x07)
929 				{
930 				case 1:
931 					m_gf1_irq = 2;
932 					break;
933 				case 2:
934 					m_gf1_irq = 5;
935 					break;
936 				case 3:
937 					m_gf1_irq = 3;
938 					break;
939 				case 4:
940 					m_gf1_irq = 7;
941 					break;
942 				case 5:
943 					m_gf1_irq = 11;
944 					break;
945 				case 6:
946 					m_gf1_irq = 12;
947 					break;
948 				case 7:
949 					m_gf1_irq = 15;
950 					break;
951 				default:
952 					m_gf1_irq = 0;
953 					logerror("GUS: Invalid GF1 IRQ set! [%02x]\n",data);
954 				}
955 				switch((data >> 3) & 0x07)
956 				{
957 				case 0:
958 					m_midi_irq = 0;
959 					break;
960 				case 1:
961 					m_midi_irq = 2;
962 					break;
963 				case 2:
964 					m_midi_irq = 5;
965 					break;
966 				case 3:
967 					m_midi_irq = 3;
968 					break;
969 				case 4:
970 					m_midi_irq = 7;
971 					break;
972 				case 5:
973 					m_midi_irq = 11;
974 					break;
975 				case 6:
976 					m_midi_irq = 12;
977 					break;
978 				case 7:
979 					m_midi_irq = 15;
980 					break;
981 				default:
982 					logerror("GUS: Invalid MIDI IRQ set! [%02x]\n",data);
983 				}
984 				if(data & 0x40)
985 					m_irq_combine = 1;
986 				else
987 					m_irq_combine = 0;
988 				logerror("GUS: IRQs set: GF1 = IRQ%i, MIDI = IRQ%i\n",m_gf1_irq,m_midi_irq);
989 			}
990 			else
991 			{
992 				switch(data & 0x07)
993 				{
994 				case 0:
995 					m_dma_channel1 = 0;
996 					break;
997 				case 1:
998 					m_dma_channel1 = 1;
999 					break;
1000 				case 2:
1001 					m_dma_channel1 = 3;
1002 					break;
1003 				case 3:
1004 					m_dma_channel1 = 5;
1005 					break;
1006 				case 4:
1007 					m_dma_channel1 = 6;
1008 					break;
1009 				case 5:
1010 					m_dma_channel1 = 7;
1011 					break;
1012 				default:
1013 					logerror("GUS: Invalid DMA channel #1 set! [%02x]\n",data);
1014 				}
1015 				switch((data >> 3) & 0x07)
1016 				{
1017 				case 0:
1018 					m_dma_channel2 = 0;
1019 					break;
1020 				case 1:
1021 					m_dma_channel2 = 1;
1022 					break;
1023 				case 2:
1024 					m_dma_channel2 = 3;
1025 					break;
1026 				case 3:
1027 					m_dma_channel2 = 5;
1028 					break;
1029 				case 4:
1030 					m_dma_channel2 = 6;
1031 					break;
1032 				case 5:
1033 					m_dma_channel2 = 7;
1034 					break;
1035 				default:
1036 					logerror("GUS: Invalid DMA channel #2 set! [%02x]\n",data);
1037 				}
1038 				if(data & 0x40)
1039 					m_dma_combine = 1;
1040 				else
1041 					m_dma_combine = 0;
1042 				logerror("GUS: DMA channels set: DMA%i, DMA%i\n",m_dma_channel1,m_dma_channel2);
1043 			}
1044 			break;
1045 		case 0x05:
1046 			m_statread = 0;
1047 			//m_other_irq_handler(0);
1048 			break;
1049 		case 0x06:
1050 			// TODO: Jumper register (joy/MIDI enable)
1051 			break;
1052 		}
1053 	}
1054 	else
1055 	{
1056 		m_fake_adlib_status = data;
1057 		logerror("GUS: Adlib status set to %02x\n",data);
1058 	}
1059 }
1060 
1061 /* port 0x2X0 - Mix control register
1062  * bit 0 - 0=Enable Line In
1063  * bit 1 - 0=Enable Line Out
1064  * bit 2 - 1=Enable MIC In
1065  * bit 3 - Enable latches (once enabled, must remain enabled)
1066  * bit 4 - Combine GF1 IRQs with MIDI IRQs
1067  * bit 5 - Enable MIDI TxD to RxD loopback
1068  * bit 6 - Control Reg Select - set next I/O write to 0x2XB to be DMA (0) or IRQ (1) channel latches */
mix_ctrl_r(offs_t offset)1069 uint8_t gf1_device::mix_ctrl_r(offs_t offset)
1070 {
1071 	return 0xff;  // read only
1072 }
1073 
mix_ctrl_w(offs_t offset,uint8_t data)1074 void gf1_device::mix_ctrl_w(offs_t offset, uint8_t data)
1075 {
1076 	if(offset == 0)
1077 		m_mix_ctrl = data;
1078 }
1079 
sb_r(offs_t offset)1080 uint8_t gf1_device::sb_r(offs_t offset)
1081 {
1082 	uint8_t val;
1083 
1084 	switch(offset)
1085 	{
1086 	case 0x00:
1087 		val = m_sb_data_2xc;
1088 		if(m_statread & 0x20)
1089 			m_sb_data_2xc ^= 0x80;  // flip MSB on read
1090 		return val;
1091 	// port 0x2XD is write-only
1092 	case 0x02:
1093 		if(m_reg_ctrl & 0x80)
1094 		{
1095 			m_statread |= 0x80;
1096 			m_nmi_handler(1);
1097 		}
1098 		return m_sb_data_2xe;
1099 	}
1100 	return 0xff;
1101 }
1102 
sb_w(offs_t offset,uint8_t data)1103 void gf1_device::sb_w(offs_t offset, uint8_t data)
1104 {
1105 	switch(offset)
1106 	{
1107 	case 0x00:
1108 		if(m_timer_ctrl & 0x20)
1109 		{
1110 			m_adlib_status |= 0x10;
1111 			m_nmi_handler(1);
1112 			logerror("GUS: SB 0x2XC IRQ active\n");
1113 		}
1114 		break;
1115 	case 0x01:
1116 		m_sb_data_2xc = data;
1117 		break;
1118 	case 0x02:
1119 		m_sb_data_2xe = data;
1120 		break;
1121 	}
1122 }
1123 
sb2x6_w(uint8_t data)1124 void gf1_device::sb2x6_w(uint8_t data)
1125 {
1126 	if(m_timer_ctrl & 0x20)
1127 	{
1128 		m_adlib_status |= 0x08;
1129 		m_nmi_handler(1);
1130 		logerror("GUS: SB 0x2X6 IRQ active\n");
1131 	}
1132 }
1133 
stat_r()1134 uint8_t gf1_device::stat_r()
1135 {
1136 	uint8_t val = m_statread & 0xf9;
1137 	if(m_mix_ctrl & 0x08)
1138 		val |= 0x02;
1139 	return val;
1140 }
1141 
stat_w(uint8_t data)1142 void gf1_device::stat_w(uint8_t data)
1143 {
1144 	m_reg_ctrl = data;
1145 }
1146 
set_irq(uint8_t source,uint8_t voice)1147 void gf1_device::set_irq(uint8_t source, uint8_t voice)
1148 {
1149 	if(source & IRQ_WAVETABLE)
1150 	{
1151 		m_irq_source = 0xe0 | (voice & 0x1f);
1152 		m_irq_source &= ~0x80;
1153 		m_wave_irq_handler(1);
1154 		m_voice_irq_fifo[m_voice_irq_ptr % 32] = m_irq_source;
1155 		m_voice_irq_ptr++;
1156 		m_voice[voice].voice_ctrl |= 0x80;
1157 	}
1158 	if(source & IRQ_VOLUME_RAMP)
1159 	{
1160 		m_irq_source = 0xe0 | (voice & 0x1f);
1161 		m_irq_source &= ~0x40;
1162 		m_ramp_irq_handler(1);
1163 		m_voice_irq_fifo[m_voice_irq_ptr % 32] = m_irq_source;
1164 		m_voice_irq_ptr++;
1165 	}
1166 }
1167 
reset_irq(uint8_t source)1168 void gf1_device::reset_irq(uint8_t source)
1169 {
1170 	if(source & IRQ_WAVETABLE)
1171 	{
1172 		m_irq_source |= 0x80;
1173 		m_wave_irq_handler(0);
1174 	}
1175 	if(source & IRQ_VOLUME_RAMP)
1176 	{
1177 		m_irq_source |= 0x40;
1178 		m_ramp_irq_handler(0);
1179 	}
1180 }
1181 
1182 // TODO: support 16-bit transfers
dack_r(int line)1183 uint8_t gf1_device::dack_r(int line)
1184 {
1185 	return m_wave_ram[m_dma_current++ & 0xfffff];
1186 }
1187 
dack_w(int line,uint8_t data)1188 void gf1_device::dack_w(int line,uint8_t data)
1189 {
1190 	if(m_dma_dram_ctrl & 0x80)  // flip data MSB
1191 	{
1192 		if(m_dma_16bit != 0) // if data is 16-bit
1193 		{
1194 			if((m_dma_current & 1))
1195 				data ^= 0x80;
1196 		}
1197 		else  // data is 8-bit
1198 		{
1199 			data ^= 0x80;
1200 		}
1201 	}
1202 	m_wave_ram[m_dma_current & 0xfffff] = data;
1203 	m_dma_current++;
1204 	m_drq1_handler(0);
1205 }
1206 
eop_w(int state)1207 void gf1_device::eop_w(int state)
1208 {
1209 	if(state == ASSERT_LINE) {
1210 		// end of transfer
1211 		m_dmatimer->reset();
1212 		//m_drq1_handler(0);
1213 		if(m_dma_dram_ctrl & 0x20)
1214 		{
1215 			m_dma_dram_ctrl |= 0x40;
1216 			m_dma_irq_handler(1);
1217 		}
1218 		logerror("GUS: End of transfer. (%05x)\n",m_dma_current);
1219 	}
1220 }
1221 
1222 
1223 /* 16-bit ISA card device implementation */
1224 
1225 static INPUT_PORTS_START( gus_joy )
1226 	PORT_START("gus_joy")
1227 	PORT_BIT( 0x0f, IP_ACTIVE_LOW,   IPT_UNUSED ) // x/y ad stick to digital converters
1228 	PORT_BIT( 0x10, IP_ACTIVE_LOW,   IPT_BUTTON1) PORT_NAME("GUS Joystick Button 1")
1229 	PORT_BIT( 0x20, IP_ACTIVE_LOW,   IPT_BUTTON2) PORT_NAME("GUS Joystick Button 2")
1230 	PORT_BIT( 0x40, IP_ACTIVE_LOW,   IPT_BUTTON3) PORT_NAME("GUS Joystick Button 3")
1231 	PORT_BIT( 0x80, IP_ACTIVE_LOW,   IPT_BUTTON4) PORT_NAME("GUS Joystick Button 4")
1232 
1233 	PORT_START("gus_joy_1")
PORT_CODE_DEC(KEYCODE_LEFT)1234 	PORT_BIT(0xff,0x80,IPT_AD_STICK_X) PORT_SENSITIVITY(100) PORT_KEYDELTA(1) PORT_MINMAX(1,0xff) PORT_CODE_DEC(KEYCODE_LEFT) PORT_CODE_INC(KEYCODE_RIGHT) PORT_CODE_DEC(JOYCODE_X_LEFT_SWITCH) PORT_CODE_INC(JOYCODE_X_RIGHT_SWITCH)
1235 
1236 	PORT_START("gus_joy_2")
1237 	PORT_BIT(0xff,0x80,IPT_AD_STICK_Y) PORT_SENSITIVITY(100) PORT_KEYDELTA(1) PORT_MINMAX(1,0xff) PORT_CODE_DEC(KEYCODE_UP) PORT_CODE_INC(KEYCODE_DOWN) PORT_CODE_DEC(JOYCODE_Y_UP_SWITCH) PORT_CODE_INC(JOYCODE_Y_DOWN_SWITCH)
1238 INPUT_PORTS_END
1239 
1240 //-------------------------------------------------
1241 //  device_add_mconfig - add device configuration
1242 //-------------------------------------------------
1243 
1244 void isa16_gus_device::device_add_mconfig(machine_config &config)
1245 {
1246 	SPEAKER(config, "lspeaker").front_left();
1247 	SPEAKER(config, "rspeaker").front_right();
1248 	GGF1(config, m_gf1, GF1_CLOCK);
1249 	m_gf1->add_route(0, "lspeaker", 0.50);
1250 	m_gf1->add_route(1, "rspeaker", 0.50);
1251 
1252 	m_gf1->txd_handler().set("mdout", FUNC(midi_port_device::write_txd));
1253 	m_gf1->txirq_handler().set(FUNC(isa16_gus_device::midi_txirq));
1254 	m_gf1->rxirq_handler().set(FUNC(isa16_gus_device::midi_rxirq));
1255 	m_gf1->wave_irq_handler().set(FUNC(isa16_gus_device::wavetable_irq));
1256 	m_gf1->ramp_irq_handler().set(FUNC(isa16_gus_device::volumeramp_irq));
1257 	m_gf1->timer1_irq_handler().set(FUNC(isa16_gus_device::timer1_irq));
1258 	m_gf1->timer2_irq_handler().set(FUNC(isa16_gus_device::timer2_irq));
1259 	m_gf1->sb_irq_handler().set(FUNC(isa16_gus_device::sb_irq));
1260 	m_gf1->dma_irq_handler().set(FUNC(isa16_gus_device::dma_irq));
1261 	m_gf1->drq1_handler().set(FUNC(isa16_gus_device::drq1_w));
1262 	m_gf1->drq2_handler().set(FUNC(isa16_gus_device::drq2_w));
1263 	m_gf1->nmi_handler().set(FUNC(isa16_gus_device::nmi_w));
1264 
1265 	MIDI_PORT(config, "mdin", midiin_slot, "midiin").rxd_handler().set(m_gf1, FUNC(acia6850_device::write_rxd));
1266 
1267 	MIDI_PORT(config, "mdout", midiout_slot, "midiout");
1268 
1269 	clock_device &acia_clock(CLOCK(config, "acia_clock", 31250*16));
1270 	acia_clock.signal_handler().set(FUNC(isa16_gus_device::write_acia_clock));
1271 }
1272 
device_input_ports() const1273 ioport_constructor isa16_gus_device::device_input_ports() const
1274 {
1275 	return INPUT_PORTS_NAME( gus_joy );
1276 }
1277 
1278 
isa16_gus_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)1279 isa16_gus_device::isa16_gus_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
1280 	device_t(mconfig, ISA16_GUS, tag, owner, clock),
1281 	device_isa16_card_interface(mconfig, *this),
1282 	m_gf1(*this, "gf1"),
1283 	m_irq_status(0)
1284 {
1285 }
1286 
device_start()1287 void isa16_gus_device::device_start()
1288 {
1289 	set_isa_device();
1290 	m_isa->install_device(0x0200, 0x0201, read8sm_delegate(*this, FUNC(isa16_gus_device::joy_r)), write8sm_delegate(*this, FUNC(isa16_gus_device::joy_w)));
1291 	m_isa->install_device(0x0220, 0x022f, read8sm_delegate(*this, FUNC(isa16_gus_device::board_r)), write8sm_delegate(*this, FUNC(isa16_gus_device::board_w)));
1292 	m_isa->install_device(0x0320, 0x0327, read8sm_delegate(*this, FUNC(isa16_gus_device::synth_r)), write8sm_delegate(*this, FUNC(isa16_gus_device::synth_w)));
1293 	m_isa->install_device(0x0388, 0x0389, read8sm_delegate(*this, FUNC(isa16_gus_device::adlib_r)), write8sm_delegate(*this, FUNC(isa16_gus_device::adlib_w)));
1294 }
1295 
device_reset()1296 void isa16_gus_device::device_reset()
1297 {
1298 }
1299 
device_stop()1300 void isa16_gus_device::device_stop()
1301 {
1302 }
1303 
board_r(offs_t offset)1304 uint8_t isa16_gus_device::board_r(offs_t offset)
1305 {
1306 	switch(offset)
1307 	{
1308 	case 0x00:
1309 	case 0x01:
1310 		return m_gf1->mix_ctrl_r(offset);
1311 		/* port 0x2X6 - IRQ status (active high)
1312 		 * bit 0 - MIDI transmit IRQ
1313 		 * bit 1 - MIDI receive IRQ
1314 		 * bit 2 - Timer 1 IRQ
1315 		 * bit 3 - Timer 2 IRQ
1316 		 * bit 4 - reserved (always 0)
1317 		 * bit 5 - wavetable IRQ
1318 		 * bit 6 - volume ramp IRQ
1319 		 * bit 7 - DRAM TC DMA IRQ
1320 		 */
1321 	case 0x06:
1322 		return m_irq_status;
1323 	case 0x08:
1324 	case 0x09:
1325 		return m_gf1->adlib_r(offset-8);
1326 	case 0x0a:
1327 	case 0x0b:
1328 		return m_gf1->adlib_cmd_r(offset-10);
1329 	case 0x0c:
1330 	case 0x0d:
1331 	case 0x0e:
1332 		return m_gf1->sb_r(offset-12);
1333 	case 0x0f:
1334 		return m_gf1->stat_r();
1335 	default:
1336 		logerror("GUS: Invalid or unimplemented read of port 0x2X%01x\n",offset);
1337 		return 0xff;
1338 	}
1339 }
1340 
board_w(offs_t offset,uint8_t data)1341 void isa16_gus_device::board_w(offs_t offset, uint8_t data)
1342 {
1343 	switch(offset)
1344 	{
1345 	case 0x00:
1346 	case 0x01:
1347 		m_gf1->mix_ctrl_w(offset,data);
1348 		break;
1349 	case 0x06:
1350 		m_gf1->sb2x6_w(data);
1351 		break;
1352 	case 0x08:
1353 	case 0x09:
1354 		m_gf1->adlib_w(offset-8,data);
1355 		break;
1356 	case 0x0a:
1357 	case 0x0b:
1358 		m_gf1->adlib_cmd_w(offset-10,data);
1359 		break;
1360 	case 0x0c:
1361 	case 0x0d:
1362 	case 0x0e:
1363 		m_gf1->sb_w(offset-12,data);
1364 		break;
1365 	case 0x0f:
1366 		m_gf1->stat_w(data);
1367 		break;
1368 	default:
1369 		logerror("GUS: Invalid or unimplemented register write %02x of port 0x2X%01x\n",data,offset);
1370 	}
1371 }
1372 
synth_r(offs_t offset)1373 uint8_t isa16_gus_device::synth_r(offs_t offset)
1374 {
1375 	switch(offset)
1376 	{
1377 	case 0x00:
1378 		return m_gf1->status_r();
1379 	case 0x01:
1380 		return m_gf1->data_r();
1381 	case 0x02:
1382 	case 0x03:
1383 		return m_gf1->global_reg_select_r(offset-2);
1384 	case 0x04:
1385 	case 0x05:
1386 		return m_gf1->global_reg_data_r(offset-4);
1387 	case 0x06:
1388 	case 0x07:
1389 		return m_gf1->dram_r(offset-6);
1390 	default:
1391 		logerror("GUS: Invalid or unimplemented register read of port 0x3X%01x\n",offset);
1392 		return 0xff;
1393 	}
1394 }
1395 
synth_w(offs_t offset,uint8_t data)1396 void isa16_gus_device::synth_w(offs_t offset, uint8_t data)
1397 {
1398 	switch(offset)
1399 	{
1400 	case 0x00:
1401 		m_gf1->control_w(data);
1402 		break;
1403 	case 0x01:
1404 		m_gf1->data_w(data);
1405 		break;
1406 	case 0x02:
1407 	case 0x03:
1408 		m_gf1->global_reg_select_w(offset-2,data);
1409 		break;
1410 	case 0x04:
1411 	case 0x05:
1412 		m_gf1->global_reg_data_w(offset-4,data);
1413 		break;
1414 	case 0x06:
1415 	case 0x07:
1416 		m_gf1->dram_w(offset-6,data);
1417 		break;
1418 	default:
1419 		logerror("GUS: Invalid or unimplemented register write %02x of port 0x3X%01x\n",data,offset);
1420 	}
1421 }
1422 
adlib_r(offs_t offset)1423 uint8_t isa16_gus_device::adlib_r(offs_t offset)
1424 {
1425 	return m_gf1->adlib_r(offset);
1426 }
1427 
adlib_w(offs_t offset,uint8_t data)1428 void isa16_gus_device::adlib_w(offs_t offset, uint8_t data)
1429 {
1430 	m_gf1->adlib_w(offset,data);
1431 }
1432 
joy_r(offs_t offset)1433 uint8_t isa16_gus_device::joy_r(offs_t offset)
1434 {
1435 	if(offset == 1)
1436 	{
1437 		uint8_t data;
1438 		int delta;
1439 		attotime new_time = machine().time();
1440 
1441 		{
1442 			data = ioport("gus_joy")->read() | 0x0f;
1443 
1444 			{
1445 				delta = ((new_time - m_joy_time) * 256 * 1000).seconds();
1446 
1447 				if (ioport("gus_joy_1")->read() < delta) data &= ~0x01;
1448 				if (ioport("gus_joy_2")->read() < delta) data &= ~0x02;
1449 			}
1450 		}
1451 		return data;
1452 	}
1453 	return 0xff;
1454 }
1455 
joy_w(offs_t offset,uint8_t data)1456 void isa16_gus_device::joy_w(offs_t offset, uint8_t data)
1457 {
1458 	m_joy_time = machine().time();
1459 }
1460 
WRITE_LINE_MEMBER(isa16_gus_device::wavetable_irq)1461 WRITE_LINE_MEMBER(isa16_gus_device::wavetable_irq)
1462 {
1463 	if(state)
1464 		set_irq(IRQ_WAVETABLE);
1465 	else
1466 		reset_irq(IRQ_WAVETABLE);
1467 }
1468 
WRITE_LINE_MEMBER(isa16_gus_device::volumeramp_irq)1469 WRITE_LINE_MEMBER(isa16_gus_device::volumeramp_irq)
1470 {
1471 	if(state)
1472 		set_irq(IRQ_VOLUME_RAMP);
1473 	else
1474 		reset_irq(IRQ_VOLUME_RAMP);
1475 }
1476 
WRITE_LINE_MEMBER(isa16_gus_device::timer1_irq)1477 WRITE_LINE_MEMBER(isa16_gus_device::timer1_irq)
1478 {
1479 	if(state)
1480 		set_irq(IRQ_TIMER1);
1481 	else
1482 		reset_irq(IRQ_TIMER1);
1483 }
1484 
WRITE_LINE_MEMBER(isa16_gus_device::timer2_irq)1485 WRITE_LINE_MEMBER(isa16_gus_device::timer2_irq)
1486 {
1487 	if(state)
1488 		set_irq(IRQ_TIMER2);
1489 	else
1490 		reset_irq(IRQ_TIMER2);
1491 }
1492 
WRITE_LINE_MEMBER(isa16_gus_device::dma_irq)1493 WRITE_LINE_MEMBER(isa16_gus_device::dma_irq)
1494 {
1495 	if(state)
1496 		set_irq(IRQ_DRAM_TC_DMA);
1497 	else
1498 		reset_irq(IRQ_DRAM_TC_DMA);
1499 }
1500 
WRITE_LINE_MEMBER(isa16_gus_device::sb_irq)1501 WRITE_LINE_MEMBER(isa16_gus_device::sb_irq)
1502 {
1503 	if(state)
1504 		set_midi_irq(IRQ_SB);
1505 	else
1506 		reset_midi_irq(IRQ_SB);
1507 }
1508 
WRITE_LINE_MEMBER(isa16_gus_device::drq1_w)1509 WRITE_LINE_MEMBER(isa16_gus_device::drq1_w)
1510 {
1511 	m_isa->set_dma_channel(m_gf1->dma_channel1(), this, true);
1512 	switch(m_gf1->dma_channel1())
1513 	{
1514 	case 1:
1515 		m_isa->drq1_w(state);
1516 		break;
1517 	case 3:
1518 		m_isa->drq3_w(state);
1519 		break;
1520 	case 5:
1521 		m_isa->drq5_w(state);
1522 		break;
1523 	case 6:
1524 		m_isa->drq6_w(state);
1525 		break;
1526 	case 7:
1527 		m_isa->drq7_w(state);
1528 		break;
1529 	default:
1530 		logerror("GUS: Invalid DMA channel %i, ignoring.\n",m_gf1->dma_channel1());
1531 	}
1532 }
1533 
WRITE_LINE_MEMBER(isa16_gus_device::drq2_w)1534 WRITE_LINE_MEMBER(isa16_gus_device::drq2_w)
1535 {
1536 	m_isa->set_dma_channel(m_gf1->dma_channel2(), this, true);
1537 	switch(m_gf1->dma_channel2())
1538 	{
1539 	case 1:
1540 		m_isa->drq1_w(state);
1541 		break;
1542 	case 3:
1543 		m_isa->drq3_w(state);
1544 		break;
1545 	case 5:
1546 		m_isa->drq5_w(state);
1547 		break;
1548 	case 6:
1549 		m_isa->drq6_w(state);
1550 		break;
1551 	case 7:
1552 		m_isa->drq7_w(state);
1553 		break;
1554 	default:
1555 		logerror("GUS: Invalid DMA channel %i, ignoring.\n",m_gf1->dma_channel2());
1556 	}
1557 }
1558 
set_irq(uint8_t source)1559 void isa16_gus_device::set_irq(uint8_t source)
1560 {
1561 	m_irq_status |= source;
1562 
1563 	switch(m_gf1->gf1_irq())
1564 	{
1565 	case 2:
1566 		m_isa->irq2_w(1);
1567 		break;
1568 	case 3:
1569 		m_isa->irq3_w(1);
1570 		break;
1571 	case 5:
1572 		m_isa->irq5_w(1);
1573 		break;
1574 	case 7:
1575 		m_isa->irq7_w(1);
1576 		break;
1577 	case 11:
1578 		m_isa->irq11_w(1);
1579 		break;
1580 	case 12:
1581 		m_isa->irq12_w(1);
1582 		break;
1583 	case 15:
1584 		m_isa->irq15_w(1);
1585 		break;
1586 	}
1587 	logerror("GUS: Set IRQ %02x\n",source);
1588 }
1589 
reset_irq(uint8_t source)1590 void isa16_gus_device::reset_irq(uint8_t source)
1591 {
1592 	m_irq_status &= ~source;
1593 
1594 	switch(m_gf1->gf1_irq())
1595 	{
1596 	case 2:
1597 		m_isa->irq2_w(0);
1598 		break;
1599 	case 3:
1600 		m_isa->irq3_w(0);
1601 		break;
1602 	case 5:
1603 		m_isa->irq5_w(0);
1604 		break;
1605 	case 7:
1606 		m_isa->irq7_w(0);
1607 		break;
1608 	case 11:
1609 		m_isa->irq11_w(0);
1610 		break;
1611 	case 12:
1612 		m_isa->irq12_w(0);
1613 		break;
1614 	case 15:
1615 		m_isa->irq15_w(0);
1616 		break;
1617 	}
1618 	logerror("GUS: Reset IRQ %02x\n",source);
1619 }
1620 
set_midi_irq(uint8_t source)1621 void isa16_gus_device::set_midi_irq(uint8_t source)
1622 {
1623 	m_irq_status |= source;
1624 
1625 	switch(m_gf1->midi_irq())
1626 	{
1627 	case 2:
1628 		m_isa->irq2_w(1);
1629 		break;
1630 	case 3:
1631 		m_isa->irq3_w(1);
1632 		break;
1633 	case 5:
1634 		m_isa->irq5_w(1);
1635 		break;
1636 	case 7:
1637 		m_isa->irq7_w(1);
1638 		break;
1639 	case 11:
1640 		m_isa->irq11_w(1);
1641 		break;
1642 	case 12:
1643 		m_isa->irq12_w(1);
1644 		break;
1645 	case 15:
1646 		m_isa->irq15_w(1);
1647 		break;
1648 	}
1649 	logerror("GUS: Set MIDI IRQ %02x\n",source);
1650 }
1651 
reset_midi_irq(uint8_t source)1652 void isa16_gus_device::reset_midi_irq(uint8_t source)
1653 {
1654 	m_irq_status &= ~source;
1655 
1656 	switch(m_gf1->midi_irq())
1657 	{
1658 	case 2:
1659 		m_isa->irq2_w(0);
1660 		break;
1661 	case 3:
1662 		m_isa->irq3_w(0);
1663 		break;
1664 	case 5:
1665 		m_isa->irq5_w(0);
1666 		break;
1667 	case 7:
1668 		m_isa->irq7_w(0);
1669 		break;
1670 	case 11:
1671 		m_isa->irq11_w(0);
1672 		break;
1673 	case 12:
1674 		m_isa->irq12_w(0);
1675 		break;
1676 	case 15:
1677 		m_isa->irq15_w(0);
1678 		break;
1679 	}
1680 	logerror("GUS: Reset MIDI IRQ %02x\n",source);
1681 }
1682 
WRITE_LINE_MEMBER(isa16_gus_device::midi_txirq)1683 WRITE_LINE_MEMBER( isa16_gus_device::midi_txirq )
1684 {
1685 	if (state)
1686 		set_midi_irq(IRQ_MIDI_TRANSMIT);
1687 	else
1688 		reset_midi_irq(IRQ_MIDI_TRANSMIT | IRQ_MIDI_RECEIVE);
1689 }
1690 
WRITE_LINE_MEMBER(isa16_gus_device::midi_rxirq)1691 WRITE_LINE_MEMBER( isa16_gus_device::midi_rxirq )
1692 {
1693 	if (state)
1694 		set_midi_irq(IRQ_MIDI_RECEIVE);
1695 	else
1696 		reset_midi_irq(IRQ_MIDI_TRANSMIT | IRQ_MIDI_RECEIVE);
1697 }
1698 
WRITE_LINE_MEMBER(isa16_gus_device::write_acia_clock)1699 WRITE_LINE_MEMBER( isa16_gus_device::write_acia_clock )
1700 {
1701 	m_gf1->write_txc(state);
1702 	m_gf1->write_rxc(state);
1703 }
1704 
WRITE_LINE_MEMBER(isa16_gus_device::nmi_w)1705 WRITE_LINE_MEMBER( isa16_gus_device::nmi_w)
1706 {
1707 	m_irq_status |= IRQ_SB;
1708 	m_isa->nmi();
1709 }
1710 
dack_r(int line)1711 uint8_t isa16_gus_device::dack_r(int line)
1712 {
1713 	if(line == m_gf1->dma_channel1())
1714 		return m_gf1->dack_r(line);
1715 	else
1716 		return 0;
1717 }
1718 
dack_w(int line,uint8_t data)1719 void isa16_gus_device::dack_w(int line,uint8_t data)
1720 {
1721 	if(line == m_gf1->dma_channel1())
1722 		m_gf1->dack_w(line,data);
1723 }
1724 
eop_w(int state)1725 void isa16_gus_device::eop_w(int state)
1726 {
1727 	m_gf1->eop_w(state);
1728 }
1729