1 // license:BSD-3-Clause 2 // copyright-holders:Olivier Galibert 3 /*************************************************************************** 4 5 h8_timer8.h 6 7 H8 8 bits timer 8 9 10 ***************************************************************************/ 11 12 #ifndef MAME_CPU_H8_H8_TIMER8_H 13 #define MAME_CPU_H8_H8_TIMER8_H 14 15 #pragma once 16 17 #include "h8.h" 18 #include "h8_intc.h" 19 20 class h8_timer8_channel_device : public device_t { 21 public: 22 enum { 23 STOPPED, 24 CHAIN_A, 25 CHAIN_OVERFLOW, 26 INPUT_UP, 27 INPUT_DOWN, 28 INPUT_UPDOWN, 29 DIV 30 }; 31 32 h8_timer8_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); h8_timer8_channel_device(const machine_config & mconfig,const char * tag,device_t * owner,const char * intc,int irq_ca,int irq_cb,int irq_v,int div1,int div2,int div3,int div4,int div5,int div6)33 h8_timer8_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, const char *intc, int irq_ca, int irq_cb, int irq_v, 34 int div1, int div2, int div3, int div4, int div5, int div6) 35 : h8_timer8_channel_device(mconfig, tag, owner, 0) 36 { 37 set_info(intc, irq_ca, irq_cb, irq_v, div1, div2, div3, div4, div5, div6); 38 } 39 40 void set_info(const char *intc, int irq_ca, int irq_cb, int irq_v, int div1, int div2, int div3, int div4, int div5, int div6); 41 42 uint8_t tcr_r(); 43 void tcr_w(uint8_t data); 44 uint8_t tcsr_r(); 45 void tcsr_w(uint8_t data); 46 uint8_t tcor_r(offs_t offset); 47 void tcor_w(offs_t offset, uint8_t data); 48 uint8_t tcnt_r(); 49 void tcnt_w(uint8_t data); 50 51 uint64_t internal_update(uint64_t current_time); 52 void set_extra_clock_bit(bool bit); 53 54 void chained_timer_overflow(); 55 void chained_timer_tcora(); 56 57 protected: 58 enum { 59 TCR_CKS = 0x07, 60 TCR_CCLR = 0x18, 61 TCR_OVIE = 0x20, 62 TCR_CMIEA = 0x40, 63 TCR_CMIEB = 0x80, 64 65 TCSR_OS = 0x0f, 66 TCSR_ADTE = 0x10, 67 TCSR_OVF = 0x20, 68 TCSR_CMFA = 0x40, 69 TCSR_CMFB = 0x80 70 }; 71 72 enum { 73 CLEAR_NONE, 74 CLEAR_A, 75 CLEAR_B, 76 CLEAR_EXTERNAL 77 }; 78 79 required_device<h8_device> cpu; 80 h8_timer8_channel_device *chained_timer; 81 h8_intc_device *intc; 82 const char *chain_tag, *intc_tag; 83 int irq_ca, irq_cb, irq_v, chain_type; 84 int div_tab[6]; 85 uint8_t tcor[2]; 86 uint8_t tcr, tcsr, tcnt; 87 bool extra_clock_bit, has_adte, has_ice; 88 int clock_type, clock_divider, clear_type, counter_cycle; 89 uint64_t last_clock_update, event_time; 90 91 h8_timer8_channel_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); 92 93 virtual void device_start() override; 94 virtual void device_reset() override; 95 96 void update_counter(uint64_t cur_time = 0); 97 void recalc_event(uint64_t cur_time = 0); 98 99 void timer_tick(); 100 void update_tcr(); 101 }; 102 103 class h8h_timer8_channel_device : public h8_timer8_channel_device { 104 public: 105 h8h_timer8_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); h8h_timer8_channel_device(const machine_config & mconfig,const char * tag,device_t * owner,const char * intc,int irq_ca,int irq_cb,int irq_v,const char * chain_tag,int chain_type,bool has_adte,bool has_ice)106 h8h_timer8_channel_device(const machine_config &mconfig, const char *tag, device_t *owner, const char *intc, int irq_ca, int irq_cb, int irq_v, 107 const char *chain_tag, int chain_type, bool has_adte, bool has_ice) 108 : h8h_timer8_channel_device(mconfig, tag, owner, 0) 109 { 110 set_info(intc, irq_ca, irq_cb, irq_v, chain_tag, chain_type, has_adte, has_ice); 111 } 112 virtual ~h8h_timer8_channel_device(); 113 114 void set_info(const char *intc, int irq_ca, int irq_cb, int irq_v, const char *chain_tag, int chain_type, bool has_adte, bool has_ice); 115 }; 116 117 DECLARE_DEVICE_TYPE(H8_TIMER8_CHANNEL, h8_timer8_channel_device) 118 DECLARE_DEVICE_TYPE(H8H_TIMER8_CHANNEL, h8h_timer8_channel_device) 119 120 #endif // MAME_CPU_H8_H8_TIMER8_H 121