1 // license:BSD-3-Clause 2 // copyright-holders:Aaron Giles 3 /*************************************************************************** 4 5 ppc.h 6 7 Interface file for the universal machine language-based 8 PowerPC emulator. 9 10 ***************************************************************************/ 11 #ifndef MAME_CPU_POWERPC_PPC_H 12 #define MAME_CPU_POWERPC_PPC_H 13 14 #pragma once 15 16 #include "cpu/drcfe.h" 17 #include "cpu/drcuml.h" 18 #include "cpu/drcumlsh.h" 19 20 #include "divtlb.h" 21 22 23 /*************************************************************************** 24 CONSTANTS 25 ***************************************************************************/ 26 27 /* general constants */ 28 #define PPC_MAX_FASTRAM 4 29 #define PPC_MAX_HOTSPOTS 16 30 31 32 /* interrupt types */ 33 #define PPC_IRQ 0 /* external IRQ */ 34 #define PPC_IRQ_LINE_0 0 /* (4XX) external IRQ0 */ 35 #define PPC_IRQ_LINE_1 1 /* (4XX) external IRQ1 */ 36 #define PPC_IRQ_LINE_2 2 /* (4XX) external IRQ2 */ 37 #define PPC_IRQ_LINE_3 3 /* (4XX) external IRQ3 */ 38 #define PPC_IRQ_LINE_4 4 /* (4XX) external IRQ4 */ 39 40 41 /* register enumeration */ 42 enum 43 { 44 PPC_PC = 1, 45 PPC_R0, 46 PPC_R1, 47 PPC_R2, 48 PPC_R3, 49 PPC_R4, 50 PPC_R5, 51 PPC_R6, 52 PPC_R7, 53 PPC_R8, 54 PPC_R9, 55 PPC_R10, 56 PPC_R11, 57 PPC_R12, 58 PPC_R13, 59 PPC_R14, 60 PPC_R15, 61 PPC_R16, 62 PPC_R17, 63 PPC_R18, 64 PPC_R19, 65 PPC_R20, 66 PPC_R21, 67 PPC_R22, 68 PPC_R23, 69 PPC_R24, 70 PPC_R25, 71 PPC_R26, 72 PPC_R27, 73 PPC_R28, 74 PPC_R29, 75 PPC_R30, 76 PPC_R31, 77 PPC_CR, 78 PPC_LR, 79 PPC_CTR, 80 PPC_XER, 81 82 PPC_F0, 83 PPC_F1, 84 PPC_F2, 85 PPC_F3, 86 PPC_F4, 87 PPC_F5, 88 PPC_F6, 89 PPC_F7, 90 PPC_F8, 91 PPC_F9, 92 PPC_F10, 93 PPC_F11, 94 PPC_F12, 95 PPC_F13, 96 PPC_F14, 97 PPC_F15, 98 PPC_F16, 99 PPC_F17, 100 PPC_F18, 101 PPC_F19, 102 PPC_F20, 103 PPC_F21, 104 PPC_F22, 105 PPC_F23, 106 PPC_F24, 107 PPC_F25, 108 PPC_F26, 109 PPC_F27, 110 PPC_F28, 111 PPC_F29, 112 PPC_F30, 113 PPC_F31, 114 PPC_FPSCR, 115 116 PPC_MSR, 117 PPC_SRR0, 118 PPC_SRR1, 119 PPC_SPRG0, 120 PPC_SPRG1, 121 PPC_SPRG2, 122 PPC_SPRG3, 123 PPC_SDR1, 124 PPC_EXIER, 125 PPC_EXISR, 126 PPC_EVPR, 127 PPC_IOCR, 128 PPC_TBL, 129 PPC_TBH, 130 PPC_DEC, 131 132 PPC_SR0, 133 PPC_SR1, 134 PPC_SR2, 135 PPC_SR3, 136 PPC_SR4, 137 PPC_SR5, 138 PPC_SR6, 139 PPC_SR7, 140 PPC_SR8, 141 PPC_SR9, 142 PPC_SR10, 143 PPC_SR11, 144 PPC_SR12, 145 PPC_SR13, 146 PPC_SR14, 147 PPC_SR15 148 }; 149 150 151 /* compiler-specific options */ 152 #define PPCDRC_STRICT_VERIFY 0x0001 /* verify all instructions */ 153 #define PPCDRC_FLUSH_PC 0x0002 /* flush the PC value before each memory access */ 154 #define PPCDRC_ACCURATE_SINGLES 0x0004 /* do excessive rounding to make single-precision results "accurate" */ 155 156 157 /* common sets of options */ 158 #define PPCDRC_COMPATIBLE_OPTIONS (PPCDRC_STRICT_VERIFY | PPCDRC_FLUSH_PC | PPCDRC_ACCURATE_SINGLES) 159 #define PPCDRC_FASTEST_OPTIONS (0) 160 161 162 163 /*************************************************************************** 164 PUBLIC FUNCTIONS 165 ***************************************************************************/ 166 167 class ppc_device : public cpu_device, public device_vtlb_interface 168 { 169 protected: 170 class frontend; 171 172 /* PowerPC flavors */ 173 enum powerpc_flavor 174 { 175 PPC_MODEL_403GA = 0x00200000, 176 PPC_MODEL_403GB = 0x00200100, 177 PPC_MODEL_403GC = 0x00200200, 178 PPC_MODEL_403GCX = 0x00201400, 179 PPC_MODEL_405GP = 0x40110000, 180 PPC_MODEL_601 = 0x00010000, 181 PPC_MODEL_603 = 0x00030000, /* "Wart" */ 182 PPC_MODEL_604 = 0x00040000, /* "Zephyr" */ 183 PPC_MODEL_602 = 0x00050200, /* "Galahad" */ 184 PPC_MODEL_603E = 0x00060103, /* "Stretch", version 1.3 */ 185 PPC_MODEL_603EV = 0x00070000, /* "Valiant" */ 186 PPC_MODEL_603R = 0x00071202, /* "Goldeneye", version 2.1 */ 187 PPC_MODEL_740 = 0x00080301, /* "Arthur", version 3.1 */ 188 PPC_MODEL_750 = PPC_MODEL_740, 189 PPC_MODEL_740P = 0x00080202, /* "Conan Doyle", version 1.2 */ 190 PPC_MODEL_750P = PPC_MODEL_740P, 191 PPC_MODEL_755 = 0x00083203, /* "Goldfinger", version 2.3 */ 192 PPC_MODEL_7400 = 0x000c0209, /* "Max", version 2.9 */ 193 PPC_MODEL_7410 = 0x800c1104, /* "Nitro", version 3.4 */ 194 PPC_MODEL_7450 = 0x80000201, /* "Vger", version 2.1 */ 195 PPC_MODEL_7451 = 0x80000203, /* "Vger", version 2.3 */ 196 PPC_MODEL_7441 = PPC_MODEL_7451, 197 PPC_MODEL_7455 = 0x80010303, /* "Apollo 6", version 3.3 */ 198 PPC_MODEL_7445 = PPC_MODEL_7455, 199 PPC_MODEL_7457 = 0x80020101, /* "Apollo 7", version 1.1 */ 200 PPC_MODEL_MPC8240 = 0x00810101, /* "Kahlua" */ 201 PPC_MODEL_MPC8241 = 0x80811014, /* "Kahlua Lt" */ 202 PPC_MODEL_MPC8245 = 0x80811014 /* "Kahlua II" */ 203 }; 204 205 // construction/destruction 206 ppc_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int address_bits, int data_bits, powerpc_flavor flavor, uint32_t cap, uint32_t tb_divisor, address_map_constructor internal_map); 207 208 public: 209 virtual ~ppc_device() override; 210 set_cache_dirty()211 void set_cache_dirty() { m_cache_dirty = true; } set_bus_frequency(uint32_t bus_frequency)212 void set_bus_frequency(uint32_t bus_frequency) { c_bus_frequency = bus_frequency; } set_bus_frequency(const XTAL & xtal)213 void set_bus_frequency(const XTAL &xtal) { set_bus_frequency(xtal.value()); } 214 215 void ppc_set_dcstore_callback(write32sm_delegate callback); 216 217 void ppcdrc_set_options(uint32_t options); 218 void ppcdrc_add_fastram(offs_t start, offs_t end, uint8_t readonly, void *base); 219 void ppcdrc_add_hotspot(offs_t pc, uint32_t opcode, uint32_t cycles); 220 221 TIMER_CALLBACK_MEMBER(decrementer_int_callback); 222 TIMER_CALLBACK_MEMBER(ppc4xx_buffered_dma_callback); 223 TIMER_CALLBACK_MEMBER(ppc4xx_fit_callback); 224 TIMER_CALLBACK_MEMBER(ppc4xx_pit_callback); 225 TIMER_CALLBACK_MEMBER(ppc4xx_spu_callback); 226 227 void ppc_cfunc_printf_exception(); 228 void ppc_cfunc_printf_debug(); 229 void ppc_cfunc_printf_probe(); 230 void ppc_cfunc_unimplemented(); 231 void ppc_cfunc_ppccom_mismatch(); 232 void ppccom_tlb_fill(); 233 void ppccom_update_fprf(); 234 void ppccom_dcstore_callback(); 235 void ppccom_execute_tlbie(); 236 void ppccom_execute_tlbia(); 237 void ppccom_execute_tlbl(); 238 void ppccom_execute_mfspr(); 239 void ppccom_execute_mftb(); 240 void ppccom_execute_mtspr(); 241 void ppccom_tlb_flush(); 242 void ppccom_execute_mfdcr(); 243 void ppccom_execute_mtdcr(); 244 void ppccom_get_dsisr(); 245 246 protected: 247 // device-level overrides 248 virtual void device_start() override; 249 virtual void device_reset() override; 250 virtual void device_stop() override; 251 252 // device_execute_interface overrides execute_min_cycles()253 virtual uint32_t execute_min_cycles() const noexcept override { return 1; } execute_max_cycles()254 virtual uint32_t execute_max_cycles() const noexcept override { return 40; } execute_input_lines()255 virtual uint32_t execute_input_lines() const noexcept override { return 1; } 256 virtual void execute_run() override; 257 virtual void execute_set_input(int inputnum, int state) override; 258 259 // device_memory_interface overrides 260 virtual space_config_vector memory_space_config() const override; 261 virtual bool memory_translate(int spacenum, int intention, offs_t &address) override; 262 263 // device_state_interface overrides 264 virtual void state_export(const device_state_entry &entry) override; 265 virtual void state_import(const device_state_entry &entry) override; 266 virtual void state_string_export(const device_state_entry &entry, std::string &str) const override; 267 268 // device_disasm_interface overrides 269 virtual std::unique_ptr<util::disasm_interface> create_disassembler() override; 270 271 /* exception types */ 272 enum 273 { 274 EXCEPTION_RESET = 1, 275 EXCEPTION_MACHCHECK = 2, 276 EXCEPTION_DSI = 3, /* PPCCAP_OEA */ 277 EXCEPTION_PROTECTION = 3, /* PPCCAP_4XX */ 278 EXCEPTION_ISI = 4, 279 EXCEPTION_EI = 5, 280 EXCEPTION_ALIGN = 6, 281 EXCEPTION_PROGRAM = 7, 282 EXCEPTION_NOFPU = 8, 283 EXCEPTION_DECREMENT = 9, 284 EXCEPTION_SYSCALL = 12, 285 EXCEPTION_TRACE = 13, 286 EXCEPTION_FPASSIST = 14, 287 EXCEPTION_ITLBMISS = 16, /* PPCCAP_603_MMU */ 288 EXCEPTION_DTLBMISSL = 17, /* PPCCAP_603_MMU */ 289 EXCEPTION_DTLBMISSS = 18, /* PPCCAP_603_MMU */ 290 EXCEPTION_COUNT 291 }; 292 293 address_space_config m_program_config; 294 address_space *m_program; 295 memory_access<32, 2, 0, ENDIANNESS_BIG>::cache m_cache32; 296 memory_access<32, 3, 0, ENDIANNESS_BIG>::cache m_cache64; 297 uint32_t c_bus_frequency; 298 299 struct internal_ppc_state 300 { 301 uint32_t pc; 302 uint32_t r[32]; 303 double f[32]; 304 uint32_t cr[8]; 305 uint32_t fpscr; 306 uint32_t msr; 307 uint32_t xerso; 308 uint32_t sr[16]; 309 uint32_t spr[1024]; 310 int icount; 311 uint32_t mode; /* current global mode */ 312 uint32_t irq_pending; 313 /* parameters for calls */ 314 uint32_t param0; 315 uint32_t param1; 316 /* PowerPC 603-specific state */ 317 uint32_t mmu603_cmp; 318 uint32_t mmu603_hash[2]; 319 uint32_t mmu603_r[4]; 320 /* parameters for subroutines */ 321 uint32_t tempaddr; /* temporary address storage */ 322 drcuml_ireg tempdata; /* temporary data storage */ 323 uint32_t updateaddr; /* update address storage */ 324 uint32_t swcount; /* counter for sw instructions */ 325 const char * format; /* format string for printing */ 326 uint32_t arg0; /* print_debug argument 1 */ 327 double fp0; /* floating point 0 */ 328 }; 329 330 internal_ppc_state *m_core; 331 332 int m_ppc_tb_base_icount; 333 int m_ppc_dec_base_icount; 334 int m_ppc_dec_trigger_cycle; 335 int m_bus_freq_multiplier; 336 337 uint32_t m_npc; 338 uint32_t m_dcr[256]; 339 340 uint32_t m_lr; 341 uint32_t m_ctr; 342 uint32_t m_xer; 343 uint32_t m_pvr; 344 uint32_t m_srr0; 345 uint32_t m_srr1; 346 uint32_t m_srr2; 347 uint32_t m_srr3; 348 uint32_t m_hid0; 349 uint32_t m_hid1; 350 uint32_t m_hid2; 351 uint32_t m_sdr1; 352 uint32_t m_sprg[4]; 353 354 uint32_t m_dsisr; 355 uint32_t m_dar; 356 uint32_t m_ear; 357 uint32_t m_dmiss; 358 uint32_t m_dcmp; 359 uint32_t m_hash1; 360 uint32_t m_hash2; 361 uint32_t m_imiss; 362 uint32_t m_icmp; 363 uint32_t m_rpa; 364 365 struct BATENT { 366 uint32_t u; 367 uint32_t l; 368 }; 369 370 BATENT m_ibat[4]; 371 BATENT m_dbat[4]; 372 373 uint32_t m_evpr; 374 uint32_t m_exier; 375 uint32_t m_exisr; 376 uint32_t m_bear; 377 uint32_t m_besr; 378 uint32_t m_iocr; 379 uint32_t m_br[8]; 380 uint32_t m_iabr; 381 uint32_t m_esr; 382 uint32_t m_iccr; 383 uint32_t m_dccr; 384 uint32_t m_pit; 385 uint32_t m_pit_counter; 386 uint32_t m_pit_int_enable; 387 uint32_t m_tsr; 388 uint32_t m_dbsr; 389 uint32_t m_sgr; 390 uint32_t m_pid; 391 uint32_t m_pbl1; 392 uint32_t m_pbl2; 393 uint32_t m_pbu1; 394 uint32_t m_pbu2; 395 uint32_t m_fit_bit; 396 uint32_t m_fit_int_enable; 397 uint32_t m_wdt_bit; 398 uint32_t m_wdt_int_enable; 399 uint32_t m_dac1; 400 uint32_t m_dac2; 401 uint32_t m_iac1; 402 uint32_t m_iac2; 403 404 struct SPU_REGS { 405 uint8_t spls; 406 uint8_t sphs; 407 uint16_t brd; 408 uint8_t spctl; 409 uint8_t sprc; 410 uint8_t sptc; 411 uint8_t sprb; 412 uint8_t sptb; 413 emu_timer *rx_timer; 414 emu_timer *tx_timer; 415 }; 416 417 SPU_REGS m_spu_old; 418 419 struct DMA_REGS { 420 uint32_t cr; 421 uint32_t da; 422 uint32_t sa; 423 uint32_t ct; 424 uint32_t cc; 425 }; 426 427 DMA_REGS m_dma[4]; 428 uint32_t m_dmasr; 429 430 int m_reserved; 431 uint32_t m_reserved_address; 432 433 int m_interrupt_pending; 434 435 uint64_t m_tb; /* 56-bit timebase register */ 436 437 // STUFF added for the 6xx series 438 uint32_t m_dec, m_dec_frac; 439 440 union FPR { 441 uint64_t id; 442 double fd; 443 }; 444 445 union FPR32 { 446 uint32_t i; 447 float f; 448 }; 449 450 FPR m_fpr[32]; 451 452 int m_is603; 453 int m_is602; 454 455 /* PowerPC 602 specific registers */ 456 uint32_t m_lt; 457 uint32_t m_sp; 458 uint32_t m_tcr; 459 uint32_t m_ibr; 460 uint32_t m_esasrr; 461 uint32_t m_sebr; 462 uint32_t m_ser; 463 464 /* architectural distinctions */ 465 powerpc_flavor m_flavor; 466 uint32_t m_cap; 467 uint8_t m_cache_line_size; 468 uint32_t m_tb_divisor; 469 470 /* PowerPC 4xx-specific state */ 471 /* PowerPC 4XX-specific serial port state */ 472 struct ppc4xx_spu_state 473 { ppc4xx_spu_stateppc4xx_spu_state474 ppc4xx_spu_state(device_t &owner) : tx_cb(owner) { } 475 476 uint8_t regs[9]; 477 uint8_t txbuf; 478 uint8_t rxbuf; 479 emu_timer * timer; 480 uint8_t rxbuffer[256]; 481 uint32_t rxin, rxout; 482 write8smo_delegate tx_cb; 483 }; 484 485 ppc4xx_spu_state m_spu; 486 emu_timer * m_fit_timer; 487 emu_timer * m_pit_timer; 488 emu_timer * m_wdog_timer; 489 uint32_t m_pit_reload; 490 uint32_t m_irqstate; 491 emu_timer * m_buffered_dma_timer[4]; 492 int m_buffered_dma_rate[4]; 493 494 /* internal stuff */ 495 std::function<u32 (offs_t)> m_pr32; 496 std::function<const void * (offs_t)> m_prptr; 497 498 uint32_t m_system_clock; 499 uint32_t m_cpu_clock; 500 uint64_t m_tb_zero_cycles; 501 uint64_t m_dec_zero_cycles; 502 emu_timer * m_decrementer_int_timer; 503 504 read32sm_delegate m_dcr_read_func; 505 write32sm_delegate m_dcr_write_func; 506 507 write32sm_delegate m_dcstore_cb; 508 509 read32_delegate::array<4> m_ext_dma_read_cb; 510 write32sm_delegate::array<4> m_ext_dma_write_cb; 511 512 /* PowerPC function pointers for memory accesses/exceptions */ 513 #ifdef PPC_H_INCLUDED_FROM_PPC_C 514 jmp_buf m_exception_jmpbuf; 515 #endif 516 uint8_t (*m_ppcread8)(address_space &space, offs_t address); 517 uint16_t (*m_ppcread16)(address_space &space, offs_t address); 518 uint32_t (*m_ppcread32)(address_space &space, offs_t address); 519 uint64_t (*m_ppcread64)(address_space &space, offs_t address); 520 void (*m_ppcwrite8)(address_space &space, offs_t address, uint8_t data); 521 void (*m_ppcwrite16)(address_space &space, offs_t address, uint16_t data); 522 void (*m_ppcwrite32)(address_space &space, offs_t address, uint32_t data); 523 void (*m_ppcwrite64)(address_space &space, offs_t address, uint64_t data); 524 uint16_t (*m_ppcread16_unaligned)(address_space &space, offs_t address); 525 uint32_t (*m_ppcread32_unaligned)(address_space &space, offs_t address); 526 uint64_t (*m_ppcread64_unaligned)(address_space &space, offs_t address); 527 void (*m_ppcwrite16_unaligned)(address_space &space, offs_t address, uint16_t data); 528 void (*m_ppcwrite32_unaligned)(address_space &space, offs_t address, uint32_t data); 529 void (*m_ppcwrite64_unaligned)(address_space &space, offs_t address, uint64_t data); 530 531 void (*m_optable19[1024])(uint32_t); 532 void (*m_optable31[1024])(uint32_t); 533 void (*m_optable59[1024])(uint32_t); 534 void (*m_optable63[1024])(uint32_t); 535 void (*m_optable[64])(uint32_t); 536 537 /* core state */ 538 drc_cache m_cache; /* pointer to the DRC code cache */ 539 std::unique_ptr<drcuml_state> m_drcuml; /* DRC UML generator state */ 540 std::unique_ptr<frontend> m_drcfe; /* pointer to the DRC front-end state */ 541 uint32_t m_drcoptions; /* configurable DRC options */ 542 543 /* parameters for subroutines */ 544 uint32_t m_arg1; /* print_debug argument 2 */ 545 546 /* tables */ 547 uint8_t m_fpmode[4]; /* FPU mode table */ 548 uint8_t m_sz_cr_table[32]; /* SZ CR table */ 549 uint8_t m_cmp_cr_table[32]; /* CMP CR table */ 550 uint8_t m_cmpl_cr_table[32]; /* CMPL CR table */ 551 uint8_t m_fcmp_cr_table[32]; /* FCMP CR table */ 552 553 /* internal stuff */ 554 uint8_t m_cache_dirty; /* true if we need to flush the cache */ 555 556 /* register mappings */ 557 uml::parameter m_regmap[32]; /* parameter to register mappings for all 32 integer registers */ 558 uml::parameter m_fdregmap[32]; /* parameter to register mappings for all 32 floating point registers */ 559 560 /* subroutines */ 561 uml::code_handle * m_entry; /* entry point */ 562 uml::code_handle * m_nocode; /* nocode exception handler */ 563 uml::code_handle * m_out_of_cycles; /* out of cycles exception handler */ 564 uml::code_handle * m_tlb_mismatch; /* tlb mismatch handler */ 565 uml::code_handle * m_swap_tgpr; /* swap TGPR handler */ 566 uml::code_handle * m_lsw[8][32]; /* lsw entries */ 567 uml::code_handle * m_stsw[8][32]; /* stsw entries */ 568 uml::code_handle * m_read8[8]; /* read byte */ 569 uml::code_handle * m_write8[8]; /* write byte */ 570 uml::code_handle * m_read16[8]; /* read half */ 571 uml::code_handle * m_read16mask[8]; /* read half */ 572 uml::code_handle * m_write16[8]; /* write half */ 573 uml::code_handle * m_write16mask[8]; /* write half */ 574 uml::code_handle * m_read32[8]; /* read word */ 575 uml::code_handle * m_read32align[8]; /* read word aligned */ 576 uml::code_handle * m_read32mask[8]; /* read word */ 577 uml::code_handle * m_write32[8]; /* write word */ 578 uml::code_handle * m_write32align[8]; /* write word aligned */ 579 uml::code_handle * m_write32mask[8]; /* write word */ 580 uml::code_handle * m_read64[8]; /* read double */ 581 uml::code_handle * m_read64mask[8]; /* read double */ 582 uml::code_handle * m_write64[8]; /* write double */ 583 uml::code_handle * m_write64mask[8]; /* write double */ 584 uml::code_handle * m_exception[EXCEPTION_COUNT]; /* array of exception handlers */ 585 uml::code_handle * m_exception_norecover[EXCEPTION_COUNT]; /* array of exception handlers */ 586 587 /* fast RAM */ 588 /* fast RAM info */ 589 struct fast_ram_info 590 { 591 offs_t start; /* start of the RAM block */ 592 offs_t end; /* end of the RAM block */ 593 bool readonly; /* true if read-only */ 594 void * base; /* base in memory where the RAM lives */ 595 }; 596 597 uint32_t m_fastram_select; 598 fast_ram_info m_fastram[PPC_MAX_FASTRAM]; 599 600 /* hotspots */ 601 /* hotspot info */ 602 struct hotspot_info 603 { 604 offs_t pc; /* PC to consider */ 605 uint32_t opcode; /* required opcode at that PC */ 606 uint32_t cycles; /* number of cycles to eat when hit */ 607 }; 608 uint32_t m_hotspot_select; 609 hotspot_info m_hotspot[PPC_MAX_HOTSPOTS]; 610 611 uint64_t m_debugger_temp; 612 613 /* internal compiler state */ 614 struct compiler_state 615 { 616 uint32_t cycles; /* accumulated cycles */ 617 uint8_t checkints; /* need to check interrupts before next instruction */ 618 uint8_t checksoftints; /* need to check software interrupts before next instruction */ 619 uml::code_label labelnum; /* index for local labels */ 620 }; 621 622 uint32_t get_cr(); 623 void set_cr(uint32_t value); 624 uint32_t get_xer(); 625 void set_xer(uint32_t value); 626 uint64_t get_timebase(); 627 void set_timebase(uint64_t newtb); 628 uint32_t get_decrementer(); 629 void set_decrementer(uint32_t newdec); 630 uint32_t ppccom_translate_address_internal(int intention, offs_t &address); 631 void ppc4xx_set_irq_line(uint32_t bitmask, int state); 632 int ppc4xx_get_irq_line(uint32_t bitmask); 633 void ppc4xx_dma_update_irq_states(); 634 bool ppc4xx_dma_decrement_count(int dmachan); 635 bool ppc4xx_dma_fetch_transmit_byte(int dmachan, uint8_t *byte); 636 bool ppc4xx_dma_handle_receive_byte(int dmachan, uint8_t byte); 637 void ppc4xx_dma_exec(int dmachan); 638 void ppc4xx_spu_update_irq_states(); 639 void ppc4xx_spu_rx_data(uint8_t data); 640 void ppc4xx_spu_timer_reset(); 641 void alloc_handle(drcuml_state *drcuml, uml::code_handle **handleptr, const char *name); 642 void load_fast_iregs(drcuml_block &block); 643 void save_fast_iregs(drcuml_block &block); 644 void load_fast_fregs(drcuml_block &block); 645 void save_fast_fregs(drcuml_block &block); 646 uint32_t compute_rlw_mask(uint8_t mb, uint8_t me); 647 uint32_t compute_crf_mask(uint8_t crm); 648 uint32_t compute_spr(uint32_t spr); 649 void code_flush_cache(); 650 void code_compile_block(uint8_t mode, offs_t pc); 651 void static_generate_entry_point(); 652 void static_generate_nocode_handler(); 653 void static_generate_out_of_cycles(); 654 void static_generate_tlb_mismatch(); 655 void static_generate_exception(uint8_t exception, int recover, const char *name); 656 void static_generate_memory_accessor(int mode, int size, int iswrite, int ismasked, const char *name, uml::code_handle *&handleptr, uml::code_handle *masked); 657 void static_generate_swap_tgpr(); 658 void static_generate_lsw_entries(int mode); 659 void static_generate_stsw_entries(int mode); 660 void generate_update_mode(drcuml_block &block); 661 void generate_update_cycles(drcuml_block &block, compiler_state *compiler, uml::parameter param, bool allow_exception); 662 void generate_checksum_block(drcuml_block &block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast); 663 void generate_sequence_instruction(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc); 664 void generate_compute_flags(drcuml_block &block, const opcode_desc *desc, int updatecr, uint32_t xermask, int invertcarry); 665 void generate_shift_flags(drcuml_block &block, const opcode_desc *desc, uint32_t op); 666 void generate_fp_flags(drcuml_block &block, const opcode_desc *desc, int updatefprf); 667 void generate_branch(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc, int source, uint8_t link); 668 void generate_branch_bo(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc, uint32_t bo, uint32_t bi, int source, int link); 669 bool generate_opcode(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc); 670 bool generate_instruction_13(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc); 671 bool generate_instruction_1f(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc); 672 bool generate_instruction_3b(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc); 673 bool generate_instruction_3f(drcuml_block &block, compiler_state *compiler, const opcode_desc *desc); 674 void log_add_disasm_comment(drcuml_block &block, uint32_t pc, uint32_t op); 675 const char *log_desc_flags_to_string(uint32_t flags); 676 void log_register_list(const char *string, const uint32_t *reglist, const uint32_t *regnostarlist); 677 void log_opcode_desc(const opcode_desc *desclist, int indent); 678 679 }; 680 681 682 //class ppc403_device : public ppc_device 683 //{ 684 //public: 685 // ppc403_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 686 // 687 //protected: 688 // virtual uint32_t execute_input_lines() const noexcept { return 8; } 689 //}; 690 // 691 // 692 //class ppc405_device : public ppc_device 693 //{ 694 //public: 695 // ppc405_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 696 // 697 //protected: 698 // virtual uint32_t execute_input_lines() const noexcept { return 8; } 699 //}; 700 701 702 class ppc603_device : public ppc_device 703 { 704 public: 705 ppc603_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 706 }; 707 708 709 class ppc603e_device : public ppc_device 710 { 711 public: 712 ppc603e_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 713 }; 714 715 716 class ppc603r_device : public ppc_device 717 { 718 public: 719 ppc603r_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 720 }; 721 722 723 class ppc602_device : public ppc_device 724 { 725 public: 726 ppc602_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 727 }; 728 729 730 class mpc8240_device : public ppc_device 731 { 732 public: 733 mpc8240_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 734 }; 735 736 737 class ppc601_device : public ppc_device 738 { 739 public: 740 ppc601_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 741 }; 742 743 744 class ppc604_device : public ppc_device 745 { 746 public: 747 ppc604_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 748 }; 749 750 751 class ppc4xx_device : public ppc_device 752 { 753 public: 754 void ppc4xx_spu_set_tx_handler(write8smo_delegate callback); 755 void ppc4xx_spu_receive_byte(uint8_t byteval); 756 757 void ppc4xx_set_dma_read_handler(int channel, read32_delegate callback, int rate); 758 void ppc4xx_set_dma_write_handler(int channel, write32sm_delegate callback, int rate); 759 void ppc4xx_set_dcr_read_handler(read32sm_delegate dcr_read_func); 760 void ppc4xx_set_dcr_write_handler(write32sm_delegate dcr_write_func); 761 762 uint8_t ppc4xx_spu_r(offs_t offset); 763 void ppc4xx_spu_w(offs_t offset, uint8_t data); 764 765 void internal_ppc4xx(address_map &map); 766 protected: 767 ppc4xx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, powerpc_flavor flavor, uint32_t cap, uint32_t tb_divisor); 768 execute_input_lines()769 virtual uint32_t execute_input_lines() const noexcept override { return 5; } 770 virtual void execute_set_input(int inputnum, int state) override; 771 }; 772 773 774 class ppc403ga_device : public ppc4xx_device 775 { 776 public: 777 ppc403ga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 778 }; 779 780 781 class ppc403gcx_device : public ppc4xx_device 782 { 783 public: 784 ppc403gcx_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 785 }; 786 787 788 class ppc405gp_device : public ppc4xx_device 789 { 790 public: 791 ppc405gp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); 792 }; 793 794 795 DECLARE_DEVICE_TYPE(PPC601, ppc601_device) 796 DECLARE_DEVICE_TYPE(PPC602, ppc602_device) 797 DECLARE_DEVICE_TYPE(PPC603, ppc603_device) 798 DECLARE_DEVICE_TYPE(PPC603E, ppc603e_device) 799 DECLARE_DEVICE_TYPE(PPC603R, ppc603r_device) 800 DECLARE_DEVICE_TYPE(PPC604, ppc604_device) 801 DECLARE_DEVICE_TYPE(MPC8240, mpc8240_device) 802 DECLARE_DEVICE_TYPE(PPC403GA, ppc403ga_device) 803 DECLARE_DEVICE_TYPE(PPC403GCX, ppc403gcx_device) 804 DECLARE_DEVICE_TYPE(PPC405GP, ppc405gp_device) 805 806 #endif // MAME_CPU_POWERPC_PPC_H 807