1 // license:BSD-3-Clause 2 // copyright-holders:R. Belmont 3 /***************************************************************************** 4 * 5 * sh4comn.h 6 * 7 * SH-4 non-specific components 8 * 9 *****************************************************************************/ 10 11 #pragma once 12 13 #ifndef __SH4COMN_H__ 14 #define __SH4COMN_H__ 15 16 #include "sh.h" 17 18 #define VERBOSE 0 19 20 #define LOG(x) do { if (VERBOSE) logerror x; } while (0) 21 22 #define EXPPRI(pl,po,p,n) (((4-(pl)) << 24) | ((15-(po)) << 16) | ((p) << 8) | (255-(n))) 23 #define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI) 24 #define INTPRI(p,n) EXPPRI(4,2,p,n) 25 26 #define FP_RS(r) m_sh2_state->m_fr[(r)] // binary representation of single precision floating point register r 27 #define FP_RFS(r) *( (float *)(m_sh2_state->m_fr+(r)) ) // single precision floating point register r 28 #define FP_RFD(r) *( (double *)(m_sh2_state->m_fr+(r)) ) // double precision floating point register r 29 #define FP_XS(r) m_sh2_state->m_xf[(r)] // binary representation of extended single precision floating point register r 30 #define FP_XFS(r) *( (float *)(m_sh2_state->m_xf+(r)) ) // single precision extended floating point register r 31 #define FP_XFD(r) *( (double *)(m_sh2_state->m_xf+(r)) ) // double precision extended floating point register r 32 #ifdef LSB_FIRST 33 #define FP_RS2(r) m_sh2_state->m_fr[(r) ^ m_sh2_state->m_fpu_pr] 34 #define FP_RFS2(r) *( (float *)(m_sh2_state->m_fr+((r) ^ m_sh2_state->m_fpu_pr)) ) 35 #define FP_XS2(r) m_sh2_state->m_xf[(r) ^ m_sh2_state->m_fpu_pr] 36 #define FP_XFS2(r) *( (float *)(m_sh2_state->m_xf+((r) ^ m_sh2_state->m_fpu_pr)) ) 37 #endif 38 39 #define FPSCR mem(&m_sh2_state->m_fpscr) 40 #define FPS32(reg) m_fs_regmap[reg] 41 #define FPD32(reg) m_fd_regmap[reg & 14] 42 enum 43 { 44 ICF = 0x00800000, 45 OCFA = 0x00080000, 46 OCFB = 0x00040000, 47 OVF = 0x00020000 48 }; 49 50 #define FD 0x00008000 51 #define BL 0x10000000 52 #define sRB 0x20000000 53 #define MD 0x40000000 54 55 /* 29 bits */ 56 #define SH34_AM 0x1fffffff 57 58 #define SH34_FLAGS (MD|sRB|BL|FD|SH_M|SH_Q|SH_I|SH_S|SH_T) 59 60 /* Bits in FPSCR */ 61 #define RM 0x00000003 62 #define DN 0x00040000 63 #define PR 0x00080000 64 #define SZ 0x00100000 65 #define FR 0x00200000 66 67 #define REGFLAG_R(n) (1 << (n)) 68 69 /* additional register flags 1 */ 70 #define REGFLAG_SGR (1 << 6) 71 #define REGFLAG_FPUL (1 << 7) 72 #define REGFLAG_FPSCR (1 << 8) 73 #define REGFLAG_DBR (1 << 9) 74 #define REGFLAG_SSR (1 << 10) 75 #define REGFLAG_SPC (1 << 11) 76 77 #endif /* __SH4COMN_H__ */ 78