1 // license:BSD-3-Clause 2 // copyright-holders:Tim Schuerewegen 3 #ifndef MAME_MACHINE_S3C24XX_H 4 #define MAME_MACHINE_S3C24XX_H 5 6 #pragma once 7 8 #include "cpu/arm7/arm7.h" 9 10 class s3c24xx_peripheral_types // TODO: better name for this 11 { 12 protected: BITS(A && x,B && m,C && n)13 template <typename A, typename B, typename C> static constexpr auto BITS(A &&x, B &&m, C &&n) 14 { 15 return (x >> n) & ((uint32_t(1) << (m - n + 1)) - 1); 16 } 17 CLR_BITS(A && x,B && m,C && n)18 template <typename A, typename B, typename C> static constexpr auto CLR_BITS(A &&x, B &&m, C &&n) 19 { 20 return x & ~(((uint32_t(1) << (m - n + 1)) - 1) << n); 21 } 22 23 struct memcon_regs_t 24 { 25 uint32_t data[0x34/4]; 26 }; 27 28 struct usbhost_regs_t 29 { 30 uint32_t data[0x5c/4]; 31 }; 32 33 struct lcdpal_regs_t 34 { 35 uint32_t data[0x400/4]; 36 }; 37 38 struct uart_regs_t 39 { 40 uint32_t ulcon; 41 uint32_t ucon; 42 uint32_t ufcon; 43 uint32_t umcon; 44 uint32_t utrstat; 45 uint32_t uerstat; 46 uint32_t ufstat; 47 uint32_t umstat; 48 uint32_t utxh; 49 uint32_t urxh; 50 uint32_t ubrdiv; 51 }; 52 53 struct pwm_regs_t 54 { 55 uint32_t tcfg0; 56 uint32_t tcfg1; 57 uint32_t tcon; 58 uint32_t tcntb0; 59 uint32_t tcmpb0; 60 uint32_t tcnto0; 61 uint32_t tcntb1; 62 uint32_t tcmpb1; 63 uint32_t tcnto1; 64 uint32_t tcntb2; 65 uint32_t tcmpb2; 66 uint32_t tcnto2; 67 uint32_t tcntb3; 68 uint32_t tcmpb3; 69 uint32_t tcnto3; 70 uint32_t tcntb4; 71 uint32_t tcnto4; 72 }; 73 74 struct wdt_regs_t 75 { 76 uint32_t wtcon; 77 uint32_t wtdat; 78 uint32_t wtcnt; 79 }; 80 81 struct iis_regs_t 82 { 83 uint32_t iiscon; 84 uint32_t iismod; 85 uint32_t iispsr; 86 uint32_t iisfcon; 87 uint32_t iisfifo; 88 }; 89 90 struct rtc_regs_t 91 { 92 uint32_t rtccon; 93 uint32_t ticnt; 94 uint32_t reserved[2]; 95 uint32_t rtcalm; 96 uint32_t almsec; 97 uint32_t almmin; 98 uint32_t almhour; 99 uint32_t almday; 100 uint32_t almmon; 101 uint32_t almyear; 102 uint32_t rtcrst; 103 uint32_t bcdsec; 104 uint32_t bcdmin; 105 uint32_t bcdhour; 106 uint32_t bcdday; 107 uint32_t bcddow; 108 uint32_t bcdmon; 109 uint32_t bcdyear; 110 }; 111 112 struct mmc_regs_t 113 { 114 uint32_t data[0x40/4]; 115 }; 116 117 struct spi_regs_t 118 { 119 uint32_t spcon; 120 uint32_t spsta; 121 uint32_t sppin; 122 uint32_t sppre; 123 uint32_t sptdat; 124 uint32_t sprdat; 125 }; 126 127 struct sdi_regs_t 128 { 129 uint32_t data[0x44/4]; 130 }; 131 132 struct cam_regs_t 133 { 134 uint32_t data[0xa4/4]; 135 }; 136 137 struct ac97_regs_t 138 { 139 uint32_t data[0x20/4]; 140 }; 141 142 143 struct memcon_t 144 { 145 void reset(); 146 147 memcon_regs_t regs; 148 }; 149 150 struct usbhost_t 151 { 152 void reset(); 153 154 usbhost_regs_t regs; 155 }; 156 157 struct lcdpal_t 158 { 159 lcdpal_regs_t regs; 160 }; 161 162 struct uart_t 163 { 164 static constexpr offs_t ULCON = 0x00 / 4; // UART Line Control 165 static constexpr offs_t UCON = 0x04 / 4; // UART Control 166 static constexpr offs_t UFCON = 0x08 / 4; // UART FIFO Control 167 static constexpr offs_t UMCON = 0x0c / 4; // UART Modem Control 168 static constexpr offs_t UTRSTAT = 0x10 / 4; // UART Tx/Rx Status 169 static constexpr offs_t UERSTAT = 0x14 / 4; // UART Rx Error Status 170 static constexpr offs_t UFSTAT = 0x18 / 4; // UART FIFO Status 171 static constexpr offs_t UMSTAT = 0x1c / 4; // UART Modem Status 172 static constexpr offs_t UTXH = 0x20 / 4; // UART Transmission Hold 173 static constexpr offs_t URXH = 0x24 / 4; // UART Receive Buffer 174 static constexpr offs_t UBRDIV = 0x28 / 4; // UART Baud Rate Divisor 175 176 void reset(); 177 178 uart_regs_t regs; 179 }; 180 181 struct pwm_t 182 { 183 static constexpr offs_t TCFG0 = 0x00 / 4; // Timer Configuration 184 static constexpr offs_t TCFG1 = 0x04 / 4; // Timer Configuration 185 static constexpr offs_t TCON = 0x08 / 4; // Timer Control 186 static constexpr offs_t TCNTB0 = 0x0c / 4; // Timer Count Buffer 0 187 static constexpr offs_t TCMPB0 = 0x10 / 4; // Timer Compare Buffer 0 188 static constexpr offs_t TCNTO0 = 0x14 / 4; // Timer Count Observation 0 189 static constexpr offs_t TCNTB1 = 0x18 / 4; // Timer Count Buffer 1 190 static constexpr offs_t TCMPB1 = 0x1c / 4; // Timer Compare Buffer 1 191 static constexpr offs_t TCNTO1 = 0x20 / 4; // Timer Count Observation 1 192 static constexpr offs_t TCNTB2 = 0x24 / 4; // Timer Count Buffer 2 193 static constexpr offs_t TCMPB2 = 0x28 / 4; // Timer Compare Buffer 2 194 static constexpr offs_t TCNTO2 = 0x2c / 4; // Timer Count Observation 2 195 static constexpr offs_t TCNTB3 = 0x30 / 4; // Timer Count Buffer 3 196 static constexpr offs_t TCMPB3 = 0x34 / 4; // Timer Compare Buffer 3 197 static constexpr offs_t TCNTO3 = 0x38 / 4; // Timer Count Observation 3 198 static constexpr offs_t TCNTB4 = 0x3c / 4; // Timer Count Buffer 4 199 static constexpr offs_t TCNTO4 = 0x40 / 4; // Timer Count Observation 4 200 201 void reset(); 202 uint16_t calc_observation(unsigned ch) const; 203 204 pwm_regs_t regs; 205 emu_timer *timer[5]; 206 uint32_t cnt[5]; 207 uint32_t cmp[5]; 208 uint32_t freq[5]; 209 }; 210 211 struct wdt_t 212 { 213 static constexpr offs_t WTCON = 0x00 / 4; // Watchdog Timer Mode 214 static constexpr offs_t WTDAT = 0x04 / 4; // Watchdog Timer Data 215 static constexpr offs_t WTCNT = 0x08 / 4; // Watchdog Timer Count 216 217 void reset(); 218 uint16_t calc_current_count() const; 219 220 wdt_regs_t regs; 221 emu_timer *timer; 222 uint32_t freq, cnt; 223 }; 224 225 struct iis_t 226 { 227 static constexpr offs_t IISCON = 0x00 / 4; // IIS Control 228 static constexpr offs_t IISMOD = 0x04 / 4; // IIS Mode 229 static constexpr offs_t IISPSR = 0x08 / 4; // IIS Prescaler 230 static constexpr offs_t IISFCON = 0x0c / 4; // IIS FIFO Control 231 static constexpr offs_t IISFIFO = 0x10 / 4; // IIS FIFO Entry 232 233 void reset(); 234 235 iis_regs_t regs; 236 emu_timer *timer; 237 uint16_t fifo[16/2]; 238 int fifo_index; 239 }; 240 241 struct rtc_t 242 { 243 static constexpr offs_t RTCCON = 0x00 / 4; // RTC Control 244 static constexpr offs_t TICNT = 0x04 / 4; // Tick Time count 245 static constexpr offs_t RTCALM = 0x10 / 4; // RTC Alarm Control 246 static constexpr offs_t ALMSEC = 0x14 / 4; // Alarm Second 247 static constexpr offs_t ALMMIN = 0x18 / 4; // Alarm Minute 248 static constexpr offs_t ALMHOUR = 0x1c / 4; // Alarm Hour 249 static constexpr offs_t ALMDAY = 0x20 / 4; // Alarm Day 250 static constexpr offs_t ALMMON = 0x24 / 4; // Alarm Month 251 static constexpr offs_t ALMYEAR = 0x28 / 4; // Alarm Year 252 static constexpr offs_t RTCRST = 0x2c / 4; // RTC Round Reset 253 static constexpr offs_t BCDSEC = 0x30 / 4; // BCD Second 254 static constexpr offs_t BCDMIN = 0x34 / 4; // BCD Minute 255 static constexpr offs_t BCDHOUR = 0x38 / 4; // BCD Hour 256 static constexpr offs_t BCDDAY = 0x3c / 4; // BCD Day 257 static constexpr offs_t BCDDOW = 0x40 / 4; // BCD Day of Week 258 static constexpr offs_t BCDMON = 0x44 / 4; // BCD Month 259 static constexpr offs_t BCDYEAR = 0x48 / 4; // BCD Year 260 261 void reset(); 262 void recalc(); 263 void update(); 264 bool check_alarm() const; 265 266 rtc_regs_t regs; 267 emu_timer *timer_tick_count; 268 emu_timer *timer_update; 269 }; 270 271 struct mmc_t 272 { 273 void reset(); 274 275 mmc_regs_t regs; 276 }; 277 278 struct spi_t 279 { 280 static constexpr offs_t SPCON = 0x00 / 4; // SPI Control 281 static constexpr offs_t SPSTA = 0x04 / 4; // SPI Status 282 static constexpr offs_t SPPIN = 0x08 / 4; // SPI Pin Control 283 static constexpr offs_t SPPRE = 0x0c / 4; // SPI Baud Rate Prescaler 284 static constexpr offs_t SPTDAT = 0x10 / 4; // SPI Tx Data 285 static constexpr offs_t SPRDAT = 0x14 / 4; // SPI Rx Data 286 287 spi_regs_t regs; 288 }; 289 290 struct sdi_t 291 { 292 sdi_regs_t regs; 293 }; 294 295 struct cam_t 296 { 297 void reset(); 298 299 cam_regs_t regs; 300 }; 301 302 struct ac97_t 303 { 304 void reset(); 305 306 ac97_regs_t regs; 307 }; 308 }; 309 310 #endif // MAME_MACHINE_S3C24XX_H 311