1 // license:GPL-2.0+
2 // copyright-holders:Jarek Burczynski,Tatsuyuki Satoh
3 /*
4 **
5 ** File: fm2612.c -- software implementation of Yamaha YM2612 FM sound generator
6 ** Split from fm.c to keep 2612 fixes from infecting other OPN chips
7 **
8 ** Copyright Jarek Burczynski (bujar at mame dot net)
9 ** Copyright Tatsuyuki Satoh , MultiArcadeMachineEmulator development
10 **
11 ** Version 1.5.1 (Genesis Plus GX ym2612.c rev. 368)
12 **
13 */
14
15 /*
16 ** History:
17 **
18 ** 2006~2009 Eke-Eke (Genesis Plus GX):
19 ** Huge thanks to Nemesis, lot of those fixes came from his tests on Sega Genesis hardware
20 ** More informations at http://gendev.spritesmind.net/forum/viewtopic.php?t=386
21 **
22 ** TODO:
23 **
24 ** - core documentation
25 ** - BUSY flag support
26 **
27 ** CHANGELOG:
28 **
29 ** 07-30-2014 dink (FB Alpha project):
30 ** - fixed missing dac channel on savestate load
31 **
32 ** xx-xx-xxxx
33 ** - fixed LFO implementation:
34 ** .added support for CH3 special mode: fixes various sound effects (birds in Warlock, bug sound in Aladdin...)
35 ** .inverted LFO AM waveform: fixes Spider-Man & Venom : Separation Anxiety (intro), California Games (surfing event)
36 ** .improved LFO timing accuracy: now updated AFTER sample output, like EG/PG updates, and without any precision loss anymore.
37 ** - improved internal timers emulation
38 ** - adjusted lowest EG rates increment values
39 ** - fixed Attack Rate not being updated in some specific cases (Batman & Robin intro)
40 ** - fixed EG behavior when Attack Rate is maximal
41 ** - fixed EG behavior when SL=0 (Mega Turrican tracks 03,09...) or/and Key ON occurs at minimal attenuation
42 ** - implemented EG output immediate changes on register writes
43 ** - fixed YM2612 initial values (after the reset): fixes missing intro in B.O.B
44 ** - implemented Detune overflow (Ariel, Comix Zone, Shaq Fu, Spiderman & many other games using GEMS sound engine)
45 ** - implemented accurate CSM mode emulation
46 ** - implemented accurate SSG-EG emulation (Asterix, Beavis&Butthead, Bubba'n Stix & many other games)
47 ** - implemented accurate address/data ports behavior
48 **
49 ** 06-23-2007 Zsolt Vasvari:
50 ** - changed the timing not to require the use of floating point calculations
51 **
52 ** 03-08-2003 Jarek Burczynski:
53 ** - fixed YM2608 initial values (after the reset)
54 ** - fixed flag and irqmask handling (YM2608)
55 ** - fixed BUFRDY flag handling (YM2608)
56 **
57 ** 14-06-2003 Jarek Burczynski:
58 ** - implemented all of the YM2608 status register flags
59 ** - implemented support for external memory read/write via YM2608
60 ** - implemented support for deltat memory limit register in YM2608 emulation
61 **
62 ** 22-05-2003 Jarek Burczynski:
63 ** - fixed LFO PM calculations (copy&paste bugfix)
64 **
65 ** 08-05-2003 Jarek Burczynski:
66 ** - fixed SSG support
67 **
68 ** 22-04-2003 Jarek Burczynski:
69 ** - implemented 100% correct LFO generator (verified on real YM2610 and YM2608)
70 **
71 ** 15-04-2003 Jarek Burczynski:
72 ** - added support for YM2608's register 0x110 - status mask
73 **
74 ** 01-12-2002 Jarek Burczynski:
75 ** - fixed register addressing in YM2608, YM2610, YM2610B chips. (verified on real YM2608)
76 ** The addressing patch used for early Neo-Geo games can be removed now.
77 **
78 ** 26-11-2002 Jarek Burczynski, Nicola Salmoria:
79 ** - recreated YM2608 ADPCM ROM using data from real YM2608's output which leads to:
80 ** - added emulation of YM2608 drums.
81 ** - output of YM2608 is two times lower now - same as YM2610 (verified on real YM2608)
82 **
83 ** 16-08-2002 Jarek Burczynski:
84 ** - binary exact Envelope Generator (verified on real YM2203);
85 ** identical to YM2151
86 ** - corrected 'off by one' error in feedback calculations (when feedback is off)
87 ** - corrected connection (algorithm) calculation (verified on real YM2203 and YM2610)
88 **
89 ** 18-12-2001 Jarek Burczynski:
90 ** - added SSG-EG support (verified on real YM2203)
91 **
92 ** 12-08-2001 Jarek Burczynski:
93 ** - corrected sin_tab and tl_tab data (verified on real chip)
94 ** - corrected feedback calculations (verified on real chip)
95 ** - corrected phase generator calculations (verified on real chip)
96 ** - corrected envelope generator calculations (verified on real chip)
97 ** - corrected FM volume level (YM2610 and YM2610B).
98 ** - changed YMxxxUpdateOne() functions (YM2203, YM2608, YM2610, YM2610B, YM2612) :
99 ** this was needed to calculate YM2610 FM channels output correctly.
100 ** (Each FM channel is calculated as in other chips, but the output of the channel
101 ** gets shifted right by one *before* sending to accumulator. That was impossible to do
102 ** with previous implementation).
103 **
104 ** 23-07-2001 Jarek Burczynski, Nicola Salmoria:
105 ** - corrected YM2610 ADPCM type A algorithm and tables (verified on real chip)
106 **
107 ** 11-06-2001 Jarek Burczynski:
108 ** - corrected end of sample bug in ADPCMA_calc_cha().
109 ** Real YM2610 checks for equality between current and end addresses (only 20 LSB bits).
110 **
111 ** 08-12-98 hiro-shi:
112 ** rename ADPCMA -> ADPCMB, ADPCMB -> ADPCMA
113 ** move ROM limit check.(CALC_CH? -> 2610Write1/2)
114 ** test program (ADPCMB_TEST)
115 ** move ADPCM A/B end check.
116 ** ADPCMB repeat flag(no check)
117 ** change ADPCM volume rate (8->16) (32->48).
118 **
119 ** 09-12-98 hiro-shi:
120 ** change ADPCM volume. (8->16, 48->64)
121 ** replace ym2610 ch0/3 (YM-2610B)
122 ** change ADPCM_SHIFT (10->8) missing bank change 0x4000-0xffff.
123 ** add ADPCM_SHIFT_MASK
124 ** change ADPCMA_DECODE_MIN/MAX.
125 */
126
127
128
129
130 /************************************************************************/
131 /* comment of hiro-shi(Hiromitsu Shioya) */
132 /* YM2610(B) = OPN-B */
133 /* YM2610 : PSG:3ch FM:4ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
134 /* YM2610B : PSG:3ch FM:6ch ADPCM(18.5KHz):6ch DeltaT ADPCM:1ch */
135 /************************************************************************/
136
137 #include "emu.h"
138 #include "fm.h"
139
140 #if (BUILD_YM2612||BUILD_YM3438)
141 #include "2612intf.h"
142 #endif /* (BUILD_YM2612||BUILD_YM3438) */
143
144
145 /* shared function building option */
146 #define BUILD_OPN (BUILD_YM2203||BUILD_YM2608||BUILD_YM2610||BUILD_YM2610B||BUILD_YM2612||BUILD_YM3438)
147 #define BUILD_OPN_PRESCALER (BUILD_YM2203||BUILD_YM2608)
148
149
150 /* globals */
151 #define TYPE_SSG 0x01 /* SSG support */
152 #define TYPE_LFOPAN 0x02 /* OPN type LFO and PAN */
153 #define TYPE_6CH 0x04 /* FM 6CH / 3CH */
154 #define TYPE_DAC 0x08 /* YM2612's DAC device */
155 #define TYPE_ADPCM 0x10 /* two ADPCM units */
156 #define TYPE_2610 0x20 /* bogus flag to differentiate 2608 from 2610 */
157
158
159 #define TYPE_YM2203 (TYPE_SSG)
160 #define TYPE_YM2608 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM)
161 #define TYPE_YM2610 (TYPE_SSG |TYPE_LFOPAN |TYPE_6CH |TYPE_ADPCM |TYPE_2610)
162 #define TYPE_YM2612 (TYPE_DAC |TYPE_LFOPAN |TYPE_6CH)
163
164
165 /* globals */
166 #define FREQ_SH 16 /* 16.16 fixed point (frequency calculations) */
167 #define EG_SH 16 /* 16.16 fixed point (envelope generator timing) */
168 #define LFO_SH 24 /* 8.24 fixed point (LFO calculations) */
169 #define TIMER_SH 16 /* 16.16 fixed point (timers calculations) */
170
171 #define FREQ_MASK ((1<<FREQ_SH)-1)
172
173 #define MAXOUT (+32767)
174 #define MINOUT (-32768)
175
176 /* envelope generator */
177 #define ENV_BITS 10
178 #define ENV_LEN (1<<ENV_BITS)
179 #define ENV_STEP (128.0/ENV_LEN)
180
181 #define MAX_ATT_INDEX (ENV_LEN-1) /* 1023 */
182 #define MIN_ATT_INDEX (0) /* 0 */
183
184 #define EG_ATT 4
185 #define EG_DEC 3
186 #define EG_SUS 2
187 #define EG_REL 1
188 #define EG_OFF 0
189
190 /* operator unit */
191 #define SIN_BITS 10
192 #define SIN_LEN (1<<SIN_BITS)
193 #define SIN_MASK (SIN_LEN-1)
194
195 #define TL_RES_LEN (256) /* 8 bits addressing (real chip) */
196
197 /* TL_TAB_LEN is calculated as:
198 * 13 - sinus amplitude bits (Y axis)
199 * 2 - sinus sign bit (Y axis)
200 * TL_RES_LEN - sinus resolution (X axis)
201 */
202 #define TL_TAB_LEN (13*2*TL_RES_LEN)
203 static signed int tl_tab[TL_TAB_LEN];
204
205 #define ENV_QUIET (TL_TAB_LEN>>3)
206
207 /* sin waveform table in 'decibel' scale */
208 static unsigned int sin_tab[SIN_LEN];
209
210 /* sustain level table (3dB per step) */
211 /* bit0, bit1, bit2, bit3, bit4, bit5, bit6 */
212 /* 1, 2, 4, 8, 16, 32, 64 (value)*/
213 /* 0.75, 1.5, 3, 6, 12, 24, 48 (dB)*/
214
215 /* 0 - 15: 0, 3, 6, 9,12,15,18,21,24,27,30,33,36,39,42,93 (dB)*/
216 /* attenuation value (10 bits) = (SL << 2) << 3 */
217 #define SC(db) (uint32_t) ( db * (4.0/ENV_STEP) )
218 static const uint32_t sl_table[16]={
219 SC( 0),SC( 1),SC( 2),SC(3 ),SC(4 ),SC(5 ),SC(6 ),SC( 7),
220 SC( 8),SC( 9),SC(10),SC(11),SC(12),SC(13),SC(14),SC(31)
221 };
222 #undef SC
223
224
225 #define RATE_STEPS (8)
226 static const uint8_t eg_inc[19*RATE_STEPS]={
227 /*cycle:0 1 2 3 4 5 6 7*/
228
229 /* 0 */ 0,1, 0,1, 0,1, 0,1, /* rates 00..11 0 (increment by 0 or 1) */
230 /* 1 */ 0,1, 0,1, 1,1, 0,1, /* rates 00..11 1 */
231 /* 2 */ 0,1, 1,1, 0,1, 1,1, /* rates 00..11 2 */
232 /* 3 */ 0,1, 1,1, 1,1, 1,1, /* rates 00..11 3 */
233
234 /* 4 */ 1,1, 1,1, 1,1, 1,1, /* rate 12 0 (increment by 1) */
235 /* 5 */ 1,1, 1,2, 1,1, 1,2, /* rate 12 1 */
236 /* 6 */ 1,2, 1,2, 1,2, 1,2, /* rate 12 2 */
237 /* 7 */ 1,2, 2,2, 1,2, 2,2, /* rate 12 3 */
238
239 /* 8 */ 2,2, 2,2, 2,2, 2,2, /* rate 13 0 (increment by 2) */
240 /* 9 */ 2,2, 2,4, 2,2, 2,4, /* rate 13 1 */
241 /*10 */ 2,4, 2,4, 2,4, 2,4, /* rate 13 2 */
242 /*11 */ 2,4, 4,4, 2,4, 4,4, /* rate 13 3 */
243
244 /*12 */ 4,4, 4,4, 4,4, 4,4, /* rate 14 0 (increment by 4) */
245 /*13 */ 4,4, 4,8, 4,4, 4,8, /* rate 14 1 */
246 /*14 */ 4,8, 4,8, 4,8, 4,8, /* rate 14 2 */
247 /*15 */ 4,8, 8,8, 4,8, 8,8, /* rate 14 3 */
248
249 /*16 */ 8,8, 8,8, 8,8, 8,8, /* rates 15 0, 15 1, 15 2, 15 3 (increment by 8) */
250 /*17 */ 16,16,16,16,16,16,16,16, /* rates 15 2, 15 3 for attack */
251 /*18 */ 0,0, 0,0, 0,0, 0,0, /* infinity rates for attack and decay(s) */
252 };
253
254
255 #define O(a) (a*RATE_STEPS)
256
257 /*note that there is no O(17) in this table - it's directly in the code */
258 static const uint8_t eg_rate_select2612[32+64+32]={ /* Envelope Generator rates (32 + 64 rates + 32 RKS) */
259 /* 32 infinite time rates (same as Rate 0) */
260 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
261 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
262 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
263 O(18),O(18),O(18),O(18),O(18),O(18),O(18),O(18),
264
265 /* rates 00-11 */
266 /*
267 O( 0),O( 1),O( 2),O( 3),
268 O( 0),O( 1),O( 2),O( 3),
269 */
270 O(18),O(18),O( 0),O( 0),
271 O( 0),O( 0),O( 2),O( 2), // Nemesis's tests
272
273 O( 0),O( 1),O( 2),O( 3),
274 O( 0),O( 1),O( 2),O( 3),
275 O( 0),O( 1),O( 2),O( 3),
276 O( 0),O( 1),O( 2),O( 3),
277 O( 0),O( 1),O( 2),O( 3),
278 O( 0),O( 1),O( 2),O( 3),
279 O( 0),O( 1),O( 2),O( 3),
280 O( 0),O( 1),O( 2),O( 3),
281 O( 0),O( 1),O( 2),O( 3),
282 O( 0),O( 1),O( 2),O( 3),
283
284 /* rate 12 */
285 O( 4),O( 5),O( 6),O( 7),
286
287 /* rate 13 */
288 O( 8),O( 9),O(10),O(11),
289
290 /* rate 14 */
291 O(12),O(13),O(14),O(15),
292
293 /* rate 15 */
294 O(16),O(16),O(16),O(16),
295
296 /* 32 dummy rates (same as 15 3) */
297 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
298 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
299 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16),
300 O(16),O(16),O(16),O(16),O(16),O(16),O(16),O(16)
301
302 };
303 #undef O
304
305 /*rate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15*/
306 /*shift 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0, 0, 0, 0 */
307 /*mask 2047, 1023, 511, 255, 127, 63, 31, 15, 7, 3, 1, 0, 0, 0, 0, 0 */
308
309 #define O(a) (a*1)
310 static const uint8_t eg_rate_shift[32+64+32]={ /* Envelope Generator counter shifts (32 + 64 rates + 32 RKS) */
311 /* 32 infinite time rates */
312 /* O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
313 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
314 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0),
315 O(0),O(0),O(0),O(0),O(0),O(0),O(0),O(0), */
316
317 /* fixed (should be the same as rate 0, even if it makes no difference since increment value is 0 for these rates) */
318 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
319 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
320 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
321 O(11),O(11),O(11),O(11),O(11),O(11),O(11),O(11),
322
323 /* rates 00-11 */
324 O(11),O(11),O(11),O(11),
325 O(10),O(10),O(10),O(10),
326 O( 9),O( 9),O( 9),O( 9),
327 O( 8),O( 8),O( 8),O( 8),
328 O( 7),O( 7),O( 7),O( 7),
329 O( 6),O( 6),O( 6),O( 6),
330 O( 5),O( 5),O( 5),O( 5),
331 O( 4),O( 4),O( 4),O( 4),
332 O( 3),O( 3),O( 3),O( 3),
333 O( 2),O( 2),O( 2),O( 2),
334 O( 1),O( 1),O( 1),O( 1),
335 O( 0),O( 0),O( 0),O( 0),
336
337 /* rate 12 */
338 O( 0),O( 0),O( 0),O( 0),
339
340 /* rate 13 */
341 O( 0),O( 0),O( 0),O( 0),
342
343 /* rate 14 */
344 O( 0),O( 0),O( 0),O( 0),
345
346 /* rate 15 */
347 O( 0),O( 0),O( 0),O( 0),
348
349 /* 32 dummy rates (same as 15 3) */
350 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
351 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
352 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),
353 O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0),O( 0)
354
355 };
356 #undef O
357
358 static const uint8_t dt_tab[4 * 32]={
359 /* this is YM2151 and YM2612 phase increment data (in 10.10 fixed point format)*/
360 /* FD=0 */
361 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
362 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
363 /* FD=1 */
364 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
365 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, 8, 8, 8, 8,
366 /* FD=2 */
367 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5,
368 5, 6, 6, 7, 8, 8, 9,10,11,12,13,14,16,16,16,16,
369 /* FD=3 */
370 2, 2, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5, 6, 6, 7,
371 8 , 8, 9,10,11,12,13,14,16,17,19,20,22,22,22,22
372 };
373
374
375 /* OPN key frequency number -> key code follow table */
376 /* fnum higher 4bit -> keycode lower 2bit */
377 static const uint8_t opn_fktable[16] = {0,0,0,0,0,0,0,1,2,3,3,3,3,3,3,3};
378
379
380 /* 8 LFO speed parameters */
381 /* each value represents number of samples that one LFO level will last for */
382 static const uint32_t lfo_samples_per_step[8] = {108, 77, 71, 67, 62, 44, 8, 5};
383
384
385
386 /*There are 4 different LFO AM depths available, they are:
387 0 dB, 1.4 dB, 5.9 dB, 11.8 dB
388 Here is how it is generated (in EG steps):
389
390 11.8 dB = 0, 2, 4, 6, 8, 10,12,14,16...126,126,124,122,120,118,....4,2,0
391 5.9 dB = 0, 1, 2, 3, 4, 5, 6, 7, 8....63, 63, 62, 61, 60, 59,.....2,1,0
392 1.4 dB = 0, 0, 0, 0, 1, 1, 1, 1, 2,...15, 15, 15, 15, 14, 14,.....0,0,0
393
394 (1.4 dB is losing precision as you can see)
395
396 It's implemented as generator from 0..126 with step 2 then a shift
397 right N times, where N is:
398 8 for 0 dB
399 3 for 1.4 dB
400 1 for 5.9 dB
401 0 for 11.8 dB
402 */
403 static const uint8_t lfo_ams_depth_shift[4] = {8, 3, 1, 0};
404
405
406
407 /*There are 8 different LFO PM depths available, they are:
408 0, 3.4, 6.7, 10, 14, 20, 40, 80 (cents)
409
410 Modulation level at each depth depends on F-NUMBER bits: 4,5,6,7,8,9,10
411 (bits 8,9,10 = FNUM MSB from OCT/FNUM register)
412
413 Here we store only first quarter (positive one) of full waveform.
414 Full table (lfo_pm_table) containing all 128 waveforms is build
415 at run (init) time.
416
417 One value in table below represents 4 (four) basic LFO steps
418 (1 PM step = 4 AM steps).
419
420 For example:
421 at LFO SPEED=0 (which is 108 samples per basic LFO step)
422 one value from "lfo_pm_output" table lasts for 432 consecutive
423 samples (4*108=432) and one full LFO waveform cycle lasts for 13824
424 samples (32*432=13824; 32 because we store only a quarter of whole
425 waveform in the table below)
426 */
427 static const uint8_t lfo_pm_output[7*8][8]={ /* 7 bits meaningful (of F-NUMBER), 8 LFO output levels per one depth (out of 32), 8 LFO depths */
428 /* FNUM BIT 4: 000 0001xxxx */
429 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
430 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
431 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
432 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
433 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
434 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
435 /* DEPTH 6 */ {0, 0, 0, 0, 0, 0, 0, 0},
436 /* DEPTH 7 */ {0, 0, 0, 0, 1, 1, 1, 1},
437
438 /* FNUM BIT 5: 000 0010xxxx */
439 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
440 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
441 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
442 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
443 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 0},
444 /* DEPTH 5 */ {0, 0, 0, 0, 0, 0, 0, 0},
445 /* DEPTH 6 */ {0, 0, 0, 0, 1, 1, 1, 1},
446 /* DEPTH 7 */ {0, 0, 1, 1, 2, 2, 2, 3},
447
448 /* FNUM BIT 6: 000 0100xxxx */
449 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
450 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
451 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 0, 0},
452 /* DEPTH 3 */ {0, 0, 0, 0, 0, 0, 0, 0},
453 /* DEPTH 4 */ {0, 0, 0, 0, 0, 0, 0, 1},
454 /* DEPTH 5 */ {0, 0, 0, 0, 1, 1, 1, 1},
455 /* DEPTH 6 */ {0, 0, 1, 1, 2, 2, 2, 3},
456 /* DEPTH 7 */ {0, 0, 2, 3, 4, 4, 5, 6},
457
458 /* FNUM BIT 7: 000 1000xxxx */
459 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
460 /* DEPTH 1 */ {0, 0, 0, 0, 0, 0, 0, 0},
461 /* DEPTH 2 */ {0, 0, 0, 0, 0, 0, 1, 1},
462 /* DEPTH 3 */ {0, 0, 0, 0, 1, 1, 1, 1},
463 /* DEPTH 4 */ {0, 0, 0, 1, 1, 1, 1, 2},
464 /* DEPTH 5 */ {0, 0, 1, 1, 2, 2, 2, 3},
465 /* DEPTH 6 */ {0, 0, 2, 3, 4, 4, 5, 6},
466 /* DEPTH 7 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
467
468 /* FNUM BIT 8: 001 0000xxxx */
469 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
470 /* DEPTH 1 */ {0, 0, 0, 0, 1, 1, 1, 1},
471 /* DEPTH 2 */ {0, 0, 0, 1, 1, 1, 2, 2},
472 /* DEPTH 3 */ {0, 0, 1, 1, 2, 2, 3, 3},
473 /* DEPTH 4 */ {0, 0, 1, 2, 2, 2, 3, 4},
474 /* DEPTH 5 */ {0, 0, 2, 3, 4, 4, 5, 6},
475 /* DEPTH 6 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
476 /* DEPTH 7 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
477
478 /* FNUM BIT 9: 010 0000xxxx */
479 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
480 /* DEPTH 1 */ {0, 0, 0, 0, 2, 2, 2, 2},
481 /* DEPTH 2 */ {0, 0, 0, 2, 2, 2, 4, 4},
482 /* DEPTH 3 */ {0, 0, 2, 2, 4, 4, 6, 6},
483 /* DEPTH 4 */ {0, 0, 2, 4, 4, 4, 6, 8},
484 /* DEPTH 5 */ {0, 0, 4, 6, 8, 8, 0xa, 0xc},
485 /* DEPTH 6 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
486 /* DEPTH 7 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
487
488 /* FNUM BIT10: 100 0000xxxx */
489 /* DEPTH 0 */ {0, 0, 0, 0, 0, 0, 0, 0},
490 /* DEPTH 1 */ {0, 0, 0, 0, 4, 4, 4, 4},
491 /* DEPTH 2 */ {0, 0, 0, 4, 4, 4, 8, 8},
492 /* DEPTH 3 */ {0, 0, 4, 4, 8, 8, 0xc, 0xc},
493 /* DEPTH 4 */ {0, 0, 4, 8, 8, 8, 0xc,0x10},
494 /* DEPTH 5 */ {0, 0, 8, 0xc,0x10,0x10,0x14,0x18},
495 /* DEPTH 6 */ {0, 0,0x10,0x18,0x20,0x20,0x28,0x30},
496 /* DEPTH 7 */ {0, 0,0x20,0x30,0x40,0x40,0x50,0x60},
497
498 };
499
500 /* all 128 LFO PM waveforms */
501 static int32_t lfo_pm_table[128*8*32]; /* 128 combinations of 7 bits meaningful (of F-NUMBER), 8 LFO depths, 32 LFO output levels per one depth */
502
503 /* register number to channel number , slot offset */
504 #define OPN_CHAN(N) (N&3)
505 #define OPN_SLOT(N) ((N>>2)&3)
506
507 /* slot number */
508 #define SLOT1 0
509 #define SLOT2 2
510 #define SLOT3 1
511 #define SLOT4 3
512
513 /* bit0 = Right enable , bit1 = Left enable */
514 #define OUTD_RIGHT 1
515 #define OUTD_LEFT 2
516 #define OUTD_CENTER 3
517
518
519 /* save output as raw 16-bit sample */
520 /* #define SAVE_SAMPLE */
521
522 #ifdef SAVE_SAMPLE
523 static FILE *sample[1];
524 #if 1 /*save to MONO file */
525 #define SAVE_ALL_CHANNELS \
526 { signed int pom = lt; \
527 fputc((unsigned short)pom&0xff,sample[0]); \
528 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
529 }
530 #else /*save to STEREO file */
531 #define SAVE_ALL_CHANNELS \
532 { signed int pom = lt; \
533 fputc((unsigned short)pom&0xff,sample[0]); \
534 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
535 pom = rt; \
536 fputc((unsigned short)pom&0xff,sample[0]); \
537 fputc(((unsigned short)pom>>8)&0xff,sample[0]); \
538 }
539 #endif
540 #endif
541
542
543 /* struct describing a single operator (SLOT) */
544 struct fm2612_FM_SLOT
545 {
546 int32_t *DT; /* detune :dt_tab[DT] */
547 uint8_t KSR; /* key scale rate :3-KSR */
548 uint32_t ar; /* attack rate */
549 uint32_t d1r; /* decay rate */
550 uint32_t d2r; /* sustain rate */
551 uint32_t rr; /* release rate */
552 uint8_t ksr; /* key scale rate :kcode>>(3-KSR) */
553 uint32_t mul; /* multiple :ML_TABLE[ML] */
554
555 /* Phase Generator */
556 uint32_t phase; /* phase counter */
557 int32_t Incr; /* phase step */
558
559 /* Envelope Generator */
560 uint8_t state; /* phase type */
561 uint32_t tl; /* total level: TL << 3 */
562 int32_t volume; /* envelope counter */
563 uint32_t sl; /* sustain level:sl_table[SL] */
564 uint32_t vol_out; /* current output from EG circuit (without AM from LFO) */
565
566 uint8_t eg_sh_ar; /* (attack state) */
567 uint8_t eg_sel_ar; /* (attack state) */
568 uint8_t eg_sh_d1r; /* (decay state) */
569 uint8_t eg_sel_d1r; /* (decay state) */
570 uint8_t eg_sh_d2r; /* (sustain state) */
571 uint8_t eg_sel_d2r; /* (sustain state) */
572 uint8_t eg_sh_rr; /* (release state) */
573 uint8_t eg_sel_rr; /* (release state) */
574
575 uint8_t ssg; /* SSG-EG waveform */
576 uint8_t ssgn; /* SSG-EG negated output */
577
578 uint8_t key; /* 0=last key was KEY OFF, 1=KEY ON */
579
580 /* LFO */
581 uint32_t AMmask; /* AM enable flag */
582
583 };
584
585 struct fm2612_FM_CH
586 {
587 fm2612_FM_SLOT SLOT[4]; /* four SLOTs (operators) */
588
589 uint8_t ALGO; /* algorithm */
590 uint8_t FB; /* feedback shift */
591 int32_t op1_out[2]; /* op1 output for feedback */
592
593 int32_t *connect1; /* SLOT1 output pointer */
594 int32_t *connect3; /* SLOT3 output pointer */
595 int32_t *connect2; /* SLOT2 output pointer */
596 int32_t *connect4; /* SLOT4 output pointer */
597
598 int32_t *mem_connect;/* where to put the delayed sample (MEM) */
599 int32_t mem_value; /* delayed sample (MEM) value */
600
601 int32_t pms; /* channel PMS */
602 uint8_t ams; /* channel AMS */
603
604 uint32_t fc; /* fnum,blk:adjusted to sample rate */
605 uint8_t kcode; /* key code: */
606 uint32_t block_fnum; /* current blk/fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
607 };
608
609
610 struct fm2612_FM_ST
611 {
612 device_t *device;
613 double freqbase; /* frequency base */
614 int timer_prescaler; /* timer prescaler */
615 uint8_t irq; /* interrupt level */
616 uint8_t irqmask; /* irq mask */
617 #if FM_BUSY_FLAG_SUPPORT
618 TIME_TYPE busy_expiry_time; /* expiry time of the busy status */
619 #endif
620 uint32_t clock; /* master clock (Hz) */
621 uint32_t rate; /* sampling rate (Hz) */
622 uint16_t address; /* address register */
623 uint8_t status; /* status flag */
624 uint32_t mode; /* mode CSM / 3SLOT */
625 uint8_t fn_h; /* freq latch */
626 uint8_t prescaler_sel; /* prescaler selector */
627 int32_t TA; /* timer a */
628 int32_t TAC; /* timer a counter */
629 uint8_t TB; /* timer b */
630 int32_t TBC; /* timer b counter */
631 /* local time tables */
632 int32_t dt_tab[8][32]; /* DeTune table */
633 /* Extention Timer and IRQ handler */
634 FM_TIMERHANDLER timer_handler;
635 FM_IRQHANDLER IRQ_Handler;
636 const ssg_callbacks *SSG;
637 };
638
639
640
641 /***********************************************************/
642 /* OPN unit */
643 /***********************************************************/
644
645 /* OPN 3slot struct */
646 struct fm2612_FM_3SLOT
647 {
648 uint32_t fc[3]; /* fnum3,blk3: calculated */
649 uint8_t fn_h; /* freq3 latch */
650 uint8_t kcode[3]; /* key code */
651 uint32_t block_fnum[3]; /* current fnum value for this slot (can be different betweeen slots of one channel in 3slot mode) */
652 uint8_t key_csm; /* CSM mode Key-ON flag */
653 };
654
655 /* OPN/A/B common state */
656 struct fm2612_FM_OPN
657 {
658 uint8_t type; /* chip type */
659 fm2612_FM_ST ST; /* general state */
660 fm2612_FM_3SLOT SL3; /* 3 slot mode state */
661 fm2612_FM_CH *P_CH; /* pointer of CH */
662 unsigned int pan[6*2]; /* fm channels output masks (0xffffffff = enable) */
663
664 uint32_t eg_cnt; /* global envelope generator counter */
665 uint32_t eg_timer; /* global envelope generator counter works at frequency = chipclock/144/3 */
666 uint32_t eg_timer_add; /* step of eg_timer */
667 uint32_t eg_timer_overflow;/* envelope generator timer overflows every 3 samples (on real chip) */
668
669
670 /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
671 but LFO works with one more bit of a precision so we really need 4096 elements */
672 uint32_t fn_table[4096]; /* fnumber->increment counter */
673 uint32_t fn_max; /* maximal phase increment (used for phase overflow) */
674
675 /* LFO */
676 uint8_t lfo_cnt; /* current LFO phase (out of 128) */
677 uint32_t lfo_timer; /* current LFO phase runs at LFO frequency */
678 uint32_t lfo_timer_add; /* step of lfo_timer */
679 uint32_t lfo_timer_overflow; /* LFO timer overflows every N samples (depends on LFO frequency) */
680 uint32_t LFO_AM; /* current LFO AM step */
681 uint32_t LFO_PM; /* current LFO PM step */
682
683 int32_t m2,c1,c2; /* Phase Modulation input for operators 2,3,4 */
684 int32_t mem; /* one sample delay memory */
685 int32_t out_fm[8]; /* outputs of working channels */
686
687 };
688
689 /* here's the virtual YM2612 */
690 struct ym2612_state
691 {
692 uint8_t REGS[512]; /* registers */
693 fm2612_FM_OPN OPN; /* OPN state */
694 fm2612_FM_CH CH[6]; /* channel state */
695 uint8_t addr_A1; /* address line A1 */
696
697 /* dac output (YM2612) */
698 int dacen;
699 int32_t dacout;
700 device_t *device;
701 };
702
703 /* log output level */
704 #define LOG_ERR 3 /* ERROR */
705 #define LOG_WAR 2 /* WARNING */
706 #define LOG_INF 1 /* INFORMATION */
707 #define LOG_LEVEL LOG_INF
708
709 #ifndef __RAINE__
710 #define LOG(d,n,x) do { if( (n)>=LOG_LEVEL ) d->logerror x; } while (0)
711 #endif
712
713 /* limitter */
714 #define Limit(val, max,min) { \
715 if ( val > max ) val = max; \
716 else if ( val < min ) val = min; \
717 }
718
719
720 /* status set and IRQ handling */
FM_STATUS_SET(fm2612_FM_ST * ST,int flag)721 static inline void FM_STATUS_SET(fm2612_FM_ST *ST,int flag)
722 {
723 /* set status flag */
724 ST->status |= flag;
725 if ( !(ST->irq) && (ST->status & ST->irqmask) )
726 {
727 ST->irq = 1;
728 /* callback user interrupt handler (IRQ is OFF to ON) */
729 if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->device,1);
730 }
731 }
732
733 /* status reset and IRQ handling */
FM_STATUS_RESET(fm2612_FM_ST * ST,int flag)734 static inline void FM_STATUS_RESET(fm2612_FM_ST *ST,int flag)
735 {
736 /* reset status flag */
737 ST->status &=~flag;
738 if ( (ST->irq) && !(ST->status & ST->irqmask) )
739 {
740 ST->irq = 0;
741 /* callback user interrupt handler (IRQ is ON to OFF) */
742 if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->device,0);
743 }
744 }
745
746 /* IRQ mask set */
FM_IRQMASK_SET(fm2612_FM_ST * ST,int flag)747 static inline void FM_IRQMASK_SET(fm2612_FM_ST *ST,int flag)
748 {
749 ST->irqmask = flag;
750 /* IRQ handling check */
751 FM_STATUS_SET(ST,0);
752 FM_STATUS_RESET(ST,0);
753 }
754
FM_KEYON(fm2612_FM_OPN * OPN,fm2612_FM_CH * CH,int s)755 static inline void FM_KEYON(fm2612_FM_OPN *OPN, fm2612_FM_CH *CH , int s )
756 {
757 fm2612_FM_SLOT *SLOT = &CH->SLOT[s];
758
759 if( !SLOT->key && !OPN->SL3.key_csm)
760 {
761 /* restart Phase Generator */
762 SLOT->phase = 0;
763
764 /* reset SSG-EG inversion flag */
765 SLOT->ssgn = 0;
766
767 if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
768 {
769 SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
770 }
771 else
772 {
773 /* force attenuation level to 0 */
774 SLOT->volume = MIN_ATT_INDEX;
775
776 /* directly switch to Decay (or Sustain) */
777 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
778 }
779
780 /* recalculate EG output */
781 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)))
782 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
783 else
784 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
785 }
786
787 SLOT->key = 1;
788 }
789
FM_KEYOFF(fm2612_FM_OPN * OPN,fm2612_FM_CH * CH,int s)790 static inline void FM_KEYOFF(fm2612_FM_OPN *OPN, fm2612_FM_CH *CH , int s )
791 {
792 fm2612_FM_SLOT *SLOT = &CH->SLOT[s];
793
794 if (SLOT->key && !OPN->SL3.key_csm)
795 {
796 if (SLOT->state>EG_REL)
797 {
798 SLOT->state = EG_REL; /* phase -> Release */
799
800 /* SSG-EG specific update */
801 if (SLOT->ssg&0x08)
802 {
803 /* convert EG attenuation level */
804 if (SLOT->ssgn ^ (SLOT->ssg&0x04))
805 SLOT->volume = (0x200 - SLOT->volume);
806
807 /* force EG attenuation level */
808 if (SLOT->volume >= 0x200)
809 {
810 SLOT->volume = MAX_ATT_INDEX;
811 SLOT->state = EG_OFF;
812 }
813
814 /* recalculate EG output */
815 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
816 }
817 }
818 }
819
820 SLOT->key = 0;
821 }
822
FM_KEYON_CSM(fm2612_FM_OPN * OPN,fm2612_FM_CH * CH,int s)823 static inline void FM_KEYON_CSM(fm2612_FM_OPN *OPN, fm2612_FM_CH *CH , int s )
824 {
825 fm2612_FM_SLOT *SLOT = &CH->SLOT[s];
826
827 if( !SLOT->key && !OPN->SL3.key_csm)
828 {
829 /* restart Phase Generator */
830 SLOT->phase = 0;
831
832 /* reset SSG-EG inversion flag */
833 SLOT->ssgn = 0;
834
835 if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
836 {
837 SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
838 }
839 else
840 {
841 /* force attenuation level to 0 */
842 SLOT->volume = MIN_ATT_INDEX;
843
844 /* directly switch to Decay (or Sustain) */
845 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
846 }
847
848 /* recalculate EG output */
849 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)))
850 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
851 else
852 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
853 }
854 }
855
FM_KEYOFF_CSM(fm2612_FM_CH * CH,int s)856 static inline void FM_KEYOFF_CSM(fm2612_FM_CH *CH , int s )
857 {
858 fm2612_FM_SLOT *SLOT = &CH->SLOT[s];
859 if (!SLOT->key)
860 {
861 if (SLOT->state>EG_REL)
862 {
863 SLOT->state = EG_REL; /* phase -> Release */
864
865 /* SSG-EG specific update */
866 if (SLOT->ssg&0x08)
867 {
868 /* convert EG attenuation level */
869 if (SLOT->ssgn ^ (SLOT->ssg&0x04))
870 SLOT->volume = (0x200 - SLOT->volume);
871
872 /* force EG attenuation level */
873 if (SLOT->volume >= 0x200)
874 {
875 SLOT->volume = MAX_ATT_INDEX;
876 SLOT->state = EG_OFF;
877 }
878
879 /* recalculate EG output */
880 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
881 }
882 }
883 }
884 }
885
886 /* OPN Mode Register Write */
set_timers(fm2612_FM_OPN * OPN,fm2612_FM_ST * ST,device_t * n,int v)887 static inline void set_timers(fm2612_FM_OPN *OPN, fm2612_FM_ST *ST, device_t *n, int v)
888 {
889 /* b7 = CSM MODE */
890 /* b6 = 3 slot mode */
891 /* b5 = reset b */
892 /* b4 = reset a */
893 /* b3 = timer enable b */
894 /* b2 = timer enable a */
895 /* b1 = load b */
896 /* b0 = load a */
897
898 if ((OPN->ST.mode ^ v) & 0xC0)
899 {
900 /* phase increment need to be recalculated */
901 OPN->P_CH[2].SLOT[SLOT1].Incr=-1;
902
903 /* CSM mode disabled and CSM key ON active*/
904 if (((v & 0xC0) != 0x80) && OPN->SL3.key_csm)
905 {
906 /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
907 FM_KEYOFF_CSM(&OPN->P_CH[2],SLOT1);
908 FM_KEYOFF_CSM(&OPN->P_CH[2],SLOT2);
909 FM_KEYOFF_CSM(&OPN->P_CH[2],SLOT3);
910 FM_KEYOFF_CSM(&OPN->P_CH[2],SLOT4);
911 OPN->SL3.key_csm = 0;
912 }
913 }
914
915 /* reload Timers */
916 if ((v&1) && !(ST->mode&1))
917 {
918 ST->TAC = (1024-ST->TA);
919 /* External timer handler */
920 if (ST->timer_handler) (ST->timer_handler)(n,0,ST->TAC * ST->timer_prescaler,ST->clock);
921 }
922 else if (!(v & 1))
923 {
924 if( ST->TAC != 0 )
925 {
926 ST->TAC = 0;
927 if (ST->timer_handler) (ST->timer_handler)(n,0,0,ST->clock);
928 }
929 }
930
931 if ((v&2) && !(ST->mode&2))
932 {
933 ST->TBC = ( 256-ST->TB)<<4;
934 /* External timer handler */
935 if (ST->timer_handler) (ST->timer_handler)(n,1,ST->TBC * ST->timer_prescaler,ST->clock);
936 }
937 else if (!(v & 2))
938 {
939 if( ST->TBC != 0 )
940 {
941 ST->TBC = 0;
942 if (ST->timer_handler) (ST->timer_handler)(n,1,0,ST->clock);
943 }
944 }
945
946 /* reset Timers flags */
947 ST->status &= (~v >> 4);
948
949 /* if IRQ should be lowered now, do so */
950 if ( (ST->irq) && !(ST->status & ST->irqmask) )
951 {
952 ST->irq = 0;
953 /* callback user interrupt handler (IRQ is ON to OFF) */
954 if(ST->IRQ_Handler) (ST->IRQ_Handler)(ST->device, 0);
955 }
956 ST->mode = v;
957 }
958
959
960 /* Timer A Overflow */
TimerAOver(fm2612_FM_ST * ST)961 static inline void TimerAOver(fm2612_FM_ST *ST)
962 {
963 /* set status (if enabled) */
964 if(ST->mode & 0x04) FM_STATUS_SET(ST,0x01);
965 /* clear or reload the counter */
966 ST->TAC = (1024-ST->TA);
967 if (ST->timer_handler) (ST->timer_handler)(ST->device,0,ST->TAC * ST->timer_prescaler,ST->clock);
968 }
969 /* Timer B Overflow */
TimerBOver(fm2612_FM_ST * ST)970 static inline void TimerBOver(fm2612_FM_ST *ST)
971 {
972 /* set status (if enabled) */
973 if(ST->mode & 0x08) FM_STATUS_SET(ST,0x02);
974 /* clear or reload the counter */
975 ST->TBC = ( 256-ST->TB)<<4;
976 if (ST->timer_handler) (ST->timer_handler)(ST->device,1,ST->TBC * ST->timer_prescaler,ST->clock);
977 }
978
979
980 #if FM_INTERNAL_TIMER
981 /* ----- internal timer mode , update timer */
982
983 /* ---------- calculate timer A ---------- */
984 #define INTERNAL_TIMER_A(ST,CSM_CH) \
985 { \
986 if( ST->TAC && (ST->timer_handler==0) ) \
987 if( (ST->TAC -= (int)(ST->freqbase*4096)) <= 0 ) \
988 { \
989 TimerAOver( ST ); \
990 /* CSM mode total level latch and auto key on */ \
991 if( ST->mode & 0x80 ) \
992 CSMKeyControll( CSM_CH ); \
993 } \
994 }
995 /* ---------- calculate timer B ---------- */
996 #define INTERNAL_TIMER_B(ST,step) \
997 { \
998 if( ST->TBC && (ST->timer_handler==0) ) \
999 if( (ST->TBC -= (int)(ST->freqbase*4096*step)) <= 0 ) \
1000 TimerBOver( ST ); \
1001 }
1002 #else /* FM_INTERNAL_TIMER */
1003 /* external timer mode */
1004 #define INTERNAL_TIMER_A(ST,CSM_CH)
1005 #define INTERNAL_TIMER_B(ST,step)
1006 #endif /* FM_INTERNAL_TIMER */
1007
1008
1009
1010 #if FM_BUSY_FLAG_SUPPORT
1011 #define FM_BUSY_CLEAR(ST) ((ST)->busy_expiry_time = UNDEFINED_TIME)
FM_STATUS_FLAG(fm2612_FM_ST * ST)1012 static inline uint8_t FM_STATUS_FLAG(fm2612_FM_ST *ST)
1013 {
1014 if( COMPARE_TIMES(ST->busy_expiry_time, UNDEFINED_TIME) != 0 )
1015 {
1016 if (COMPARE_TIMES(ST->busy_expiry_time, FM_GET_TIME_NOW(&ST->device->machine())) > 0)
1017 return ST->status | 0x80; /* with busy */
1018 /* expire */
1019 FM_BUSY_CLEAR(ST);
1020 }
1021 return ST->status;
1022 }
1023 #if 0
1024 static inline void FM_BUSY_SET(fm2612_FM_ST *ST,int busyclock )
1025 {
1026 TIME_TYPE expiry_period = MULTIPLY_TIME_BY_INT(attotime::from_hz(ST->clock), busyclock * ST->timer_prescaler);
1027 ST->busy_expiry_time = ADD_TIMES(FM_GET_TIME_NOW(&ST->device->machine()), expiry_period);
1028 }
1029 #endif
1030 #else
1031 #define FM_STATUS_FLAG(ST) ((ST)->status)
1032 #define FM_BUSY_SET(ST,bclock) {}
1033 #define FM_BUSY_CLEAR(ST) {}
1034 #endif
1035
1036
1037 /* set algorithm connection */
setup_connection(fm2612_FM_OPN * OPN,fm2612_FM_CH * CH,int ch)1038 static void setup_connection(fm2612_FM_OPN *OPN, fm2612_FM_CH *CH, int ch)
1039 {
1040 int32_t *carrier = &OPN->out_fm[ch];
1041
1042 int32_t **om1 = &CH->connect1;
1043 int32_t **om2 = &CH->connect3;
1044 int32_t **oc1 = &CH->connect2;
1045
1046 int32_t **memc = &CH->mem_connect;
1047
1048 switch( CH->ALGO )
1049 {
1050 case 0:
1051 /* M1---C1---MEM---M2---C2---OUT */
1052 *om1 = &OPN->c1;
1053 *oc1 = &OPN->mem;
1054 *om2 = &OPN->c2;
1055 *memc= &OPN->m2;
1056 break;
1057 case 1:
1058 /* M1------+-MEM---M2---C2---OUT */
1059 /* C1-+ */
1060 *om1 = &OPN->mem;
1061 *oc1 = &OPN->mem;
1062 *om2 = &OPN->c2;
1063 *memc= &OPN->m2;
1064 break;
1065 case 2:
1066 /* M1-----------------+-C2---OUT */
1067 /* C1---MEM---M2-+ */
1068 *om1 = &OPN->c2;
1069 *oc1 = &OPN->mem;
1070 *om2 = &OPN->c2;
1071 *memc= &OPN->m2;
1072 break;
1073 case 3:
1074 /* M1---C1---MEM------+-C2---OUT */
1075 /* M2-+ */
1076 *om1 = &OPN->c1;
1077 *oc1 = &OPN->mem;
1078 *om2 = &OPN->c2;
1079 *memc= &OPN->c2;
1080 break;
1081 case 4:
1082 /* M1---C1-+-OUT */
1083 /* M2---C2-+ */
1084 /* MEM: not used */
1085 *om1 = &OPN->c1;
1086 *oc1 = carrier;
1087 *om2 = &OPN->c2;
1088 *memc= &OPN->mem; /* store it anywhere where it will not be used */
1089 break;
1090 case 5:
1091 /* +----C1----+ */
1092 /* M1-+-MEM---M2-+-OUT */
1093 /* +----C2----+ */
1094 *om1 = nullptr; /* special mark */
1095 *oc1 = carrier;
1096 *om2 = carrier;
1097 *memc= &OPN->m2;
1098 break;
1099 case 6:
1100 /* M1---C1-+ */
1101 /* M2-+-OUT */
1102 /* C2-+ */
1103 /* MEM: not used */
1104 *om1 = &OPN->c1;
1105 *oc1 = carrier;
1106 *om2 = carrier;
1107 *memc= &OPN->mem; /* store it anywhere where it will not be used */
1108 break;
1109 case 7:
1110 /* M1-+ */
1111 /* C1-+-OUT */
1112 /* M2-+ */
1113 /* C2-+ */
1114 /* MEM: not used*/
1115 *om1 = carrier;
1116 *oc1 = carrier;
1117 *om2 = carrier;
1118 *memc= &OPN->mem; /* store it anywhere where it will not be used */
1119 break;
1120 }
1121
1122 CH->connect4 = carrier;
1123 }
1124
1125 /* set detune & multiple */
set_det_mul(fm2612_FM_ST * ST,fm2612_FM_CH * CH,fm2612_FM_SLOT * SLOT,int v)1126 static inline void set_det_mul(fm2612_FM_ST *ST,fm2612_FM_CH *CH,fm2612_FM_SLOT *SLOT,int v)
1127 {
1128 SLOT->mul = (v&0x0f)? (v&0x0f)*2 : 1;
1129 SLOT->DT = ST->dt_tab[(v>>4)&7];
1130 CH->SLOT[SLOT1].Incr=-1;
1131 }
1132
1133 /* set total level */
set_tl(fm2612_FM_CH * CH,fm2612_FM_SLOT * SLOT,int v)1134 static inline void set_tl(fm2612_FM_CH *CH,fm2612_FM_SLOT *SLOT , int v)
1135 {
1136 SLOT->tl = (v&0x7f)<<(ENV_BITS-7); /* 7bit TL */
1137
1138 /* recalculate EG output */
1139 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)) && (SLOT->state > EG_REL))
1140 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1141 else
1142 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1143 }
1144
1145 /* set attack rate & key scale */
set_ar_ksr(uint8_t type,fm2612_FM_CH * CH,fm2612_FM_SLOT * SLOT,int v)1146 static inline void set_ar_ksr(uint8_t type, fm2612_FM_CH *CH,fm2612_FM_SLOT *SLOT,int v)
1147 {
1148 uint8_t old_KSR = SLOT->KSR;
1149
1150 SLOT->ar = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1151
1152 SLOT->KSR = 3-(v>>6);
1153 if (SLOT->KSR != old_KSR)
1154 {
1155 CH->SLOT[SLOT1].Incr=-1;
1156 }
1157
1158 /* Even if it seems unnecessary, in some odd case, KSR and KC are modified */
1159 /* and could result in SLOT->kc remaining unchanged. */
1160 /* In such case, AR values would not be recalculated despite SLOT->ar has changed */
1161 /* This actually fixes the intro of "The Adventures of Batman & Robin" (Eke-Eke) */
1162 if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
1163 {
1164 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1165 SLOT->eg_sel_ar = eg_rate_select2612[SLOT->ar + SLOT->ksr ];
1166 }
1167 else
1168 {
1169 SLOT->eg_sh_ar = 0;
1170 SLOT->eg_sel_ar = 18*RATE_STEPS; /* verified by Nemesis on real hardware */
1171 }
1172 }
1173
1174 /* set decay rate */
set_dr(uint8_t type,fm2612_FM_SLOT * SLOT,int v)1175 static inline void set_dr(uint8_t type, fm2612_FM_SLOT *SLOT,int v)
1176 {
1177 SLOT->d1r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1178
1179 SLOT->eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
1180 SLOT->eg_sel_d1r= eg_rate_select2612[SLOT->d1r + SLOT->ksr];
1181 }
1182
1183 /* set sustain rate */
set_sr(uint8_t type,fm2612_FM_SLOT * SLOT,int v)1184 static inline void set_sr(uint8_t type, fm2612_FM_SLOT *SLOT,int v)
1185 {
1186 SLOT->d2r = (v&0x1f) ? 32 + ((v&0x1f)<<1) : 0;
1187
1188 SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
1189 SLOT->eg_sel_d2r= eg_rate_select2612[SLOT->d2r + SLOT->ksr];
1190 }
1191
1192 /* set release rate */
set_sl_rr(uint8_t type,fm2612_FM_SLOT * SLOT,int v)1193 static inline void set_sl_rr(uint8_t type, fm2612_FM_SLOT *SLOT,int v)
1194 {
1195 SLOT->sl = sl_table[ v>>4 ];
1196
1197 /* check EG state changes */
1198 if ((SLOT->state == EG_DEC) && (SLOT->volume >= (int32_t)(SLOT->sl)))
1199 SLOT->state = EG_SUS;
1200
1201 SLOT->rr = 34 + ((v&0x0f)<<2);
1202
1203 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
1204 SLOT->eg_sel_rr = eg_rate_select2612[SLOT->rr + SLOT->ksr];
1205 }
1206
1207 /* advance LFO to next sample */
advance_lfo(fm2612_FM_OPN * OPN)1208 static inline void advance_lfo(fm2612_FM_OPN *OPN)
1209 {
1210 if (OPN->lfo_timer_overflow) /* LFO enabled ? */
1211 {
1212 /* increment LFO timer */
1213 OPN->lfo_timer += OPN->lfo_timer_add;
1214
1215 /* when LFO is enabled, one level will last for 108, 77, 71, 67, 62, 44, 8 or 5 samples */
1216 while (OPN->lfo_timer >= OPN->lfo_timer_overflow)
1217 {
1218 OPN->lfo_timer -= OPN->lfo_timer_overflow;
1219
1220 /* There are 128 LFO steps */
1221 OPN->lfo_cnt = ( OPN->lfo_cnt + 1 ) & 127;
1222
1223 /* triangle (inverted) */
1224 /* AM: from 126 to 0 step -2, 0 to 126 step +2 */
1225 if (OPN->lfo_cnt<64)
1226 OPN->LFO_AM = (OPN->lfo_cnt ^ 63) << 1;
1227 else
1228 OPN->LFO_AM = (OPN->lfo_cnt & 63) << 1;
1229
1230 /* PM works with 4 times slower clock */
1231 OPN->LFO_PM = OPN->lfo_cnt >> 2;
1232 }
1233 }
1234 }
1235
1236 /* changed from static inline to static here to work around gcc 4.2.1 codegen bug */
advance_eg_channel(fm2612_FM_OPN * OPN,fm2612_FM_SLOT * SLOT)1237 static void advance_eg_channel(fm2612_FM_OPN *OPN, fm2612_FM_SLOT *SLOT)
1238 {
1239 unsigned int out;
1240 unsigned int i = 4; /* four operators per channel */
1241
1242 do
1243 {
1244 switch(SLOT->state)
1245 {
1246 case EG_ATT: /* attack phase */
1247 if (!(OPN->eg_cnt & ((1<<SLOT->eg_sh_ar)-1)))
1248 {
1249 /* update attenuation level */
1250 SLOT->volume += (~SLOT->volume * (eg_inc[SLOT->eg_sel_ar + ((OPN->eg_cnt>>SLOT->eg_sh_ar)&7)]))>>4;
1251
1252 /* check phase transition*/
1253 if (SLOT->volume <= MIN_ATT_INDEX)
1254 {
1255 SLOT->volume = MIN_ATT_INDEX;
1256 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC; /* special case where SL=0 */
1257 }
1258
1259 /* recalculate EG output */
1260 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04))) /* SSG-EG Output Inversion */
1261 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1262 else
1263 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1264 }
1265 break;
1266
1267 case EG_DEC: /* decay phase */
1268 if (!(OPN->eg_cnt & ((1<<SLOT->eg_sh_d1r)-1)))
1269 {
1270 /* SSG EG type */
1271 if (SLOT->ssg&0x08)
1272 {
1273 /* update attenuation level */
1274 if (SLOT->volume < 0x200)
1275 {
1276 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_d1r + ((OPN->eg_cnt>>SLOT->eg_sh_d1r)&7)];
1277
1278 /* recalculate EG output */
1279 if (SLOT->ssgn ^ (SLOT->ssg&0x04)) /* SSG-EG Output Inversion */
1280 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1281 else
1282 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1283 }
1284
1285 }
1286 else
1287 {
1288 /* update attenuation level */
1289 SLOT->volume += eg_inc[SLOT->eg_sel_d1r + ((OPN->eg_cnt>>SLOT->eg_sh_d1r)&7)];
1290
1291 /* recalculate EG output */
1292 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1293 }
1294
1295 /* check phase transition*/
1296 if (SLOT->volume >= (int32_t)(SLOT->sl))
1297 SLOT->state = EG_SUS;
1298 }
1299 break;
1300
1301 case EG_SUS: /* sustain phase */
1302 if (!(OPN->eg_cnt & ((1<<SLOT->eg_sh_d2r)-1)))
1303 {
1304 /* SSG EG type */
1305 if (SLOT->ssg&0x08)
1306 {
1307 /* update attenuation level */
1308 if (SLOT->volume < 0x200)
1309 {
1310 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_d2r + ((OPN->eg_cnt>>SLOT->eg_sh_d2r)&7)];
1311
1312 /* recalculate EG output */
1313 if (SLOT->ssgn ^ (SLOT->ssg&0x04)) /* SSG-EG Output Inversion */
1314 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1315 else
1316 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1317 }
1318 }
1319 else
1320 {
1321 /* update attenuation level */
1322 SLOT->volume += eg_inc[SLOT->eg_sel_d2r + ((OPN->eg_cnt>>SLOT->eg_sh_d2r)&7)];
1323
1324 /* check phase transition*/
1325 if ( SLOT->volume >= MAX_ATT_INDEX )
1326 SLOT->volume = MAX_ATT_INDEX;
1327 /* do not change SLOT->state (verified on real chip) */
1328
1329 /* recalculate EG output */
1330 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1331 }
1332 }
1333 break;
1334
1335 case EG_REL: /* release phase */
1336 if (!(OPN->eg_cnt & ((1<<SLOT->eg_sh_rr)-1)))
1337 {
1338 /* SSG EG type */
1339 if (SLOT->ssg&0x08)
1340 {
1341 /* update attenuation level */
1342 if (SLOT->volume < 0x200)
1343 SLOT->volume += 4 * eg_inc[SLOT->eg_sel_rr + ((OPN->eg_cnt>>SLOT->eg_sh_rr)&7)];
1344 /* check phase transition */
1345 if (SLOT->volume >= 0x200)
1346 {
1347 SLOT->volume = MAX_ATT_INDEX;
1348 SLOT->state = EG_OFF;
1349 }
1350 }
1351 else
1352 {
1353 /* update attenuation level */
1354 SLOT->volume += eg_inc[SLOT->eg_sel_rr + ((OPN->eg_cnt>>SLOT->eg_sh_rr)&7)];
1355
1356 /* check phase transition*/
1357 if (SLOT->volume >= MAX_ATT_INDEX)
1358 {
1359 SLOT->volume = MAX_ATT_INDEX;
1360 SLOT->state = EG_OFF;
1361 }
1362 }
1363
1364 /* recalculate EG output */
1365 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1366
1367 }
1368 break;
1369 }
1370
1371 out = ((uint32_t)SLOT->volume);
1372
1373 /* negate output (changes come from alternate bit, init comes from attack bit) */
1374 if ((SLOT->ssg&0x08) && (SLOT->ssgn&2) && (SLOT->state > EG_REL))
1375 out ^= MAX_ATT_INDEX;
1376
1377 /* we need to store the result here because we are going to change ssgn
1378 in next instruction */
1379 SLOT->vol_out = out + SLOT->tl;
1380
1381 SLOT++;
1382 i--;
1383 }while (i);
1384
1385 }
1386
1387 /* SSG-EG update process */
1388 /* The behavior is based upon Nemesis tests on real hardware */
1389 /* This is actually executed before each samples */
update_ssg_eg_channel(fm2612_FM_SLOT * SLOT)1390 static void update_ssg_eg_channel(fm2612_FM_SLOT *SLOT)
1391 {
1392 unsigned int i = 4; /* four operators per channel */
1393
1394 do
1395 {
1396 /* detect SSG-EG transition */
1397 /* this is not required during release phase as the attenuation has been forced to MAX and output invert flag is not used */
1398 /* if an Attack Phase is programmed, inversion can occur on each sample */
1399 if ((SLOT->ssg & 0x08) && (SLOT->volume >= 0x200) && (SLOT->state > EG_REL))
1400 {
1401 if (SLOT->ssg & 0x01) /* bit 0 = hold SSG-EG */
1402 {
1403 /* set inversion flag */
1404 if (SLOT->ssg & 0x02)
1405 SLOT->ssgn = 4;
1406
1407 /* force attenuation level during decay phases */
1408 if ((SLOT->state != EG_ATT) && !(SLOT->ssgn ^ (SLOT->ssg & 0x04)))
1409 SLOT->volume = MAX_ATT_INDEX;
1410 }
1411 else /* loop SSG-EG */
1412 {
1413 /* toggle output inversion flag or reset Phase Generator */
1414 if (SLOT->ssg & 0x02)
1415 SLOT->ssgn ^= 4;
1416 else
1417 SLOT->phase = 0;
1418
1419 /* same as Key ON */
1420 if (SLOT->state != EG_ATT)
1421 {
1422 if ((SLOT->ar + SLOT->ksr) < 94 /*32+62*/)
1423 {
1424 SLOT->state = (SLOT->volume <= MIN_ATT_INDEX) ? ((SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC) : EG_ATT;
1425 }
1426 else
1427 {
1428 /* Attack Rate is maximal: directly switch to Decay or Substain */
1429 SLOT->volume = MIN_ATT_INDEX;
1430 SLOT->state = (SLOT->sl == MIN_ATT_INDEX) ? EG_SUS : EG_DEC;
1431 }
1432 }
1433 }
1434
1435 /* recalculate EG output */
1436 if (SLOT->ssgn ^ (SLOT->ssg&0x04))
1437 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1438 else
1439 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1440 }
1441
1442 /* next slot */
1443 SLOT++;
1444 i--;
1445 } while (i);
1446 }
1447
1448
update_phase_lfo_slot(fm2612_FM_OPN * OPN,fm2612_FM_SLOT * SLOT,int32_t pms,uint32_t block_fnum)1449 static inline void update_phase_lfo_slot(fm2612_FM_OPN *OPN, fm2612_FM_SLOT *SLOT, int32_t pms, uint32_t block_fnum)
1450 {
1451 uint32_t fnum_lfo = ((block_fnum & 0x7f0) >> 4) * 32 * 8;
1452 int32_t lfo_fn_table_index_offset = lfo_pm_table[ fnum_lfo + pms + OPN->LFO_PM ];
1453
1454 block_fnum = block_fnum*2 + lfo_fn_table_index_offset;
1455
1456 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
1457 {
1458 uint8_t blk = (block_fnum&0x7000) >> 12;
1459 uint32_t fn = block_fnum & 0xfff;
1460
1461 /* recalculate keyscale code */
1462 int kc = (blk<<2) | opn_fktable[(fn >> 7) & 0xf];
1463
1464 /* recalculate (frequency) phase increment counter */
1465 int fc = (OPN->fn_table[fn]>>(7-blk)) + SLOT->DT[kc];
1466
1467 /* (frequency) phase overflow (credits to Nemesis) */
1468 if (fc < 0) fc += OPN->fn_max;
1469
1470 /* update phase */
1471 SLOT->phase += (fc * SLOT->mul) >> 1;
1472 }
1473 else /* LFO phase modulation = zero */
1474 {
1475 SLOT->phase += SLOT->Incr;
1476 }
1477 }
1478
update_phase_lfo_channel(fm2612_FM_OPN * OPN,fm2612_FM_CH * CH)1479 static inline void update_phase_lfo_channel(fm2612_FM_OPN *OPN, fm2612_FM_CH *CH)
1480 {
1481 uint32_t block_fnum = CH->block_fnum;
1482
1483 uint32_t fnum_lfo = ((block_fnum & 0x7f0) >> 4) * 32 * 8;
1484 int32_t lfo_fn_table_index_offset = lfo_pm_table[ fnum_lfo + CH->pms + OPN->LFO_PM ];
1485
1486 block_fnum = block_fnum*2 + lfo_fn_table_index_offset;
1487
1488 if (lfo_fn_table_index_offset) /* LFO phase modulation active */
1489 {
1490 uint8_t blk = (block_fnum&0x7000) >> 12;
1491 uint32_t fn = block_fnum & 0xfff;
1492
1493 /* recalculate keyscale code */
1494 int kc = (blk<<2) | opn_fktable[(fn >> 7) & 0xf];
1495
1496 /* recalculate (frequency) phase increment counter */
1497 int fc = (OPN->fn_table[fn]>>(7-blk));
1498
1499 /* (frequency) phase overflow (credits to Nemesis) */
1500 int finc = fc + CH->SLOT[SLOT1].DT[kc];
1501 if (finc < 0) finc += OPN->fn_max;
1502 CH->SLOT[SLOT1].phase += (finc*CH->SLOT[SLOT1].mul) >> 1;
1503
1504 finc = fc + CH->SLOT[SLOT2].DT[kc];
1505 if (finc < 0) finc += OPN->fn_max;
1506 CH->SLOT[SLOT2].phase += (finc*CH->SLOT[SLOT2].mul) >> 1;
1507
1508 finc = fc + CH->SLOT[SLOT3].DT[kc];
1509 if (finc < 0) finc += OPN->fn_max;
1510 CH->SLOT[SLOT3].phase += (finc*CH->SLOT[SLOT3].mul) >> 1;
1511
1512 finc = fc + CH->SLOT[SLOT4].DT[kc];
1513 if (finc < 0) finc += OPN->fn_max;
1514 CH->SLOT[SLOT4].phase += (finc*CH->SLOT[SLOT4].mul) >> 1;
1515 }
1516 else /* LFO phase modulation = zero */
1517 {
1518 CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
1519 CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
1520 CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
1521 CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
1522 }
1523 }
1524
1525 /* update phase increment and envelope generator */
refresh_fc_eg_slot(fm2612_FM_OPN * OPN,fm2612_FM_SLOT * SLOT,int fc,int kc)1526 static inline void refresh_fc_eg_slot(fm2612_FM_OPN *OPN, fm2612_FM_SLOT *SLOT , int fc , int kc )
1527 {
1528 int ksr = kc >> SLOT->KSR;
1529
1530 fc += SLOT->DT[kc];
1531
1532 /* detects frequency overflow (credits to Nemesis) */
1533 if (fc < 0) fc += OPN->fn_max;
1534
1535 /* (frequency) phase increment counter */
1536 SLOT->Incr = (fc * SLOT->mul) >> 1;
1537
1538 if( SLOT->ksr != ksr )
1539 {
1540 SLOT->ksr = ksr;
1541
1542 /* calculate envelope generator rates */
1543 if ((SLOT->ar + SLOT->ksr) < 32+62)
1544 {
1545 SLOT->eg_sh_ar = eg_rate_shift [SLOT->ar + SLOT->ksr ];
1546 SLOT->eg_sel_ar = eg_rate_select2612[SLOT->ar + SLOT->ksr ];
1547 }
1548 else
1549 {
1550 SLOT->eg_sh_ar = 0;
1551 SLOT->eg_sel_ar = 18*RATE_STEPS; /* verified by Nemesis on real hardware (Attack phase is blocked) */
1552 }
1553
1554 SLOT->eg_sh_d1r = eg_rate_shift [SLOT->d1r + SLOT->ksr];
1555 SLOT->eg_sh_d2r = eg_rate_shift [SLOT->d2r + SLOT->ksr];
1556 SLOT->eg_sh_rr = eg_rate_shift [SLOT->rr + SLOT->ksr];
1557
1558 SLOT->eg_sel_d1r= eg_rate_select2612[SLOT->d1r + SLOT->ksr];
1559 SLOT->eg_sel_d2r= eg_rate_select2612[SLOT->d2r + SLOT->ksr];
1560 SLOT->eg_sel_rr = eg_rate_select2612[SLOT->rr + SLOT->ksr];
1561 }
1562 }
1563
1564 /* update phase increment counters */
1565 /* Changed from static inline to static to work around gcc 4.2.1 codegen bug */
refresh_fc_eg_chan(fm2612_FM_OPN * OPN,fm2612_FM_CH * CH)1566 static void refresh_fc_eg_chan(fm2612_FM_OPN *OPN, fm2612_FM_CH *CH )
1567 {
1568 if( CH->SLOT[SLOT1].Incr==-1)
1569 {
1570 int fc = CH->fc;
1571 int kc = CH->kcode;
1572 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT1] , fc , kc );
1573 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT2] , fc , kc );
1574 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT3] , fc , kc );
1575 refresh_fc_eg_slot(OPN, &CH->SLOT[SLOT4] , fc , kc );
1576 }
1577 }
1578
1579 #define volume_calc(OP) ((OP)->vol_out + (AM & (OP)->AMmask))
1580
op_calc(uint32_t phase,unsigned int env,signed int pm)1581 static inline signed int op_calc(uint32_t phase, unsigned int env, signed int pm)
1582 {
1583 uint32_t p;
1584
1585 p = (env<<3) + sin_tab[ ( ((signed int)((phase & ~FREQ_MASK) + (pm<<15))) >> FREQ_SH ) & SIN_MASK ];
1586
1587 if (p >= TL_TAB_LEN)
1588 return 0;
1589 return tl_tab[p];
1590 }
1591
op_calc1(uint32_t phase,unsigned int env,signed int pm)1592 static inline signed int op_calc1(uint32_t phase, unsigned int env, signed int pm)
1593 {
1594 uint32_t p;
1595
1596 p = (env<<3) + sin_tab[ ( ((signed int)((phase & ~FREQ_MASK) + pm )) >> FREQ_SH ) & SIN_MASK ];
1597
1598 if (p >= TL_TAB_LEN)
1599 return 0;
1600 return tl_tab[p];
1601 }
1602
chan_calc(ym2612_state * F2612,fm2612_FM_OPN * OPN,fm2612_FM_CH * CH)1603 static inline void chan_calc(ym2612_state *F2612, fm2612_FM_OPN *OPN, fm2612_FM_CH *CH)
1604 {
1605 uint32_t AM = OPN->LFO_AM >> CH->ams;
1606 unsigned int eg_out = volume_calc(&CH->SLOT[SLOT1]);
1607
1608 OPN->m2 = OPN->c1 = OPN->c2 = OPN->mem = 0;
1609
1610 *CH->mem_connect = CH->mem_value; /* restore delayed sample (MEM) value to m2 or c2 */
1611
1612 {
1613 int32_t out = CH->op1_out[0] + CH->op1_out[1];
1614 CH->op1_out[0] = CH->op1_out[1];
1615
1616 if( !CH->connect1 )
1617 {
1618 /* algorithm 5 */
1619 OPN->mem = OPN->c1 = OPN->c2 = CH->op1_out[0];
1620 }
1621 else
1622 {
1623 /* other algorithms */
1624 *CH->connect1 += CH->op1_out[0];
1625 }
1626
1627
1628 CH->op1_out[1] = 0;
1629 if( eg_out < ENV_QUIET ) /* SLOT 1 */
1630 {
1631 if (!CH->FB)
1632 out=0;
1633
1634 CH->op1_out[1] = op_calc1(CH->SLOT[SLOT1].phase, eg_out, (out<<CH->FB) );
1635 }
1636 }
1637
1638 eg_out = volume_calc(&CH->SLOT[SLOT3]);
1639 if( eg_out < ENV_QUIET ) /* SLOT 3 */
1640 *CH->connect3 += op_calc(CH->SLOT[SLOT3].phase, eg_out, OPN->m2);
1641
1642 eg_out = volume_calc(&CH->SLOT[SLOT2]);
1643 if( eg_out < ENV_QUIET ) /* SLOT 2 */
1644 *CH->connect2 += op_calc(CH->SLOT[SLOT2].phase, eg_out, OPN->c1);
1645
1646 eg_out = volume_calc(&CH->SLOT[SLOT4]);
1647 if( eg_out < ENV_QUIET ) /* SLOT 4 */
1648 *CH->connect4 += op_calc(CH->SLOT[SLOT4].phase, eg_out, OPN->c2);
1649
1650
1651 /* store current MEM */
1652 CH->mem_value = OPN->mem;
1653
1654 /* update phase counters AFTER output calculations */
1655 if(CH->pms)
1656 {
1657 /* add support for 3 slot mode */
1658 if ((OPN->ST.mode & 0xC0) && (CH == &F2612->CH[2]))
1659 {
1660 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT1], CH->pms, OPN->SL3.block_fnum[1]);
1661 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT2], CH->pms, OPN->SL3.block_fnum[2]);
1662 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT3], CH->pms, OPN->SL3.block_fnum[0]);
1663 update_phase_lfo_slot(OPN, &CH->SLOT[SLOT4], CH->pms, CH->block_fnum);
1664 }
1665 else update_phase_lfo_channel(OPN, CH);
1666 }
1667 else /* no LFO phase modulation */
1668 {
1669 CH->SLOT[SLOT1].phase += CH->SLOT[SLOT1].Incr;
1670 CH->SLOT[SLOT2].phase += CH->SLOT[SLOT2].Incr;
1671 CH->SLOT[SLOT3].phase += CH->SLOT[SLOT3].Incr;
1672 CH->SLOT[SLOT4].phase += CH->SLOT[SLOT4].Incr;
1673 }
1674 }
1675
FMCloseTable(void)1676 static void FMCloseTable( void )
1677 {
1678 #ifdef SAVE_SAMPLE
1679 fclose(sample[0]);
1680 #endif
1681 return;
1682 }
1683
1684
1685 /* CSM Key Controll */
CSMKeyControll(fm2612_FM_OPN * OPN,fm2612_FM_CH * CH)1686 static inline void CSMKeyControll(fm2612_FM_OPN *OPN, fm2612_FM_CH *CH)
1687 {
1688 /* all key ON (verified by Nemesis on real hardware) */
1689 FM_KEYON_CSM(OPN,CH,SLOT1);
1690 FM_KEYON_CSM(OPN,CH,SLOT2);
1691 FM_KEYON_CSM(OPN,CH,SLOT3);
1692 FM_KEYON_CSM(OPN,CH,SLOT4);
1693 OPN->SL3.key_csm = 1;
1694 }
1695
1696 #ifdef MAME_EMU_SAVE_H
1697 /* FM channel save , internal state only */
FMsave_state_channel(device_t * device,fm2612_FM_CH * CH,int num_ch)1698 static void FMsave_state_channel(device_t *device,fm2612_FM_CH *CH,int num_ch)
1699 {
1700 /* channel */
1701 device->save_pointer(STRUCT_MEMBER(CH, op1_out), num_ch);
1702 device->save_pointer(STRUCT_MEMBER(CH, fc), num_ch);
1703
1704 /* slots */
1705 for(int ch=0;ch<num_ch;ch++,CH++)
1706 {
1707 device->save_item(STRUCT_MEMBER(CH->SLOT, phase), ch);
1708 device->save_item(STRUCT_MEMBER(CH->SLOT, state), ch);
1709 device->save_item(STRUCT_MEMBER(CH->SLOT, volume), ch);
1710 }
1711 }
1712
FMsave_state_st(device_t * device,fm2612_FM_ST * ST)1713 static void FMsave_state_st(device_t *device,fm2612_FM_ST *ST)
1714 {
1715 #if FM_BUSY_FLAG_SUPPORT
1716 device->save_item(NAME(ST->busy_expiry_time) );
1717 #endif
1718 device->save_item(NAME(ST->address) );
1719 device->save_item(NAME(ST->irq) );
1720 device->save_item(NAME(ST->irqmask) );
1721 device->save_item(NAME(ST->status) );
1722 device->save_item(NAME(ST->mode) );
1723 device->save_item(NAME(ST->prescaler_sel) );
1724 device->save_item(NAME(ST->fn_h) );
1725 device->save_item(NAME(ST->TA) );
1726 device->save_item(NAME(ST->TAC) );
1727 device->save_item(NAME(ST->TB) );
1728 device->save_item(NAME(ST->TBC) );
1729 }
1730 #endif /* MAME_EMU_SAVE_H */
1731
1732 #if BUILD_OPN
1733 /* write a OPN mode register 0x20-0x2f */
OPNWriteMode(fm2612_FM_OPN * OPN,int r,int v)1734 static void OPNWriteMode(fm2612_FM_OPN *OPN, int r, int v)
1735 {
1736 uint8_t c;
1737 fm2612_FM_CH *CH;
1738
1739 switch(r)
1740 {
1741 case 0x21: /* Test */
1742 break;
1743 case 0x22: /* LFO FREQ (YM2608/YM2610/YM2610B/YM2612) */
1744 if (v&8) /* LFO enabled ? */
1745 {
1746 OPN->lfo_timer_overflow = lfo_samples_per_step[v&7] << LFO_SH;
1747 }
1748 else
1749 {
1750 /* hold LFO waveform in reset state */
1751 OPN->lfo_timer_overflow = 0;
1752 OPN->lfo_timer = 0;
1753 OPN->lfo_cnt = 0;
1754 OPN->LFO_PM = 0;
1755 OPN->LFO_AM = 126;
1756 }
1757 break;
1758 case 0x24: /* timer A High 8*/
1759 OPN->ST.TA = (OPN->ST.TA & 0x03)|(((int)v)<<2);
1760 break;
1761 case 0x25: /* timer A Low 2*/
1762 OPN->ST.TA = (OPN->ST.TA & 0x3fc)|(v&3);
1763 break;
1764 case 0x26: /* timer B */
1765 OPN->ST.TB = v;
1766 break;
1767 case 0x27: /* mode, timer control */
1768 set_timers( OPN, &(OPN->ST),OPN->ST.device,v );
1769 break;
1770 case 0x28: /* key on / off */
1771 c = v & 0x03;
1772 if( c == 3 ) break;
1773 if( (v&0x04) && (OPN->type & TYPE_6CH) ) c+=3;
1774 CH = OPN->P_CH;
1775 CH = &CH[c];
1776 if(v&0x10) FM_KEYON(OPN,CH,SLOT1); else FM_KEYOFF(OPN,CH,SLOT1);
1777 if(v&0x20) FM_KEYON(OPN,CH,SLOT2); else FM_KEYOFF(OPN,CH,SLOT2);
1778 if(v&0x40) FM_KEYON(OPN,CH,SLOT3); else FM_KEYOFF(OPN,CH,SLOT3);
1779 if(v&0x80) FM_KEYON(OPN,CH,SLOT4); else FM_KEYOFF(OPN,CH,SLOT4);
1780 break;
1781 }
1782 }
1783
1784 /* write a OPN register (0x30-0xff) */
OPNWriteReg(fm2612_FM_OPN * OPN,int r,int v)1785 static void OPNWriteReg(fm2612_FM_OPN *OPN, int r, int v)
1786 {
1787 fm2612_FM_CH *CH;
1788 fm2612_FM_SLOT *SLOT;
1789
1790 uint8_t c = OPN_CHAN(r);
1791
1792 if (c == 3) return; /* 0xX3,0xX7,0xXB,0xXF */
1793
1794 if (r >= 0x100) c+=3;
1795
1796 CH = OPN->P_CH;
1797 CH = &CH[c];
1798
1799 SLOT = &(CH->SLOT[OPN_SLOT(r)]);
1800
1801 switch( r & 0xf0 ) {
1802 case 0x30: /* DET , MUL */
1803 set_det_mul(&OPN->ST,CH,SLOT,v);
1804 break;
1805
1806 case 0x40: /* TL */
1807 set_tl(CH,SLOT,v);
1808 break;
1809
1810 case 0x50: /* KS, AR */
1811 set_ar_ksr(OPN->type,CH,SLOT,v);
1812 break;
1813
1814 case 0x60: /* bit7 = AM ENABLE, DR */
1815 set_dr(OPN->type, SLOT,v);
1816
1817 if(OPN->type & TYPE_LFOPAN) /* YM2608/2610/2610B/2612 */
1818 {
1819 SLOT->AMmask = (v&0x80) ? ~0 : 0;
1820 }
1821 break;
1822
1823 case 0x70: /* SR */
1824 set_sr(OPN->type,SLOT,v);
1825 break;
1826
1827 case 0x80: /* SL, RR */
1828 set_sl_rr(OPN->type,SLOT,v);
1829 break;
1830
1831 case 0x90: /* SSG-EG */
1832 SLOT->ssg = v&0x0f;
1833
1834 /* recalculate EG output */
1835 if ((SLOT->ssg&0x08) && (SLOT->ssgn ^ (SLOT->ssg&0x04)) && (SLOT->state > EG_REL))
1836 SLOT->vol_out = ((uint32_t)(0x200 - SLOT->volume) & MAX_ATT_INDEX) + SLOT->tl;
1837 else
1838 SLOT->vol_out = (uint32_t)SLOT->volume + SLOT->tl;
1839
1840 /* SSG-EG envelope shapes :
1841
1842 E AtAlH
1843 1 0 0 0 \\\\
1844
1845 1 0 0 1 \___
1846
1847 1 0 1 0 \/\/
1848 ___
1849 1 0 1 1 \
1850
1851 1 1 0 0 ////
1852 ___
1853 1 1 0 1 /
1854
1855 1 1 1 0 /\/\
1856
1857 1 1 1 1 /___
1858
1859
1860 E = SSG-EG enable
1861
1862
1863 The shapes are generated using Attack, Decay and Sustain phases.
1864
1865 Each single character in the diagrams above represents this whole
1866 sequence:
1867
1868 - when KEY-ON = 1, normal Attack phase is generated (*without* any
1869 difference when compared to normal mode),
1870
1871 - later, when envelope level reaches minimum level (max volume),
1872 the EG switches to Decay phase (which works with bigger steps
1873 when compared to normal mode - see below),
1874
1875 - later when envelope level passes the SL level,
1876 the EG swithes to Sustain phase (which works with bigger steps
1877 when compared to normal mode - see below),
1878
1879 - finally when envelope level reaches maximum level (min volume),
1880 the EG switches to Attack phase again (depends on actual waveform).
1881
1882 Important is that when switch to Attack phase occurs, the phase counter
1883 of that operator will be zeroed-out (as in normal KEY-ON) but not always.
1884 (I havent found the rule for that - perhaps only when the output level is low)
1885
1886 The difference (when compared to normal Envelope Generator mode) is
1887 that the resolution in Decay and Sustain phases is 4 times lower;
1888 this results in only 256 steps instead of normal 1024.
1889 In other words:
1890 when SSG-EG is disabled, the step inside of the EG is one,
1891 when SSG-EG is enabled, the step is four (in Decay and Sustain phases).
1892
1893 Times between the level changes are the same in both modes.
1894
1895
1896 Important:
1897 Decay 1 Level (so called SL) is compared to actual SSG-EG output, so
1898 it is the same in both SSG and no-SSG modes, with this exception:
1899
1900 when the SSG-EG is enabled and is generating raising levels
1901 (when the EG output is inverted) the SL will be found at wrong level !!!
1902 For example, when SL=02:
1903 0 -6 = -6dB in non-inverted EG output
1904 96-6 = -90dB in inverted EG output
1905 Which means that EG compares its level to SL as usual, and that the
1906 output is simply inverted afterall.
1907
1908
1909 The Yamaha's manuals say that AR should be set to 0x1f (max speed).
1910 That is not necessary, but then EG will be generating Attack phase.
1911
1912 */
1913
1914
1915 break;
1916
1917 case 0xa0:
1918 switch( OPN_SLOT(r) )
1919 {
1920 case 0: /* 0xa0-0xa2 : FNUM1 */
1921 {
1922 uint32_t fn = (((uint32_t)( (OPN->ST.fn_h)&7))<<8) + v;
1923 uint8_t blk = OPN->ST.fn_h>>3;
1924 /* keyscale code */
1925 CH->kcode = (blk<<2) | opn_fktable[(fn >> 7) & 0xf];
1926 /* phase increment counter */
1927 CH->fc = OPN->fn_table[fn*2]>>(7-blk);
1928
1929 /* store fnum in clear form for LFO PM calculations */
1930 CH->block_fnum = (blk<<11) | fn;
1931
1932 CH->SLOT[SLOT1].Incr=-1;
1933 }
1934 break;
1935 case 1: /* 0xa4-0xa6 : FNUM2,BLK */
1936 OPN->ST.fn_h = v&0x3f;
1937 break;
1938 case 2: /* 0xa8-0xaa : 3CH FNUM1 */
1939 if(r < 0x100)
1940 {
1941 uint32_t fn = (((uint32_t)(OPN->SL3.fn_h&7))<<8) + v;
1942 uint8_t blk = OPN->SL3.fn_h>>3;
1943 /* keyscale code */
1944 OPN->SL3.kcode[c]= (blk<<2) | opn_fktable[(fn >> 7) & 0xf];
1945 /* phase increment counter */
1946 OPN->SL3.fc[c] = OPN->fn_table[fn*2]>>(7-blk);
1947 OPN->SL3.block_fnum[c] = (blk<<11) | fn;
1948 (OPN->P_CH)[2].SLOT[SLOT1].Incr=-1;
1949 }
1950 break;
1951 case 3: /* 0xac-0xae : 3CH FNUM2,BLK */
1952 if(r < 0x100)
1953 OPN->SL3.fn_h = v&0x3f;
1954 break;
1955 }
1956 break;
1957
1958 case 0xb0:
1959 switch( OPN_SLOT(r) )
1960 {
1961 case 0: /* 0xb0-0xb2 : FB,ALGO */
1962 {
1963 int feedback = (v>>3)&7;
1964 CH->ALGO = v&7;
1965 CH->FB = feedback ? feedback+6 : 0;
1966 setup_connection( OPN, CH, c );
1967 }
1968 break;
1969 case 1: /* 0xb4-0xb6 : L , R , AMS , PMS (YM2612/YM2610B/YM2610/YM2608) */
1970 if( OPN->type & TYPE_LFOPAN)
1971 {
1972 /* b0-2 PMS */
1973 CH->pms = (v & 7) * 32; /* CH->pms = PM depth * 32 (index in lfo_pm_table) */
1974
1975 /* b4-5 AMS */
1976 CH->ams = lfo_ams_depth_shift[(v>>4) & 0x03];
1977
1978 /* PAN : b7 = L, b6 = R */
1979 OPN->pan[ c*2 ] = (v & 0x80) ? ~0 : 0;
1980 OPN->pan[ c*2+1 ] = (v & 0x40) ? ~0 : 0;
1981
1982 }
1983 break;
1984 }
1985 break;
1986 }
1987 }
1988
1989 /* initialize time tables */
init_timetables(fm2612_FM_OPN * OPN,double freqbase)1990 static void init_timetables(fm2612_FM_OPN *OPN, double freqbase)
1991 {
1992 int i,d;
1993 double rate;
1994
1995 /* DeTune table */
1996 for (d = 0;d <= 3;d++)
1997 {
1998 for (i = 0;i <= 31;i++)
1999 {
2000 rate = ((double)dt_tab[d*32 + i]) * freqbase * (1<<(FREQ_SH-10)); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
2001 OPN->ST.dt_tab[d][i] = (int32_t) rate;
2002 OPN->ST.dt_tab[d+4][i] = -OPN->ST.dt_tab[d][i];
2003 }
2004 }
2005
2006 /* there are 2048 FNUMs that can be generated using FNUM/BLK registers
2007 but LFO works with one more bit of a precision so we really need 4096 elements */
2008 /* calculate fnumber -> increment counter table */
2009 for(i = 0; i < 4096; i++)
2010 {
2011 /* freq table for octave 7 */
2012 /* OPN phase increment counter = 20bit */
2013 /* the correct formula is : F-Number = (144 * fnote * 2^20 / M) / 2^(B-1) */
2014 /* where sample clock is M/144 */
2015 /* this means the increment value for one clock sample is FNUM * 2^(B-1) = FNUM * 64 for octave 7 */
2016 /* we also need to handle the ratio between the chip frequency and the emulated frequency (can be 1.0) */
2017 OPN->fn_table[i] = (uint32_t)( (double)i * 32 * freqbase * (1<<(FREQ_SH-10)) ); /* -10 because chip works with 10.10 fixed point, while we use 16.16 */
2018 }
2019
2020 /* maximal frequency is required for Phase overflow calculation, register size is 17 bits (Nemesis) */
2021 OPN->fn_max = (uint32_t)( (double)0x20000 * freqbase * (1<<(FREQ_SH-10)) );
2022 }
2023
2024 /* prescaler set (and make time tables) */
OPNSetPres(fm2612_FM_OPN * OPN,int pres,int timer_prescaler,int SSGpres)2025 static void OPNSetPres(fm2612_FM_OPN *OPN, int pres, int timer_prescaler, int SSGpres)
2026 {
2027 /* frequency base */
2028 OPN->ST.freqbase = (OPN->ST.rate) ? ((double)OPN->ST.clock / OPN->ST.rate) / pres : 0;
2029
2030 /* EG is updated every 3 samples */
2031 OPN->eg_timer_add = (uint32_t)((1<<EG_SH) * OPN->ST.freqbase);
2032 OPN->eg_timer_overflow = ( 3 ) * (1<<EG_SH);
2033
2034 /* LFO timer increment (every samples) */
2035 OPN->lfo_timer_add = (uint32_t)((1<<LFO_SH) * OPN->ST.freqbase);
2036
2037 /* Timer base time */
2038 OPN->ST.timer_prescaler = timer_prescaler;
2039
2040 /* SSG part prescaler set */
2041 if( SSGpres ) (*OPN->ST.SSG->set_clock)( OPN->ST.device, OPN->ST.clock * 2 / SSGpres );
2042
2043 /* make time tables */
2044 init_timetables(OPN, OPN->ST.freqbase);
2045 }
2046
reset_channels(fm2612_FM_ST * ST,fm2612_FM_CH * CH,int num)2047 static void reset_channels(fm2612_FM_ST *ST , fm2612_FM_CH *CH , int num)
2048 {
2049 int c,s;
2050
2051 for( c = 0 ; c < num ; c++ )
2052 {
2053 CH[c].fc = 0;
2054 for(s = 0 ; s < 4 ; s++ )
2055 {
2056 CH[c].SLOT[s].ssg = 0;
2057 CH[c].SLOT[s].ssgn = 0;
2058 CH[c].SLOT[s].state= EG_OFF;
2059 CH[c].SLOT[s].volume = MAX_ATT_INDEX;
2060 CH[c].SLOT[s].vol_out= MAX_ATT_INDEX;
2061 }
2062 }
2063 }
2064
2065 /* initialize generic tables */
init_tables(void)2066 static void init_tables(void)
2067 {
2068 signed int i,x;
2069 signed int n;
2070 double o,m;
2071
2072 /* build Linear Power Table */
2073 for (x=0; x<TL_RES_LEN; x++)
2074 {
2075 m = (1<<16) / pow(2, (x+1) * (ENV_STEP/4.0) / 8.0);
2076 m = floor(m);
2077
2078 /* we never reach (1<<16) here due to the (x+1) */
2079 /* result fits within 16 bits at maximum */
2080
2081 n = (int)m; /* 16 bits here */
2082 n >>= 4; /* 12 bits here */
2083 if (n&1) /* round to nearest */
2084 n = (n>>1)+1;
2085 else
2086 n = n>>1;
2087 /* 11 bits here (rounded) */
2088 n <<= 2; /* 13 bits here (as in real chip) */
2089
2090
2091 /* 14 bits (with sign bit) */
2092 tl_tab[ x*2 + 0 ] = n;
2093 tl_tab[ x*2 + 1 ] = -tl_tab[ x*2 + 0 ];
2094
2095 /* one entry in the 'Power' table use the following format, xxxxxyyyyyyyys with: */
2096 /* s = sign bit */
2097 /* yyyyyyyy = 8-bits decimal part (0-TL_RES_LEN) */
2098 /* xxxxx = 5-bits integer 'shift' value (0-31) but, since Power table output is 13 bits, */
2099 /* any value above 13 (included) would be discarded. */
2100 for (i=1; i<13; i++)
2101 {
2102 tl_tab[ x*2+0 + i*2*TL_RES_LEN ] = tl_tab[ x*2+0 ]>>i;
2103 tl_tab[ x*2+1 + i*2*TL_RES_LEN ] = -tl_tab[ x*2+0 + i*2*TL_RES_LEN ];
2104 }
2105 }
2106
2107 /* build Logarithmic Sinus table */
2108 for (i=0; i<SIN_LEN; i++)
2109 {
2110 /* non-standard sinus */
2111 m = sin( ((i*2)+1) * M_PI / SIN_LEN ); /* checked against the real chip */
2112 /* we never reach zero here due to ((i*2)+1) */
2113
2114 if (m>0.0)
2115 o = 8*log(1.0/m)/log(2.0); /* convert to 'decibels' */
2116 else
2117 o = 8*log(-1.0/m)/log(2.0); /* convert to 'decibels' */
2118
2119 o = o / (ENV_STEP/4);
2120
2121 n = (int)(2.0*o);
2122 if (n&1) /* round to nearest */
2123 n = (n>>1)+1;
2124 else
2125 n = n>>1;
2126
2127 /* 13-bits (8.5) value is formatted for above 'Power' table */
2128 sin_tab[ i ] = n*2 + (m>=0.0? 0: 1 );
2129 }
2130
2131 /* build LFO PM modulation table */
2132 for(i = 0; i < 8; i++) /* 8 PM depths */
2133 {
2134 uint8_t fnum;
2135 for (fnum=0; fnum<128; fnum++) /* 7 bits meaningful of F-NUMBER */
2136 {
2137 uint8_t value;
2138 uint8_t step;
2139 uint32_t offset_depth = i;
2140 uint32_t offset_fnum_bit;
2141 uint32_t bit_tmp;
2142
2143 for (step=0; step<8; step++)
2144 {
2145 value = 0;
2146 for (bit_tmp=0; bit_tmp<7; bit_tmp++) /* 7 bits */
2147 {
2148 if (fnum & (1<<bit_tmp)) /* only if bit "bit_tmp" is set */
2149 {
2150 offset_fnum_bit = bit_tmp * 8;
2151 value += lfo_pm_output[offset_fnum_bit + offset_depth][step];
2152 }
2153 }
2154 /* 32 steps for LFO PM (sinus) */
2155 lfo_pm_table[(fnum*32*8) + (i*32) + step + 0] = value;
2156 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+ 8] = value;
2157 lfo_pm_table[(fnum*32*8) + (i*32) + step +16] = -value;
2158 lfo_pm_table[(fnum*32*8) + (i*32) +(step^7)+24] = -value;
2159 }
2160
2161 }
2162 }
2163
2164 #ifdef SAVE_SAMPLE
2165 sample[0]=fopen("sampsum.pcm","wb");
2166 #endif
2167 }
2168
2169 #endif /* BUILD_OPN */
2170
2171 #if (BUILD_YM2612||BUILD_YM3438)
2172 /*******************************************************************************/
2173 /* YM2612 local section */
2174 /*******************************************************************************/
2175
2176 /* Generate samples for one of the YM2612s */
ym2612_update_one(void * chip,std::vector<write_stream_view> & buffer,u8 output_bits)2177 void ym2612_update_one(void *chip, std::vector<write_stream_view> &buffer, u8 output_bits)
2178 {
2179 // TODO : 'ladder' effects for Mega Drive/Genesis
2180 const u8 output_shift = (output_bits > 14) ? 0 : (14 - output_bits);
2181 const s32 output_nandmask = (1 << output_shift) - 1;
2182 ym2612_state *F2612 = (ym2612_state *)chip;
2183 fm2612_FM_OPN *OPN = &F2612->OPN;
2184 int32_t *out_fm = OPN->out_fm;
2185 int i;
2186 fm2612_FM_CH *cch[6];
2187 int lt,rt;
2188
2189 /* set bufer */
2190 auto &bufL = buffer[0];
2191 auto &bufR = buffer[1];
2192
2193 cch[0] = &F2612->CH[0];
2194 cch[1] = &F2612->CH[1];
2195 cch[2] = &F2612->CH[2];
2196 cch[3] = &F2612->CH[3];
2197 cch[4] = &F2612->CH[4];
2198 cch[5] = &F2612->CH[5];
2199
2200 /* refresh PG and EG */
2201 refresh_fc_eg_chan( OPN, cch[0] );
2202 refresh_fc_eg_chan( OPN, cch[1] );
2203 if( (OPN->ST.mode & 0xc0) )
2204 {
2205 /* 3SLOT MODE */
2206 if( cch[2]->SLOT[SLOT1].Incr==-1)
2207 {
2208 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT1] , OPN->SL3.fc[1] , OPN->SL3.kcode[1] );
2209 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT2] , OPN->SL3.fc[2] , OPN->SL3.kcode[2] );
2210 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT3] , OPN->SL3.fc[0] , OPN->SL3.kcode[0] );
2211 refresh_fc_eg_slot(OPN, &cch[2]->SLOT[SLOT4] , cch[2]->fc , cch[2]->kcode );
2212 }
2213 }
2214 else
2215 refresh_fc_eg_chan( OPN, cch[2] );
2216
2217 refresh_fc_eg_chan( OPN, cch[3] );
2218 refresh_fc_eg_chan( OPN, cch[4] );
2219 refresh_fc_eg_chan( OPN, cch[5] );
2220
2221 /* buffering */
2222 for(i=0; i < bufL.samples() ; i++)
2223 {
2224 /* clear outputs */
2225 out_fm[0] = 0;
2226 out_fm[1] = 0;
2227 out_fm[2] = 0;
2228 out_fm[3] = 0;
2229 out_fm[4] = 0;
2230 out_fm[5] = 0;
2231
2232 /* update SSG-EG output */
2233 update_ssg_eg_channel(&cch[0]->SLOT[SLOT1]);
2234 update_ssg_eg_channel(&cch[1]->SLOT[SLOT1]);
2235 update_ssg_eg_channel(&cch[2]->SLOT[SLOT1]);
2236 update_ssg_eg_channel(&cch[3]->SLOT[SLOT1]);
2237 update_ssg_eg_channel(&cch[4]->SLOT[SLOT1]);
2238 update_ssg_eg_channel(&cch[5]->SLOT[SLOT1]);
2239
2240 /* calculate FM */
2241 chan_calc(F2612, OPN, cch[0]);
2242 chan_calc(F2612, OPN, cch[1]);
2243 chan_calc(F2612, OPN, cch[2]);
2244 chan_calc(F2612, OPN, cch[3]);
2245 chan_calc(F2612, OPN, cch[4]);
2246 if( F2612->dacen )
2247 *cch[5]->connect4 += F2612->dacout << 5;
2248 else
2249 chan_calc(F2612, OPN, cch[5]);
2250
2251 /* advance LFO */
2252 advance_lfo(OPN);
2253
2254 /* advance envelope generator */
2255 OPN->eg_timer += OPN->eg_timer_add;
2256 while (OPN->eg_timer >= OPN->eg_timer_overflow)
2257 {
2258 OPN->eg_timer -= OPN->eg_timer_overflow;
2259 OPN->eg_cnt++;
2260
2261 advance_eg_channel(OPN, &cch[0]->SLOT[SLOT1]);
2262 advance_eg_channel(OPN, &cch[1]->SLOT[SLOT1]);
2263 advance_eg_channel(OPN, &cch[2]->SLOT[SLOT1]);
2264 advance_eg_channel(OPN, &cch[3]->SLOT[SLOT1]);
2265 advance_eg_channel(OPN, &cch[4]->SLOT[SLOT1]);
2266 advance_eg_channel(OPN, &cch[5]->SLOT[SLOT1]);
2267 }
2268
2269 if (out_fm[0] > 8191) out_fm[0] = 8191;
2270 else if (out_fm[0] < -8192) out_fm[0] = -8192;
2271 if (out_fm[1] > 8191) out_fm[1] = 8191;
2272 else if (out_fm[1] < -8192) out_fm[1] = -8192;
2273 if (out_fm[2] > 8191) out_fm[2] = 8191;
2274 else if (out_fm[2] < -8192) out_fm[2] = -8192;
2275 if (out_fm[3] > 8191) out_fm[3] = 8191;
2276 else if (out_fm[3] < -8192) out_fm[3] = -8192;
2277 if (out_fm[4] > 8191) out_fm[4] = 8191;
2278 else if (out_fm[4] < -8192) out_fm[4] = -8192;
2279 if (out_fm[5] > 8191) out_fm[5] = 8191;
2280 else if (out_fm[5] < -8192) out_fm[5] = -8192;
2281
2282 /* 6-channels mixing */
2283 lt = (((out_fm[0]) & OPN->pan[0]) & ~output_nandmask);
2284 rt = (((out_fm[0]) & OPN->pan[1]) & ~output_nandmask);
2285 lt += (((out_fm[1]) & OPN->pan[2]) & ~output_nandmask);
2286 rt += (((out_fm[1]) & OPN->pan[3]) & ~output_nandmask);
2287 lt += (((out_fm[2]) & OPN->pan[4]) & ~output_nandmask);
2288 rt += (((out_fm[2]) & OPN->pan[5]) & ~output_nandmask);
2289 lt += (((out_fm[3]) & OPN->pan[6]) & ~output_nandmask);
2290 rt += (((out_fm[3]) & OPN->pan[7]) & ~output_nandmask);
2291 lt += (((out_fm[4]) & OPN->pan[8]) & ~output_nandmask);
2292 rt += (((out_fm[4]) & OPN->pan[9]) & ~output_nandmask);
2293 lt += (((out_fm[5]) & OPN->pan[10]) & ~output_nandmask);
2294 rt += (((out_fm[5]) & OPN->pan[11]) & ~output_nandmask);
2295
2296 // Limit( lt, MAXOUT, MINOUT );
2297 // Limit( rt, MAXOUT, MINOUT );
2298
2299 #ifdef SAVE_SAMPLE
2300 SAVE_ALL_CHANNELS
2301 #endif
2302
2303 /* buffering */
2304 bufL.put_int(i, lt, 32768);
2305 bufR.put_int(i, rt, 32768);
2306
2307 /* CSM mode: if CSM Key ON has occurred, CSM Key OFF need to be sent */
2308 /* only if Timer A does not overflow again (i.e CSM Key ON not set again) */
2309 OPN->SL3.key_csm <<= 1;
2310
2311 /* timer A control */
2312 INTERNAL_TIMER_A( &OPN->ST , cch[2] )
2313
2314 /* CSM Mode Key ON still disabled */
2315 /* CSM Mode Key OFF (verified by Nemesis on real hardware) */
2316 FM_KEYOFF_CSM(cch[2],SLOT1);
2317 FM_KEYOFF_CSM(cch[2],SLOT2);
2318 FM_KEYOFF_CSM(cch[2],SLOT3);
2319 FM_KEYOFF_CSM(cch[2],SLOT4);
2320 OPN->SL3.key_csm = 0;
2321 }
2322
2323 /* timer B control */
2324 INTERNAL_TIMER_B(&OPN->ST,length)
2325 }
2326
2327 #ifdef MAME_EMU_SAVE_H
ym2612_postload(void * chip)2328 void ym2612_postload(void *chip)
2329 {
2330 if (chip)
2331 {
2332 ym2612_state *F2612 = (ym2612_state *)chip;
2333 int r;
2334
2335 /* DAC data & port */
2336 F2612->dacout = (((int)F2612->REGS[0x2a] - 0x80) << 1) | (BIT(F2612->REGS[0x2c], 3));
2337 F2612->dacen = F2612->REGS[0x2b] & 0x80;
2338 /* OPN registers */
2339 /* DT / MULTI , TL , KS / AR , AMON / DR , SR , SL / RR , SSG-EG */
2340 for(r=0x30;r<0x9e;r++)
2341 if((r&3) != 3)
2342 {
2343 OPNWriteReg(&F2612->OPN,r,F2612->REGS[r]);
2344 OPNWriteReg(&F2612->OPN,r|0x100,F2612->REGS[r|0x100]);
2345 }
2346 /* FB / CONNECT , L / R / AMS / PMS */
2347 for(r=0xb0;r<0xb6;r++)
2348 if((r&3) != 3)
2349 {
2350 OPNWriteReg(&F2612->OPN,r,F2612->REGS[r]);
2351 OPNWriteReg(&F2612->OPN,r|0x100,F2612->REGS[r|0x100]);
2352 }
2353 /* channels */
2354 /*FM_channel_postload(F2612->CH,6);*/
2355 }
2356 }
2357
YM2612_save_state(ym2612_state * F2612,device_t * device)2358 static void YM2612_save_state(ym2612_state *F2612, device_t *device)
2359 {
2360 device->save_item(NAME(F2612->REGS));
2361 FMsave_state_st(device,&F2612->OPN.ST);
2362 FMsave_state_channel(device,F2612->CH,6);
2363 /* 3slots */
2364 device->save_item(NAME(F2612->OPN.SL3.fc));
2365 device->save_item(NAME(F2612->OPN.SL3.fn_h));
2366 device->save_item(NAME(F2612->OPN.SL3.kcode));
2367 /* address register1 */
2368 device->save_item(NAME(F2612->addr_A1));
2369 }
2370 #endif /* MAME_EMU_SAVE_H */
2371
2372 /* initialize YM2612 emulator(s) */
ym2612_init(device_t * device,int clock,int rate,FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler)2373 void * ym2612_init(device_t *device, int clock, int rate,
2374 FM_TIMERHANDLER timer_handler,FM_IRQHANDLER IRQHandler)
2375 {
2376 ym2612_state *F2612;
2377
2378 /* allocate extend state space */
2379 F2612 = auto_alloc_clear(device->machine(), <ym2612_state>());
2380 /* allocate total level table (128kb space) */
2381 init_tables();
2382
2383 F2612->device = device;
2384 F2612->OPN.type = TYPE_YM2612;
2385 F2612->OPN.P_CH = F2612->CH;
2386 F2612->OPN.ST.device = device;
2387 F2612->OPN.ST.clock = clock;
2388 F2612->OPN.ST.rate = rate;
2389 /* F2612->OPN.ST.irq = 0; */
2390 /* F2612->OPN.ST.status = 0; */
2391 /* Extend handler */
2392 F2612->OPN.ST.timer_handler = timer_handler;
2393 F2612->OPN.ST.IRQ_Handler = IRQHandler;
2394
2395 #ifdef MAME_EMU_SAVE_H
2396 YM2612_save_state(F2612, device);
2397 #endif
2398 return F2612;
2399 }
2400
ym2612_clock_changed(void * chip,int clock,int rate)2401 void ym2612_clock_changed(void *chip, int clock, int rate)
2402 {
2403 ym2612_state *F2612 = (ym2612_state *)chip;
2404
2405 F2612->OPN.ST.clock = clock;
2406 F2612->OPN.ST.rate = rate;
2407 }
2408
2409 /* shut down emulator */
ym2612_shutdown(void * chip)2410 void ym2612_shutdown(void *chip)
2411 {
2412 ym2612_state *F2612 = (ym2612_state *)chip;
2413
2414 FMCloseTable();
2415 auto_free(F2612->OPN.ST.device->machine(), F2612);
2416 }
2417
2418 /* reset one of chip */
ym2612_reset_chip(void * chip)2419 void ym2612_reset_chip(void *chip)
2420 {
2421 int i;
2422 ym2612_state *F2612 = (ym2612_state *)chip;
2423 fm2612_FM_OPN *OPN = &F2612->OPN;
2424
2425 OPNSetPres( OPN, 6*24, 6*24, 0);
2426 /* status clear */
2427 FM_IRQMASK_SET(&OPN->ST,0x03);
2428 FM_BUSY_CLEAR(&OPN->ST);
2429 OPNWriteMode(OPN,0x27,0x30); /* mode 0 , timer reset */
2430
2431 OPN->eg_timer = 0;
2432 OPN->eg_cnt = 0;
2433
2434 OPN->lfo_timer = 0;
2435 OPN->lfo_cnt = 0;
2436 OPN->LFO_AM = 126;
2437 OPN->LFO_PM = 0;
2438
2439 OPN->ST.status = 0;
2440 OPN->ST.mode = 0;
2441
2442 OPNWriteMode(OPN,0x27,0x30);
2443 OPNWriteMode(OPN,0x26,0x00);
2444 OPNWriteMode(OPN,0x25,0x00);
2445 OPNWriteMode(OPN,0x24,0x00);
2446
2447 reset_channels( &OPN->ST , &F2612->CH[0] , 6 );
2448
2449 for(i = 0xb6 ; i >= 0xb4 ; i-- )
2450 {
2451 OPNWriteReg(OPN,i ,0xc0);
2452 OPNWriteReg(OPN,i|0x100,0xc0);
2453 }
2454 for(i = 0xb2 ; i >= 0x30 ; i-- )
2455 {
2456 OPNWriteReg(OPN,i ,0);
2457 OPNWriteReg(OPN,i|0x100,0);
2458 }
2459
2460 /* DAC mode clear */
2461 F2612->dacen = 0;
2462 F2612->dacout = 0;
2463 }
2464
2465 /* YM2612 write */
2466 /* n = number */
2467 /* a = address */
2468 /* v = value */
ym2612_write(void * chip,int a,uint8_t v)2469 int ym2612_write(void *chip, int a, uint8_t v)
2470 {
2471 ym2612_state *F2612 = (ym2612_state *)chip;
2472 int addr;
2473
2474 v &= 0xff; /* adjust to 8 bit bus */
2475
2476 switch( a&3)
2477 {
2478 case 0: /* address port 0 */
2479 F2612->OPN.ST.address = v;
2480 F2612->addr_A1 = 0;
2481 break;
2482
2483 case 1: /* data port 0 */
2484 if (F2612->addr_A1 != 0)
2485 break; /* verified on real YM2608 */
2486
2487 addr = F2612->OPN.ST.address;
2488 F2612->REGS[addr] = v;
2489 switch( addr & 0xf0 )
2490 {
2491 case 0x20: /* 0x20-0x2f Mode */
2492 switch( addr )
2493 {
2494 case 0x2a: /* DAC data (YM2612) */
2495 ym2612_device::update_request(F2612->OPN.ST.device);
2496 F2612->dacout = (F2612->dacout & 0x001) | (((int)v - 0x80) << 1);
2497 break;
2498 case 0x2b: /* DAC Sel (YM2612) */
2499 /* b7 = dac enable */
2500 F2612->dacen = v & 0x80;
2501 break;
2502 case 0x2c: /* Test (YM2612) */
2503 /* b3 = dac lowest bit */
2504 F2612->dacout = (F2612->dacout & ~0x001) | BIT(v, 3);
2505 break;
2506 default: /* OPN section */
2507 ym2612_device::update_request(F2612->OPN.ST.device);
2508 /* write register */
2509 OPNWriteMode(&(F2612->OPN),addr,v);
2510 }
2511 break;
2512 default: /* 0x30-0xff OPN section */
2513 ym2612_device::update_request(F2612->OPN.ST.device);
2514 /* write register */
2515 OPNWriteReg(&(F2612->OPN),addr,v);
2516 }
2517 break;
2518
2519 case 2: /* address port 1 */
2520 F2612->OPN.ST.address = v;
2521 F2612->addr_A1 = 1;
2522 break;
2523
2524 case 3: /* data port 1 */
2525 if (F2612->addr_A1 != 1)
2526 break; /* verified on real YM2608 */
2527
2528 addr = F2612->OPN.ST.address;
2529 F2612->REGS[addr | 0x100] = v;
2530 ym2612_device::update_request(F2612->OPN.ST.device);
2531 OPNWriteReg(&(F2612->OPN),addr | 0x100,v);
2532 break;
2533 }
2534 return F2612->OPN.ST.irq;
2535 }
2536
ym2612_read(void * chip,int a)2537 uint8_t ym2612_read(void *chip,int a)
2538 {
2539 ym2612_state *F2612 = (ym2612_state *)chip;
2540
2541 switch( a&3)
2542 {
2543 case 0: /* status 0 */
2544 return FM_STATUS_FLAG(&F2612->OPN.ST);
2545 case 1:
2546 case 2:
2547 case 3:
2548 LOG(F2612->device,LOG_WAR,("YM2612 #%p:A=%d read unmapped area\n",F2612->OPN.ST.device,a));
2549 return FM_STATUS_FLAG(&F2612->OPN.ST);
2550 }
2551 return 0;
2552 }
2553
ym2612_timer_over(void * chip,int c)2554 int ym2612_timer_over(void *chip,int c)
2555 {
2556 ym2612_state *F2612 = (ym2612_state *)chip;
2557
2558 if( c )
2559 { /* Timer B */
2560 TimerBOver( &(F2612->OPN.ST) );
2561 }
2562 else
2563 { /* Timer A */
2564 ym2612_device::update_request(F2612->OPN.ST.device);
2565 /* timer update */
2566 TimerAOver( &(F2612->OPN.ST) );
2567 /* CSM mode key,TL controll */
2568 if ((F2612->OPN.ST.mode & 0xc0) == 0x80)
2569 { /* CSM mode total level latch and auto key on */
2570 CSMKeyControll( &F2612->OPN, &(F2612->CH[2]) );
2571 }
2572 }
2573 return F2612->OPN.ST.irq;
2574 }
2575
2576 #endif /* (BUILD_YM2612||BUILD_YM3238) */
2577