1 // license:BSD-3-Clause 2 // copyright-holders:Andrew Gardner, Couriersud 3 #include "netlist/devices/net_lib.h" 4 5 #ifdef NLBASE_H_ 6 #error Somehow nl_base.h made it into the include chain. 7 #endif 8 9 #define USE_FRONTIERS 1 10 11 /* if we use frontiers, use fixed STV for smaller matrix sizes */ 12 #if (USE_FRONTIERS) 13 #define USE_FIXED_STV 1 14 #else 15 #define USE_FIXED_STV 0 16 #endif 17 18 /* 19 * Schematic errors: 20 * 21 * The kungfu master schematics differ from the kidnik schematics in wiring 22 * D4, D5 and Q4 with other components. The manual corrections to the 23 * kungfu master schematics make sense and thus are used here. 24 * 25 * opamp XU1.B according to schematics has no feedback loop between output and 26 * inputs. The arrangement of components in the schematic however indicate that 27 * this is not the case and indeed a connection exists. This results in sounds 28 * at output XU1.14 to contain more detail. 29 * 30 * You can observe sounds at XU1.14 by doing 31 * 32 * NL_LOGS=XU1.14 ./mame64 kidniki 33 * nlwav -o x.wav log_XU1.14.log 34 * play x.wav 35 * 36 * VERIFICATION NEEDED: Are D4 and D5 Cathodes connected? 37 * 38 * This has quite some impact on the drums. 39 * 40 */ 41 42 #define FIX_SCHEMATIC_ERRORS (1) 43 #define D4_AND_D5_CONNECTED (1) 44 45 /* On M62 boards with pcb pictures available 46 * D6 is missing, although the pcb print exists. 47 * We are replacing this with a 10m Resistor. 48 */ 49 50 #define D6_EXISTS (0) 51 52 /* 53 * J4 connects channel C either to sound_ic or sound. 54 * 55 * 1: Connect C to channel to sound_ic 56 * 57 */ 58 59 #define J4 (1) 60 61 /* ---------------------------------------------------------------------------- 62 * Library section header START 63 * ---------------------------------------------------------------------------*/ 64 65 #ifndef __PLIB_PREPROCESSOR__ 66 67 #endif 68 69 /* ---------------------------------------------------------------------------- 70 * Library section header END 71 * ---------------------------------------------------------------------------*/ 72 73 /* ---------------------------------------------------------------------------- 74 * Kidniki schematics 75 * ---------------------------------------------------------------------------*/ 76 77 static NETLIST_START(kidniki_schematics) 78 // EESCHEMA NETLIST VERSION 1.1 (SPICE FORMAT) CREATION DATE: SAT 06 JUN 2015 01:06:26 PM CEST 79 // TO EXCLUDE A COMPONENT FROM THE SPICE NETLIST ADD [SPICE_NETLIST_ENABLED] USER FIELD SET TO: N 80 // TO REORDER THE COMPONENT SPICE NODE SEQUENCE ADD [SPICE_NODE_SEQUENCE] USER FIELD AND DEFINE SEQUENCE: 2,1,0 81 // SHEET NAME:/ 82 // IGNORED O_AUDIO0: O_AUDIO0 49 0 83 // .END 84 85 #if FIX_SCHEMATIC_ERRORS 86 NET_C(XU1.7, C40.1) 87 #endif 88 CAP(C200, CAP_N(100)) 89 CAP(C28, CAP_U(1)) 90 CAP(C31, CAP_N(470)) 91 CAP(C32, CAP_N(3.3)) 92 CAP(C33, CAP_U(1)) 93 CAP(C34, CAP_N(1)) 94 CAP(C35, CAP_N(1)) 95 CAP(C36, CAP_N(6.8)) 96 CAP(C37, CAP_N(22)) 97 CAP(C38, CAP_N(1)) 98 CAP(C39, CAP_N(1)) 99 CAP(C40, CAP_P(12)) 100 CAP(C41, CAP_U(1)) 101 CAP(C42, CAP_N(1.2)) 102 CAP(C43, CAP_N(1.2)) 103 CAP(C44, CAP_U(1)) 104 CAP(C45, CAP_N(22)) 105 CAP(C47, CAP_U(1)) 106 CAP(C48, CAP_N(470)) 107 CAP(C49, CAP_N(3.3)) 108 CAP(C50, CAP_N(22)) 109 CAP(C51, CAP_N(22)) 110 CAP(C52, CAP_N(27)) 111 CAP(C53, CAP_N(27)) 112 CAP(C56, CAP_N(6.8)) 113 CAP(C57, CAP_N(6.8)) 114 CAP(C59, CAP_N(6.8)) 115 CAP(C60, CAP_N(22)) 116 CAP(C61, CAP_N(22)) 117 CAP(C62, CAP_N(6.8)) 118 CAP(C63, CAP_N(1)) 119 CAP(C64, CAP_N(68)) 120 CAP(C65, CAP_N(68)) 121 CAP(C66, CAP_N(68)) 122 CAP(C67, CAP_N(15)) 123 CAP(C68, CAP_N(15)) 124 CAP(C69, CAP_N(10)) 125 CAP(C70, CAP_N(22)) 126 CAP(C72, CAP_N(12)) 127 CAP(C73, CAP_N(10)) 128 CAP(C76, CAP_N(68)) 129 CAP(C77, CAP_N(12)) 130 131 DIODE(D3, "1S1588") 132 DIODE(D4, "1S1588") 133 DIODE(D5, "1S1588") 134 135 POT(RV1, RES_K(50)) 136 137 QBJT_EB(Q10, "2SC945") 138 QBJT_EB(Q3, "2SC945") 139 QBJT_EB(Q4, "2SC945") 140 QBJT_EB(Q5, "2SC945") 141 QBJT_EB(Q6, "2SC945") 142 QBJT_EB(Q7, "2SC945") 143 QBJT_EB(Q9, "2SC945") 144 145 LM2902_DIP(XU1) 146 LM358_DIP(XU2) 147 148 MC14584B_DIP(XU3) 149 150 RES(R100, RES_K(560)) 151 RES(R101, RES_K(150)) 152 RES(R102, RES_K(150)) 153 RES(R103, RES_K(470)) 154 RES(R104, RES_K(22)) 155 RES(R105, RES_K(470)) 156 RES(R106, RES_K(150)) 157 RES(R107, RES_K(150)) 158 RES(R108, RES_K(560)) 159 RES(R119, RES_K(22)) 160 RES(R200, RES_K(100)) 161 RES(R201, RES_K(100)) 162 RES(R27, RES_K(6.8)) 163 RES(R28, RES_K(150)) 164 RES(R29, RES_K(2.7)) 165 RES(R30, RES_K(10)) 166 RES(R31, RES_K(5.1)) 167 RES(R32, RES_K(4.7)) 168 RES(R34, RES_K(100)) 169 RES(R35, RES_K(100)) 170 RES(R36, RES_K(100)) 171 RES(R37, RES_K(47)) 172 RES(R38, 820) 173 RES(R39, RES_K(22)) 174 RES(R40, RES_K(10)) 175 RES(R41, RES_K(10)) 176 RES(R42, RES_K(150)) 177 RES(R43, 470) 178 RES(R44, RES_K(100)) 179 RES(R45, RES_K(1)) 180 RES(R46, RES_K(12)) 181 RES(R48, 470) 182 RES(R48_2, RES_K(100)) 183 RES(R49, RES_K(10)) 184 RES(R50, RES_K(2.2)) 185 RES(R51, RES_K(150)) 186 RES(R52, RES_K(100)) 187 RES(R53, RES_K(100)) 188 RES(R54, 680) 189 RES(R55, RES_K(510)) 190 RES(R57, 560) 191 RES(R58, RES_K(39)) 192 RES(R59, 560) 193 RES(R60, RES_K(39)) 194 RES(R61, RES_K(100)) 195 RES(R62, RES_K(100)) 196 RES(R63, RES_K(1)) 197 RES(R65, RES_K(1)) 198 RES(R65_1, RES_K(27)) 199 RES(R66, RES_M(1)) 200 RES(R67, RES_K(100)) 201 RES(R68, RES_K(100)) 202 RES(R69, RES_K(1)) 203 RES(R70, RES_K(10)) 204 RES(R71, RES_K(100)) 205 RES(R72, RES_K(100)) 206 RES(R73, RES_K(10)) 207 RES(R74, RES_K(10)) 208 RES(R75, RES_K(10)) 209 RES(R76, RES_K(47)) 210 RES(R81, 220) 211 RES(R82, RES_M(2.2)) 212 RES(R83, RES_K(12)) 213 RES(R84, RES_K(1)) 214 RES(R85, RES_M(2.2)) 215 RES(R86, RES_K(10)) 216 RES(R87, RES_K(68)) 217 RES(R89, RES_K(22)) 218 RES(R90, RES_K(390)) 219 RES(R91, RES_K(100)) 220 RES(R92, RES_K(22)) 221 RES(R93, RES_K(1)) 222 RES(R94, RES_K(22)) 223 RES(R95, RES_K(330)) 224 RES(R96, RES_K(150)) 225 RES(R97, RES_K(150)) 226 RES(R98, RES_K(680)) 227 228 #if USE_FIXED_STV 229 ANALOG_INPUT(STV, 2) 230 #else 231 RES(R78, RES_K(3.3)) 232 RES(R77, RES_K(2.2)) 233 CAP(C58, CAP_U(47)) 234 NET_C(R77.2, C58.1, I_V0.Q) 235 NET_C(R78.1, I_V5.Q) 236 #endif 237 238 NET_C(R95.1, XU3.2, R96.2) 239 NET_C(R95.2, XU3.1, C69.1) 240 NET_C(XU3.3, R103.2, C73.1) 241 NET_C(XU3.4, R103.1, R102.2) 242 NET_C(XU3.5, R105.2, C72.1) 243 NET_C(XU3.6, R105.1, R106.2) 244 NET_C(XU3.7, C69.2, C73.2, C72.2, C77.2, C67.2, C68.2, R65.2, R38.2, XU1.11, R54.2, Q4.E, R63.2, C47.2, R72.2, R67.2, R71.2, R68.2, C48.2, R46.2, C28.1, C32.1, R43.2, XU2.4, C56.1, C52.1, R48.2, R93.2, R94.2, R119.2, R104.2, R53.2, R34.2, R81.2, R92.2, R89.2, C33.1, R37.2, R36.1, R91.1, I_V0.Q, RV1.3) 245 NET_C(XU3.8, R108.1, R107.2) 246 NET_C(XU3.9, R108.2, C77.1) 247 NET_C(XU3.10, R100.1, R101.2) 248 NET_C(XU3.11, R100.2, C67.1) 249 NET_C(XU3.12, R98.1, R97.2) 250 NET_C(XU3.13, R98.2, C68.1) 251 NET_C(XU3.14, XU1.4, R66.1, R70.1, Q6.C, Q5.C, XU2.8, R86.1, R83.1, Q3.C, I_V5.Q) 252 NET_C(R96.1, R102.1, R106.1, R107.1, R101.1, R97.1, R65.1, C63.2) 253 NET_C(C63.1, R65_1.2) 254 NET_C(R65_1.1, R44.2, C38.2, C40.2, XU1.6) 255 #if USE_FIXED_STV 256 NET_C(R30.1, R41.1, R40.1, R76.2, /* R78.2, R77.1, C58.2*/ STV) 257 #else 258 NET_C(R30.1, R41.1, R40.1, R76.2, R78.2, R77.1, C58.2) 259 #endif 260 NET_C(R30.2, XU1.5) 261 NET_C(R44.1, C39.1, C40.1, R48_2.2) 262 NET_C(C38.1, C39.2, R38.1) 263 NET_C(XU1.1, XU1.2, R39.1, R32.2) 264 NET_C(XU1.3, C34.1, R41.2) 265 NET_C(XU1.7, R45.2) 266 NET_C(XU1.8, XU1.9, R31.2, C36.2) 267 NET_C(XU1.10, R42.1, C32.2) 268 NET_C(XU1.12, C49.1, C31.1, R40.2, C61.1, C60.1) 269 NET_C(XU1.13, R27.1, R28.2) 270 NET_C(XU1.14, R28.1, R29.2, I_SINH0) 271 NET_C(R48_2.1, C45.2, R54.1) 272 NET_C(C45.1, R55.1, Q7.B) 273 NET_C(R55.2, R90.2, C33.2, R37.1, Q3.E) 274 NET_C(R45.1, C44.2) 275 NET_C(C44.1, R66.2, Q4.B) 276 #if FIX_SCHEMATIC_ERRORS 277 #if D4_AND_D5_CONNECTED 278 /* needs verification */ 279 NET_C(Q4.C, D4.K, D5.K) 280 NET_C(C42.1, C43.1, R46.1, C35.2) 281 #else 282 NET_C(Q4.C, D5.K) 283 NET_C(C42.1, C43.1, R46.1, C35.2, D4.K) 284 #endif 285 #else 286 NET_C(Q4.C, C42.1, C43.1, R46.1, C35.2, D4.K, D5.K) 287 #endif 288 NET_C(R70.2, R69.2, Q7.C) 289 NET_C(R63.1, Q7.E) 290 NET_C(R69.1, C49.2) 291 NET_C(C42.2, R58.1, D5.A) 292 NET_C(R58.2, R57.1, C47.1) 293 NET_C(R57.2, Q6.E) 294 NET_C(Q6.B, R61.1) 295 NET_C(C50.1, R67.1, R61.2) 296 NET_C(C50.2, R72.1, I_OH0.Q) 297 NET_C(C51.1, R68.1, R62.2) 298 NET_C(C51.2, R71.1, I_CH0.Q) 299 NET_C(R62.1, Q5.B) 300 NET_C(Q5.E, R59.2) 301 NET_C(R60.1, C43.2, D4.A) 302 NET_C(R60.2, R59.1, C48.1) 303 NET_C(C35.1, C34.2, R39.2) 304 NET_C(R32.1, C31.2) 305 NET_C(R27.2, C28.2) 306 NET_C(R29.1, R31.1, R50.2, R49.1, RV1.1) 307 NET_C(R42.2, R51.1, C36.1) 308 NET_C(R51.2, C41.1) 309 NET_C(C41.2, R43.1, I_SOUNDIC0) 310 NET_C(XU2.1, XU2.2, R73.1) 311 NET_C(XU2.3, R76.1, C200.2) 312 NET_C(XU2.5, C56.2, R75.1) 313 NET_C(XU2.6, XU2.7, R50.1, C53.2) 314 NET_C(R75.2, R74.1, C53.1) 315 NET_C(R74.2, C52.2, R73.2) 316 NET_C(R49.2, R48.1, I_SOUND0) 317 NET_C(Q9.E, R81.1) 318 NET_C(Q9.C, R84.2, R83.2, R82.1, C59.1) 319 NET_C(Q9.B, R82.2, C62.1) 320 NET_C(Q10.E, R93.1) 321 NET_C(Q10.C, R87.2, R86.2, R85.1, C76.1) 322 NET_C(Q10.B, R85.2, C64.1) 323 NET_C(R84.1, C61.2) 324 NET_C(C60.2, R87.1) 325 NET_C(C64.2, C65.1, R94.1, D3.K) 326 NET_C(C65.2, C66.1, R119.1) 327 NET_C(C66.2, C76.2, R104.1) 328 NET_C(R53.1, R52.2, C37.1) 329 NET_C(R34.1, C37.2, I_BD0.Q) 330 NET_C(R52.1, D3.A) 331 NET_C(R92.1, C62.2, C57.1) 332 NET_C(R89.1, C57.2, C59.2, R90.1) 333 NET_C(Q3.B, R35.1) 334 NET_C(R35.2, R36.2, C70.1) 335 NET_C(R91.2, C70.2, I_SD0.Q) 336 NET_C(I_MSM3K0.Q, R200.2) 337 NET_C(I_MSM2K0.Q, R201.2) 338 NET_C(R200.1, R201.1, C200.1) 339 340 /* Amplifier stage */ 341 342 CAP(C26, CAP_U(1)) 343 RES(R25, 560) 344 RES(R26, RES_K(47)) 345 CAP(C29, CAP_U(0.01)) 346 347 NET_C(RV1.2, C26.1) 348 NET_C(C26.2, R25.1) 349 NET_C(R25.2, R26.1, C29.1) 350 NET_C(R26.2, C29.2, GND) 351 352 NETLIST_END() 353 354 /* ---------------------------------------------------------------------------- 355 * Kidniki audio 356 * ---------------------------------------------------------------------------*/ 357 358 NETLIST_START(kidniki) 359 360 #if (1 || USE_FRONTIERS) 361 SOLVER(Solver, 48000) 362 PARAM(Solver.ACCURACY, 1e-7) 363 PARAM(Solver.NR_LOOPS, 300) 364 PARAM(Solver.GS_LOOPS, 10) 365 //PARAM(Solver.METHOD, "SOR") 366 PARAM(Solver.METHOD, "MAT_CR") 367 PARAM(Solver.FPTYPE, "DOUBLE") 368 //PARAM(Solver.METHOD, "MAT") 369 //PARAM(Solver.PIVOT, 1) 370 //PARAM(Solver.Solver_0.METHOD, "GMRES") 371 PARAM(Solver.SOR_FACTOR, 1.313) 372 PARAM(Solver.DYNAMIC_TS, 0) 373 PARAM(Solver.DYNAMIC_LTE, 5e-4) 374 PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 20e-6) 375 PARAM(Solver.SORT_TYPE, "PREFER_IDENTITY_TOP_LEFT") 376 //PARAM(Solver.SORT_TYPE, "PREFER_BAND_MATRIX") 377 #else 378 //PARAM(Solver.SORT_TYPE, "PREFER_BAND_MATRIX") 379 SOLVER(Solver, 48000) 380 PARAM(Solver.ACCURACY, 1e-7) 381 PARAM(Solver.NR_LOOPS, 10000) 382 PARAM(Solver.GS_LOOPS, 100) 383 //PARAM(Solver.METHOD, "MAT_CR") 384 PARAM(Solver.METHOD, "GMRES") 385 #endif 386 387 #if (USE_FRONTIERS) 388 PARAM(Solver.PARALLEL, 2) // More does not help 389 #else 390 PARAM(Solver.PARALLEL, 0) 391 #endif 392 393 LOCAL_SOURCE(kidniki_schematics) 394 395 ANALOG_INPUT(I_V5, 5) 396 //ANALOG_INPUT(I_V0, 0) 397 ALIAS(I_V0.Q, GND) 398 399 /* AY 8910 internal resistors */ 400 401 RES(R_AY45L_A, 1000) 402 RES(R_AY45L_B, 1000) 403 RES(R_AY45L_C, 1000) 404 405 RES(R_AY45M_A, 1000) 406 RES(R_AY45M_B, 1000) 407 RES(R_AY45M_C, 1000) 408 409 NET_C(I_V5, R_AY45L_A.1, R_AY45L_B.1, R_AY45L_C.1, R_AY45M_A.1, R_AY45M_B.1, R_AY45M_C.1) 410 NET_C(R_AY45L_A.2, R_AY45L_B.2, R_AY45M_A.2, R_AY45M_B.2, R_AY45M_C.2) 411 412 #if (J4) 413 ALIAS(I_SOUNDIC0, R_AY45L_C.2) 414 #else 415 NET_C(R_AY45L_A.2, R_AY45L_C.2) 416 ALIAS(I_SOUNDIC0, I_V0.Q) 417 #endif 418 419 ALIAS(I_SOUND0, R_AY45L_A.2) 420 421 TTL_INPUT(SINH, 1) 422 423 #if (D6_EXISTS) 424 DIODE(D6, "1N914") 425 NET_C(D6.K, SINH) 426 ALIAS(I_SINH0, D6.A) 427 #else 428 RES(SINH_DUMMY, RES_M(10)) 429 NET_C(SINH_DUMMY.1, SINH) 430 ALIAS(I_SINH0, SINH_DUMMY.2) 431 #endif 432 433 NET_MODEL("AY8910PORT FAMILY(TYPE=NMOS OVL=0.05 OVH=0.05 ORL=100.0 ORH=0.5k)") 434 435 LOGIC_INPUT(I_SD0, 1, "AY8910PORT") 436 LOGIC_INPUT(I_BD0, 1, "AY8910PORT") 437 LOGIC_INPUT(I_CH0, 1, "AY8910PORT") 438 LOGIC_INPUT(I_OH0, 1, "AY8910PORT") 439 440 NET_C(I_V5, I_SD0.VCC, I_BD0.VCC, I_CH0.VCC, I_OH0.VCC, SINH.VCC) 441 NET_C(GND, I_SD0.GND, I_BD0.GND, I_CH0.GND, I_OH0.GND, SINH.GND) 442 443 ANALOG_INPUT(I_MSM2K0, 0) 444 ANALOG_INPUT(I_MSM3K0, 0) 445 446 INCLUDE(kidniki_schematics) 447 448 #if (USE_FRONTIERS) 449 OPTIMIZE_FRONTIER(C63.2, RES_K(27), RES_K(1)) 450 OPTIMIZE_FRONTIER(R31.2, RES_K(5.1), 50) 451 OPTIMIZE_FRONTIER(R29.2, RES_K(2.7), 50) 452 OPTIMIZE_FRONTIER(R87.2, RES_K(68), 50) 453 454 OPTIMIZE_FRONTIER(R50.1, RES_K(2.2), 50) 455 OPTIMIZE_FRONTIER(R55.2, RES_K(1000), 50) 456 OPTIMIZE_FRONTIER(R84.2, RES_K(50), RES_K(5)) 457 #endif 458 459 NETLIST_END() 460