1 // license:CC0 2 // copyright-holders:Aaron Giles 3 4 // 5 // Netlist for Speed Freak 6 // 7 // Derived from the utterly terrible schematics in the Speed Freak 8 // manual. Newly-drawn schematics are available upon request. 9 // 10 // Special thanks to: 11 // * Frank Palazzolo for helping to verify connections and parts 12 // * Brian Tarachi for supplying his corrected schematics 13 // 14 // Known problems/issues: 15 // 16 // * Works pretty well. Needs more detailed comparison with clean 17 // audio recordings from PCBs, but it's pretty close. 18 // 19 20 #include "netlist/devices/net_lib.h" 21 #include "nl_cinemat_common.h" 22 23 24 // 25 // Optimizations 26 // 27 28 #define HLE_CLOCK_GENERATOR (1) 29 #define HLE_CLOCK_INPUT (1) 30 31 32 // 33 // Main netlist 34 // 35 36 NETLIST_START(speedfrk) 37 38 SOLVER(Solver, 1000) 39 PARAM(Solver.DYNAMIC_TS, 1) 40 PARAM(Solver.DYNAMIC_MIN_TIMESTEP, 2e-5) 41 42 TTL_INPUT(I_OUT_0, 1) // active low 43 TTL_INPUT(I_OUT_1, 1) // active low 44 TTL_INPUT(I_OUT_2, 1) // active low 45 TTL_INPUT(I_OUT_3, 1) // active low 46 TTL_INPUT(I_OUT_4, 1) // active low 47 TTL_INPUT(I_OUT_7, 1) // active low 48 49 NET_C(GND, I_OUT_0.GND, I_OUT_1.GND, I_OUT_2.GND, I_OUT_3.GND, I_OUT_4.GND, I_OUT_7.GND) 50 NET_C(I_V5, I_OUT_0.VCC, I_OUT_1.VCC, I_OUT_2.VCC, I_OUT_3.VCC, I_OUT_4.VCC, I_OUT_7.VCC) 51 52 CINEMAT_LOCAL_MODELS 53 54 ANALOG_INPUT(I_V5, 5) 55 56 // RES(R1, 2.7) 57 // RES(R2, 2.7) 58 // RES(R3, 2.7) 59 // RES(R4, 2.7) 60 // RES(R5, 150) // PCB verified 61 // RES(R6, 150) 62 // RES(R7, RES_K(10)) // PCB verified 63 // RES(R8, RES_K(68)) // PCB verified 64 // RES(R9, RES_K(2.2)) // PCB verified 65 // RES(R10, 820) // PCB verified 66 // RES(R11, RES_K(47)) // PCB verified 67 // RES(R12, RES_K(1)) ?? 68 RES(R13, 150) 69 RES(R14, RES_K(2.2)) // PCB verified 70 RES(R15, RES_K(10)) // PCB verified 71 RES(R16, RES_K(2.2)) // PCB verified 72 RES(R17, RES_K(1)) // PCB verified 73 RES(R18, RES_K(8.2)) // PCB verified 74 RES(R19, RES_K(3.9)) // PCB verified 75 RES(R20, RES_K(4.7)) // PCB verified 76 RES(R21, RES_K(3.3)) // PCB verified 77 RES(R22, RES_K(10)) // PCB verified 78 RES(R23, RES_K(4.7)) // PCB verified 79 RES(R24, RES_K(10)) 80 RES(R25, RES_K(18)) // PCB verified 81 RES(R26, RES_K(18)) // PCB verified 82 RES(R27, RES_K(6.8)) // PCB verified 83 RES(R28, RES_K(10)) // PCB verified 84 RES(R29, RES_K(2.2)) // PCB verified 85 RES(R30, 330) // PCB verified 86 RES(R31, 330) // PCB verified 87 RES(R32, RES_K(1)) // PCB verified 88 RES(R33, RES_K(1)) // PCB verified 89 RES(R34, RES_K(1)) // PCB verified 90 // RES(R35, 0) // PCB verified: not populated 91 RES(R36, RES_K(1)) // PCB verified 92 RES(R37, RES_K(1)) // PCB verified 93 RES(R38, RES_K(1)) // PCB verified 94 RES(R39, RES_K(1)) // PCB verified 95 RES(R40, RES_K(1)) // PCB verified 96 RES(R41, RES_K(1)) // PCB verified 97 RES(R42, RES_K(1)) // PCB verified 98 RES(R43, RES_K(1)) // PCB verified 99 RES(R44, RES_K(30)) // PCB verified 100 RES(R45, RES_K(4.7)) // PCB verified 101 RES(R46, RES_K(10)) // PCB verified 102 103 // CAP(C4, CAP_U(4.7)) 104 // CAP(C5, CAP_U(4.7)) 105 CAP(C12, CAP_U(0.001)) 106 CAP(C13, CAP_U(0.001)) 107 CAP(C17, CAP_U(0.02)) 108 CAP(C20, CAP_U(0.1)) 109 CAP(C23, CAP_U(0.1)) 110 111 // CAP(C1, CAP_U(50)) 112 // CAP(C2, CAP_U(50)) 113 // CAP(C3, CAP_U(4.7)) 114 // CAP(C6, CAP_U(0.002)) 115 // CAP(C7, CAP_U(0.002)) 116 // CAP(C8, CAP_U(0.01)) 117 // CAP(C9, CAP_U(0.1)) 118 // CAP(C10, CAP_U(0.1)) 119 // CAP(C11, CAP_U(0.02)) 120 121 // D_1N914B(CR1) // OK 122 // D_1N914B(CR2) // OK 123 D_1N914B(CR3) // OK 124 125 // Q_2N6292(Q1) // NPN 126 // Q_2N6107(Q2) // PNP 127 Q_2N3904(Q3) // NPN 128 // Q_2N3904(Q3) // NPN -- unknown type 129 130 TTL_74LS04_DIP(U2) // Hex Inverting Gates 131 NET_C(U2.7, GND) 132 NET_C(U2.14, I_V5) 133 134 TL081_DIP(U3) // Op. Amp. 135 NET_C(U3.4, GND) 136 NET_C(U3.7, I_V5) 137 138 TTL_74LS163_DIP(U4) // Synchronous 4-Bit Counters 139 NET_C(U4.8, GND) 140 NET_C(U4.16, I_V5) 141 142 TTL_74LS107_DIP(U5) // DUAL J-K FLIP-FLOPS WITH CLEAR 143 NET_C(U5.7, GND) 144 NET_C(U5.14, I_V5) 145 146 TTL_74LS08_DIP(U6) // Quad 2-Input AND Gates 147 NET_C(U6.7, GND) 148 NET_C(U6.14, I_V5) 149 150 TTL_74LS163_DIP(U7) // Synchronous 4-Bit Counters 151 NET_C(U7.8, GND) 152 NET_C(U7.16, I_V5) 153 154 TTL_74LS163_DIP(U8) // Synchronous 4-Bit Counters 155 NET_C(U8.8, GND) 156 NET_C(U8.16, I_V5) 157 158 TTL_74LS163_DIP(U9) // Synchronous 4-Bit Counters 159 NET_C(U9.8, GND) 160 NET_C(U9.16, I_V5) 161 162 // TTL_7915_DIP(U8) // -15V Regulator -- not needed 163 // TTL_7815_DIP(U9) // +15V Regulator -- not needed 164 165 TTL_74LS04_DIP(U10) // Hex Inverting Gates 166 NET_C(U10.7, GND) 167 NET_C(U10.14, I_V5) 168 169 TTL_74LS08_DIP(U11) // Quad 2-Input AND Gates 170 NET_C(U11.7, GND) 171 NET_C(U11.14, I_V5) 172 173 TTL_74LS75_DIP(U12) // 4-Bit Bistable Latches with Complementary Outputs 174 NET_C(U12.12, GND) 175 NET_C(U12.5, I_V5) 176 177 TTL_74LS164_DIP(U13) // 8-bit parallel-out serial shift registers 178 NET_C(U13.7, GND) 179 NET_C(U13.14, I_V5) 180 181 TTL_74LS164_DIP(U14) // 8-bit parallel-out serial shift registers 182 NET_C(U14.7, GND) 183 NET_C(U14.14, I_V5) 184 185 TTL_74LS163_DIP(U15) // Synchronous 4-Bit Counters 186 NET_C(U15.8, GND) 187 NET_C(U15.16, I_V5) 188 189 TTL_74LS107_DIP(U17) // DUAL J-K FLIP-FLOPS WITH CLEAR 190 NET_C(U17.7, GND) 191 NET_C(U17.14, I_V5) 192 193 TTL_74LS393_DIP(U18) // Dual 4-Stage Binary Counter 194 NET_C(U18.7, GND) 195 NET_C(U18.14, I_V5) 196 197 TTL_74LS86_DIP(U19) // Quad 2-Input XOR Gates 198 NET_C(U19.7, GND) 199 NET_C(U19.14, I_V5) 200 201 TTL_74LS164_DIP(U20) // 8-bit parallel-out serial shift registers 202 NET_C(U20.7, GND) 203 NET_C(U20.14, I_V5) 204 205 LM555_DIP(U22) // 5-5-5 Timer 206 207 TTL_74LS163_DIP(U23) // Dual 4-Stage Binary Counter 208 NET_C(U23.8, GND) 209 NET_C(U23.16, I_V5) 210 211 TTL_74LS164_DIP(U24) // 8-bit parallel-out serial shift registers 212 NET_C(U24.7, GND) 213 NET_C(U24.14, I_V5) 214 215 // 216 // 76kHz coming from the logic PCB 217 // 218 CLOCK(J4_2, 76000) 219 NET_C(J4_2.GND, GND) 220 NET_C(J4_2.VCC, I_V5) 221 222 #if (HLE_CLOCK_GENERATOR) 223 // 224 // Skip the clock generator and just do it directly 225 // 226 CLOCK(C2MHZ, 2000000) 227 NET_C(C2MHZ.GND, GND) 228 NET_C(C2MHZ.VCC, I_V5) 229 NET_C(GND, R30.1, R30.2, R31.1, R31.2, C12.1, C12.2, C13.1, C13.2, U10.1, U10.3, U10.5) 230 #else 231 NET_C(R30.1, U10.1, C13.1) 232 NET_C(R30.2, U10.2, C12.1) 233 NET_C(C12.2, U10.3, R31.1) 234 NET_C(R31.2, U10.4, C13.2, U10.5) 235 ALIAS(C2MHZ, U10.6) 236 #endif 237 238 #if (HLE_CLOCK_INPUT) 239 // 240 // The clock input from the main PCB is run through a voltage 241 // converter which eats a lot of time and is unnecessary since 242 // we're just generating a TTL signal already. 243 // 244 NET_C(J4_2.Q, U5.12) 245 NET_C(GND, R27.1, R27.2, R28.1, R28.2, R29.1, R29.2, CR3.A, CR3.K, U3.2, U3.3) 246 #else 247 NET_C(J4_2.Q, U3.3) 248 NET_C(R27.1, GND) 249 NET_C(R27.2, U3.2, R28.1) 250 NET_C(R28.2, I_V5) 251 NET_C(U3.6, R29.1) 252 NET_C(R29.2, CR3.K, U5.12) 253 #endif 254 255 NET_C(CR3.A, GND) 256 NET_C(U5.1, R41.1) 257 NET_C(R41.2, I_V5) 258 NET_C(U5.4, GND) 259 NET_C(U5.13, U5.10, U10.9, U4.15) 260 NET_C(U5.3, U5.8) 261 NET_C(U5.2, U5.11) 262 NET_C(U5.6, U4.9) 263 NET_C(U5.9, U4.2, C2MHZ.Q) 264 265 NET_C(U10.8, U4.7) 266 NET_C(U4.3, U4.1, I_V5) 267 NET_C(U4.6, R36.1) 268 NET_C(U4.4, U4.5, GND) 269 NET_C(U4.14, U18.1, U6.13, U7.2) 270 NET_C(U4.10, I_V5) // need to verify 271 272 NET_C(U18.6, U18.13) 273 NET_C(U18.2, U18.12, GND) 274 NET_C(U18.8, U17.12) 275 NET_C(U18.10, U20.8, U24.8) 276 NET_C(U18.11, U23.2) 277 278 NET_C(I_OUT_0, U2.13) 279 NET_C(U2.12, U2.1) 280 ALIAS(STEERING, U2.12) 281 NET_C(U2.2, U6.4) 282 NET_C(U6.6, U19.13, U19.5) 283 NET_C(U19.12, R39.1) 284 NET_C(R39.2, I_V5) 285 286 NET_C(I_OUT_1, U6.9) 287 NET_C(U6.10, R32.2) 288 NET_C(R32.1, I_V5) 289 NET_C(U6.8, U2.5, U6.12, U12.4, U12.13) 290 NET_C(U2.6, R14.2, U6.5) 291 NET_C(R14.1, Q3.B) 292 NET_C(Q3.E, GND) 293 NET_C(Q3.C, R13.1) 294 NET_C(R13.2, GND) 295 ALIAS(LAMP, R13.2) 296 297 NET_C(U19.11, U20.1) 298 NET_C(U20.9, R42.1) 299 // NET_C(R42.2, I_V5) 300 NET_C(U20.2, U19.3) 301 NET_C(U20.12, U19.1) 302 NET_C(U20.13, U19.4) 303 304 NET_C(U19.6, U24.1, U24.2) 305 NET_C(U24.12, U19.2) 306 NET_C(U24.9, R43.1) 307 NET_C(R43.2, I_V5) 308 NET_C(U24.13, R44.1, U11.12, U11.9, U11.5, U11.2) 309 310 NET_C(U23.1, U23.3, U23.5, U23.7, R40.2) 311 NET_C(U23.10, R40.2) // need to verify 312 NET_C(R40.1, I_V5) 313 NET_C(U23.4, U23.6, GND) 314 NET_C(U23.9, U19.8, U17.9) 315 NET_C(U23.15, U19.10) 316 NET_C(U19.9, R39.1) 317 318 NET_C(I_OUT_7, U2.9) 319 NET_C(U2.8, U17.10, U17.13) 320 NET_C(U17.8, U17.11, U17.1, U17.4, R34.1) 321 NET_C(R34.2, I_V5) 322 NET_C(U17.5, R25.1) 323 NET_C(U17.3, R26.1) 324 325 NET_C(R44.2, U22.7, R45.1, R46.2) 326 NET_C(R45.2, U22.4, U22.8, I_V5) 327 NET_C(R46.1, U22.6, U22.2, C23.2) 328 NET_C(C23.1, GND) 329 NET_C(U22.1, GND) 330 NET_C(U22.5, C17.2) 331 NET_C(C17.1, GND) 332 333 NET_C(I_OUT_4, U6.2) 334 NET_C(U22.3, U6.1) 335 NET_C(U6.3, R15.1) 336 337 NET_C(U6.11, U15.2, U9.2, U8.2) 338 NET_C(U15.1, U15.7, R42.1) 339 NET_C(R42.2, I_V5) 340 NET_C(U9.1, U9.7, U8.1, U8.7, R37.1) 341 NET_C(R37.2, I_V5) 342 NET_C(U15.15, U10.11, U7.10) 343 NET_C(U15.6, U14.3) 344 NET_C(U15.5, U14.4) 345 NET_C(U15.4, U14.5) 346 NET_C(U15.3, U14.6) 347 NET_C(U15.10, U9.15) 348 NET_C(U15.9, U9.9, U8.9, U10.10) 349 350 NET_C(U9.6, U14.10) 351 NET_C(U9.5, U14.11) 352 NET_C(U9.4, U14.12) 353 NET_C(U9.3, U14.13, U13.1, U13.2) 354 NET_C(U9.10, U8.15) 355 356 NET_C(U8.6, U13.3) 357 NET_C(U8.5, U13.4) 358 NET_C(U8.4, U13.5) 359 NET_C(U8.3, U13.6) 360 NET_C(U8.10, R36.1) 361 NET_C(R36.2, I_V5) 362 363 NET_C(I_OUT_2, U2.11) 364 NET_C(I_OUT_3, U2.3) 365 NET_C(U2.10, U14.1, U14.2) 366 NET_C(U2.4, U14.8, U13.8) 367 NET_C(U14.9, U13.9, R38.1) 368 NET_C(R38.2, I_V5) 369 370 NET_C(U12.9, U11.13) 371 NET_C(U12.10, U11.10) 372 NET_C(U12.15, U11.4) 373 NET_C(U12.16, U11.1) 374 NET_C(U12.7, U13.10) 375 NET_C(U12.6, U13.11) 376 NET_C(U12.3, U13.12) 377 NET_C(U12.2, U13.13) 378 379 NET_C(U11.11, R17.1) 380 NET_C(U11.8, R16.1) 381 NET_C(U11.6, R19.1) 382 NET_C(U11.3, R18.1) 383 NET_C(R17.2, R16.2, R19.2, R18.2, R20.1) 384 385 NET_C(U7.1, U7.5, R33.2) 386 NET_C(R33.1, I_V5) 387 NET_C(U7.7, STEERING) 388 NET_C(U7.9, U10.12) 389 NET_C(U7.15, U10.13) 390 NET_C(U7.3, U7.4, U7.6, GND) 391 NET_C(U7.11, R22.1) 392 NET_C(U7.12, R23.1) 393 NET_C(U7.13, R24.1) 394 NET_C(R22.2, R23.2, R24.2, C20.2, R21.1) 395 NET_C(C20.1, GND) 396 397 NET_C(R15.2, R25.2, R26.2, R21.2, R20.2) 398 ALIAS(OUTPUT, R20.2) 399 400 // 401 // Unconnected outputs 402 // 403 404 HINT(U4.11, NC) // Q3 405 HINT(U4.12, NC) // Q2 406 HINT(U4.13, NC) // Q1 407 HINT(U5.5, NC) // Q2 408 HINT(U7.14, NC) // Q0 409 HINT(U8.11, NC) // Q3 410 HINT(U8.12, NC) // Q2 411 HINT(U8.13, NC) // Q1 412 HINT(U8.14, NC) // Q0 413 HINT(U9.11, NC) // Q3 414 HINT(U9.12, NC) // Q2 415 HINT(U9.13, NC) // Q1 416 HINT(U9.14, NC) // Q0 417 HINT(U10.2, NC) // QQ1 -- part of 2MHz clock gen 418 HINT(U10.4, NC) // QQ2 -- part of 2MHz clock gen 419 HINT(U10.6, NC) // QQ3 -- part of 2MHz clock gen 420 HINT(U12.1, NC) // QQ0 421 HINT(U12.8, NC) // QQ3 422 HINT(U12.11, NC) // QQ2 423 HINT(U12.14, NC) // QQ1 424 HINT(U15.11, NC) // Q3 425 HINT(U15.12, NC) // Q2 426 HINT(U15.13, NC) // Q1 427 HINT(U15.14, NC) // Q0 428 HINT(U17.2, NC) // QQ1 429 HINT(U17.6, NC) // QQ2 430 HINT(U18.3, NC) // Q0 431 HINT(U18.4, NC) // Q1 432 HINT(U18.5, NC) // Q2 433 HINT(U18.9, NC) // Q2 434 HINT(U20.3, NC) // Q0 435 HINT(U20.4, NC) // Q1 436 HINT(U20.5, NC) // Q2 437 HINT(U20.6, NC) // Q3 438 HINT(U20.10, NC) // Q4 439 HINT(U20.11, NC) // Q5 440 HINT(U23.11, NC) // Q3 441 HINT(U23.12, NC) // Q2 442 HINT(U23.13, NC) // Q1 443 HINT(U23.14, NC) // Q0 444 HINT(U24.3, NC) // Q0 445 HINT(U24.4, NC) // Q1 446 HINT(U24.5, NC) // Q2 447 HINT(U24.6, NC) // Q3 448 HINT(U24.10, NC) // Q4 449 HINT(U24.11, NC) // Q5 450 451 NETLIST_END() 452