1 // license:BSD-3-Clause
2 // copyright-holders:Hans Ostermeyer, R. Belmont
3 /*
4 * apollo.c - APOLLO DN3500/DN3000 driver
5 *
6 * Created on: May 12, 2010
7 * Author: Hans Ostermeyer
8 *
9 * Adapted February 19, 2012 for general MAME/MESS standards by R. Belmont
10 *
11 * TODO: Remove need for instruction hook.
12 * Convert to modern address map.
13 *
14 * see also:
15 * - Domain Series 3000/Series 4000 Hardware Architecture Handbook (Order No. 007861 Rev. 02)
16 * - Domain Personal Workstations and Servers Technical Reference (Apollo Order No. 008778-A01)
17 * - Servicing the Domain Personal Workstations and Servers (Apollo Order No. 007859-A01)
18 * - http://www.bitsavers.org/pdf/apollo/002398-04_Domain_Engineering_Handbook_Rev4_Jan87.pdf
19 * - http://www.bitsavers.org/pdf/apollo/008778-03_DOMAIN_Series_3000_4000_Technical_Reference_Aug87.pdf
20 * - http://www.bitsavers.org/pdf/apollo/AEGIS_Internals_and_Data_Structures_Jan86.pdf
21 * - http://www.bitsavers.org/pdf/apollo/019411-A00_Addendum_to_Domain_Personal_Workstations_and_Servers_Hardware_Architecture_Handbook_1991.pdf
22 * - data sheets from Intel and Motorola
23 */
24
25 #include "emu.h"
26
27 #define VERBOSE 0
28
29 #include "includes/apollo.h"
30
31 #include "cpu/m68000/m68000.h"
32
33 // we use set_verbose
34 #include "bus/isa/omti8621.h"
35 #include "bus/isa/3c505.h"
36
37 #include "debugger.h"
38
39 #include "apollo_dsp.lh"
40
41
42 #define TERMINAL_TAG "terminal"
43
44 // we use this to prevent excessive logging (if emulation runs amok)
45 // error.log will be 10 MB for 100000 lines
46 #define APOLLO_MAX_NO_OF_LOG_LINES 1000000
47
48 // ISA/AT Bus notes
49 // I/O space: to get the Apollo address = take the PC I/O address, keep the low 3 bits how they are, and shift the rest left 7, inserting zeros.
50 // then add 0x40000 for the I/O base.
51 //
52 // example: 3c503 Ethernet is at I/O 300h on PC, which is (%1100000000 -> 1 1000 0000 0000 0000) + 0x40000 = 0x58000
53 //
54 // Memory space: addresses from 0x80000 to 0xffffff are supported, including the possibility of stock PC MDA at a0000
55
56 #define ATBUS_IO_BASE 0x040000
57 #define ATBUS_IO_END 0x05ffff
58 #define ATBUS_MEMORY_BASE 0x080000
59 #define ATBUS_MEMORY_END 0xffffff
60
61 #define DN3500_RAM_SIZE 16 // 8, 16 or 32 MB
62
63 #if DN3500_RAM_SIZE == 8
64 #define DN3500_RAM_BASE 0x1000000
65 #define DN3500_RAM_END 0x17fffff
66 #define DN3500_RAM_CONFIG_BYTE 0x64 // 4-4-0-0
67 #elif DN3500_RAM_SIZE == 16
68 #define DN3500_RAM_BASE 0x1000000
69 #define DN3500_RAM_END 0x1ffffff
70 #define DN3500_RAM_CONFIG_BYTE 0x60 // 4-4-4-4
71 #else /* DN3500_RAM_SIZE == 32 */
72 #define DN3500_RAM_BASE 0x1000000
73 #define DN3500_RAM_END 0x3ffffff
74 #define DN3500_RAM_CONFIG_BYTE 0x20 // 8-8-8-8
75 #endif
76
77 #define DN3000_RAM_BASE 0x100000
78 #define DN3000_RAM_END 0x8fffff
79 #define DN3000_RAM_CONFIG_8MB 0x20 // 2-2-2-2
80
81 #define DN5500_RAM_SIZE 32 // 16 or 32 MB
82
83 #if DN5500_RAM_SIZE == 16
84 #define DN5500_RAM_BASE 0x1000000
85 #define DN5500_RAM_END 0x1ffffff
86 #define DN5500_RAM_CONFIG_BYTE 0x14 // 8-8-0-0
87 #define DN5500_MEM_PRESENT_BYTE 0xAA // 8-8-0-0
88 #else /* DN5500_RAM_SIZE == 32 */
89 #define DN5500_RAM_BASE 0x1000000
90 #define DN5500_RAM_END 0x2ffffff
91 #define DN5500_RAM_CONFIG_BYTE 0x20 // 8-8-8-8
92 #define DN5500_MEM_PRESENT_BYTE 0x00 // 8-8-8-8
93 #endif
94
95 #define NODE_TYPE_DN3000 3000
96 #define NODE_TYPE_DN3500 3500
97 #define NODE_TYPE_DN5500 5500
98 #define NODE_TYPE_DSP3000 -3000
99 #define NODE_TYPE_DSP3500 -3500
100 #define NODE_TYPE_DSP5500 -5500
101
102 #define DEFAULT_NODE_ID 0x12345
103
104 static uint8_t cache_control_register = 0x00;
105 static uint8_t cache_status_register = 0xff;
106 static uint8_t task_alias_register = 0x00;
107
108 static offs_t parity_error_offset = 0;
109 static uint16_t parity_error_byte_mask = 0;
110 static int parity_error_handler_is_installed = 0;
111 static int parity_error_handler_install_counter = 0;
112
113 static uint16_t latch_page_on_parity_error_register = 0x0000;
114 static uint16_t master_req_register = 0x0000;
115
116 static uint32_t ram_base_address;
117 static uint32_t ram_end_address;
118
119 static int node_type;
120
121 // FIXME: value of ram_config_byte must match with default/selected RAM size
122 static uint8_t ram_config_byte;
123
124 static uint32_t log_line_counter = 0;
125
126 /***************************************************************************
127 cpu_context - return a string describing which CPU is currently executing and their PC
128 ***************************************************************************/
129
apollo_cpu_context(running_machine & machine)130 std::string apollo_cpu_context(running_machine &machine) {
131 osd_ticks_t t = osd_ticks();
132 int s = (t / osd_ticks_per_second()) % 3600;
133 int ms = (t / (osd_ticks_per_second() / 1000)) % 1000;
134
135 return util::string_format("%s %d.%03d", machine.describe_context().c_str(), s, ms);
136 }
137
138 /*-------------------------------------------------
139 apollo_set_cpu_has_fpu - enable/disable the FPU
140 -------------------------------------------------*/
141
apollo_set_cpu_has_fpu(m68000_base_device * device,int onoff)142 void apollo_set_cpu_has_fpu(m68000_base_device *device, int onoff)
143 {
144 if (device == nullptr || (device->type() != M68020PMMU && device->type() != M68030))
145 {
146 DLOG1(("set_cpu_has_fpu: unexpected CPU device"));
147 }
148 else
149 {
150 device->set_fpu_enable(onoff);
151 DLOG1(("apollo_set_cpu_has_fpu: FPU has been %s", onoff ? "enabled" : "disabled"));
152 }
153 }
154
155 /***************************************************************************
156 apollo_check_log - check for excessive logging
157 ***************************************************************************/
158
apollo_check_log()159 void apollo_check_log() {
160 if (++log_line_counter >= APOLLO_MAX_NO_OF_LOG_LINES) {
161 fatalerror("apollo_check_log: maximum number of log lines exceeded.\n");
162 }
163 }
164
165 /***************************************************************************
166 apollo_is_dn3000 - return 1 if node is DN3000 or DSP3000, 0 otherwise
167 ***************************************************************************/
168
apollo_is_dn3000(void)169 int apollo_is_dn3000(void) {
170 return node_type == NODE_TYPE_DN3000 || node_type == NODE_TYPE_DSP3000;
171 }
172
173 /***************************************************************************
174 apollo_is_dn5500 - return 1 if node is DN5500 or DSP5500, 0 otherwise
175 ***************************************************************************/
176
apollo_is_dn5500(void)177 int apollo_is_dn5500(void) {
178 return node_type == NODE_TYPE_DN5500 || node_type == NODE_TYPE_DSP5500;
179 }
180
181 /***************************************************************************
182 apollo_is_dsp3x00 - return 1 if node is DSP3x00 or DSP5500, 0 otherwise
183 ***************************************************************************/
184
apollo_is_dsp3x00(void)185 int apollo_is_dsp3x00(void) {
186 switch (node_type)
187 {
188 case NODE_TYPE_DSP3000:
189 case NODE_TYPE_DSP3500:
190 case NODE_TYPE_DSP5500:
191 return 1;
192 }
193 return 0;
194 }
195
196 /***************************************************************************
197 apollo_get_ram_config_byte - get the ram configuration byte
198 ***************************************************************************/
199
apollo_get_ram_config_byte(void)200 uint8_t apollo_get_ram_config_byte(void) {
201 return ram_config_byte;
202 }
203
204 #if 0
205 /***************************************************************************
206 apollo_instruction_hook
207 must be called by the CPU core before executing each instruction
208 ***************************************************************************/
209 uint32_t apollo_state::apollo_instruction_hook(offs_t offset)
210 {
211 static uint16_t idle_counter = 0;
212
213 // m_maincpu->ir still has previous instruction
214 uint16_t last_ir = m_maincpu->ir;
215
216 // get next instruction (or 0 if unavailable)
217 uint16_t next_ir = (m_maincpu->pref_addr == REG_PC(m_maincpu)) ? m_maincpu->pref_data : 0;
218
219 // check for NULLPROC:
220 // 027C F8FF AND.W #F8FF,SR
221 // 60FA BRA *-4
222
223 if ((next_ir == 0x60fa && last_ir == 0x027c) || (next_ir == 0x027c && last_ir == 0x60fa))
224 {
225 // we are within the idle loop, slow down CPU to reduce power usage
226 m_maincpu->remaining_cycles -= 500;
227
228 if (apollo_config(APOLLO_CONF_IDLE_SLEEP) && apollo_is_dsp3x00() && ++idle_counter >= 1000)
229 {
230 // slow down even more on DSP3x00
231 idle_counter -= 100;
232 // sleep 1 ms
233 osd_sleep(osd_ticks_per_second() / 1000);
234 }
235 }
236 else
237 {
238 // we are outside of the idle loop
239 idle_counter = 0;
240 }
241
242 if (!m_maincpu->get_fpu_enable() && !m_maincpu->pmmu_enabled && (m_maincpu->ir & 0xff00) == 0xf200)
243 {
244 // set APOLLO_CSR_SR_FP_TRAP in cpu status register for /sau7/self_test
245 apollo_csr_set_status_register(APOLLO_CSR_SR_FP_TRAP, APOLLO_CSR_SR_FP_TRAP);
246 }
247
248 if (m_maincpu->t1_flag && !m_maincpu->s_flag)
249 {
250 // FIXME: trace emulation is disabled in m68kcpu.h; why???
251 m68ki_exception_trace(m_maincpu);
252 }
253
254 return apollo_debug_instruction_hook(m_maincpu, offset);
255 }
256
257 #endif
258
259 /***************************************************************************
260 apollo bus error
261 ***************************************************************************/
262
apollo_bus_error()263 void apollo_state::apollo_bus_error()
264 {
265 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
266 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
267
268 apollo_csr_set_status_register(APOLLO_CSR_SR_CPU_TIMEOUT, APOLLO_CSR_SR_CPU_TIMEOUT);
269 }
270
cpu_space_map(address_map & map)271 void apollo_state::cpu_space_map(address_map &map)
272 {
273 map(0xfffffff2, 0xffffffff).r(FUNC(apollo_state::apollo_irq_acknowledge));
274 }
275
apollo_irq_acknowledge(offs_t offset)276 u16 apollo_state::apollo_irq_acknowledge(offs_t offset)
277 {
278 m_maincpu->set_input_line(offset+1, CLEAR_LINE);
279
280 MLOG2(("apollo_irq_acknowledge: interrupt level=%d", offset+1));
281
282 if (offset+1 == 6)
283 return apollo_pic_get_vector();
284 else
285 return m68000_base_device::autovector(offset+1);
286 }
287
288 /***************************************************************************
289 DN3500 Cache Control/Status Register at 0x10200
290 ***************************************************************************/
291
cache_control_register_w(offs_t offset,uint8_t data)292 void apollo_state::cache_control_register_w(offs_t offset, uint8_t data){
293 if (apollo_is_dn5500())
294 {
295 SLOG1(("Error: writing DN5500 Cache Status Register at offset %02x = %02x", offset, data));
296 }
297 else
298 {
299 cache_control_register = data;
300 cache_status_register = (cache_status_register & 0x7f) | (cache_control_register & 0x80);
301 SLOG2(("writing Cache Control Register at offset %02x = %02x", offset, data));
302 }
303 }
304
cache_status_register_r(offs_t offset)305 uint8_t apollo_state::cache_status_register_r(offs_t offset){
306 uint8_t data = cache_status_register;
307
308 if (apollo_is_dn5500()) {
309 #define DN5500_CSR_NOT_HSI_PRESENT 8
310 #define DN5500_CSR_MEM_TIME 1
311 data |= DN5500_CSR_NOT_HSI_PRESENT;
312 }
313
314 SLOG2(("reading Cache Status Register at offset %02x = %02x", offset, data));
315 return data;
316 }
317
apollo_set_cache_status_register(device_t * device,uint8_t mask,uint8_t data)318 void apollo_set_cache_status_register(device_t *device,uint8_t mask, uint8_t data) {
319 uint16_t new_value = (cache_status_register & ~mask) | (data & mask);
320 if (new_value != cache_status_register) {
321 cache_status_register = new_value;
322 DLOG2(("setting Cache Status Register with data=%02x and mask=%02x to %02x",
323 data, mask, cache_status_register));
324 }
325 }
326
327 /***************************************************************************
328 DN3500 Task Alias Register at 0x10300
329 ***************************************************************************/
330
task_alias_register_w(offs_t offset,uint8_t data)331 void apollo_state::task_alias_register_w(offs_t offset, uint8_t data){
332 task_alias_register = data;
333 apollo_set_cache_status_register(this,0x07, data);
334 SLOG(("writing Task Alias Register at offset %02x = %02x",offset, data));
335 }
336
task_alias_register_r(offs_t offset)337 uint8_t apollo_state::task_alias_register_r(offs_t offset){
338 uint8_t data = 0xff;
339 SLOG(("reading Task Alias Register at offset %02x = %02x", offset, data));
340 return data;
341 }
342
343 /***************************************************************************
344 DN3000/DN3500 Latch Page on Parity Error Register at 0x9300/0x11300
345 ***************************************************************************/
346
latch_page_on_parity_error_register_w(offs_t offset,uint16_t data)347 void apollo_state::latch_page_on_parity_error_register_w(offs_t offset, uint16_t data){
348 latch_page_on_parity_error_register = data;
349 SLOG1(("writing Latch Page on Error Parity Register at offset %02x = %04x", offset*2, data));
350 }
351
latch_page_on_parity_error_register_r(offs_t offset)352 uint16_t apollo_state::latch_page_on_parity_error_register_r(offs_t offset){
353 uint16_t data = latch_page_on_parity_error_register;
354 SLOG2(("reading Latch Page on Error Parity Register at offset %02x = %04x", offset*2, data));
355 return data;
356 }
357
358 /***************************************************************************
359 DN3500 Master REQ Register at 0x11600
360 ***************************************************************************/
361
master_req_register_w(offs_t offset,uint8_t data)362 void apollo_state::master_req_register_w(offs_t offset, uint8_t data){
363 master_req_register = data;
364 SLOG2(("writing Master REQ Register at offset %02x = %02x", offset, data));
365 }
366
master_req_register_r(offs_t offset)367 uint8_t apollo_state::master_req_register_r(offs_t offset){
368 uint8_t data = 0xff;
369 SLOG1(("reading Master REQ Register at offset %02x = %02x", offset, data));
370 return data;
371 }
372
373 /***************************************************************************
374 DN3500 Selective Clear Locations at 0x11600
375 ***************************************************************************/
376
selective_clear_locations_w(offs_t offset,uint16_t data)377 void apollo_state::selective_clear_locations_w(offs_t offset, uint16_t data){
378 SLOG2(("writing Selective Clear Locations at offset %02x = %02x", offset*2, data));
379 switch (offset * 2) {
380 case 0x00: // Clear All
381 apollo_csr_set_status_register(APOLLO_CSR_SR_CLEAR_ALL, 0);
382 break;
383 case 0x04: // clear floating-point trap
384 apollo_csr_set_status_register(APOLLO_CSR_SR_FP_TRAP, 0);
385 break;
386 case 0x06: // clear Parity error interrupt
387 apollo_csr_set_status_register(APOLLO_CSR_SR_PARITY_BYTE_MASK, 0);
388 break;
389 case 0x08: // clear Bus Error Status (CPU Timeout)
390 apollo_csr_set_status_register(APOLLO_CSR_SR_CPU_TIMEOUT, 0);
391 break;
392 case 0x0e: // Clear (Flush) Cache
393 break;
394 }
395 }
396
selective_clear_locations_r(offs_t offset)397 uint16_t apollo_state::selective_clear_locations_r(offs_t offset){
398 uint16_t data = 0xffff;
399 SLOG1(("reading Selective Clear Locations at offset %02x = %02x", offset*2, data));
400 return data;
401 }
402
403 /***************************************************************************
404 DN3000/DN3500 RAM with parity (and null proc loop delay for DomainOS)
405 ***************************************************************************/
406
ram_with_parity_r(offs_t offset,uint32_t mem_mask)407 uint32_t apollo_state::ram_with_parity_r(offs_t offset, uint32_t mem_mask){
408 uint32_t data = m_messram_ptr[parity_error_offset+offset];
409
410 SLOG2(("memory dword read with parity error at %08x = %08x & %08x parity_byte=%04x",
411 ram_base_address + parity_error_offset*4 + offset*4,data, mem_mask, parity_error_byte_mask));
412
413 if (parity_error_byte_mask != 0) {
414 latch_page_on_parity_error_register = (ram_base_address + parity_error_offset * 4) >> 10;
415
416 apollo_csr_set_status_register(APOLLO_CSR_CR_PARITY_BYTE_MASK, apollo_csr_get_status_register() |parity_error_byte_mask);
417
418 if (apollo_csr_get_control_register() & APOLLO_CSR_CR_INTERRUPT_ENABLE) {
419 // force parity error (if NMI is enabled)
420 m_maincpu->set_input_line(7, ASSERT_LINE);
421
422 }
423 }
424 return data;
425 }
426
ram_with_parity_w(offs_t offset,uint32_t data,uint32_t mem_mask)427 void apollo_state::ram_with_parity_w(offs_t offset, uint32_t data, uint32_t mem_mask){
428 COMBINE_DATA(m_messram_ptr+offset);
429
430 if (apollo_csr_get_control_register() & APOLLO_CSR_CR_FORCE_BAD_PARITY) {
431 parity_error_byte_mask = (apollo_csr_get_control_register()
432 & APOLLO_CSR_CR_PARITY_BYTE_MASK);
433
434 if (!apollo_is_dn3000()) {
435 parity_error_byte_mask ^= APOLLO_CSR_CR_PARITY_BYTE_MASK;
436 }
437
438 parity_error_offset = offset;
439
440 // SLOG1(("memory dword write with parity to %08x = %08x & %08x parity_byte=%04x",
441 // ram_base_address +offset * 4, data, mem_mask, parity_error_byte_mask));
442
443 if (parity_error_handler_is_installed == 0) {
444 // no more than 192 read/write handlers may be used
445 // see table_assign_handler in memory.c
446 if (parity_error_handler_install_counter < 40) {
447 m_maincpu->space(AS_PROGRAM).install_read_handler(ram_base_address+offset*4, ram_base_address+offset*4+3, read32s_delegate(*this, FUNC(apollo_state::ram_with_parity_r)));
448 parity_error_handler_is_installed = 1;
449 parity_error_handler_install_counter++;
450 }
451 }
452 } else if (parity_error_handler_is_installed && offset == parity_error_offset) {
453 SLOG1(("memory dword write with parity to %08x = %08x & %08x reset %d",
454 ram_base_address +parity_error_offset*4, data, mem_mask, parity_error_handler_install_counter));
455
456 // uninstall not supported, reinstall previous read handler instead
457
458 // memory_install_rom(space, ram_base_address, ram_end_address, messram_ptr.v);
459 m_maincpu->space(AS_PROGRAM).install_rom(ram_base_address,ram_end_address,&m_messram_ptr[0]);
460
461 parity_error_handler_is_installed = 0;
462 parity_error_byte_mask = 0;
463 }
464 }
465
466 /***************************************************************************
467 DN3000/DN3500 unmapped memory
468 ***************************************************************************/
469
apollo_unmapped_r(offs_t offset,uint32_t mem_mask)470 uint32_t apollo_state::apollo_unmapped_r(offs_t offset, uint32_t mem_mask)
471 {
472 offs_t address = offset * 4;
473
474 m68000_base_device *m68k = m_maincpu;
475
476 if ((address & 0xfff00000) == 0xfa800000 && VERBOSE < 2) {
477 // ?
478 } else if ((address & 0xfff00ff7) == 0xfd800000 && VERBOSE < 2) {
479 // omit logging for memory sizing in FPA address space
480 // strange: MD seems to search for the 3C505 Boot ROM
481 // note (6.10.2010): might be color7 address space (!?!)
482 } else if ((address & 0xfc03ffff) == 0x00000000 && VERBOSE < 2) {
483 // omit logging for memory sizing in standalone utilities
484 } else if (address == 0xfff90000 && VERBOSE < 2) {
485 // omit logging for FPA trial access
486 } else if (address == 0x00030000 && VERBOSE < 2) {
487 // omit logging for Bus error test address in DN3500 boot prom and self_test
488 } else if (address == 0x0000ac00 && VERBOSE < 2) {
489 // omit logging for Bus error test address in DN3000 boot prom
490 } else {
491 SLOG1(("unmapped memory dword read from %08x with mask %08x (ir=%04x)", address , mem_mask, m68k->state_int(M68K_IR)));
492 }
493
494 /* unmapped; access causes a bus error */
495 apollo_bus_error();
496 return 0xffffffff;
497 }
498
apollo_unmapped_w(offs_t offset,uint32_t data,uint32_t mem_mask)499 void apollo_state::apollo_unmapped_w(offs_t offset, uint32_t data, uint32_t mem_mask)
500 {
501 SLOG(("unmapped memory dword write to %08x = %08x & %08x", offset * 4, data, mem_mask));
502
503 /* unmapped; access causes a bus error */
504 apollo_bus_error();
505 }
506
507 /***************************************************************************
508 DN3000/DN3500 ROM write
509 ***************************************************************************/
510
apollo_rom_w(offs_t offset,uint32_t data,uint32_t mem_mask)511 void apollo_state::apollo_rom_w(offs_t offset, uint32_t data, uint32_t mem_mask)
512 {
513 offs_t address = offset * 4;
514 offs_t pc = m_maincpu->pcbase();
515
516 if (pc == 0x00002c1c && address == 0x00000004 && VERBOSE < 2) {
517 // don't log invalid code in 3500_boot_12191_7.bin
518 } else {
519 SLOG1(("ROM dword write to %08x = %08x & %08x", offset * 4, data, mem_mask));
520 }
521 }
522
523 /***************************************************************************
524 DN3000/DN3500 AT Bus I/O space
525 ***************************************************************************/
526
apollo_atbus_io_r(offs_t offset,uint16_t mem_mask)527 uint16_t apollo_state::apollo_atbus_io_r(offs_t offset, uint16_t mem_mask)
528 {
529 uint32_t isa_addr = (offset & 3) + ((offset & ~0x1ff) >> 7);
530
531 // Motorola CPU is MSB first, ISA Bus is LSB first
532 uint16_t data = m_isa->io16_swap_r(isa_addr, mem_mask);
533
534 SLOG2(("apollo_atbus_io_r at %08x -> %04x = %04x & %04x", ATBUS_IO_BASE + offset*2, isa_addr*2, data, mem_mask));
535
536 return data;
537 }
538
apollo_atbus_io_w(offs_t offset,uint16_t data,uint16_t mem_mask)539 void apollo_state::apollo_atbus_io_w(offs_t offset, uint16_t data, uint16_t mem_mask)
540 {
541 uint32_t isa_addr = (offset & 3) + ((offset & ~0x1ff) >> 7);
542
543 SLOG2(("apollo_atbus_io_w at %08x -> %04x = %04x & %04x", ATBUS_IO_BASE + offset*2, isa_addr*2, data, mem_mask));
544
545 // Motorola CPU is MSB first, ISA Bus is LSB first
546 m_isa->io16_swap_w(isa_addr, data, mem_mask);
547 }
548
549 /***************************************************************************
550 DN3000/DN3500 AT Bus memory space
551 ***************************************************************************/
552
apollo_atbus_memory_r(offs_t offset,uint16_t mem_mask)553 uint16_t apollo_state::apollo_atbus_memory_r(offs_t offset, uint16_t mem_mask)
554 {
555 uint16_t data;
556
557 // Motorola CPU is MSB first, ISA Bus is LSB first
558 data = m_isa->mem16_swap_r(offset, mem_mask);
559
560 SLOG2(("apollo_atbus_memory_r at %08x = %04x & %04x", ATBUS_MEMORY_BASE + offset * 2, data, mem_mask));
561 return data;
562 }
563
apollo_atbus_memory_w(offs_t offset,uint16_t data,uint16_t mem_mask)564 void apollo_state::apollo_atbus_memory_w(offs_t offset, uint16_t data, uint16_t mem_mask)
565 {
566 SLOG2(("apollo_atbus_memory_w at %08x = %04x & %04x", ATBUS_MEMORY_BASE + offset*2, data, mem_mask));
567
568 // Motorola CPU is MSB first, ISA Bus is LSB first
569 m_isa->mem16_swap_w(offset, data, mem_mask);
570 }
571
572 /***************************************************************************
573 DN3000/DN3500 AT Bus unmapped read/write
574 ***************************************************************************/
575
apollo_atbus_unmap_io_r(offs_t offset,uint16_t mem_mask)576 uint16_t apollo_state::apollo_atbus_unmap_io_r(offs_t offset, uint16_t mem_mask)
577 {
578 // ISA bus has 0xff for unmapped addresses
579 uint16_t data = 0xffff;
580 uint32_t isa_addr = (offset & 3) + ((offset & ~0x1ff) >> 7);
581 SLOG1(("apollo_atbus_unmap_io_r at %08x -> %04x = %04x & %04x", ATBUS_IO_BASE + offset*2, isa_addr*2, data, mem_mask));
582 return data;
583 }
584
apollo_atbus_unmap_io_w(offs_t offset,uint16_t data,uint16_t mem_mask)585 void apollo_state::apollo_atbus_unmap_io_w(offs_t offset, uint16_t data, uint16_t mem_mask)
586 {
587 uint32_t isa_addr = (offset & 3) + ((offset & ~0x1ff) >> 7);
588 SLOG1(("apollo_atbus_unmap_io_w at %08x -> %04x = %04x & %04x", ATBUS_IO_BASE + offset*2, isa_addr*2, data, mem_mask));
589 }
590
apollo_atbus_unmap_r(offs_t offset,uint8_t mem_mask)591 uint8_t apollo_state::apollo_atbus_unmap_r(offs_t offset, uint8_t mem_mask)
592 {
593 // ISA bus has 0xff for unmapped addresses
594 uint8_t data = 0xff;
595 SLOG2(("apollo_atbus_unmap_r at %08x = %02x & %02x", ATBUS_MEMORY_BASE + offset, data, mem_mask));
596 return data;
597 }
598
apollo_atbus_unmap_w(offs_t offset,uint8_t data,uint8_t mem_mask)599 void apollo_state::apollo_atbus_unmap_w(offs_t offset, uint8_t data, uint8_t mem_mask)
600 {
601 SLOG1(("apollo_atbus_unmap_w at %08x = %02x & %02x", ATBUS_MEMORY_BASE + offset, data, mem_mask));
602 }
603
604 /***************************************************************************
605 DN5500 Memory Present Register at 0x11400-0x114ff
606 Strange: documented but not used
607 ***************************************************************************/
608
dn5500_memory_present_register_w(offs_t offset,uint8_t data)609 void apollo_state::dn5500_memory_present_register_w(offs_t offset, uint8_t data){
610 SLOG(("Error: writing DN5500 Memory Present Register at offset %02x = %02x", offset, data));
611 }
612
dn5500_memory_present_register_r(offs_t offset)613 uint8_t apollo_state::dn5500_memory_present_register_r(offs_t offset){
614 uint8_t data = DN5500_MEM_PRESENT_BYTE;
615 SLOG(("reading DN5500 Memory Present Register at offset %02x = %02x", offset, data));
616 return data;
617 }
618
619 /***************************************************************************
620 DN5500 11500 Registers at 0x11500-0x115ff (undocumented, what does it do?)
621 ***************************************************************************/
622
dn5500_11500_w(offs_t offset,uint8_t data)623 void apollo_state::dn5500_11500_w(offs_t offset, uint8_t data){
624 SLOG1(("writing DN5500 11500 at offset %02x = %02x", offset, data));
625 }
626
dn5500_11500_r(offs_t offset)627 uint8_t apollo_state::dn5500_11500_r(offs_t offset){
628 uint8_t data = 0xff;
629 SLOG1(("reading DN5500 11500 at offset %02x = %02x", offset, data));
630 return data;
631 }
632
633 /***************************************************************************
634 DN5500 I/O Protection Map at 0x7000000-0x700FFFF
635 ***************************************************************************/
636
dn5500_io_protection_map_w(offs_t offset,uint8_t data)637 void apollo_state::dn5500_io_protection_map_w(offs_t offset, uint8_t data){
638 // TODO
639 SLOG1(("writing DN5500 I/O Protection Map at offset %02x = %02x", offset, data));
640 }
641
dn5500_io_protection_map_r(offs_t offset)642 uint8_t apollo_state::dn5500_io_protection_map_r(offs_t offset){
643 uint8_t data = 0xff;
644 SLOG1(("reading DN5500 I/O Protection Map at offset %02x = %02x", offset, data));
645 return data;
646 }
647
648 #if 0
649 /***************************************************************************
650 DN3000/DN3500 at f8000000 - ffffffff (used by fpa and/or color7?)
651 ***************************************************************************/
652
653 uint32_t apollo_state::apollo_f8_r(offs_t offset, uint32_t mem_mask){
654 offs_t address = 0xf8000000 + offset * 4;
655 uint32_t data = 0xffffffff;
656 SLOG2(("unexpected memory dword read from %08x = %08x & %08x",
657 address, data, mem_mask));
658 return data;
659 }
660
661 void apollo_state::apollo_f8_w(offs_t offset, uint32_t data, uint32_t mem_mask){
662 offs_t address = 0xf8000000 +offset * 4;
663
664 SLOG2(("unexpected memory dword write to %08x = %08x & %08x",
665 address, data, mem_mask));
666 }
667 #endif
668
669 /***************************************************************************
670 ADDRESS MAPS
671 ***************************************************************************/
672
dn3500_map(address_map & map)673 void apollo_state::dn3500_map(address_map &map)
674 {
675 map(0x00000000, 0xffffffff).rw(FUNC(apollo_state::apollo_unmapped_r), FUNC(apollo_state::apollo_unmapped_w));
676
677 map(0x000000, 0x00ffff).rom(); /* boot ROM */
678 map(0x000000, 0x00ffff).w(FUNC(apollo_state::apollo_rom_w));
679 map(0x010000, 0x0100ff).rw(FUNC(apollo_state::apollo_csr_status_register_r), FUNC(apollo_state::apollo_csr_status_register_w));
680 map(0x010100, 0x0101ff).rw(FUNC(apollo_state::apollo_csr_control_register_r), FUNC(apollo_state::apollo_csr_control_register_w));
681 map(0x010200, 0x0102ff).rw(FUNC(apollo_state::cache_status_register_r), FUNC(apollo_state::cache_control_register_w));
682 map(0x010300, 0x0103ff).rw(FUNC(apollo_state::task_alias_register_r), FUNC(apollo_state::task_alias_register_w));
683 map(0x010400, 0x0104ff).rw(m_sio, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
684 map(0x010500, 0x0105ff).rw(m_sio2, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
685 map(0x010800, 0x0108ff).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)).umask32(0x00ff00ff);
686 map(0x010900, 0x0109ff).rw(FUNC(apollo_state::apollo_rtc_r), FUNC(apollo_state::apollo_rtc_w));
687 map(0x010c00, 0x010cff).rw(FUNC(apollo_state::/*"dma1",*/apollo_dma_1_r), FUNC(apollo_state::apollo_dma_1_w));
688 map(0x010d00, 0x010dff).rw(FUNC(apollo_state::/*"dma2",*/apollo_dma_2_r), FUNC(apollo_state::apollo_dma_2_w));
689 map(0x011000, 0x0110ff).rw(m_pic8259_master, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
690 map(0x011100, 0x0111ff).rw(m_pic8259_slave, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
691 map(0x011200, 0x0112ff).rw(m_node_id, FUNC(apollo_ni::read), FUNC(apollo_ni::write));
692 map(0x011300, 0x0113ff).rw(FUNC(apollo_state::latch_page_on_parity_error_register_r), FUNC(apollo_state::latch_page_on_parity_error_register_w));
693 map(0x011600, 0x0116ff).rw(FUNC(apollo_state::master_req_register_r), FUNC(apollo_state::master_req_register_w));
694
695 map(0x016400, 0x0164ff).rw(FUNC(apollo_state::selective_clear_locations_r), FUNC(apollo_state::selective_clear_locations_w));
696 map(0x017000, 0x017fff).rw(FUNC(apollo_state::apollo_address_translation_map_r), FUNC(apollo_state::apollo_address_translation_map_w));
697
698 map(ATBUS_IO_BASE, ATBUS_IO_END).rw(FUNC(apollo_state::apollo_atbus_io_r), FUNC(apollo_state::apollo_atbus_io_w));
699 map(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END).rw(FUNC(apollo_state::apollo_atbus_memory_r), FUNC(apollo_state::apollo_atbus_memory_w));
700
701 // FIXME: must match with RAM size in driver/apollo_sio.c
702 // map(DN3500_RAM_BASE, DN3500_RAM_END).ram(); /* 8MB RAM */
703 map(DN3500_RAM_BASE, DN3500_RAM_END).ram().w(FUNC(apollo_state::ram_with_parity_w)).share(RAM_TAG);
704
705 map(0x05d800, 0x05dc07).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_mcr_r), FUNC(apollo_graphics_15i::apollo_mcr_w));
706 map(0xfa0000, 0xfdffff).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_mgm_r), FUNC(apollo_graphics_15i::apollo_mgm_w));
707
708 map(0x05e800, 0x05ec07).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_ccr_r), FUNC(apollo_graphics_15i::apollo_ccr_w));
709 map(0x0a0000, 0x0bffff).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_cgm_r), FUNC(apollo_graphics_15i::apollo_cgm_w));
710
711 // map(0x03020000, 0x0303ffff) Cache Tag Store (DN4500 only)
712 // map(0x04000000, 0x0400ffff) Cache Tag Data (DN4500 only)
713 // map(0x0e000000, 0x0fffffff) FPA address space
714
715 // map(0xf8000000, 0xffffffff).rw(FUNC(apollo_state::apollo_f8_r), FUNC(apollo_state::apollo_f8_w));
716 }
717
dsp3500_map(address_map & map)718 void apollo_state::dsp3500_map(address_map &map)
719 {
720 map(0x00000000, 0xffffffff).rw(FUNC(apollo_state::apollo_unmapped_r), FUNC(apollo_state::apollo_unmapped_w));
721 map(0x000000, 0x00ffff).rom(); /* boot ROM */
722 map(0x000000, 0x00ffff).w(FUNC(apollo_state::apollo_rom_w));
723 map(0x010000, 0x0100ff).rw(FUNC(apollo_state::apollo_csr_status_register_r), FUNC(apollo_state::apollo_csr_status_register_w));
724 map(0x010100, 0x0101ff).rw(FUNC(apollo_state::apollo_csr_control_register_r), FUNC(apollo_state::apollo_csr_control_register_w));
725 map(0x010200, 0x0102ff).rw(FUNC(apollo_state::cache_status_register_r), FUNC(apollo_state::cache_control_register_w));
726 map(0x010300, 0x0103ff).rw(FUNC(apollo_state::task_alias_register_r), FUNC(apollo_state::task_alias_register_w));
727 map(0x010400, 0x0104ff).rw(m_sio, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
728 map(0x010500, 0x0105ff).rw(m_sio2, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
729 map(0x010800, 0x0108ff).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)).umask32(0x00ff00ff);
730 map(0x010900, 0x0109ff).rw(FUNC(apollo_state::apollo_rtc_r), FUNC(apollo_state::apollo_rtc_w));
731 map(0x010c00, 0x010cff).rw(FUNC(apollo_state::/*"dma1",*/apollo_dma_1_r), FUNC(apollo_state::apollo_dma_1_w));
732 map(0x010d00, 0x010dff).rw(FUNC(apollo_state::/*"dma2",*/apollo_dma_2_r), FUNC(apollo_state::apollo_dma_2_w));
733 map(0x011000, 0x0110ff).rw(m_pic8259_master, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
734 map(0x011100, 0x0111ff).rw(m_pic8259_slave, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
735 map(0x011200, 0x0112ff).rw(m_node_id, FUNC(apollo_ni::read), FUNC(apollo_ni::write));
736 map(0x011300, 0x0113ff).rw(FUNC(apollo_state::latch_page_on_parity_error_register_r), FUNC(apollo_state::latch_page_on_parity_error_register_w));
737 map(0x011600, 0x0116ff).rw(FUNC(apollo_state::master_req_register_r), FUNC(apollo_state::master_req_register_w));
738
739 map(0x016400, 0x0164ff).rw(FUNC(apollo_state::selective_clear_locations_r), FUNC(apollo_state::selective_clear_locations_w));
740 map(0x017000, 0x017fff).rw(FUNC(apollo_state::apollo_address_translation_map_r), FUNC(apollo_state::apollo_address_translation_map_w));
741
742 map(ATBUS_IO_BASE, ATBUS_IO_END).rw(FUNC(apollo_state::apollo_atbus_io_r), FUNC(apollo_state::apollo_atbus_io_w));
743
744 map(DN3500_RAM_BASE, DN3500_RAM_END).ram().w(FUNC(apollo_state::ram_with_parity_w)).share(RAM_TAG);
745
746 map(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END).rw(FUNC(apollo_state::apollo_atbus_memory_r), FUNC(apollo_state::apollo_atbus_memory_w));
747
748 // map(0xf8000000, 0xffffffff).rw(FUNC(apollo_state::apollo_f8_r), FUNC(apollo_state::apollo_f8_w));
749 }
750
dn3000_map(address_map & map)751 void apollo_state::dn3000_map(address_map &map)
752 {
753 map(0x000000, 0xffffff).rw(FUNC(apollo_state::apollo_unmapped_r), FUNC(apollo_state::apollo_unmapped_w));
754
755 map(0x000000, 0x007fff).rom(); /* boot ROM */
756 map(0x000000, 0x007fff).w(FUNC(apollo_state::apollo_rom_w));
757 map(0x008000, 0x0080ff).rw(FUNC(apollo_state::apollo_csr_status_register_r), FUNC(apollo_state::apollo_csr_status_register_w));
758 map(0x008100, 0x0081ff).rw(FUNC(apollo_state::apollo_csr_control_register_r), FUNC(apollo_state::apollo_csr_control_register_w));
759 map(0x008400, 0x0087ff).rw(m_sio, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
760 map(0x008800, 0x0088ff).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)).umask32(0x00ff00ff);
761 map(0x008900, 0x0089ff).rw(FUNC(apollo_state::apollo_rtc_r), FUNC(apollo_state::apollo_rtc_w));
762 map(0x009000, 0x0090ff).rw(FUNC(apollo_state::/*"dma1",*/apollo_dma_1_r), FUNC(apollo_state::apollo_dma_1_w));
763 map(0x009100, 0x0091ff).rw(FUNC(apollo_state::/*"dma2",*/apollo_dma_2_r), FUNC(apollo_state::apollo_dma_2_w));
764 map(0x009200, 0x0092ff).rw(FUNC(apollo_state::apollo_dma_page_register_r), FUNC(apollo_state::apollo_dma_page_register_w));
765 map(0x009300, 0x0093ff).rw(FUNC(apollo_state::latch_page_on_parity_error_register_r), FUNC(apollo_state::latch_page_on_parity_error_register_w));
766 map(0x009400, 0x0094ff).rw(m_pic8259_master, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
767 map(0x009500, 0x0095ff).rw(m_pic8259_slave, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
768 map(0x009600, 0x0096ff).rw(m_node_id, FUNC(apollo_ni::read), FUNC(apollo_ni::write));
769
770 map(ATBUS_IO_BASE, ATBUS_IO_END).rw(FUNC(apollo_state::apollo_atbus_io_r), FUNC(apollo_state::apollo_atbus_io_w));
771 map(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END).rw(FUNC(apollo_state::apollo_atbus_memory_r), FUNC(apollo_state::apollo_atbus_memory_w));
772
773 // FIXME: must match with RAM size in driver/apollo_sio.c
774 // map(DN3000_RAM_BASE, DN3000_RAM_END).ram(); /* 8MB RAM */
775 map(DN3000_RAM_BASE, DN3000_RAM_END).ram().w(FUNC(apollo_state::ram_with_parity_w)).share(RAM_TAG);
776
777 map(0x05d800, 0x05dc07).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_mcr_r), FUNC(apollo_graphics_15i::apollo_mcr_w));
778 map(0xfa0000, 0xfdffff).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_mgm_r), FUNC(apollo_graphics_15i::apollo_mgm_w));
779
780 map(0x05e800, 0x05ec07).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_ccr_r), FUNC(apollo_graphics_15i::apollo_ccr_w));
781 map(0x0a0000, 0x0bffff).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_cgm_r), FUNC(apollo_graphics_15i::apollo_cgm_w));
782 }
783
dsp3000_map(address_map & map)784 void apollo_state::dsp3000_map(address_map &map)
785 {
786 map(0x000000, 0xffffff).rw(FUNC(apollo_state::apollo_unmapped_r), FUNC(apollo_state::apollo_unmapped_w));
787
788 map(0x000000, 0x007fff).rom(); /* boot ROM */
789 map(0x000000, 0x007fff).w(FUNC(apollo_state::apollo_rom_w));
790 map(0x008000, 0x0080ff).rw(FUNC(apollo_state::apollo_csr_status_register_r), FUNC(apollo_state::apollo_csr_status_register_w));
791 map(0x008100, 0x0081ff).rw(FUNC(apollo_state::apollo_csr_control_register_r), FUNC(apollo_state::apollo_csr_control_register_w));
792 map(0x008400, 0x0087ff).rw(m_sio, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
793 map(0x008800, 0x0088ff).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)).umask32(0x00ff00ff);
794 map(0x008900, 0x0089ff).rw(FUNC(apollo_state::apollo_rtc_r), FUNC(apollo_state::apollo_rtc_w));
795
796 map(0x009000, 0x0090ff).rw(FUNC(apollo_state::/*"dma1",*/apollo_dma_1_r), FUNC(apollo_state::apollo_dma_1_w));
797 map(0x009100, 0x0091ff).rw(FUNC(apollo_state::/*"dma2",*/apollo_dma_2_r), FUNC(apollo_state::apollo_dma_2_w));
798 map(0x009200, 0x0092ff).rw(FUNC(apollo_state::apollo_dma_page_register_r), FUNC(apollo_state::apollo_dma_page_register_w));
799 map(0x009300, 0x0093ff).rw(FUNC(apollo_state::latch_page_on_parity_error_register_r), FUNC(apollo_state::latch_page_on_parity_error_register_w));
800 map(0x009400, 0x0094ff).rw(m_pic8259_master, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
801 map(0x009500, 0x0095ff).rw(m_pic8259_slave, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
802 map(0x009600, 0x0096ff).rw(m_node_id, FUNC(apollo_ni::read), FUNC(apollo_ni::write));
803
804 map(ATBUS_IO_BASE, ATBUS_IO_END).rw(FUNC(apollo_state::apollo_atbus_io_r), FUNC(apollo_state::apollo_atbus_io_w));
805 map(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END).rw(FUNC(apollo_state::apollo_atbus_memory_r), FUNC(apollo_state::apollo_atbus_memory_w));
806
807 // FIXME: must match with RAM size in driver/apollo_sio.c
808 // map(DN3000_RAM_BASE, DN3000_RAM_END).ram(); /* 8MB RAM */
809 map(DN3000_RAM_BASE, DN3000_RAM_END).ram().w(FUNC(apollo_state::ram_with_parity_w)).share(RAM_TAG);
810
811 }
812
813
dn5500_map(address_map & map)814 void apollo_state::dn5500_map(address_map &map)
815 {
816 map(0x00000000, 0xffffffff).rw(FUNC(apollo_state::apollo_unmapped_r), FUNC(apollo_state::apollo_unmapped_w));
817 map(0x000000, 0x00ffff).rom(); /* boot ROM */
818 map(0x000000, 0x00ffff).w(FUNC(apollo_state::apollo_rom_w));
819 map(0x010000, 0x0100ff).rw(FUNC(apollo_state::apollo_csr_status_register_r), FUNC(apollo_state::apollo_csr_status_register_w));
820 map(0x010100, 0x0101ff).rw(FUNC(apollo_state::apollo_csr_control_register_r), FUNC(apollo_state::apollo_csr_control_register_w));
821 map(0x010200, 0x0102ff).rw(FUNC(apollo_state::cache_status_register_r), FUNC(apollo_state::cache_control_register_w));
822 map(0x010300, 0x0103ff).rw(FUNC(apollo_state::task_alias_register_r), FUNC(apollo_state::task_alias_register_w));
823 map(0x010400, 0x0104ff).rw(m_sio, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
824 map(0x010500, 0x0105ff).rw(m_sio2, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
825 map(0x010800, 0x0108ff).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)).umask32(0x00ff00ff);
826 map(0x010900, 0x0109ff).rw(FUNC(apollo_state::apollo_rtc_r), FUNC(apollo_state::apollo_rtc_w));
827 map(0x010c00, 0x010cff).rw(FUNC(apollo_state::/*"dma1",*/apollo_dma_1_r), FUNC(apollo_state::apollo_dma_1_w));
828 map(0x010d00, 0x010dff).rw(FUNC(apollo_state::/*"dma2",*/apollo_dma_2_r), FUNC(apollo_state::apollo_dma_2_w));
829 map(0x011000, 0x0110ff).rw(m_pic8259_master, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
830 map(0x011100, 0x0111ff).rw(m_pic8259_slave, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
831 map(0x011200, 0x0112ff).rw(m_node_id, FUNC(apollo_ni::read), FUNC(apollo_ni::write));
832 map(0x011300, 0x0113ff).rw(FUNC(apollo_state::latch_page_on_parity_error_register_r), FUNC(apollo_state::latch_page_on_parity_error_register_w));
833 map(0x011400, 0x0114ff).rw(FUNC(apollo_state::dn5500_memory_present_register_r), FUNC(apollo_state::dn5500_memory_present_register_w));
834 map(0x011500, 0x0115ff).rw(FUNC(apollo_state::dn5500_11500_r), FUNC(apollo_state::dn5500_11500_w));
835 map(0x011600, 0x0116ff).rw(FUNC(apollo_state::master_req_register_r), FUNC(apollo_state::master_req_register_w));
836
837 map(0x016400, 0x0164ff).rw(FUNC(apollo_state::selective_clear_locations_r), FUNC(apollo_state::selective_clear_locations_w));
838 map(0x017000, 0x017fff).rw(FUNC(apollo_state::apollo_address_translation_map_r), FUNC(apollo_state::apollo_address_translation_map_w));
839
840 map(ATBUS_IO_BASE, ATBUS_IO_END).rw(FUNC(apollo_state::apollo_atbus_io_r), FUNC(apollo_state::apollo_atbus_io_w));
841 map(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END).rw(FUNC(apollo_state::apollo_atbus_memory_r), FUNC(apollo_state::apollo_atbus_memory_w));
842
843 // FIXME: must match with RAM size in driver/apollo_sio.c
844 // map(DN3500_RAM_BASE, DN3500_RAM_END).ram(); /* 8MB RAM */
845 map(DN5500_RAM_BASE, DN5500_RAM_END).ram().w(FUNC(apollo_state::ram_with_parity_w)).share(RAM_TAG);
846
847 map(0x05d800, 0x05dc07).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_mcr_r), FUNC(apollo_graphics_15i::apollo_mcr_w));
848 map(0xfa0000, 0xfdffff).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_mgm_r), FUNC(apollo_graphics_15i::apollo_mgm_w));
849
850 map(0x05e800, 0x05ec07).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_ccr_r), FUNC(apollo_graphics_15i::apollo_ccr_w));
851 map(0x0a0000, 0x0bffff).rw(m_graphics, FUNC(apollo_graphics_15i::apollo_cgm_r), FUNC(apollo_graphics_15i::apollo_cgm_w));
852
853 // map(0x03020000, 0x0303ffff) Cache Tag Store (DN4500 only)
854 // map(0x04000000, 0x0400ffff) Cache Tag Data (DN4500 only)
855 map(0x07000000, 0x0700FFFF).rw(FUNC(apollo_state::dn5500_io_protection_map_r), FUNC(apollo_state::dn5500_io_protection_map_w));
856 // map(0x0e000000, 0x0fffffff) FPA address space
857
858 // map(0xf8000000, 0xffffffff).rw(FUNC(apollo_state::apollo_f8_r), FUNC(apollo_state::apollo_f8_w));
859 }
860
dsp5500_map(address_map & map)861 void apollo_state::dsp5500_map(address_map &map)
862 {
863 map(0x00000000, 0xffffffff).rw(FUNC(apollo_state::apollo_unmapped_r), FUNC(apollo_state::apollo_unmapped_w));
864 map(0x000000, 0x00ffff).rom(); /* boot ROM */
865 map(0x000000, 0x00ffff).w(FUNC(apollo_state::apollo_rom_w));
866 map(0x010000, 0x0100ff).rw(FUNC(apollo_state::apollo_csr_status_register_r), FUNC(apollo_state::apollo_csr_status_register_w));
867 map(0x010100, 0x0101ff).rw(FUNC(apollo_state::apollo_csr_control_register_r), FUNC(apollo_state::apollo_csr_control_register_w));
868 map(0x010200, 0x0102ff).rw(FUNC(apollo_state::cache_status_register_r), FUNC(apollo_state::cache_control_register_w));
869 map(0x010300, 0x0103ff).rw(FUNC(apollo_state::task_alias_register_r), FUNC(apollo_state::task_alias_register_w));
870 map(0x010400, 0x0104ff).rw(m_sio, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
871 map(0x010500, 0x0105ff).rw(m_sio2, FUNC(apollo_sio::read), FUNC(apollo_sio::write));
872 map(0x010800, 0x0108ff).rw(m_ptm, FUNC(ptm6840_device::read), FUNC(ptm6840_device::write)).umask32(0x00ff00ff);
873 map(0x010900, 0x0109ff).rw(FUNC(apollo_state::apollo_rtc_r), FUNC(apollo_state::apollo_rtc_w));
874 map(0x010c00, 0x010cff).rw(FUNC(apollo_state::/*"dma1",*/apollo_dma_1_r), FUNC(apollo_state::apollo_dma_1_w));
875 map(0x010d00, 0x010dff).rw(FUNC(apollo_state::/*"dma2",*/apollo_dma_2_r), FUNC(apollo_state::apollo_dma_2_w));
876 map(0x011000, 0x0110ff).rw(m_pic8259_master, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
877 map(0x011100, 0x0111ff).rw(m_pic8259_slave, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
878 map(0x011200, 0x0112ff).rw(m_node_id, FUNC(apollo_ni::read), FUNC(apollo_ni::write));
879 map(0x011300, 0x0113ff).rw(FUNC(apollo_state::latch_page_on_parity_error_register_r), FUNC(apollo_state::latch_page_on_parity_error_register_w));
880 map(0x011400, 0x0114ff).rw(FUNC(apollo_state::dn5500_memory_present_register_r), FUNC(apollo_state::dn5500_memory_present_register_w));
881 map(0x011500, 0x0115ff).rw(FUNC(apollo_state::dn5500_11500_r), FUNC(apollo_state::dn5500_11500_w));
882 map(0x011600, 0x0116ff).rw(FUNC(apollo_state::master_req_register_r), FUNC(apollo_state::master_req_register_w));
883
884 map(0x016400, 0x0164ff).rw(FUNC(apollo_state::selective_clear_locations_r), FUNC(apollo_state::selective_clear_locations_w));
885 map(0x017000, 0x017fff).rw(FUNC(apollo_state::apollo_address_translation_map_r), FUNC(apollo_state::apollo_address_translation_map_w));
886
887 map(ATBUS_IO_BASE, ATBUS_IO_END).rw(FUNC(apollo_state::apollo_atbus_io_r), FUNC(apollo_state::apollo_atbus_io_w));
888 map(ATBUS_MEMORY_BASE, ATBUS_MEMORY_END).rw(FUNC(apollo_state::apollo_atbus_memory_r), FUNC(apollo_state::apollo_atbus_memory_w));
889
890 // FIXME: must match with RAM size in driver/apollo_sio.c
891 map(DN5500_RAM_BASE, DN5500_RAM_END).ram().w(FUNC(apollo_state::ram_with_parity_w)).share(RAM_TAG);
892
893 map(0x07000000, 0x0700FFFF).rw(FUNC(apollo_state::dn5500_io_protection_map_r), FUNC(apollo_state::dn5500_io_protection_map_w));
894 // map(0xf8000000, 0xffffffff).rw(FUNC(apollo_state::apollo_f8_r), FUNC(apollo_state::apollo_f8_w));
895 }
896
897 /***************************************************************************
898 Machine Reset
899 ***************************************************************************/
900
machine_reset()901 void apollo_state::machine_reset()
902 {
903 MLOG1(("machine_reset"));
904
905 MACHINE_RESET_CALL_MEMBER(apollo);
906
907 #ifdef APOLLO_XXL
908 // set configuration
909 omti8621_device::set_verbose(apollo_config(APOLLO_CONF_DISK_TRACE));
910 #endif
911
912 if (apollo_config(APOLLO_CONF_NODE_ID))
913 {
914 // set node ID from UID of logical volume 1 of logical unit 0
915 m_node_id->set_node_id_from_disk();
916 }
917
918 #if 0
919 m_maincpu->set_instruction_hook(read32sm_delegate(*this, FUNC(apollo_state::apollo_instruction_hook)));
920 #endif
921 }
922
WRITE_LINE_MEMBER(apollo_state::apollo_reset_instr_callback)923 WRITE_LINE_MEMBER(apollo_state::apollo_reset_instr_callback)
924 {
925 MLOG1(("apollo_reset_instr_callback"));
926
927 // reset the CPU board devices
928 MACHINE_RESET_CALL_MEMBER(apollo);
929
930 // reset the ISA bus devices
931 m_isa->reset();
932
933 if (!apollo_is_dsp3x00())
934 {
935 m_graphics->reset();
936 m_keyboard->reset();
937 #ifdef APOLLO_XXL
938 m_sio2->reset();
939 #endif
940 }
941 }
942
943 /***************************************************************************
944 Machine Start
945 ***************************************************************************/
946
machine_start()947 void apollo_state::machine_start(){
948 memory_share *messram = memshare(RAM_TAG);
949 //MLOG1(("machine_start_dn3500: ram size is %d MB", (int)messram->bytes()/(1024*1024)));
950
951 // clear ram
952 memset(messram->ptr(), 0x55, messram->bytes());
953
954 MACHINE_START_CALL_MEMBER(apollo);
955
956 // install nop handlers for unmapped ISA bus addresses
957 m_isa->install16_device((ATBUS_IO_BASE - 0x40000) >> 7, (ATBUS_IO_END - 0x40000) >> 7, read16s_delegate(*this, FUNC(apollo_state::apollo_atbus_unmap_io_r)), write16s_delegate(*this, FUNC(apollo_state::apollo_atbus_unmap_io_w)));
958 m_isa->install_memory(0, ATBUS_MEMORY_END, read8s_delegate(*this, FUNC(apollo_state::apollo_atbus_unmap_r)), write8s_delegate(*this, FUNC(apollo_state::apollo_atbus_unmap_w)));
959 }
960
961 /***************************************************************************
962 Driver Init
963 ***************************************************************************/
964
init_dn3500()965 void apollo_state::init_dn3500()
966 {
967 // MLOG1(("driver_init_dn3500"));
968
969 /* hook the RESET line, which resets a slew of other components */
970 m_maincpu->set_reset_callback(*this, FUNC(apollo_state::apollo_reset_instr_callback));
971
972 ram_base_address = DN3500_RAM_BASE;
973 ram_end_address = DN3500_RAM_END;
974
975 node_type= NODE_TYPE_DN3500;
976 ram_config_byte= DN3500_RAM_CONFIG_BYTE;
977
978 init_apollo();
979 }
980
init_dsp3500()981 void apollo_state::init_dsp3500()
982 {
983 init_dn3500();
984 // MLOG1(("driver_init_dsp3500"));
985 node_type = NODE_TYPE_DSP3500;
986 }
987
init_dn3000()988 void apollo_state::init_dn3000()
989 {
990 init_dn3500();
991 // MLOG1(("driver_init_dn3000"));
992
993 ram_base_address = DN3000_RAM_BASE;
994 ram_end_address = DN3000_RAM_END;
995
996 node_type = NODE_TYPE_DN3000;
997 ram_config_byte= DN3000_RAM_CONFIG_8MB;
998 }
999
init_dsp3000()1000 void apollo_state::init_dsp3000()
1001 {
1002 init_dn3000();
1003 // MLOG1(("driver_init_dsp3000"));
1004 node_type = NODE_TYPE_DSP3000;
1005 }
1006
init_dn5500()1007 void apollo_state::init_dn5500()
1008 {
1009 init_dn3500();
1010 // MLOG1(("driver_init_dn5500"));
1011
1012 ram_base_address = DN5500_RAM_BASE;
1013 ram_end_address = DN5500_RAM_END;
1014
1015 node_type = NODE_TYPE_DN5500;
1016 ram_config_byte= DN5500_RAM_CONFIG_BYTE;
1017 }
1018
init_dsp5500()1019 void apollo_state::init_dsp5500()
1020 {
1021 init_dn5500();
1022 // MLOG1(("driver_init_dsp5500"));
1023 node_type = NODE_TYPE_DSP5500;
1024 }
1025
1026 /***************************************************************************
1027 Input Ports
1028 ***************************************************************************/
1029
1030 static INPUT_PORTS_START( dn3500 )
PORT_INCLUDE(apollo_config)1031 PORT_INCLUDE(apollo_config)
1032 INPUT_PORTS_END
1033
1034 static INPUT_PORTS_START( dsp3500 )
1035 PORT_INCLUDE(apollo_config)
1036 INPUT_PORTS_END
1037
1038 READ_LINE_MEMBER( apollo_state::apollo_kbd_is_german )
1039 {
1040 return (apollo_config(APOLLO_CONF_GERMAN_KBD) != 0) ? ASSERT_LINE : CLEAR_LINE;
1041 }
1042
1043 /***************************************************************************
1044 MACHINE DRIVERS
1045 ***************************************************************************/
1046
dn3500(machine_config & config)1047 void apollo_state::dn3500(machine_config &config)
1048 {
1049 /* basic machine hardware */
1050 M68030(config, m_maincpu, 25000000); /* 25 MHz 68030 */
1051 m_maincpu->set_addrmap(AS_PROGRAM, &apollo_state::dn3500_map);
1052 m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &apollo_state::cpu_space_map);
1053
1054 config.set_maximum_quantum(attotime::from_hz(60));
1055
1056 apollo(config);
1057
1058 /* internal ram */
1059 RAM(config, m_ram).set_default_size("8M").set_extra_options("4M,8M,16M,32M");
1060
1061 #ifdef APOLLO_XXL
1062 apollo_stdio_device &stdio(APOLLO_STDIO(config, APOLLO_STDIO_TAG, 0));
1063 stdio.tx_cb().set(m_sio, FUNC(apollo_sio::rx_b_w));
1064 #endif
1065 }
1066
dsp3500(machine_config & config)1067 void apollo_state::dsp3500(machine_config &config)
1068 {
1069 M68030(config, m_maincpu, 25000000); /* 25 MHz 68030 */
1070 m_maincpu->set_addrmap(AS_PROGRAM, &apollo_state::dsp3500_map);
1071 m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &apollo_state::cpu_space_map);
1072 config.set_maximum_quantum(attotime::from_hz(60));
1073
1074 apollo_terminal(config);
1075
1076 /* internal ram */
1077 RAM(config, RAM_TAG).set_default_size("8M").set_extra_options("4M,8M,16M,32M");
1078
1079 /* terminal hardware */
1080 config.set_default_layout(layout_apollo_dsp);
1081 }
1082
dn3500_19i(machine_config & config)1083 void apollo_state::dn3500_19i(machine_config &config)
1084 {
1085 dn3500(config);
1086 /* video hardware 19" monochrome */
1087 APOLLO_MONO19I(config, m_graphics, 0);
1088 APOLLO_KBD(config, m_keyboard, 0);
1089 m_keyboard->tx_cb().set(m_sio, FUNC(apollo_sio::rx_a_w));
1090 m_keyboard->german_cb().set(FUNC(apollo_state::apollo_kbd_is_german));
1091 }
1092
dn3500_15i(machine_config & config)1093 void apollo_state::dn3500_15i(machine_config &config)
1094 {
1095 dn3500(config);
1096 /* video hardware is 15" monochrome or color */
1097 APOLLO_GRAPHICS(config, m_graphics, 0);
1098 APOLLO_KBD(config, m_keyboard, 0);
1099 m_keyboard->tx_cb().set(m_sio, FUNC(apollo_sio::rx_a_w));
1100 m_keyboard->german_cb().set(FUNC(apollo_state::apollo_kbd_is_german));
1101 }
1102
dn3000(machine_config & config)1103 void apollo_state::dn3000(machine_config &config)
1104 {
1105 dn3500(config);
1106 M68020PMMU(config.replace(), m_maincpu, 12000000); /* 12 MHz */
1107 m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &apollo_state::cpu_space_map);
1108 m_maincpu->set_addrmap(AS_PROGRAM, &apollo_state::dn3000_map);
1109 config.device_remove( APOLLO_SIO2_TAG );
1110 m_ram->set_default_size("8M").set_extra_options("4M");
1111
1112 // FIXME: is this interrupt really only connected on DN3000?
1113 m_rtc->irq().set(FUNC(apollo_state::apollo_rtc_irq_function));
1114 }
1115
dsp3000(machine_config & config)1116 void apollo_state::dsp3000(machine_config &config)
1117 {
1118 M68020PMMU(config, m_maincpu, 12000000); /* 12 MHz */
1119 m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &apollo_state::cpu_space_map);
1120 m_maincpu->set_addrmap(AS_PROGRAM, &apollo_state::dsp3000_map);
1121 config.set_maximum_quantum(attotime::from_hz(60));
1122
1123 apollo_terminal(config);
1124
1125 /* internal ram */
1126 RAM(config, m_ram).set_default_size("8M").set_extra_options("4M");
1127
1128 config.device_remove( APOLLO_SIO2_TAG );
1129
1130 /* terminal hardware */
1131 config.set_default_layout(layout_apollo_dsp);
1132 }
1133
dn3000_19i(machine_config & config)1134 void apollo_state::dn3000_19i(machine_config &config)
1135 {
1136 dn3000(config);
1137 /* video hardware 19" monochrome */
1138 APOLLO_MONO19I(config, m_graphics, 0);
1139 APOLLO_KBD(config, m_keyboard, 0);
1140 m_keyboard->tx_cb().set(m_sio, FUNC(apollo_sio::rx_a_w));
1141 m_keyboard->german_cb().set(FUNC(apollo_state::apollo_kbd_is_german));
1142 }
1143
dn3000_15i(machine_config & config)1144 void apollo_state::dn3000_15i(machine_config &config)
1145 {
1146 dn3000(config);
1147 /* video hardware 15" monochrome */
1148 APOLLO_GRAPHICS(config, m_graphics, 0);
1149 APOLLO_KBD(config, m_keyboard, 0);
1150 m_keyboard->tx_cb().set(m_sio, FUNC(apollo_sio::rx_a_w));
1151 m_keyboard->german_cb().set(FUNC(apollo_state::apollo_kbd_is_german));
1152 }
1153
dn5500(machine_config & config)1154 void apollo_state::dn5500(machine_config &config)
1155 {
1156 dn3500(config);
1157 M68040(config.replace(), m_maincpu, 25000000); /* 25 MHz */
1158 m_maincpu->set_addrmap(AS_PROGRAM, &apollo_state::dn5500_map);
1159 }
1160
dsp5500(machine_config & config)1161 void apollo_state::dsp5500(machine_config &config)
1162 {
1163 M68040(config, m_maincpu, 25000000); /* 25 MHz */
1164 m_maincpu->set_addrmap(AS_PROGRAM, &apollo_state::dsp5500_map);
1165 m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &apollo_state::cpu_space_map);
1166 config.set_maximum_quantum(attotime::from_hz(60));
1167
1168 apollo_terminal(config);
1169
1170 /* internal ram */
1171 // FIXME: guess, to fix validation
1172 RAM(config, RAM_TAG).set_default_size("8M").set_extra_options("4M,8M,16M,32M");
1173
1174 /* terminal hardware */
1175 config.set_default_layout(layout_apollo_dsp);
1176 }
1177
dn5500_19i(machine_config & config)1178 void apollo_state::dn5500_19i(machine_config &config)
1179 {
1180 dn5500(config);
1181 /* video hardware 19" monochrome */
1182 APOLLO_MONO19I(config, m_graphics, 0);
1183 APOLLO_KBD(config, m_keyboard, 0);
1184 m_keyboard->tx_cb().set(m_sio, FUNC(apollo_sio::rx_a_w));
1185 m_keyboard->german_cb().set(FUNC(apollo_state::apollo_kbd_is_german));
1186 }
1187
dn5500_15i(machine_config & config)1188 void apollo_state::dn5500_15i(machine_config &config)
1189 {
1190 dn5500(config);
1191 /* video hardware 15" monochrome */
1192 APOLLO_GRAPHICS(config, m_graphics, 0);
1193 APOLLO_KBD(config, m_keyboard, 0);
1194 m_keyboard->tx_cb().set(m_sio, FUNC(apollo_sio::rx_a_w));
1195 m_keyboard->german_cb().set(FUNC(apollo_state::apollo_kbd_is_german));
1196 }
1197
1198 /***************************************************************************
1199 ROM Definitions
1200 ***************************************************************************/
1201
1202 ROM_START( dn3500 )
1203 // dn3500 boot ROM (Note: use sha1sum -b <rom file>)
1204 ROM_REGION( 0x0100000, MAINCPU, 0 ) /* 68000 code */
1205
1206 // http://www.bitsavers.org/bits/Apollo/firmware/3500_BOOT_12191_7.bin
1207 // Note: file name must be converted to lower case (i.e. 3500_boot_12191_7.bin)
1208 // Note: this duplicates boot rom md7c-rev-8.00-1989-08-16-17-23-52.bin
1209 ROM_SYSTEM_BIOS( 0, "md7c-rev-8.00", "MD7C REV 8.00, 1989/08/16.17:23:52" )
1210 ROMX_LOAD( "3500_boot_12191_7.bin", 0x00000, 0x10000, CRC(3132067d) SHA1(36f3c83d9f2df42f2537b09ca2f051a8c9dfbfc2) , ROM_BIOS(0) )
1211 ROM_END
1212
1213 ROM_START( dn5500 )
1214 // dn5500 boot ROM (Note: use sha1sum -b <rom file>)
1215 ROM_REGION( 0x0100000, MAINCPU, 0 ) /* 68000 code */
1216
1217 ROM_SYSTEM_BIOS( 0, "md7c-rev-8.00", "MD7C REV 8.00, 1989/08/16.17:23:52" )
1218 ROMX_LOAD( "5500_boot_a1631-80046_1-30-92.bin", 0x00000, 0x10000, CRC(7b9ed610) SHA1(7315a884ec4551c44433c6079cc06509223cb02b) , ROM_BIOS(0) )
1219 ROM_END
1220
1221 ROM_START( dn3000)
1222 ROM_REGION( 0x0090000, MAINCPU, 0 ) /* 68000 code */
1223
1224 ROM_SYSTEM_BIOS( 0, "md8-rev-7.0", "MD8 REV 7.0, 1988/08/16.15:14:39" )
1225 ROMX_LOAD( "3000_boot_8475_7.bin", 0x00000, 0x08000, CRC(0fe2d471) SHA1(6c383d2266719a3d069b7bf015f6945179395e7a), ROM_BIOS(0) )
1226 ROM_END
1227
1228 #define rom_dsp3500 rom_dn3500
1229 #define rom_dn3500_15i rom_dn3500
1230 #define rom_dn3500_19i rom_dn3500
1231
1232 #define rom_dsp3000 rom_dn3000
1233 #define rom_dn3000_19i rom_dn3000
1234
1235 #define rom_dsp5500 rom_dn5500
1236 #define rom_dn5500_15i rom_dn5500
1237 #define rom_dn5500_19i rom_dn5500
1238
1239 /***************************************************************************
1240 GAME DRIVERS
1241 ***************************************************************************/
1242
1243 #define DN_FLAGS 0
1244 #define DSP_FLAGS 0
1245 //#define DSP_FLAGS MACHINE_NO_SOUND
1246
1247 /* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
1248 COMP( 1989, dn3500, 0, 0, dn3500_15i, dn3500, apollo_state, init_dn3500, "Apollo", "Apollo DN3500", DN_FLAGS )
1249 COMP( 1989, dsp3500, dn3500, 0, dsp3500, dsp3500, apollo_state, init_dsp3500, "Apollo", "Apollo DSP3500", DSP_FLAGS )
1250 COMP( 1989, dn3500_19i, dn3500, 0, dn3500_19i, dn3500, apollo_state, init_dn3500, "Apollo", "Apollo DN3500 19\" Monochrome", DN_FLAGS )
1251
1252 COMP( 1988, dn3000, dn3500, 0, dn3000_15i, dn3500, apollo_state, init_dn3000, "Apollo", "Apollo DN3000", DN_FLAGS )
1253 COMP( 1988, dsp3000, dn3500, 0, dsp3000, dsp3500, apollo_state, init_dsp3000, "Apollo", "Apollo DSP3000", DSP_FLAGS )
1254 COMP( 1988, dn3000_19i, dn3500, 0, dn3000_19i, dn3500, apollo_state, init_dn3000, "Apollo", "Apollo DN3000 19\" Monochrome", DN_FLAGS )
1255
1256 COMP( 1991, dn5500, dn3500, 0, dn5500_15i, dn3500, apollo_state, init_dn5500, "Apollo", "Apollo DN5500", MACHINE_NOT_WORKING )
1257 COMP( 1991, dsp5500, dn3500, 0, dsp5500, dsp3500, apollo_state, init_dsp5500, "Apollo", "Apollo DSP5500", MACHINE_NOT_WORKING )
1258 COMP( 1991, dn5500_19i, dn3500, 0, dn5500_19i, dn3500, apollo_state, init_dn5500, "Apollo", "Apollo DN5500 19\" Monochrome", MACHINE_NOT_WORKING )
1259