1 // license:BSD-3-Clause 2 // copyright-holders:Patrick Mackinlay 3 4 #ifndef MAME_VIDEO_SGI_GR1_H 5 #define MAME_VIDEO_SGI_GR1_H 6 7 #pragma once 8 9 #include "machine/bankdev.h" 10 #include "screen.h" 11 #include "video/sgi_ge5.h" 12 #include "video/sgi_re2.h" 13 #include "video/sgi_xmap2.h" 14 #include "video/bt45x.h" 15 #include "video/bt431.h" 16 17 class sgi_gr1_device : public device_t 18 { 19 public: 20 sgi_gr1_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock = 0); 21 imperfect_features()22 static constexpr feature_type imperfect_features() { return feature::GRAPHICS; } 23 24 // configuration out_vblank()25 auto out_vblank() { return subdevice<screen_device>("screen")->screen_vblank(); } out_int()26 auto out_int() { return subdevice<sgi_ge5_device>("ge5")->out_int(); } out_int_fifo()27 auto out_int_fifo() { return m_int_fifo_cb.bind(); } 28 dma_r()29 u32 dma_r() { return subdevice<sgi_ge5_device>("ge5")->buffer_r(0); } dma_w(u32 data)30 void dma_w(u32 data) { fifo_w(0, data, 0xffffffffU); } 31 32 void reset_w(int state); 33 34 void map(address_map &map); 35 36 protected: 37 void map_bank(address_map& map); 38 39 // device_t overrides 40 virtual ioport_constructor device_input_ports() const override; 41 virtual void device_add_mconfig(machine_config &config) override; 42 virtual void device_start() override; 43 virtual void device_reset() override; 44 45 // display registers 46 u8 dr0_r(); 47 u8 dr1_r(); 48 u8 dr2_r(); 49 u8 dr3_r(); 50 u8 dr4_r(); 51 void dr0_w(u8 data); 52 void dr1_w(u8 data); 53 void dr2_w(u8 data); 54 void dr3_w(u8 data); 55 void dr4_w(u8 data); 56 57 u64 fifo_r(); 58 void fifo_w(offs_t offset, u32 data, u32 mem_mask); 59 60 private: 61 required_device<address_map_bank_device> m_bank; 62 required_device<screen_device> m_screen; 63 required_device<sgi_ge5_device> m_ge; 64 required_device<sgi_re2_device> m_re; 65 required_device_array<sgi_xmap2_device, 5> m_xmap; 66 required_device_array<bt431_device, 2> m_cursor; 67 required_device_array<bt457_device, 3> m_ramdac; 68 69 devcb_write_line m_int_fifo_cb; 70 71 enum dr0_mask : u8 72 { 73 DR0_GRF1EN = 0x01, // grf1 board enable (active low, disable for RE2) 74 DR0_PGRINBIT = 0x02, // reflects PGROUTBIT (PGR) 75 DR0_PGROUTBIT = 0x04, // routed to PGRINBIT (PGR) 76 DR0_ZBUF0 = 0x08, // mzb1 card is installed (active low, ro, MGR) 77 DR0_SMALLMON0 = 0x08, // small monitor installed (active low, non-MGR) 78 79 DR0_WM = 0xf7, // write mask 80 }; 81 enum dr1_mask : u8 82 { 83 DR1_SE = 0x01, // sync on green enable (active low, rw) 84 DR1_CWEN = 0x02, // wtl3132 cwen- 85 DR1_VRLS = 0x04, // vertical retrace latency select 86 DR1_MTYPE = 0x06, // monitor type msb (rw) 87 DR1_TURBO = 0x08, // turbo option installed (active low, ro) 88 DR1_OVERLAY0A = 0x10, // dac overlay bit 0 bank a (ro) 89 90 DR1_WM = 0xe7, // write mask 91 }; 92 enum dr2_mask : u8 93 { 94 DR2_SCREENON = 0x01, // standby (rw) 95 DR2_UNCOM2 = 0x02, // uncomitted bit to xilinx 96 DR2_LEDOFF = 0x04, // disable led 97 DR2_BITPLANES = 0x08, // extra bitplanes installed (active low, ro) 98 DR2_ZBUF = 0x10, // z-buffer installed (active low, non-MGR, ro) 99 100 DR2_WM = 0xe7, // write mask 101 }; 102 enum dr3_mask : u8 103 { 104 DR3_GENSTATEN = 0x01, // enable genlock status out 105 DR3_LSBBLUEOUT = 0x01, // latch blue lsb out (VGR only) 106 DR3_LCARESET = 0x02, // reset xilinx lca (active low, rw) 107 DR3_MONITORRESET = 0x04, // reset monitor type (rw) 108 DR3_FIFOEMPTY = 0x08, // fifo empty (active low, ro) 109 DR3_FIFOFULL = 0x10, // fifo half full (active low, ro) 110 111 DR3_WM = 0xe7, // write mask 112 }; 113 enum dr4_mask : u8 114 { 115 DR4_MONITORMASK = 0x03, // monitor type lsb (rw) 116 DR4_EXTCLKSEL = 0x04, // select external pixel clock (rw) 117 DR4_MEGOPT = 0x08, // 1M video rams installed (ro) 118 DR4_GESTALL = 0x10, // ge stalled (active low, ro) 119 DR4_ACLKEN = 0x20, // asynchronous clock enabled (wo) 120 DR4_SCLKEN = 0x40, // synchronous clock enabled (wo) 121 DR4_MS = 0x80, // select upper 4K color map (rw) 122 123 DR4_RM = 0x9f, // read mask 124 DR4_WM = 0xe7, // write mask 125 }; 126 127 u8 m_dr0; 128 u8 m_dr1; 129 u8 m_dr2; 130 u8 m_dr3; 131 u8 m_dr4; 132 133 util::fifo<u64, 512> m_fifo; 134 135 bool m_reset; 136 }; 137 138 DECLARE_DEVICE_TYPE(SGI_GR1, sgi_gr1_device) 139 140 #endif // MAME_VIDEO_SGI_GR1_H 141