1 // license:BSD-3-Clause
2 // copyright-holders:Sandro Ronco
3 // thanks-to:rfka01
4 /*********************************************************************
5
6 NCR Decision mate slot bus and module emulation
7
8 From the NCR System Technical manual:
9
10 "The lower part of the controller board contains the I/0 bus together with
11 seven user-accessible connectors. These connectors are identified on the board
12 as J1 through J7 (reading from left to right), and correspond to the seven slots
13 (numbers 1 through 7) at the rear of the cabinet.
14 Position J1 is reserved for the connection of any one of the memory expansion modules
15 (K200, K202, K208).
16 Position J7 is reserved for the connection of either the diagnostic module (K220),
17 or the customer-installable 16-bit processor module (K231).
18 Positions J2 through J6 are the general purpose slots for the connection of the peripheral
19 adapter and other interfaces to the computer. These five positions are identical, and Figure 2.2
20 defines the type of connector, while the pin assignments are shown in Figure 2.3."
21
22 Pinout (/ indicates an inverted signal, ie, one that would have a bar over it
23 on a schematic diagram)
24
25 a c
26 |-------------------------|
27 |+5V 1 +5 V |
28 | |
29 | 2 +12 V |
30 | |
31 System Reset Output, act. low |RESET/ 3 RESET IN/| active low, general system RESET
32 | |
33 I/O Write |IOW/ 4 IOR/ | I/O read R/W lines are Processor control lines
34 | |
35 Memory Write |MEMW/ 5 MEMR/ | Memory read active low, Tri-State possible
36 | |
37 BD0-BD7: Switch by IFSEL |BD1 6 BDO | BD0 - BD7: Data-Bus lines (8 bit)
38 (I/O-Read). Normal Output. | | bidirectional, active high
39 |BD3 7 BD2 |
40 | |
41 Direction can be changed |BD5 8 BD4 | Bus-Driver to peripheral Bus (LS245)
42 by DIR/ signal. | | automatic detection
43 |BD7 9 BD6 |
44 | |
45 Ready Signal from the |READY DMA 10 ABTRI / | Address Bus Tri-State, active low signal
46 mem. contr. (XACK), act. hi. | |
47 End of Process-EOP signals that|EOP/ 11 | cf. 8234A-6 spec.
48 DMA service has been completed | |
49 |INTACK/ 12 IFSEL 4/ |
50 | |
51 Change peripheral from board |AUTO/ 13 DIR/ | Direction of the databus driver. Low signal
52 type 1 to 2.NC on type 1 | | change to input.
53 Test Hold. External request |THOLD/ 14 HLDA | Hold Acknowledge. A response from the Z80
54 to set the Z80 in hold state. | | The Z80 CPU is in hold state, active high.
55 Processor-Clock: inverse signal|PCLK/ 15 CLK1 | Clock Output 1 MHz
56 of the CPU clock, freq. 4MHz | |
57 Logic Ground |LGRD 16 TRAMD/ | Test RAM-Disable. For ext. ROM or RAM expansion.
58 | | Switching with the System RAM, RAM output disabled. act. low
59 |BA19 17 BA18 | BA0-BA19: Buffered 20bit Address Bus
60 | |
61 |BA17 18 BA16 |
62 | |
63 |BA15 19 BA14 | Range to 1MB Normal output, active high
64 | |
65 |BA13 20 BA12 |
66 | |
67 |BA11 21 BA10 | Tri-State possible with ABTRI/ signal
68 | |
69 |BA9 22 BA8 |
70 | |
71 |BA7 23 BA6 |
72 | |
73 |BA5 24 BA4 |
74 | |
75 |BA3 25 BA2 |
76 | |
77 |BA1 26 BAO |
78 | |
79 IFSEL 0-4, active low |IFSEL3/ 27 IFSEL2/ | The select of the I/O pprts in the peripherals is made
80 The interface does not need | | by any IFSEL and BA3 (BA3/). (10 peripherals). Automatic
81 own address decoder |IFSEL1/ 28 IFSELO/ | change of the data bus direction. This change is not possible
82 | | while a dma function is performed
83 DRQ0-DRQ1: DMA Request for |DRQ1 29 DRQ0 | Asynchr. channel requests are used by peripherals
84 resp. channels, act. high | | to request DMA service
85 DACK0-DACK1: |DACK1 / 30 DACK0/ | DMA-Acknowledge Channels 0 and 1, active low
86 | | These lines indicate an active DMA channel
87 |WAIT/ 31 INT/ |
88 | |
89 Logic Ground |LGRD 32 LGRD | Logic Ground
90 |-------------------------|
91
92 Two additional plug/socket connections are possible on the bus. These are made on the solder side of the controller board
93 and are designated J2A and J7 A. These connectors are not considered to be user accessible , rather for factory use ,
94 or for use by field engineers and system integrators. Normally, these two connectors are used for:
95 ??? J2A - The connection of the fixed disk interface board, or a custom design board.
96 ??? J7A - The connection of the 16-bit processor board (factory option and kit K230).
97
98 The processor and diagnostics module for Slots J7 and J7A have the following additional signals in addition to the ones present on Slots J2-J6.
99 Note that the middle row of the connector (row "b") carries some signals too:
100
101 A2 - OPT 2
102 Signals A19-A26 and C19-C26 are called e.g. A7 instead of BA7 in the processor module schematic (fig. 2.14, page 2.21 System Technical Manual Hardware)
103 Signals A6-A9 and C6-D9 are called e.g. D4 instead of BD4 in the processor module schematic
104 B10 - READYP
105 B11 - HOLD
106 B12 - SWITCH 16/
107 B13 - HLDA 16
108 B14 - 16 BITAV
109 B15 - STDMARQ
110 B16 - LGRD
111 B17 - 16 BITSET/
112 B20 - MEMRQ/
113 B32 - LGRD
114
115 The memory modules on J1 share the same physical connector with the other expansion modules, but carry different signals:
116
117 A1 - +5V C1 - +5V
118 A2 C2
119 A3 - AOUT7 C3
120 A4 - AOUT6 C4 - AOUT5
121 A5 - AOUT4 C5 - AOUT3
122 A6 C6
123 A7 C7
124 A8 C8
125 A9 C9
126 A10 C10 - AOUT2
127 A11 C11 - AOUT1
128 A12 - OD0 C12 - AOUT0
129 A13 - OD1 C13 - OD2
130 A14 - OD3 C14
131 A15 C15
132 A16 - LGRD C16 - LGRD
133 A17 C17
134 A18 C18
135 A19 - ID0 C19
136 A20 - ID1 C20
137 A21 - ID2 C21
138 A22 - ID3 C22
139 A23 - ID4 C23 - CAS7/
140 A24 - ID5 C24 - CAS6/
141 A25 - ID6 C25 - CAS5/
142 A26 - ID7 C26 - CAS4/
143 A27 - CAS2/ C27 - CAS1/
144 A28 - CAS3/ C28
145 A29 - OD4 C29 - OD5
146 A30 - RAS/ C30 - WE/
147 A31 - OD6 C31 - OD7
148 A32 - LGRD C32 - LGRD
149
150
151 ***************************************************************************/
152
153
154 #include "emu.h"
155 #include "dmvbus.h"
156
157
158 /***************************************************************************
159 PARAMETERS
160 ***************************************************************************/
161
162 //**************************************************************************
163 // GLOBAL VARIABLES
164 //**************************************************************************
165
166 DEFINE_DEVICE_TYPE(DMVCART_SLOT, dmvcart_slot_device, "dmvcart_slot", "Decision Mate V cartridge slot")
167
168 //**************************************************************************
169 // DMV cartridge interface
170 //**************************************************************************
171
172 //-------------------------------------------------
173 // device_dmvslot_interface - constructor
174 //-------------------------------------------------
175
device_dmvslot_interface(const machine_config & mconfig,device_t & device)176 device_dmvslot_interface::device_dmvslot_interface(const machine_config &mconfig, device_t &device) :
177 device_interface(device, "dmvbus"),
178 m_bus(dynamic_cast<dmvcart_slot_device *>(device.owner()))
179 {
180 }
181
182
183 //-------------------------------------------------
184 // ~device_dmvslot_interface - destructor
185 //-------------------------------------------------
186
~device_dmvslot_interface()187 device_dmvslot_interface::~device_dmvslot_interface()
188 {
189 }
190
191
192 //**************************************************************************
193 // LIVE DEVICE
194 //**************************************************************************
195
196 //-------------------------------------------------
197 // dmvcart_slot_device - constructor
198 //-------------------------------------------------
dmvcart_slot_device(const machine_config & mconfig,const char * tag,device_t * owner,uint32_t clock)199 dmvcart_slot_device::dmvcart_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
200 device_t(mconfig, DMVCART_SLOT, tag, owner, clock),
201 device_single_card_slot_interface<device_dmvslot_interface>(mconfig, *this),
202 m_prog_read_cb(*this),
203 m_prog_write_cb(*this),
204 m_out_int_cb(*this),
205 m_out_irq_cb(*this),
206 m_out_thold_cb(*this),
207 m_memspace(*this, finder_base::DUMMY_TAG, -1),
208 m_iospace(*this, finder_base::DUMMY_TAG, -1),
209 m_cart(nullptr)
210 {
211 }
212
213
214 //-------------------------------------------------
215 // dmvcart_slot_device - destructor
216 //-------------------------------------------------
217
~dmvcart_slot_device()218 dmvcart_slot_device::~dmvcart_slot_device()
219 {
220 }
221
222 //-------------------------------------------------
223 // device_start - device-specific startup
224 //-------------------------------------------------
225
device_start()226 void dmvcart_slot_device::device_start()
227 {
228 m_cart = get_card_device();
229
230 // resolve callbacks
231 m_prog_read_cb.resolve_safe(0);
232 m_prog_write_cb.resolve_safe();
233 m_out_int_cb.resolve_safe();
234 m_out_irq_cb.resolve_safe();
235 m_out_thold_cb.resolve_safe();
236 }
237
238 /*-------------------------------------------------
239 read
240 -------------------------------------------------*/
241
read(offs_t offset,uint8_t & data)242 bool dmvcart_slot_device::read(offs_t offset, uint8_t &data)
243 {
244 if (m_cart)
245 return m_cart->read(offset, data);
246 return false;
247 }
248
249 /*-------------------------------------------------
250 write
251 -------------------------------------------------*/
252
write(offs_t offset,uint8_t data)253 bool dmvcart_slot_device::write(offs_t offset, uint8_t data)
254 {
255 if (m_cart)
256 return m_cart->write(offset, data);
257 return false;
258 }
259
260 /*-------------------------------------------------
261 read
262 -------------------------------------------------*/
263
ram_read(uint8_t cas,offs_t offset,uint8_t & data)264 void dmvcart_slot_device::ram_read(uint8_t cas, offs_t offset, uint8_t &data)
265 {
266 if (m_cart)
267 m_cart->ram_read(cas, offset, data);
268 }
269
270 /*-------------------------------------------------
271 write
272 -------------------------------------------------*/
273
ram_write(uint8_t cas,offs_t offset,uint8_t data)274 void dmvcart_slot_device::ram_write(uint8_t cas, offs_t offset, uint8_t data)
275 {
276 if (m_cart)
277 return m_cart->ram_write(cas, offset, data);
278 }
279
280 /*-------------------------------------------------
281 IO read
282 -------------------------------------------------*/
283
io_read(int ifsel,offs_t offset,uint8_t & data)284 void dmvcart_slot_device::io_read(int ifsel, offs_t offset, uint8_t &data)
285 {
286 if (m_cart)
287 m_cart->io_read(ifsel, offset, data);
288 }
289
290
291 /*-------------------------------------------------
292 IO write
293 -------------------------------------------------*/
294
io_write(int ifsel,offs_t offset,uint8_t data)295 void dmvcart_slot_device::io_write(int ifsel, offs_t offset, uint8_t data)
296 {
297 if (m_cart)
298 m_cart->io_write(ifsel, offset, data);
299 }
300
301 /*-------------------------------------------------
302 av16bit
303 -------------------------------------------------*/
304
av16bit()305 bool dmvcart_slot_device::av16bit()
306 {
307 if (m_cart)
308 return m_cart->av16bit();
309 return false;
310 }
311
312 /*-------------------------------------------------
313 hold_w
314 -------------------------------------------------*/
315
hold_w(int state)316 void dmvcart_slot_device::hold_w(int state)
317 {
318 if (m_cart)
319 m_cart->hold_w(state);
320 }
321
switch16_w(int state)322 void dmvcart_slot_device::switch16_w(int state)
323 {
324 if (m_cart)
325 m_cart->switch16_w(state);
326 }
327
timint_w(int state)328 void dmvcart_slot_device::timint_w(int state)
329 {
330 if (m_cart)
331 m_cart->timint_w(state);
332 }
333
keyint_w(int state)334 void dmvcart_slot_device::keyint_w(int state)
335 {
336 if (m_cart)
337 m_cart->keyint_w(state);
338 }
339
busint_w(int state)340 void dmvcart_slot_device::busint_w(int state)
341 {
342 if (m_cart)
343 m_cart->busint_w(state);
344 }
345
flexint_w(int state)346 void dmvcart_slot_device::flexint_w(int state)
347 {
348 if (m_cart)
349 m_cart->flexint_w(state);
350 }
351
irq2_w(int state)352 void dmvcart_slot_device::irq2_w(int state)
353 {
354 if (m_cart)
355 m_cart->irq2_w(state);
356 }
357
irq2a_w(int state)358 void dmvcart_slot_device::irq2a_w(int state)
359 {
360 if (m_cart)
361 m_cart->irq2a_w(state);
362 }
363
irq3_w(int state)364 void dmvcart_slot_device::irq3_w(int state)
365 {
366 if (m_cart)
367 m_cart->irq3_w(state);
368 }
369
irq4_w(int state)370 void dmvcart_slot_device::irq4_w(int state)
371 {
372 if (m_cart)
373 m_cart->irq4_w(state);
374 }
375
irq5_w(int state)376 void dmvcart_slot_device::irq5_w(int state)
377 {
378 if (m_cart)
379 m_cart->irq5_w(state);
380 }
381
irq6_w(int state)382 void dmvcart_slot_device::irq6_w(int state)
383 {
384 if (m_cart)
385 m_cart->irq6_w(state);
386 }
387