1 // license:BSD-3-Clause
2 // copyright-holders:Steve Ellenoff,R. Belmont,Ryan Holtz
3 #include "emu.h"
4 #include "arm7core.h"
5 #include "arm7help.h"
6
7
8 const arm7_cpu_device::arm7thumb_drcophandler arm7_cpu_device::drcthumb_handler[0x40*0x10] =
9 {
10 // #define THUMB_SHIFT_R ((uint16_t)0x0800)
11 &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
12 &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
13 &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
14 &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0, &arm7_cpu_device::drctg00_0,
15 &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
16 &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
17 &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
18 &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1, &arm7_cpu_device::drctg00_1,
19 // #define THUMB_INSN_ADDSUB ((uint16_t)0x0800) // #define THUMB_ADDSUB_TYPE ((uint16_t)0x0600)
20 &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
21 &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
22 &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
23 &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0, &arm7_cpu_device::drctg01_0,
24 &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10, &arm7_cpu_device::drctg01_10,
25 &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11, &arm7_cpu_device::drctg01_11,
26 &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12, &arm7_cpu_device::drctg01_12,
27 &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13, &arm7_cpu_device::drctg01_13,
28 // #define THUMB_INSN_CMP ((uint16_t)0x0800)
29 &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
30 &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
31 &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
32 &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0, &arm7_cpu_device::drctg02_0,
33 &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
34 &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
35 &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
36 &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1, &arm7_cpu_device::drctg02_1,
37 // #define THUMB_INSN_SUB ((uint16_t)0x0800)
38 &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
39 &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
40 &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
41 &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0, &arm7_cpu_device::drctg03_0,
42 &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
43 &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
44 &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
45 &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1, &arm7_cpu_device::drctg03_1,
46 //#define THUMB_GROUP4_TYPE ((uint16_t)0x0c00) //#define THUMB_ALUOP_TYPE ((uint16_t)0x03c0) // #define THUMB_HIREG_OP ((uint16_t)0x0300) // #define THUMB_HIREG_H ((uint16_t)0x00c0)
47 &arm7_cpu_device::drctg04_00_00, &arm7_cpu_device::drctg04_00_01, &arm7_cpu_device::drctg04_00_02, &arm7_cpu_device::drctg04_00_03, &arm7_cpu_device::drctg04_00_04, &arm7_cpu_device::drctg04_00_05, &arm7_cpu_device::drctg04_00_06, &arm7_cpu_device::drctg04_00_07,
48 &arm7_cpu_device::drctg04_00_08, &arm7_cpu_device::drctg04_00_09, &arm7_cpu_device::drctg04_00_0a, &arm7_cpu_device::drctg04_00_0b, &arm7_cpu_device::drctg04_00_0c, &arm7_cpu_device::drctg04_00_0d, &arm7_cpu_device::drctg04_00_0e, &arm7_cpu_device::drctg04_00_0f,
49 &arm7_cpu_device::drctg04_01_00, &arm7_cpu_device::drctg04_01_01, &arm7_cpu_device::drctg04_01_02, &arm7_cpu_device::drctg04_01_03, &arm7_cpu_device::drctg04_01_10, &arm7_cpu_device::drctg04_01_11, &arm7_cpu_device::drctg04_01_12, &arm7_cpu_device::drctg04_01_13,
50 &arm7_cpu_device::drctg04_01_20, &arm7_cpu_device::drctg04_01_21, &arm7_cpu_device::drctg04_01_22, &arm7_cpu_device::drctg04_01_23, &arm7_cpu_device::drctg04_01_30, &arm7_cpu_device::drctg04_01_31, &arm7_cpu_device::drctg04_01_32, &arm7_cpu_device::drctg04_01_33,
51 &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
52 &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
53 &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
54 &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203, &arm7_cpu_device::drctg04_0203,
55 //#define THUMB_GROUP5_TYPE ((uint16_t)0x0e00)
56 &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0, &arm7_cpu_device::drctg05_0,
57 &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1, &arm7_cpu_device::drctg05_1,
58 &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2, &arm7_cpu_device::drctg05_2,
59 &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3, &arm7_cpu_device::drctg05_3,
60 &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4, &arm7_cpu_device::drctg05_4,
61 &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5, &arm7_cpu_device::drctg05_5,
62 &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6, &arm7_cpu_device::drctg05_6,
63 &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7, &arm7_cpu_device::drctg05_7,
64 //#define THUMB_LSOP_L ((uint16_t)0x0800)
65 &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
66 &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
67 &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
68 &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0, &arm7_cpu_device::drctg06_0,
69 &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
70 &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
71 &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
72 &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1, &arm7_cpu_device::drctg06_1,
73 //#define THUMB_LSOP_L ((uint16_t)0x0800)
74 &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
75 &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
76 &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
77 &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0, &arm7_cpu_device::drctg07_0,
78 &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
79 &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
80 &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
81 &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1, &arm7_cpu_device::drctg07_1,
82 // #define THUMB_HALFOP_L ((uint16_t)0x0800)
83 &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
84 &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
85 &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
86 &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0, &arm7_cpu_device::drctg08_0,
87 &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
88 &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
89 &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
90 &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1, &arm7_cpu_device::drctg08_1,
91 // #define THUMB_STACKOP_L ((uint16_t)0x0800)
92 &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
93 &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
94 &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
95 &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0, &arm7_cpu_device::drctg09_0,
96 &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
97 &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
98 &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
99 &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1, &arm7_cpu_device::drctg09_1,
100 // #define THUMB_RELADDR_SP ((uint16_t)0x0800)
101 &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
102 &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
103 &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
104 &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0, &arm7_cpu_device::drctg0a_0,
105 &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
106 &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
107 &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
108 &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1, &arm7_cpu_device::drctg0a_1,
109 // #define THUMB_STACKOP_TYPE ((uint16_t)0x0f00)
110 &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_0, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1, &arm7_cpu_device::drctg0b_1,
111 &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_2, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3, &arm7_cpu_device::drctg0b_3,
112 &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_4, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5, &arm7_cpu_device::drctg0b_5,
113 &arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_6, &arm7_cpu_device::drctg0b_7, &arm7_cpu_device::drctg0b_7, &arm7_cpu_device::drctg0b_7, &arm7_cpu_device::drctg0b_7,
114 &arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_8, &arm7_cpu_device::drctg0b_9, &arm7_cpu_device::drctg0b_9, &arm7_cpu_device::drctg0b_9, &arm7_cpu_device::drctg0b_9,
115 &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_a, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b, &arm7_cpu_device::drctg0b_b,
116 &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_c, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d, &arm7_cpu_device::drctg0b_d,
117 &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_e, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f, &arm7_cpu_device::drctg0b_f,
118 // #define THUMB_MULTLS ((uint16_t)0x0800)
119 &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
120 &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
121 &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
122 &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0, &arm7_cpu_device::drctg0c_0,
123 &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
124 &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
125 &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
126 &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1, &arm7_cpu_device::drctg0c_1,
127 // #define THUMB_COND_TYPE ((uint16_t)0x0f00)
128 &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_0, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1, &arm7_cpu_device::drctg0d_1,
129 &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_2, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3, &arm7_cpu_device::drctg0d_3,
130 &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_4, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5, &arm7_cpu_device::drctg0d_5,
131 &arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_6, &arm7_cpu_device::drctg0d_7, &arm7_cpu_device::drctg0d_7, &arm7_cpu_device::drctg0d_7, &arm7_cpu_device::drctg0d_7,
132 &arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_8, &arm7_cpu_device::drctg0d_9, &arm7_cpu_device::drctg0d_9, &arm7_cpu_device::drctg0d_9, &arm7_cpu_device::drctg0d_9,
133 &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_a, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b, &arm7_cpu_device::drctg0d_b,
134 &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_c, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d, &arm7_cpu_device::drctg0d_d,
135 &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_e, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f, &arm7_cpu_device::drctg0d_f,
136 // #define THUMB_BLOP_LO ((uint16_t)0x0800)
137 &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
138 &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
139 &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
140 &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0, &arm7_cpu_device::drctg0e_0,
141 &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
142 &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
143 &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
144 &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1, &arm7_cpu_device::drctg0e_1,
145 // #define THUMB_BLOP_LO ((uint16_t)0x0800)
146 &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
147 &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
148 &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
149 &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0, &arm7_cpu_device::drctg0f_0,
150 &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
151 &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
152 &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
153 &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1, &arm7_cpu_device::drctg0f_1,
154 };
155
156 /* Shift operations */
157
drctg00_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)158 void arm7_cpu_device::drctg00_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Shift left */
159 {
160 uint32_t op = desc->opptr.l[0];
161 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
162 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
163 int32_t offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
164
165 UML_MOV(block, uml::I0, DRC_RS); // rrs
166 if (offs != 0)
167 {
168 UML_SHL(block, DRC_RD, DRC_RS, offs);
169 UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
170 UML_TEST(block, uml::I0, 1 << (31 - (offs - 1)));
171 UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
172 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
173 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
174 }
175 else
176 {
177 UML_MOV(block, DRC_RD, DRC_RS);
178 }
179 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
180 DRCHandleALUNZFlags(DRC_RD);
181 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
182 UML_ADD(block, DRC_PC, DRC_PC, 2);
183 }
184
drctg00_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)185 void arm7_cpu_device::drctg00_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Shift right */
186 {
187 uint32_t op = desc->opptr.l[0];
188 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
189 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
190 int32_t offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
191
192 UML_MOV(block, uml::I0, DRC_RS); // rrs
193 if (offs != 0)
194 {
195 UML_SHR(block, DRC_RD, DRC_RS, offs);
196 UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
197 UML_TEST(block, uml::I0, 1 << (31 - (offs - 1)));
198 UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
199 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
200 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
201 }
202 else
203 {
204 UML_MOV(block, DRC_RD, 0);
205 UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
206 UML_TEST(block, uml::I0, 0x80000000);
207 UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
208 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
209 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
210 }
211 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
212 DRCHandleALUNZFlags(DRC_RD);
213 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
214 UML_ADD(block, DRC_PC, DRC_PC, 2);
215 }
216
217 /* Arithmetic */
218
drctg01_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)219 void arm7_cpu_device::drctg01_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
220 {
221 uint32_t op = desc->opptr.l[0];
222 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
223 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
224 int32_t offs = (op & THUMB_SHIFT_AMT) >> THUMB_SHIFT_AMT_SHIFT;
225
226 /* ASR.. */
227 UML_MOV(block, uml::I0, DRC_RS);
228 if (offs == 0)
229 {
230 offs = 32;
231 }
232 if (offs >= 32)
233 {
234 UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
235 UML_SHR(block, uml::I1, uml::I0, 31);
236 UML_TEST(block, uml::I1, ~0);
237 UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
238 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
239 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
240 UML_TEST(block, uml::I0, 0x80000000);
241 UML_MOVc(block, uml::COND_NZ, DRC_RD, ~0);
242 UML_MOVc(block, uml::COND_Z, DRC_RD, 0);
243 }
244 else
245 {
246 UML_AND(block, DRC_CPSR, DRC_CPSR, ~C_MASK);
247 UML_TEST(block, uml::I0, 1 << (offs - 1));
248 UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
249 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
250 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
251 UML_SHR(block, uml::I1, uml::I0, offs);
252 UML_SHL(block, uml::I2, ~0, 32 - offs);
253 UML_TEST(block, uml::I0, 0x80000000);
254 UML_MOVc(block, uml::COND_Z, uml::I2, 0);
255 UML_OR(block, DRC_RD, uml::I1, uml::I2);
256 }
257 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
258 DRCHandleALUNZFlags(DRC_RD);
259 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
260 UML_ADD(block, DRC_PC, DRC_PC, 2);
261 }
262
drctg01_10(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)263 void arm7_cpu_device::drctg01_10(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
264 {
265 uint32_t op = desc->opptr.l[0];
266 uint32_t rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
267 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
268 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
269 UML_ADD(block, DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
270 DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
271 }
272
drctg01_11(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)273 void arm7_cpu_device::drctg01_11(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* SUB Rd, Rs, Rn */
274 {
275 uint32_t op = desc->opptr.l[0];
276 uint32_t rn = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
277 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
278 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
279 UML_SUB(block, DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
280 DRCHandleThumbALUSubFlags(DRC_REG(rd), DRC_REG(rs), DRC_REG(rn));
281 }
282
drctg01_12(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)283 void arm7_cpu_device::drctg01_12(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADD Rd, Rs, #imm */
284 {
285 uint32_t op = desc->opptr.l[0];
286 uint32_t imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
287 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
288 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
289 UML_ADD(block, DRC_REG(rd), DRC_REG(rs), imm);
290 DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rs), imm);
291 }
292
drctg01_13(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)293 void arm7_cpu_device::drctg01_13(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* SUB Rd, Rs, #imm */
294 {
295 uint32_t op = desc->opptr.l[0];
296 uint32_t imm = (op & THUMB_ADDSUB_RNIMM) >> THUMB_ADDSUB_RNIMM_SHIFT;
297 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
298 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
299 UML_SUB(block, DRC_REG(rd), DRC_REG(rs), imm);
300 DRCHandleThumbALUSubFlags(DRC_REG(rd), DRC_REG(rs), imm);
301 }
302
303 /* CMP / MOV */
304
drctg02_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)305 void arm7_cpu_device::drctg02_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
306 {
307 uint32_t op = desc->opptr.l[0];
308 uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
309 uint32_t op2 = (op & THUMB_INSN_IMM);
310 UML_MOV(block, DRC_REG(rd), op2);
311 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
312 DRCHandleALUNZFlags(DRC_REG(rd));
313 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
314 UML_ADD(block, DRC_PC, DRC_PC, 2);
315 }
316
drctg02_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)317 void arm7_cpu_device::drctg02_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
318 {
319 uint32_t op = desc->opptr.l[0];
320 uint32_t rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
321 uint32_t op2 = op & THUMB_INSN_IMM;
322
323 UML_SUB(block, uml::I3, DRC_REG(rn), op2);
324 DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rn), op2);
325 }
326
327 /* ADD/SUB immediate */
328
drctg03_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)329 void arm7_cpu_device::drctg03_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADD Rd, #Offset8 */
330 {
331 uint32_t op = desc->opptr.l[0];
332 uint32_t rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
333 uint32_t op2 = op & THUMB_INSN_IMM;
334 uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
335 UML_ADD(block, DRC_REG(rd), DRC_REG(rn), op2);
336 DRCHandleThumbALUAddFlags(DRC_REG(rd), DRC_REG(rn), op2);
337 }
338
drctg03_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)339 void arm7_cpu_device::drctg03_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* SUB Rd, #Offset8 */
340 {
341 uint32_t op = desc->opptr.l[0];
342 uint32_t rn = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
343 uint32_t op2 = op & THUMB_INSN_IMM;
344 uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
345 UML_SUB(block, DRC_REG(rd), DRC_REG(rn), op2);
346 DRCHandleThumbALUSubFlags(DRC_REG(rd), DRC_REG(rn), op2);
347 }
348
349 /* Rd & Rm instructions */
350
drctg04_00_00(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)351 void arm7_cpu_device::drctg04_00_00(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* AND Rd, Rs */
352 {
353 uint32_t op = desc->opptr.l[0];
354 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
355 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
356 UML_AND(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
357 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
358 DRCHandleALUNZFlags(DRC_REG(rd));
359 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
360 UML_ADD(block, DRC_PC, DRC_PC, 2);
361 }
362
drctg04_00_01(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)363 void arm7_cpu_device::drctg04_00_01(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* EOR Rd, Rs */
364 {
365 uint32_t op = desc->opptr.l[0];
366 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
367 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
368 UML_XOR(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
369 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
370 DRCHandleALUNZFlags(DRC_REG(rd));
371 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
372 UML_ADD(block, DRC_PC, DRC_PC, 2);
373 }
374
drctg04_00_02(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)375 void arm7_cpu_device::drctg04_00_02(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* LSL Rd, Rs */
376 {
377 uint32_t op = desc->opptr.l[0];
378 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
379 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
380 uml::code_label skip;
381 uml::code_label offsg32;
382 uml::code_label offs32;
383
384 UML_AND(block, uml::I1, DRC_REG(rs), 0xff);
385 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK | C_MASK));
386
387 UML_CMP(block, uml::I1, 0);
388 UML_JMPc(block, uml::COND_E, skip = compiler.labelnum++);
389
390 UML_CMP(block, uml::I1, 32);
391 UML_JMPc(block, uml::COND_A, offsg32 = compiler.labelnum++);
392 UML_JMPc(block, uml::COND_E, offs32 = compiler.labelnum++);
393
394 UML_SHL(block, DRC_REG(rd), DRC_REG(rd), uml::I1);
395 UML_SUB(block, uml::I1, uml::I1, 1);
396 UML_SUB(block, uml::I1, 31, uml::I1);
397 UML_SHL(block, uml::I1, 1, uml::I1);
398 UML_TEST(block, DRC_REG(rd), uml::I1);
399 UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
400 UML_MOVc(block, uml::COND_Z, uml::I0, 0);
401 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
402 UML_JMP(block, skip);
403
404 UML_LABEL(block, offs32);
405 UML_TEST(block, DRC_REG(rd), 1);
406 UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
407 UML_MOVc(block, uml::COND_Z, uml::I0, 0);
408 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
409 UML_MOV(block, DRC_REG(rd), 0);
410 UML_JMP(block, skip);
411
412 UML_LABEL(block, offsg32);
413 UML_MOV(block, DRC_REG(rd), 0);
414
415 UML_LABEL(block, skip);
416
417 DRCHandleALUNZFlags(DRC_REG(rd));
418 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
419 UML_ADD(block, DRC_PC, DRC_PC, 2);
420 }
421
drctg04_00_03(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)422 void arm7_cpu_device::drctg04_00_03(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* LSR Rd, Rs */
423 {
424 uint32_t op = desc->opptr.l[0];
425 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
426 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
427 uml::code_label skip;
428 uml::code_label offsg32;
429 uml::code_label offs32;
430
431 UML_AND(block, uml::I1, DRC_REG(rs), 0xff);
432 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK | C_MASK));
433 UML_CMP(block, uml::I1, 0);
434 UML_JMPc(block, uml::COND_E, skip = compiler.labelnum++);
435
436 UML_CMP(block, uml::I1, 32);
437 UML_JMPc(block, uml::COND_A, offsg32 = compiler.labelnum++);
438 UML_JMPc(block, uml::COND_E, offs32 = compiler.labelnum++);
439
440 UML_SHR(block, DRC_REG(rd), DRC_REG(rd), uml::I1);
441 UML_SUB(block, uml::I1, uml::I1, 1); // WP: TODO, Check this used to be "block, I1, 1"
442 UML_SHL(block, uml::I1, 1, uml::I1);
443 UML_TEST(block, DRC_REG(rd), uml::I1);
444 UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
445 UML_MOVc(block, uml::COND_Z, uml::I0, 0);
446 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
447 UML_JMP(block, skip);
448
449 UML_LABEL(block, offs32);
450 UML_TEST(block, DRC_REG(rd), 0x80000000);
451 UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
452 UML_MOVc(block, uml::COND_Z, uml::I0, 0);
453 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
454 UML_MOV(block, DRC_REG(rd), 0);
455 UML_JMP(block, skip);
456
457 UML_LABEL(block, offsg32);
458 UML_MOV(block, DRC_REG(rd), 0);
459
460 UML_LABEL(block, skip);
461
462 DRCHandleALUNZFlags(DRC_REG(rd));
463 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
464 UML_ADD(block, DRC_PC, DRC_PC, 2);
465 }
466
drctg04_00_04(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)467 void arm7_cpu_device::drctg04_00_04(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ASR Rd, Rs */
468 {
469 uint32_t op = desc->opptr.l[0];
470 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
471 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
472 uml::code_label skip;
473 uml::code_label offs32;
474
475 UML_MOV(block, uml::I0, DRC_REG(rd));
476 UML_AND(block, uml::I1, DRC_REG(rs), 0xff);
477 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK | C_MASK));
478 UML_CMP(block, uml::I1, 0);
479 UML_JMPc(block, uml::COND_E, skip = compiler.labelnum++);
480
481 UML_SHR(block, uml::I2, uml::I0, uml::I1);
482 UML_SUB(block, uml::I1, 32, uml::I1);
483 UML_SHL(block, uml::I1, ~0, uml::I1);
484 UML_TEST(block, uml::I0, 0x80000000);
485 UML_MOVc(block, uml::COND_NZ, DRC_REG(rd), uml::I1);
486 UML_MOVc(block, uml::COND_Z, DRC_REG(rd), 0);
487 UML_OR(block, DRC_REG(rd), DRC_REG(rd), uml::I2);
488 UML_JMPc(block, uml::COND_B, offs32 = compiler.labelnum++);
489
490 UML_TEST(block, uml::I0, 0x80000000);
491 UML_MOVc(block, uml::COND_NZ, DRC_REG(rd), ~0);
492 UML_MOVc(block, uml::COND_Z, DRC_REG(rd), 0);
493 UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
494 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
495 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
496 UML_JMP(block, skip);
497
498 UML_LABEL(block, offs32);
499 UML_SUB(block, uml::I1, uml::I1, 1);
500 UML_SHL(block, uml::I1, 1, uml::I1);
501 UML_TEST(block, uml::I0, uml::I1);
502 UML_MOVc(block, uml::COND_NZ, uml::I1, C_MASK);
503 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
504 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I1);
505 UML_JMP(block, skip);
506
507 UML_LABEL(block, skip);
508 DRCHandleALUNZFlags(DRC_REG(rd));
509 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
510 UML_ADD(block, DRC_PC, DRC_PC, 2);
511
512 }
513
drctg04_00_05(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)514 void arm7_cpu_device::drctg04_00_05(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADC Rd, Rs */
515 {
516 uint32_t op = desc->opptr.l[0];
517 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
518 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
519 UML_TEST(block, DRC_CPSR, C_MASK);
520 UML_MOVc(block, uml::COND_NZ, uml::I3, 1);
521 UML_MOVc(block, uml::COND_Z, uml::I3, 0);
522 UML_ADD(block, uml::I3, uml::I3, DRC_REG(rd));
523 UML_ADD(block, uml::I3, uml::I3, DRC_REG(rs));
524 DRCHandleThumbALUAddFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
525 UML_MOV(block, DRC_REG(rd), uml::I3);
526 }
527
drctg04_00_06(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)528 void arm7_cpu_device::drctg04_00_06(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* SBC Rd, Rs */
529 {
530 uint32_t op = desc->opptr.l[0];
531 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
532 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
533 UML_TEST(block, DRC_CPSR, C_MASK);
534 UML_MOVc(block, uml::COND_NZ, uml::I3, 0);
535 UML_MOVc(block, uml::COND_Z, uml::I3, 1);
536 UML_SUB(block, uml::I3, DRC_REG(rs), uml::I3);
537 UML_ADD(block, uml::I3, DRC_REG(rd), uml::I3);
538 DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
539 UML_MOV(block, DRC_REG(rd), uml::I3);
540 }
541
drctg04_00_07(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)542 void arm7_cpu_device::drctg04_00_07(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ROR Rd, Rs */
543 {
544 uint32_t op = desc->opptr.l[0];
545 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
546 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
547 UML_MOV(block, uml::I0, DRC_REG(rd));
548 UML_AND(block, uml::I1, DRC_REG(rs), 0x1f);
549 UML_SHR(block, DRC_REG(rd), uml::I0, uml::I1);
550 UML_SUB(block, uml::I2, 32, uml::I1);
551 UML_SHL(block, uml::I2, uml::I0, uml::I2);
552 UML_OR(block, DRC_REG(rd), DRC_REG(rd), uml::I2);
553 UML_SUB(block, uml::I1, uml::I1, 1);
554 UML_SHL(block, uml::I1, 1, uml::I1);
555 UML_TEST(block, uml::I0, uml::I1);
556 UML_MOVc(block, uml::COND_NZ, uml::I0, C_MASK);
557 UML_MOVc(block, uml::COND_Z, uml::I0, 0);
558 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK | C_MASK));
559 DRCHandleALUNZFlags(DRC_REG(rd));
560 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
561 UML_ADD(block, DRC_PC, DRC_PC, 2);
562 }
563
drctg04_00_08(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)564 void arm7_cpu_device::drctg04_00_08(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* TST Rd, Rs */
565 {
566 uint32_t op = desc->opptr.l[0];
567 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
568 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
569 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
570 UML_AND(block, uml::I2, DRC_REG(rd), DRC_REG(rs));
571 DRCHandleALUNZFlags(uml::I2);
572 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
573 UML_ADD(block, DRC_PC, DRC_PC, 2);
574 }
575
drctg04_00_09(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)576 void arm7_cpu_device::drctg04_00_09(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* NEG Rd, Rs */
577 {
578 uint32_t op = desc->opptr.l[0];
579 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
580 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
581 UML_MOV(block, uml::I3, DRC_REG(rs));
582 UML_SUB(block, DRC_REG(rd), 0, uml::I3);
583 DRCHandleThumbALUSubFlags(DRC_REG(rd), 0, uml::I3);
584 }
585
drctg04_00_0a(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)586 void arm7_cpu_device::drctg04_00_0a(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* CMP Rd, Rs */
587 {
588 uint32_t op = desc->opptr.l[0];
589 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
590 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
591 UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
592 DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
593 }
594
drctg04_00_0b(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)595 void arm7_cpu_device::drctg04_00_0b(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* CMN Rd, Rs - check flags, add dasm */
596 {
597 uint32_t op = desc->opptr.l[0];
598 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
599 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
600 UML_ADD(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
601 DRCHandleThumbALUAddFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
602 }
603
drctg04_00_0c(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)604 void arm7_cpu_device::drctg04_00_0c(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ORR Rd, Rs */
605 {
606 uint32_t op = desc->opptr.l[0];
607 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
608 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
609 UML_OR(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs));
610 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
611 DRCHandleALUNZFlags(DRC_REG(rd));
612 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
613 UML_ADD(block, DRC_PC, DRC_PC, 2);
614 }
615
drctg04_00_0d(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)616 void arm7_cpu_device::drctg04_00_0d(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* MUL Rd, Rs */
617 {
618 uint32_t op = desc->opptr.l[0];
619 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
620 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
621 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
622 UML_MULU(block, DRC_REG(rd), uml::I1, DRC_REG(rd), DRC_REG(rs));
623 DRCHandleALUNZFlags(DRC_REG(rd));
624 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
625 UML_ADD(block, DRC_PC, DRC_PC, 2);
626 }
627
drctg04_00_0e(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)628 void arm7_cpu_device::drctg04_00_0e(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* BIC Rd, Rs */
629 {
630 uint32_t op = desc->opptr.l[0];
631 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
632 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
633 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
634 UML_XOR(block, uml::I0, DRC_REG(rs), ~0);
635 UML_AND(block, DRC_REG(rd), DRC_REG(rd), uml::I0);
636 DRCHandleALUNZFlags(DRC_REG(rd));
637 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
638 UML_ADD(block, DRC_PC, DRC_PC, 2);
639 }
640
drctg04_00_0f(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)641 void arm7_cpu_device::drctg04_00_0f(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* MVN Rd, Rs */
642 {
643 uint32_t op = desc->opptr.l[0];
644 uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
645 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
646 UML_XOR(block, uml::I0, DRC_REG(rs), ~0);
647 UML_MOV(block, DRC_REG(rd), uml::I0);
648 UML_AND(block, DRC_CPSR, DRC_CPSR, ~(Z_MASK | N_MASK));
649 DRCHandleALUNZFlags(DRC_REG(rd));
650 UML_OR(block, DRC_CPSR, DRC_CPSR, uml::I0);
651 UML_ADD(block, DRC_PC, DRC_PC, 2);
652 }
653
654 /* ADD Rd, Rs group */
655
drctg04_01_00(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)656 void arm7_cpu_device::drctg04_01_00(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
657 {
658 uint32_t op = desc->opptr.l[0];
659 uint32_t pc = desc->pc;
660 fatalerror("%08x: G4-1-0 Undefined Thumb instruction: %04x %x\n", pc, op, (op & THUMB_HIREG_H) >> THUMB_HIREG_H_SHIFT);
661 }
662
drctg04_01_01(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)663 void arm7_cpu_device::drctg04_01_01(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADD Rd, HRs */
664 {
665 uint32_t op = desc->opptr.l[0];
666 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
667 uint32_t rd = op & THUMB_HIREG_RD;
668 UML_ADD(block, DRC_REG(rd), DRC_REG(rd), DRC_REG(rs+8));
669 if (rs == 7)
670 {
671 UML_ADD(block, DRC_REG(rd), DRC_REG(rd), 4);
672 }
673 UML_ADD(block, DRC_PC, DRC_PC, 2);
674 }
675
drctg04_01_02(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)676 void arm7_cpu_device::drctg04_01_02(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADD HRd, Rs */
677 {
678 uint32_t op = desc->opptr.l[0];
679 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
680 uint32_t rd = op & THUMB_HIREG_RD;
681 UML_ADD(block, DRC_REG(rd+8), DRC_REG(rd+8), DRC_REG(rs));
682 if (rd == 7)
683 {
684 UML_ADD(block, DRC_REG(rd), DRC_REG(rd), 4);
685 }
686 UML_ADD(block, DRC_PC, DRC_PC, 2);
687 }
688
drctg04_01_03(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)689 void arm7_cpu_device::drctg04_01_03(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Add HRd, HRs */
690 {
691 uint32_t op = desc->opptr.l[0];
692 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
693 uint32_t rd = op & THUMB_HIREG_RD;
694 UML_ADD(block, DRC_REG(rd+8), DRC_REG(rd+8), DRC_REG(rs+8));
695 // emulate the effects of pre-fetch
696 if (rs == 7)
697 {
698 UML_ADD(block, DRC_REG(rd+8), DRC_REG(rd+8), 4);
699 }
700 if (rd == 7)
701 {
702 UML_ADD(block, DRC_REG(rd+8), DRC_REG(rd+8), 2);
703 }
704 UML_ADD(block, DRC_PC, DRC_PC, 2);
705 }
706
drctg04_01_10(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)707 void arm7_cpu_device::drctg04_01_10(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* CMP Rd, Rs */
708 {
709 uint32_t op = desc->opptr.l[0];
710 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
711 uint32_t rd = op & THUMB_HIREG_RD;
712 UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs));
713 DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs));
714 }
715
drctg04_01_11(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)716 void arm7_cpu_device::drctg04_01_11(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* CMP Rd, Hs */
717 {
718 uint32_t op = desc->opptr.l[0];
719 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
720 uint32_t rd = op & THUMB_HIREG_RD;
721 UML_SUB(block, uml::I3, DRC_REG(rd), DRC_REG(rs+8));
722 DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd), DRC_REG(rs+8));
723 }
724
drctg04_01_12(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)725 void arm7_cpu_device::drctg04_01_12(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* CMP Hd, Rs */
726 {
727 uint32_t op = desc->opptr.l[0];
728 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
729 uint32_t rd = op & THUMB_HIREG_RD;
730 UML_SUB(block, uml::I3, DRC_REG(rd+8), DRC_REG(rs));
731 DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd+8), DRC_REG(rs));
732 }
733
drctg04_01_13(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)734 void arm7_cpu_device::drctg04_01_13(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* CMP Hd, Hs */
735 {
736 uint32_t op = desc->opptr.l[0];
737 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
738 uint32_t rd = op & THUMB_HIREG_RD;
739 UML_SUB(block, uml::I3, DRC_REG(rd+8), DRC_REG(rs+8));
740 DRCHandleThumbALUSubFlags(uml::I3, DRC_REG(rd+8), DRC_REG(rs+8));
741 }
742
743 /* MOV group */
744
drctg04_01_20(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)745 void arm7_cpu_device::drctg04_01_20(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* MOV Rd, Rs (undefined) */
746 {
747 uint32_t op = desc->opptr.l[0];
748 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
749 uint32_t rd = op & THUMB_HIREG_RD;
750 UML_MOV(block, DRC_REG(rd), DRC_REG(rs));
751 UML_ADD(block, DRC_PC, DRC_PC, 2);
752 }
753
drctg04_01_21(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)754 void arm7_cpu_device::drctg04_01_21(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* MOV Rd, Hs */
755 {
756 uint32_t op = desc->opptr.l[0];
757 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
758 uint32_t rd = op & THUMB_HIREG_RD;
759 UML_MOV(block, DRC_REG(rd), DRC_REG(rs+8));
760 if (rs == 7)
761 {
762 UML_ADD(block, DRC_REG(rd), DRC_REG(rd), 4);
763 }
764 UML_ADD(block, DRC_PC, DRC_PC, 2);
765 }
766
drctg04_01_22(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)767 void arm7_cpu_device::drctg04_01_22(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* MOV Hd, Rs */
768 {
769 uint32_t op = desc->opptr.l[0];
770 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
771 uint32_t rd = op & THUMB_HIREG_RD;
772 UML_MOV(block, DRC_REG(rd+8), DRC_REG(rs));
773 // CHECKME
774 if (rd != 7)
775 {
776 UML_ADD(block, DRC_PC, DRC_PC, 2);
777 }
778 else
779 {
780 UML_AND(block, DRC_PC, DRC_PC, ~1);
781 }
782 }
783
drctg04_01_23(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)784 void arm7_cpu_device::drctg04_01_23(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* MOV Hd, Hs */
785 {
786 uint32_t op = desc->opptr.l[0];
787 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
788 uint32_t rd = op & THUMB_HIREG_RD;
789 UML_MOV(block, DRC_REG(rd+8), DRC_REG(rs+8));
790 if (rs == 7)
791 {
792 UML_ADD(block, DRC_REG(rd+8), DRC_REG(rd+8), 4);
793 }
794 if (rd != 7)
795 {
796 UML_ADD(block, DRC_PC, DRC_PC, 2);
797 }
798 else
799 {
800 UML_AND(block, DRC_PC, DRC_PC, ~1);
801 }
802
803 }
804
drctg04_01_30(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)805 void arm7_cpu_device::drctg04_01_30(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
806 {
807 uint32_t op = desc->opptr.l[0];
808 uml::code_label switch_state;
809 uml::code_label done;
810 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
811 UML_MOV(block, uml::I0, DRC_REG(rs));
812 UML_TEST(block, uml::I0, 1);
813 UML_JMPc(block, uml::COND_Z, switch_state = compiler.labelnum++);
814 UML_AND(block, uml::I0, uml::I0, ~1);
815 UML_JMP(block, done = compiler.labelnum++);
816
817 UML_LABEL(block, switch_state);
818 UML_AND(block, DRC_CPSR, DRC_CPSR, ~T_MASK);
819 UML_TEST(block, uml::I0, 2);
820 UML_MOVc(block, uml::COND_NZ, uml::I1, 2);
821 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
822 UML_ADD(block, uml::I0, uml::I0, uml::I1);
823
824 UML_LABEL(block, done);
825 UML_MOV(block, DRC_PC, uml::I0);
826 }
827
drctg04_01_31(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)828 void arm7_cpu_device::drctg04_01_31(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
829 {
830 uint32_t op = desc->opptr.l[0];
831 uml::code_label switch_state;
832 uml::code_label done;
833 uint32_t rs = (op & THUMB_HIREG_RS) >> THUMB_HIREG_RS_SHIFT;
834 UML_MOV(block, uml::I0, DRC_REG(rs+8));
835 if(rs == 7)
836 {
837 UML_ADD(block, uml::I0, uml::I0, 2);
838 }
839 UML_TEST(block, uml::I0, 1);
840 UML_JMPc(block, uml::COND_Z, switch_state = compiler.labelnum++);
841 UML_AND(block, uml::I0, uml::I0, ~1);
842 UML_JMP(block, done = compiler.labelnum++);
843
844 UML_LABEL(block, switch_state);
845 UML_AND(block, DRC_CPSR, DRC_CPSR, ~T_MASK);
846 UML_TEST(block, uml::I0, 2);
847 UML_MOVc(block, uml::COND_NZ, uml::I1, 2);
848 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
849 UML_ADD(block, uml::I0, uml::I0, uml::I1);
850
851 UML_LABEL(block, done);
852 UML_MOV(block, DRC_PC, uml::I0);
853 }
854
drctg04_01_32(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)855 void arm7_cpu_device::drctg04_01_32(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
856 {
857 uint32_t op = desc->opptr.l[0];
858 uint32_t pc = desc->pc;
859 fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
860 }
861
drctg04_01_33(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)862 void arm7_cpu_device::drctg04_01_33(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
863 {
864 uint32_t op = desc->opptr.l[0];
865 uint32_t pc = desc->pc;
866 fatalerror("%08x: G4-3 Undefined Thumb instruction: %04x\n", pc, op);
867 }
868
drctg04_0203(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)869 void arm7_cpu_device::drctg04_0203(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
870 {
871 uint32_t op = desc->opptr.l[0];
872 uint32_t rd = (op & THUMB_INSN_IMM_RD) >> THUMB_INSN_IMM_RD_SHIFT;
873 uint32_t imm = 4 + ((op & THUMB_INSN_IMM) << 2);
874 UML_AND(block, uml::I0, DRC_PC, ~2);
875 UML_ADD(block, uml::I0, uml::I0, imm);
876 UML_CALLH(block, *m_impstate.read32);
877 UML_MOV(block, DRC_REG(rd), uml::I0);
878 UML_ADD(block, DRC_PC, DRC_PC, 2);
879 }
880
881 /* LDR* STR* group */
882
drctg05_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)883 void arm7_cpu_device::drctg05_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* STR Rd, [Rn, Rm] */
884 {
885 uint32_t op = desc->opptr.l[0];
886 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
887 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
888 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
889 UML_MOV(block, uml::I1, DRC_REG(rd));
890 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
891 UML_CALLH(block, *m_impstate.write32);
892 UML_ADD(block, DRC_PC, DRC_PC, 2);
893 }
894
drctg05_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)895 void arm7_cpu_device::drctg05_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* STRH Rd, [Rn, Rm] */
896 {
897 uint32_t op = desc->opptr.l[0];
898 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
899 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
900 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
901 UML_MOV(block, uml::I1, DRC_REG(rd));
902 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
903 UML_CALLH(block, *m_impstate.write16);
904 UML_ADD(block, DRC_PC, DRC_PC, 2);
905 }
906
drctg05_2(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)907 void arm7_cpu_device::drctg05_2(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* STRB Rd, [Rn, Rm] */
908 {
909 uint32_t op = desc->opptr.l[0];
910 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
911 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
912 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
913 UML_MOV(block, uml::I1, DRC_REG(rd));
914 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
915 UML_CALLH(block, *m_impstate.write16);
916 UML_ADD(block, DRC_PC, DRC_PC, 2);
917 }
918
drctg05_3(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)919 void arm7_cpu_device::drctg05_3(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* LDSB Rd, [Rn, Rm] todo, add dasm */
920 {
921 uint32_t op = desc->opptr.l[0];
922 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
923 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
924 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
925 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
926 UML_CALLH(block, *m_impstate.read8);
927 UML_SEXT(block, DRC_REG(rd), uml::I0, uml::SIZE_BYTE);
928 UML_ADD(block, DRC_PC, DRC_PC, 2);
929 }
930
drctg05_4(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)931 void arm7_cpu_device::drctg05_4(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* LDR Rd, [Rn, Rm] */
932 {
933 uint32_t op = desc->opptr.l[0];
934 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
935 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
936 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
937 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
938 UML_CALLH(block, *m_impstate.read32);
939 UML_MOV(block, DRC_REG(rd), uml::I0);
940 UML_ADD(block, DRC_PC, DRC_PC, 2);
941 }
942
drctg05_5(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)943 void arm7_cpu_device::drctg05_5(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* LDRH Rd, [Rn, Rm] */
944 {
945 uint32_t op = desc->opptr.l[0];
946 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
947 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
948 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
949 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
950 UML_CALLH(block, *m_impstate.read16);
951 UML_MOV(block, DRC_REG(rd), uml::I0);
952 UML_ADD(block, DRC_PC, DRC_PC, 2);
953 }
954
drctg05_6(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)955 void arm7_cpu_device::drctg05_6(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* LDRB Rd, [Rn, Rm] */
956 {
957 uint32_t op = desc->opptr.l[0];
958 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
959 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
960 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
961 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
962 UML_CALLH(block, *m_impstate.read8);
963 UML_MOV(block, DRC_REG(rd), uml::I0);
964 UML_ADD(block, DRC_PC, DRC_PC, 2);
965 }
966
drctg05_7(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)967 void arm7_cpu_device::drctg05_7(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* LDSH Rd, [Rn, Rm] */
968 {
969 uint32_t op = desc->opptr.l[0];
970 uint32_t rm = (op & THUMB_GROUP5_RM) >> THUMB_GROUP5_RM_SHIFT;
971 uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
972 uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
973 UML_ADD(block, uml::I0, DRC_REG(rn), DRC_REG(rm));
974 UML_CALLH(block, *m_impstate.read16);
975 UML_SEXT(block, DRC_REG(rd), uml::I0, uml::SIZE_WORD);
976 UML_ADD(block, DRC_PC, DRC_PC, 2);
977 }
978
979 /* Word Store w/ Immediate Offset */
980
drctg06_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)981 void arm7_cpu_device::drctg06_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Store */
982 {
983 uint32_t op = desc->opptr.l[0];
984 uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
985 uint32_t rd = op & THUMB_ADDSUB_RD;
986 int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
987 UML_ADD(block, uml::I0, DRC_REG(rn), offs);
988 UML_MOV(block, uml::I1, DRC_REG(rd));
989 UML_CALLH(block, *m_impstate.write32);
990 UML_ADD(block, DRC_PC, DRC_PC, 2);
991 }
992
drctg06_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)993 void arm7_cpu_device::drctg06_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Load */
994 {
995 uint32_t op = desc->opptr.l[0];
996 uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
997 uint32_t rd = op & THUMB_ADDSUB_RD;
998 int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
999 UML_ADD(block, uml::I0, DRC_REG(rn), offs);
1000 UML_CALLH(block, *m_impstate.read32);
1001 UML_MOV(block, DRC_REG(rd), uml::I0);
1002 UML_ADD(block, DRC_PC, DRC_PC, 2);
1003 }
1004
1005 /* Byte Store w/ Immeidate Offset */
1006
drctg07_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1007 void arm7_cpu_device::drctg07_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Store */
1008 {
1009 uint32_t op = desc->opptr.l[0];
1010 uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1011 uint32_t rd = op & THUMB_ADDSUB_RD;
1012 int32_t offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
1013 UML_ADD(block, uml::I0, DRC_REG(rn), offs);
1014 UML_MOV(block, uml::I1, DRC_REG(rd));
1015 UML_CALLH(block, *m_impstate.write8);
1016 UML_ADD(block, DRC_PC, DRC_PC, 2);
1017 }
1018
drctg07_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1019 void arm7_cpu_device::drctg07_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Load */
1020 {
1021 uint32_t op = desc->opptr.l[0];
1022 uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1023 uint32_t rd = op & THUMB_ADDSUB_RD;
1024 int32_t offs = (op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT;
1025 UML_ADD(block, uml::I0, DRC_REG(rn), offs);
1026 UML_CALLH(block, *m_impstate.read8);
1027 UML_MOV(block, DRC_REG(rd), uml::I0);
1028 UML_ADD(block, DRC_PC, DRC_PC, 2);
1029 }
1030
1031 /* Load/Store Halfword */
1032
drctg08_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1033 void arm7_cpu_device::drctg08_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Store */
1034 {
1035 uint32_t op = desc->opptr.l[0];
1036 uint32_t offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
1037 uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1038 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
1039 UML_ADD(block, uml::I0, DRC_REG(rn), offs << 1);
1040 UML_MOV(block, uml::I1, DRC_REG(rd));
1041 UML_CALLH(block, *m_impstate.write16);
1042 UML_ADD(block, DRC_PC, DRC_PC, 2);
1043 }
1044
drctg08_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1045 void arm7_cpu_device::drctg08_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Load */
1046 {
1047 uint32_t op = desc->opptr.l[0];
1048 uint32_t offs = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
1049 uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
1050 uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
1051 UML_ADD(block, uml::I0, DRC_REG(rn), offs << 1);
1052 UML_CALLH(block, *m_impstate.read16);
1053 UML_MOV(block, DRC_REG(rd), uml::I0);
1054 UML_ADD(block, DRC_PC, DRC_PC, 2);
1055 }
1056
1057 /* Stack-Relative Load/Store */
1058
drctg09_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1059 void arm7_cpu_device::drctg09_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Store */
1060 {
1061 uint32_t op = desc->opptr.l[0];
1062 uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
1063 int32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
1064 UML_ADD(block, uml::I0, DRC_REG(13), offs);
1065 UML_MOV(block, uml::I1, DRC_REG(rd));
1066 UML_CALLH(block, *m_impstate.write32);
1067 UML_ADD(block, DRC_PC, DRC_PC, 2);
1068 }
1069
drctg09_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1070 void arm7_cpu_device::drctg09_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Load */
1071 {
1072 uint32_t op = desc->opptr.l[0];
1073 uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
1074 uint32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
1075 UML_ADD(block, uml::I0, DRC_REG(13), offs);
1076 UML_CALLH(block, *m_impstate.read32);
1077 UML_MOV(block, DRC_REG(rd), uml::I0);
1078 UML_ADD(block, DRC_PC, DRC_PC, 2);
1079 }
1080
1081 /* Get relative address */
1082
drctg0a_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1083 void arm7_cpu_device::drctg0a_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADD Rd, PC, #nn */
1084 {
1085 uint32_t op = desc->opptr.l[0];
1086 uint32_t rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
1087 int32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
1088 UML_ADD(block, uml::I0, DRC_PC, 4);
1089 UML_AND(block, uml::I0, uml::I0, ~2);
1090 UML_ADD(block, DRC_REG(rd), uml::I0, offs);
1091 UML_ADD(block, DRC_PC, DRC_PC, 2);
1092 }
1093
drctg0a_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1094 void arm7_cpu_device::drctg0a_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADD Rd, SP, #nn */
1095 {
1096 uint32_t op = desc->opptr.l[0];
1097 uint32_t rd = (op & THUMB_RELADDR_RD) >> THUMB_RELADDR_RD_SHIFT;
1098 int32_t offs = (uint8_t)(op & THUMB_INSN_IMM) << 2;
1099 UML_ADD(block, DRC_REG(rd), DRC_REG(13), offs);
1100 UML_ADD(block, DRC_PC, DRC_PC, 2);
1101 }
1102
1103 /* Stack-Related Opcodes */
1104
drctg0b_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1105 void arm7_cpu_device::drctg0b_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* ADD SP, #imm */
1106 {
1107 uint32_t op = desc->opptr.l[0];
1108 int32_t addr = (op & THUMB_INSN_IMM);
1109 addr &= ~THUMB_INSN_IMM_S;
1110 addr = ((op & THUMB_INSN_IMM_S) ? -(addr << 2) : (addr << 2));
1111 UML_ADD(block, DRC_REG(13), DRC_REG(13), addr);
1112 UML_ADD(block, DRC_PC, DRC_PC, 2);
1113 }
1114
drctg0b_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1115 void arm7_cpu_device::drctg0b_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1116 {
1117 uint32_t op = desc->opptr.l[0];
1118 uint32_t pc = desc->pc;
1119 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1120 }
1121
drctg0b_2(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1122 void arm7_cpu_device::drctg0b_2(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1123 {
1124 uint32_t op = desc->opptr.l[0];
1125 uint32_t pc = desc->pc;
1126 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1127 }
1128
drctg0b_3(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1129 void arm7_cpu_device::drctg0b_3(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1130 {
1131 uint32_t op = desc->opptr.l[0];
1132 uint32_t pc = desc->pc;
1133 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1134 }
1135
drctg0b_4(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1136 void arm7_cpu_device::drctg0b_4(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* PUSH {Rlist} */
1137 {
1138 uint32_t op = desc->opptr.l[0];
1139 for (int32_t offs = 7; offs >= 0; offs--)
1140 {
1141 if (op & (1 << offs))
1142 {
1143 UML_SUB(block, DRC_REG(13), DRC_REG(13), 4);
1144 UML_MOV(block, uml::I0, DRC_REG(13));
1145 UML_MOV(block, uml::I1, DRC_REG(offs));
1146 UML_CALLH(block, *m_impstate.write32);
1147 }
1148 }
1149 UML_ADD(block, DRC_PC, DRC_PC, 2);
1150 }
1151
drctg0b_5(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1152 void arm7_cpu_device::drctg0b_5(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* PUSH {Rlist}{LR} */
1153 {
1154 uint32_t op = desc->opptr.l[0];
1155 UML_SUB(block, DRC_REG(13), DRC_REG(13), 4);
1156 UML_MOV(block, uml::I0, DRC_REG(13));
1157 UML_MOV(block, uml::I1, DRC_REG(14));
1158 UML_CALLH(block, *m_impstate.write32);
1159 for (int32_t offs = 7; offs >= 0; offs--)
1160 {
1161 if (op & (1 << offs))
1162 {
1163 UML_SUB(block, DRC_REG(13), DRC_REG(13), 4);
1164 UML_MOV(block, uml::I0, DRC_REG(13));
1165 UML_MOV(block, uml::I1, DRC_REG(offs));
1166 UML_CALLH(block, *m_impstate.write32);
1167 }
1168 }
1169 UML_ADD(block, DRC_PC, DRC_PC, 2);
1170 }
1171
drctg0b_6(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1172 void arm7_cpu_device::drctg0b_6(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1173 {
1174 uint32_t op = desc->opptr.l[0];
1175 uint32_t pc = desc->pc;
1176 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1177 }
1178
drctg0b_7(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1179 void arm7_cpu_device::drctg0b_7(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1180 {
1181 uint32_t op = desc->opptr.l[0];
1182 uint32_t pc = desc->pc;
1183 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1184 }
1185
drctg0b_8(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1186 void arm7_cpu_device::drctg0b_8(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1187 {
1188 uint32_t op = desc->opptr.l[0];
1189 uint32_t pc = desc->pc;
1190 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1191 }
1192
drctg0b_9(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1193 void arm7_cpu_device::drctg0b_9(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1194 {
1195 uint32_t op = desc->opptr.l[0];
1196 uint32_t pc = desc->pc;
1197 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1198 }
1199
drctg0b_a(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1200 void arm7_cpu_device::drctg0b_a(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1201 {
1202 uint32_t op = desc->opptr.l[0];
1203 uint32_t pc = desc->pc;
1204 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1205 }
1206
drctg0b_b(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1207 void arm7_cpu_device::drctg0b_b(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1208 {
1209 uint32_t op = desc->opptr.l[0];
1210 uint32_t pc = desc->pc;
1211 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1212 }
1213
drctg0b_c(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1214 void arm7_cpu_device::drctg0b_c(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* POP {Rlist} */
1215 {
1216 uint32_t op = desc->opptr.l[0];
1217 for (int32_t offs = 0; offs < 8; offs++)
1218 {
1219 if (op & (1 << offs))
1220 {
1221 UML_MOV(block, uml::I0, DRC_REG(13));
1222 UML_CALLH(block, *m_impstate.read32);
1223 UML_MOV(block, DRC_REG(offs), uml::I0);
1224 UML_ADD(block, DRC_REG(13), DRC_REG(13), 4);
1225 }
1226 }
1227 UML_ADD(block, DRC_PC, DRC_PC, 2);
1228 }
1229
drctg0b_d(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1230 void arm7_cpu_device::drctg0b_d(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* POP {Rlist}{PC} */
1231 {
1232 uint32_t op = desc->opptr.l[0];
1233 uml::code_label arch5up;
1234 uml::code_label done;
1235 uml::code_label switch_mode;
1236 for (int32_t offs = 0; offs < 8; offs++)
1237 {
1238 if (op & (1 << offs))
1239 {
1240 UML_MOV(block, uml::I0, DRC_REG(13));
1241 UML_CALLH(block, *m_impstate.read32);
1242 UML_MOV(block, DRC_REG(offs), uml::I0);
1243 UML_ADD(block, DRC_REG(13), DRC_REG(13), 4);
1244 }
1245 }
1246 UML_MOV(block, uml::I0, DRC_REG(13));
1247 UML_CALLH(block, *m_impstate.read32);
1248 UML_CMP(block, uml::mem(&m_archRev), 4);
1249 UML_JMPc(block, uml::COND_A, arch5up = compiler.labelnum++);
1250 UML_AND(block, DRC_PC, uml::I0, ~1);
1251
1252 UML_LABEL(block, arch5up);
1253
1254 UML_TEST(block, uml::I0, 1);
1255 UML_JMPc(block, uml::COND_Z, switch_mode = compiler.labelnum++);
1256
1257 UML_AND(block, uml::I0, uml::I0, ~1);
1258 UML_MOV(block, DRC_PC, uml::I0);
1259 UML_JMP(block, done);
1260
1261 UML_LABEL(block, switch_mode);
1262 UML_AND(block, DRC_CPSR, DRC_CPSR, ~T_MASK);
1263 UML_TEST(block, uml::I0, 2);
1264 UML_MOVc(block, uml::COND_NZ, uml::I1, 2);
1265 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
1266 UML_ADD(block, uml::I0, uml::I0, uml::I1);
1267 UML_MOV(block, DRC_PC, uml::I0);
1268
1269 UML_LABEL(block, done);
1270 UML_ADD(block, DRC_REG(13), DRC_REG(13), 4);
1271 }
1272
drctg0b_e(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1273 void arm7_cpu_device::drctg0b_e(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1274 {
1275 uint32_t op = desc->opptr.l[0];
1276 uint32_t pc = desc->pc;
1277 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1278 }
1279
drctg0b_f(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1280 void arm7_cpu_device::drctg0b_f(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1281 {
1282 uint32_t op = desc->opptr.l[0];
1283 uint32_t pc = desc->pc;
1284 fatalerror("%08x: Gb Undefined Thumb instruction: %04x\n", pc, op);
1285 }
1286
1287 /* Multiple Load/Store */
1288
1289 // "The address should normally be a word aligned quantity and non-word aligned addresses do not affect the instruction."
1290 // "However, the bottom 2 bits of the address will appear on A[1:0] and might be interpreted by the memory system."
1291
1292 // GBA "BB Ball" performs an unaligned read with A[1:0] = 2 and expects A[1] not to be ignored [BP 800B90A,(R4&3)!=0]
1293 // GBA "Gadget Racers" performs an unaligned read with A[1:0] = 1 and expects A[0] to be ignored [BP B72,(R0&3)!=0]
1294
drctg0c_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1295 void arm7_cpu_device::drctg0c_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Store */
1296 {
1297 uint32_t op = desc->opptr.l[0];
1298 uint32_t rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
1299 UML_MOV(block, uml::I2, DRC_REG(rd));
1300 for (int32_t offs = 0; offs < 8; offs++)
1301 {
1302 if (op & (1 << offs))
1303 {
1304 UML_AND(block, uml::I0, uml::I2, ~3);
1305 UML_MOV(block, uml::I1, DRC_REG(offs));
1306 UML_CALLH(block, *m_impstate.write32);
1307 UML_ADD(block, uml::I2, uml::I2, 4);
1308 }
1309 }
1310 UML_MOV(block, DRC_REG(rd), uml::I2);
1311 UML_ADD(block, DRC_PC, DRC_PC, 2);
1312 }
1313
drctg0c_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1314 void arm7_cpu_device::drctg0c_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* Load */
1315 {
1316 uint32_t op = desc->opptr.l[0];
1317 uint32_t rd = (op & THUMB_MULTLS_BASE) >> THUMB_MULTLS_BASE_SHIFT;
1318 int rd_in_list = op & (1 << rd);
1319 UML_MOV(block, uml::I2, DRC_REG(rd));
1320 for (int32_t offs = 0; offs < 8; offs++)
1321 {
1322 if (op & (1 << offs))
1323 {
1324 UML_AND(block, uml::I0, uml::I2, ~1);
1325 UML_CALLH(block, *m_impstate.read32);
1326 UML_ADD(block, uml::I2, uml::I2, 4);
1327 }
1328 }
1329 if (!rd_in_list)
1330 {
1331 UML_MOV(block, DRC_REG(rd), uml::I2);
1332 }
1333 UML_ADD(block, DRC_PC, DRC_PC, 2);
1334 }
1335
1336 /* Conditional Branch */
1337
drctg0d_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1338 void arm7_cpu_device::drctg0d_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_EQ:
1339 {
1340 uint32_t op = desc->opptr.l[0];
1341 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1342 UML_TEST(block, DRC_CPSR, Z_MASK);
1343 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1344 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1345 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1346 }
1347
drctg0d_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1348 void arm7_cpu_device::drctg0d_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_NE:
1349 {
1350 uint32_t op = desc->opptr.l[0];
1351 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1352 UML_TEST(block, DRC_CPSR, Z_MASK);
1353 UML_MOVc(block, uml::COND_Z, uml::I0, offs);
1354 UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
1355 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1356 }
1357
drctg0d_2(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1358 void arm7_cpu_device::drctg0d_2(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_CS:
1359 {
1360 uint32_t op = desc->opptr.l[0];
1361 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1362 UML_TEST(block, DRC_CPSR, C_MASK);
1363 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1364 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1365 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1366 }
1367
drctg0d_3(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1368 void arm7_cpu_device::drctg0d_3(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_CC:
1369 {
1370 uint32_t op = desc->opptr.l[0];
1371 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1372 UML_TEST(block, DRC_CPSR, C_MASK);
1373 UML_MOVc(block, uml::COND_Z, uml::I0, offs);
1374 UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
1375 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1376 }
1377
drctg0d_4(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1378 void arm7_cpu_device::drctg0d_4(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_MI:
1379 {
1380 uint32_t op = desc->opptr.l[0];
1381 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1382 UML_TEST(block, DRC_CPSR, N_MASK);
1383 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1384 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1385 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1386 }
1387
drctg0d_5(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1388 void arm7_cpu_device::drctg0d_5(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_PL:
1389 {
1390 uint32_t op = desc->opptr.l[0];
1391 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1392 UML_TEST(block, DRC_CPSR, N_MASK);
1393 UML_MOVc(block, uml::COND_Z, uml::I0, offs);
1394 UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
1395 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1396 }
1397
drctg0d_6(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1398 void arm7_cpu_device::drctg0d_6(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_VS:
1399 {
1400 uint32_t op = desc->opptr.l[0];
1401 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1402 UML_TEST(block, DRC_CPSR, V_MASK);
1403 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1404 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1405 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1406 }
1407
drctg0d_7(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1408 void arm7_cpu_device::drctg0d_7(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_VC:
1409 {
1410 uint32_t op = desc->opptr.l[0];
1411 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1412 UML_TEST(block, DRC_CPSR, V_MASK);
1413 UML_MOVc(block, uml::COND_Z, uml::I0, offs);
1414 UML_MOVc(block, uml::COND_NZ, uml::I0, 2);
1415 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1416 }
1417
drctg0d_8(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1418 void arm7_cpu_device::drctg0d_8(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_HI:
1419 {
1420 uint32_t op = desc->opptr.l[0];
1421 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1422 UML_TEST(block, DRC_CPSR, C_MASK);
1423 UML_MOVc(block, uml::COND_NZ, uml::I0, 1);
1424 UML_MOVc(block, uml::COND_Z, uml::I0, 0);
1425 UML_TEST(block, DRC_CPSR, Z_MASK);
1426 UML_MOVc(block, uml::COND_NZ, uml::I1, 0);
1427 UML_MOVc(block, uml::COND_Z, uml::I1, 1);
1428 UML_AND(block, uml::I0, uml::I0, uml::I1);
1429 UML_TEST(block, uml::I0, 1);
1430 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1431 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1432 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1433 }
1434
drctg0d_9(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1435 void arm7_cpu_device::drctg0d_9(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_LS:
1436 {
1437 uint32_t op = desc->opptr.l[0];
1438 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1439 UML_TEST(block, DRC_CPSR, C_MASK);
1440 UML_MOVc(block, uml::COND_Z, uml::I0, 1);
1441 UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1442 UML_TEST(block, DRC_CPSR, Z_MASK);
1443 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
1444 UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
1445 UML_AND(block, uml::I0, uml::I0, uml::I1);
1446 UML_TEST(block, uml::I0, 1);
1447 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1448 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1449 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1450 }
1451
drctg0d_a(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1452 void arm7_cpu_device::drctg0d_a(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_GE:
1453 {
1454 uint32_t op = desc->opptr.l[0];
1455 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1456 UML_TEST(block, DRC_CPSR, N_MASK);
1457 UML_MOVc(block, uml::COND_Z, uml::I0, 1);
1458 UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1459 UML_TEST(block, DRC_CPSR, V_MASK);
1460 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
1461 UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
1462 UML_CMP(block, uml::I0, uml::I1);
1463 UML_MOVc(block, uml::COND_E, uml::I0, offs);
1464 UML_MOVc(block, uml::COND_NE, uml::I0, 2);
1465 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1466 }
1467
drctg0d_b(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1468 void arm7_cpu_device::drctg0d_b(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_LT:
1469 {
1470 uint32_t op = desc->opptr.l[0];
1471 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1472 UML_TEST(block, DRC_CPSR, N_MASK);
1473 UML_MOVc(block, uml::COND_Z, uml::I0, 1);
1474 UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1475 UML_TEST(block, DRC_CPSR, V_MASK);
1476 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
1477 UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
1478 UML_CMP(block, uml::I0, uml::I1);
1479 UML_MOVc(block, uml::COND_NE, uml::I0, offs);
1480 UML_MOVc(block, uml::COND_E, uml::I0, 2);
1481 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1482 }
1483
drctg0d_c(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1484 void arm7_cpu_device::drctg0d_c(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_GT:
1485 {
1486 uint32_t op = desc->opptr.l[0];
1487 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1488 UML_TEST(block, DRC_CPSR, N_MASK);
1489 UML_MOVc(block, uml::COND_Z, uml::I0, 1);
1490 UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1491 UML_TEST(block, DRC_CPSR, V_MASK);
1492 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
1493 UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
1494 UML_CMP(block, uml::I0, uml::I1);
1495 UML_MOVc(block, uml::COND_E, uml::I0, 1);
1496 UML_MOVc(block, uml::COND_NE, uml::I0, 0);
1497 UML_TEST(block, DRC_CPSR, Z_MASK);
1498 UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
1499 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
1500 UML_AND(block, uml::I0, uml::I0, uml::I1);
1501 UML_TEST(block, uml::I0, 1);
1502 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1503 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1504 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1505 }
1506
drctg0d_d(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1507 void arm7_cpu_device::drctg0d_d(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_LE:
1508 {
1509 uint32_t op = desc->opptr.l[0];
1510 int32_t offs = ((int8_t)(op & THUMB_INSN_IMM) << 1) + 4;
1511 UML_TEST(block, DRC_CPSR, N_MASK);
1512 UML_MOVc(block, uml::COND_Z, uml::I0, 1);
1513 UML_MOVc(block, uml::COND_NZ, uml::I0, 0);
1514 UML_TEST(block, DRC_CPSR, V_MASK);
1515 UML_MOVc(block, uml::COND_Z, uml::I1, 0);
1516 UML_MOVc(block, uml::COND_NZ, uml::I1, 1);
1517 UML_CMP(block, uml::I0, uml::I1);
1518 UML_MOVc(block, uml::COND_NE, uml::I0, 1);
1519 UML_MOVc(block, uml::COND_E, uml::I0, 0);
1520 UML_TEST(block, DRC_CPSR, Z_MASK);
1521 UML_MOVc(block, uml::COND_NZ, uml::I1, 0);
1522 UML_MOVc(block, uml::COND_Z, uml::I1, 1);
1523 UML_AND(block, uml::I0, uml::I0, uml::I1);
1524 UML_TEST(block, uml::I0, 1);
1525 UML_MOVc(block, uml::COND_NZ, uml::I0, offs);
1526 UML_MOVc(block, uml::COND_Z, uml::I0, 2);
1527 UML_ADD(block, DRC_PC, DRC_PC, uml::I0);
1528 }
1529
drctg0d_e(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1530 void arm7_cpu_device::drctg0d_e(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // COND_AL:
1531 {
1532 uint32_t op = desc->opptr.l[0];
1533 uint32_t pc = desc->pc;
1534 fatalerror("%08x: Undefined Thumb instruction: %04x (ARM9 reserved)\n", pc, op);
1535 }
1536
drctg0d_f(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1537 void arm7_cpu_device::drctg0d_f(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) // SWI (this is sort of a "hole" in the opcode encoding)
1538 {
1539 UML_MOV(block, uml::mem(&m_pendingSwi), 1);
1540 UML_CALLH(block, *m_impstate.check_irq);
1541 }
1542
1543 /* B #offs */
1544
drctg0e_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1545 void arm7_cpu_device::drctg0e_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1546 {
1547 uint32_t op = desc->opptr.l[0];
1548 int32_t offs = (op & THUMB_BRANCH_OFFS) << 1;
1549 if (offs & 0x00000800)
1550 {
1551 offs |= 0xfffff800;
1552 }
1553 UML_ADD(block, DRC_PC, DRC_PC, offs + 4);
1554 }
1555
drctg0e_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1556 void arm7_cpu_device::drctg0e_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1557 {
1558 uint32_t op = desc->opptr.l[0];
1559 uint32_t offs = (op & THUMB_BLOP_OFFS) << 1;
1560 UML_MOV(block, uml::I0, DRC_REG(14));
1561 UML_ADD(block, uml::I0, uml::I0, offs);
1562 UML_AND(block, uml::I0, uml::I0, ~3);
1563 UML_ADD(block, DRC_REG(14), DRC_PC, 4);
1564 UML_OR(block, DRC_REG(14), DRC_REG(14), 1);
1565 UML_MOV(block, DRC_PC, uml::I0);
1566 }
1567
1568 /* BL */
1569
drctg0f_0(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1570 void arm7_cpu_device::drctg0f_0(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc)
1571 {
1572 uint32_t op = desc->opptr.l[0];
1573 uint32_t addr = (op & THUMB_BLOP_OFFS) << 12;
1574 if (addr & (1 << 22))
1575 {
1576 addr |= 0xff800000;
1577 }
1578 addr += 4;
1579 UML_ADD(block, DRC_REG(14), DRC_PC, addr);
1580 UML_ADD(block, DRC_PC, DRC_PC, 2);
1581 }
1582
drctg0f_1(drcuml_block & block,compiler_state & compiler,const opcode_desc * desc)1583 void arm7_cpu_device::drctg0f_1(drcuml_block &block, compiler_state &compiler, const opcode_desc *desc) /* BL */
1584 {
1585 uint32_t op = desc->opptr.l[0];
1586 uint32_t addr = (op & THUMB_BLOP_OFFS) << 1;
1587 UML_AND(block, uml::I0, DRC_REG(14), ~1);
1588 UML_ADD(block, uml::I0, uml::I0, addr);
1589 UML_ADD(block, DRC_REG(14), DRC_PC, 2);
1590 UML_OR(block, DRC_REG(14), DRC_REG(14), 1);
1591 UML_MOV(block, DRC_PC, uml::I0);
1592 }
1593