1 // license:BSD-3-Clause 2 // copyright-holders:R. Belmont 3 #pragma once 4 5 #ifndef __SH4REGS_H__ 6 #define __SH4REGS_H__ 7 8 /* 00000001111111100000000011111100 */ 9 #define PTEH 0x2000 /* FF000000 */ 10 #define PTEL 0x2001 /* FF000004 */ 11 #define TTB 0x2002 /* FF000008 */ 12 #define TEA 0x2003 /* FF00000C */ 13 #define MMUCR 0x2004 /* FF000010 */ 14 #define BASRA 0x2005 /* FF000014 */ 15 #define BASRB 0x2006 /* FF000018 */ 16 #define CCR 0x2007 /* FF00001C */ 17 #define TRA 0x2008 /* FF000020 */ 18 #define EXPEVT 0x2009 /* FF000024 */ 19 #define INTEVT 0x200A /* FF000028 */ 20 #define VERSION 0x200C /* FF000030 */ 21 #define PTEA 0x200D /* FF000034 */ 22 #define QACR0 0x200E /* FF000038 */ 23 #define QACR1 0x200F /* FF00003C */ 24 #define PRR 0x2011 /* FF000044 */ 25 #define BARA 0x2400 /* FF200000 */ 26 #define BAMRA 0x2401 /* FF200004 */ 27 #define BBRA 0x2402 /* FF200008 */ 28 #define BARB 0x2403 /* FF20000C */ 29 #define BAMRB 0x2404 /* FF200010 */ 30 #define BBRB 0x2405 /* FF200014 */ 31 #define BDRB 0x2406 /* FF200018 */ 32 #define BDMRB 0x2407 /* FF20001C */ 33 #define BRCR 0x2408 /* FF200020 */ 34 #define BCR1 0x3000 /* FF800000 */ 35 #define BCR2 0x3001 /* FF800004 */ 36 #define BCR3 0x3014 /* FF800050 */ 37 #define BCR4 0x17C /* FE0A00F0 */ 38 #define WCR1 0x3002 /* FF800008 */ 39 #define WCR2 0x3003 /* FF80000C */ 40 #define WCR3 0x3004 /* FF800010 */ 41 #define MCR 0x3005 /* FF800014 */ 42 #define PCR 0x3006 /* FF800018 */ 43 #define RTCSR 0x3007 /* FF80001C */ 44 #define RTCNT 0x3008 /* FF800020 */ 45 #define RTCOR 0x3009 /* FF800024 */ 46 #define RFCR 0x300A /* FF800028 */ 47 #define PCTRA 0x300B /* FF80002C */ 48 #define PDTRA 0x300C /* FF800030 */ 49 #define PCTRB 0x3010 /* FF800040 */ 50 #define PDTRB 0x3011 /* FF800044 */ 51 #define GPIOIC 0x3012 /* FF800048 */ 52 #define SDMR2 0x3200 /* FF900000 */ 53 #define SDMR3 0x3280 /* FF940000 */ 54 #define SH4_SAR0_ADDR 0x3400 /* FFA00000 */ 55 #define SH4_DAR0_ADDR 0x3401 /* FFA00004 */ 56 #define SH4_DMATCR0_ADDR 0x3402 /* FFA00008 */ 57 #define SH4_CHCR0_ADDR 0x3403 /* FFA0000C */ 58 #define SH4_SAR1_ADDR 0x3404 /* FFA00010 */ 59 #define SH4_DAR1_ADDR 0x3405 /* FFA00014 */ 60 #define SH4_DMATCR1_ADDR 0x3406 /* FFA00018 */ 61 #define SH4_CHCR1_ADDR 0x3407 /* FFA0001C */ 62 #define SH4_SAR2_ADDR 0x3408 /* FFA00020 */ 63 #define SH4_DAR2_ADDR 0x3409 /* FFA00024 */ 64 #define SH4_DMATCR2_ADDR 0x340A /* FFA00028 */ 65 #define SH4_CHCR2_ADDR 0x340B /* FFA0002C */ 66 #define SH4_SAR3_ADDR 0x340C /* FFA00030 */ 67 #define SH4_DAR3_ADDR 0x340D /* FFA00034 */ 68 #define SH4_DMATCR3_ADDR 0x340E /* FFA00038 */ 69 #define SH4_CHCR3_ADDR 0x340F /* FFA0003C */ 70 #define SH4_DMAOR_ADDR 0x3410 /* FFA00040 */ 71 #define SAR4 0x3414 /* FFA00050 */ 72 #define DAR4 0x3415 /* FFA00054 */ 73 #define DMATCR4 0x3416 /* FFA00058 */ 74 #define CHCR4 0x3417 /* FFA0005C */ 75 #define SAR5 0x3418 /* FFA00060 */ 76 #define DAR5 0x3419 /* FFA00064 */ 77 #define DMATCR5 0x341A /* FFA00068 */ 78 #define CHCR5 0x341B /* FFA0006C */ 79 #define SAR6 0x341C /* FFA00070 */ 80 #define DAR6 0x341D /* FFA00074 */ 81 #define DMATCR6 0x341E /* FFA00078 */ 82 #define CHCR6 0x341F /* FFA0007C */ 83 #define SAR7 0x3420 /* FFA00080 */ 84 #define DAR7 0x3421 /* FFA00084 */ 85 #define DMATCR7 0x3422 /* FFA00088 */ 86 #define CHCR7 0x3423 /* FFA0008C */ 87 #define FRQCR 0x3800 /* FFC00000 */ 88 #define STBCR 0x3801 /* FFC00004 */ 89 #define WTCNT 0x3802 /* FFC00008 */ 90 #define WTCSR 0x3803 /* FFC0000C */ 91 #define STBCR2 0x3804 /* FFC00010 */ 92 #define R64CNT 0x3900 /* FFC80000 */ 93 #define RSECCNT 0x3901 /* FFC80004 */ 94 #define RMINCNT 0x3902 /* FFC80008 */ 95 #define RHRCNT 0x3903 /* FFC8000C */ 96 #define RWKCNT 0x3904 /* FFC80010 */ 97 #define RDAYCNT 0x3905 /* FFC80014 */ 98 #define RMONCNT 0x3906 /* FFC80018 */ 99 #define RYRCNT 0x3907 /* FFC8001C */ 100 #define RSECAR 0x3908 /* FFC80020 */ 101 #define RMINAR 0x3909 /* FFC80024 */ 102 #define RHRAR 0x390A /* FFC80028 */ 103 #define RWKAR 0x390B /* FFC8002C */ 104 #define RDAYAR 0x390C /* FFC80030 */ 105 #define RMONAR 0x390D /* FFC80034 */ 106 #define RCR1 0x390E /* FFC80038 */ 107 #define RCR2 0x390F /* FFC8003C */ 108 #define RCR3 0x3914 /* FFC80050 */ 109 #define RYRAR 0x3915 /* FFC80054 */ 110 #define ICR 0x3A00 /* FFD00000 */ 111 #define IPRA 0x3A01 /* FFD00004 */ 112 #define IPRB 0x3A02 /* FFD00008 */ 113 #define IPRC 0x3A03 /* FFD0000C */ 114 #define IPRD 0x3A04 /* FFD00010 */ 115 #define INTPRI00 0x100 /* FE080000 */ 116 #define INTREQ00 0x108 /* FE080020 */ 117 #define INTMSK00 0x110 /* FE080040 */ 118 #define INTMSKCLR00 0x118 /* FE080060 */ 119 #define CLKSTP00 0x140 /* FE0A0000 */ 120 #define CLKSTPCLR00 0x142 /* FE0A0008 */ 121 #define TSTR2 0x201 /* FE100004 */ 122 #define TCOR3 0x202 /* FE100008 */ 123 #define TCNT3 0x203 /* FE10000C */ 124 #define TCR3 0x204 /* FE100010 */ 125 #define TCOR4 0x205 /* FE100014 */ 126 #define TCNT4 0x206 /* FE100018 */ 127 #define TCR4 0x207 /* FE10001C */ 128 #define SH4_TOCR_ADDR 0x3B00 /* FFD80000 */ 129 #define SH4_TSTR_ADDR 0x3B01 /* FFD80004 */ 130 #define SH4_TCOR0_ADDR 0x3B02 /* FFD80008 */ 131 #define SH4_TCNT0_ADDR 0x3B03 /* FFD8000C */ 132 #define SH4_TCR0_ADDR 0x3B04 /* FFD80010 */ 133 #define SH4_TCOR1_ADDR 0x3B05 /* FFD80014 */ 134 #define SH4_TCNT1_ADDR 0x3B06 /* FFD80018 */ 135 #define SH4_TCR1_ADDR 0x3B07 /* FFD8001C */ 136 #define SH4_TCOR2_ADDR 0x3B08 /* FFD80020 */ 137 #define SH4_TCNT2_ADDR 0x3B09 /* FFD80024 */ 138 #define SH4_TCR2_ADDR 0x3B0A /* FFD80028 */ 139 #define SH4_TCPR2_ADDR 0x3B0B /* FFD8002C */ 140 #define SCSMR1 0x3C00 /* FFE00000 */ 141 #define SCBRR1 0x3C01 /* FFE00004 */ 142 #define SCSCR1 0x3C02 /* FFE00008 */ 143 #define SCTDR1 0x3C03 /* FFE0000C */ 144 #define SCSSR1 0x3C04 /* FFE00010 */ 145 #define SCRDR1 0x3C05 /* FFE00014 */ 146 #define SCSCMR1 0x3C06 /* FFE00018 */ 147 #define SCSPTR1 0x3C07 /* FFE0001C */ 148 #define SCSMR2 0x3D00 /* FFE80000 */ 149 #define SCBRR2 0x3D01 /* FFE80004 */ 150 #define SCSCR2 0x3D02 /* FFE80008 */ 151 #define SCFTDR2 0x3D03 /* FFE8000C */ 152 #define SCFSR2 0x3D04 /* FFE80010 */ 153 #define SCFRDR2 0x3D05 /* FFE80014 */ 154 #define SCFCR2 0x3D06 /* FFE80018 */ 155 #define SCFDR2 0x3D07 /* FFE8001C */ 156 #define SCSPTR2 0x3D08 /* FFE80020 */ 157 #define SCLSR2 0x3D09 /* FFE80024 */ 158 #define SDIR 0x3E00 /* FFF00000 */ 159 #define SDDR 0x3E02 /* FFF00008 */ 160 #define SDINT 0x3E05 /* FFF00014 */ 161 #define SIZEREGS 15878 162 163 164 165 #define MMUCR_LRUI 0xfc000000 166 #define MMUCR_URB 0x00fc0000 167 #define MMUCR_URC 0x0000fc00 168 #define MMUCR_SQMD 0x00000200 169 #define MMUCR_SV 0x00000100 170 #define MMUCR_TI 0x00000004 171 #define MMUCR_AT 0x00000001 172 173 /* constants */ 174 #define PVR_SH7091 0x040205c1 175 #define PVR_SH7750 0x04020500 // from TN-SH7-361B/E 176 #define PVR_SH7750S 0x04020600 177 #define PVR_SH7750R 0x04050000 178 #define PRR_SH7750R 0x00000100 179 #define PVR_SH7751 0x04110000 180 #define PVR_SH7751R 0x04050000 181 #define PRR_SH7751R 0x00000110 182 183 #endif /* __SH4REGS_H__ */ 184