1 // license:BSD-3-Clause
2 // copyright-holders:Wilbert Pol
3 /*******************************************************************
4
5 TLCS-900 instruction set
6
7 *******************************************************************/
8
9
10 enum e_operand
11 {
12 p_A=1, /* current register set register A */
13 p_C8, /* current register set byte */
14 p_C16, /* current register set word */
15 p_C32, /* current register set long word */
16 p_MC16, /* current register set mul/div register word */
17 p_CC, /* condition */
18 p_CR8,
19 p_CR16,
20 p_CR32,
21 p_D8, /* byte displacement */
22 p_D16, /* word displacement */
23 p_F, /* F register */
24 p_I3, /* immediate 3 bit (part of last byte) */
25 p_I8, /* immediate byte */
26 p_I16, /* immediate word */
27 p_I24, /* immediate 3 byte address */
28 p_I32, /* immediate long word */
29 p_M, /* memory location (defined by extension) */
30 p_M8, /* (8) */
31 p_M16, /* (i16) */
32 p_R, /* register (defined by extension) */
33 p_SR /* status register */
34 };
35
36
condition_true(uint8_t cond)37 int tlcs900_device::condition_true( uint8_t cond )
38 {
39 switch ( cond & 0x0f )
40 {
41 /* F */
42 case 0x00:
43 return 0;
44
45 /* LT */
46 case 0x01:
47 return ( ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
48 ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) );
49
50 /* LE */
51 case 0x02:
52 return ( ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
53 ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) ||
54 ( m_sr.b.l & FLAG_ZF ) );
55
56 /* ULE */
57 case 0x03:
58 return ( m_sr.b.l & ( FLAG_ZF | FLAG_CF ) );
59
60 /* OV */
61 case 0x04:
62 return ( m_sr.b.l & FLAG_VF );
63
64 /* MI */
65 case 0x05:
66 return ( m_sr.b.l & FLAG_SF );
67
68 /* Z */
69 case 0x06:
70 return ( m_sr.b.l & FLAG_ZF );
71
72 /* C */
73 case 0x07:
74 return ( m_sr.b.l & FLAG_CF );
75
76 /* T */
77 case 0x08:
78 return 1;
79
80 /* GE */
81 case 0x09:
82 return ! ( ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
83 ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) );
84
85 /* GT */
86 case 0x0A:
87 return ! ( ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_SF ) ||
88 ( ( m_sr.b.l & ( FLAG_SF | FLAG_VF ) ) == FLAG_VF ) ||
89 ( m_sr.b.l & FLAG_ZF ) );
90
91 /* UGT */
92 case 0x0B:
93 return ! ( m_sr.b.l & ( FLAG_ZF | FLAG_CF ) );
94
95 /* NOV */
96 case 0x0C:
97 return ! ( m_sr.b.l & FLAG_VF );
98
99 /* PL */
100 case 0x0D:
101 return ! ( m_sr.b.l & FLAG_SF );
102
103 /* NZ */
104 case 0x0E:
105 return ! ( m_sr.b.l & FLAG_ZF );
106
107 /* NC */
108 case 0x0F:
109 return ! ( m_sr.b.l & FLAG_CF );
110 }
111 return 0;
112 }
113
114
get_reg8_current(uint8_t reg)115 uint8_t* tlcs900_device::get_reg8_current( uint8_t reg )
116 {
117 switch( reg & 7 )
118 {
119 /* W */
120 case 0:
121 return &m_xwa[m_regbank].b.h;
122
123 /* A */
124 case 1:
125 return &m_xwa[m_regbank].b.l;
126
127 /* B */
128 case 2:
129 return &m_xbc[m_regbank].b.h;
130
131 /* C */
132 case 3:
133 return &m_xbc[m_regbank].b.l;
134
135 /* D */
136 case 4:
137 return &m_xde[m_regbank].b.h;
138
139 /* E */
140 case 5:
141 return &m_xde[m_regbank].b.l;
142
143 /* H */
144 case 6:
145 return &m_xhl[m_regbank].b.h;
146
147 /* L */
148 case 7:
149 return &m_xhl[m_regbank].b.l;
150 }
151 /* keep compiler happy */
152 return &m_dummy.b.l;
153 }
154
155
get_reg16_current(uint8_t reg)156 uint16_t* tlcs900_device::get_reg16_current( uint8_t reg )
157 {
158 switch( reg & 7 )
159 {
160 /* WA */
161 case 0:
162 return &m_xwa[m_regbank].w.l;
163
164 /* BC */
165 case 1:
166 return &m_xbc[m_regbank].w.l;
167
168 /* DE */
169 case 2:
170 return &m_xde[m_regbank].w.l;
171
172 /* HL */
173 case 3:
174 return &m_xhl[m_regbank].w.l;
175
176 /* IX */
177 case 4:
178 return &m_xix.w.l;
179
180 /* IY */
181 case 5:
182 return &m_xiy.w.l;
183
184 /* IZ */
185 case 6:
186 return &m_xiz.w.l;
187
188 /* SP */
189 /* TODO: Use correct user/system SP */
190 case 7:
191 return &m_xssp.w.l;
192 }
193 /* keep compiler happy */
194 return &m_dummy.w.l;
195 }
196
197
get_reg32_current(uint8_t reg)198 uint32_t* tlcs900_device::get_reg32_current( uint8_t reg )
199 {
200 switch( reg & 7 )
201 {
202 /* XWA */
203 case 0:
204 return &m_xwa[m_regbank].d;
205
206 /* XBC */
207 case 1:
208 return &m_xbc[m_regbank].d;
209
210 /* XDE */
211 case 2:
212 return &m_xde[m_regbank].d;
213
214 /* XHL */
215 case 3:
216 return &m_xhl[m_regbank].d;
217
218 /* XIX */
219 case 4:
220 return &m_xix.d;
221
222 /* XIY */
223 case 5:
224 return &m_xiy.d;
225
226 /* XIZ */
227 case 6:
228 return &m_xiz.d;
229
230 /* XSP */
231 case 7:
232 /* TODO: Add selector for user/system stack pointer */
233 return &m_xssp.d;
234 }
235 /* keep compiler happy */
236 return &m_dummy.d;
237 }
238
239
get_reg(uint8_t reg)240 PAIR* tlcs900_device::get_reg( uint8_t reg )
241 {
242 uint8_t regbank;
243
244 switch( reg & 0xf0 )
245 {
246 case 0x00: case 0x10: case 0x20: case 0x30: /* explicit register bank */
247 case 0xd0: /* "previous" register bank */
248 case 0xe0: /* current register bank */
249 regbank = ( reg & 0xf0 ) >> 4;
250 if ( regbank == 0x0d )
251 regbank = ( m_regbank - 1 ) & 0x03;
252
253 if ( regbank == 0x0e )
254 regbank = m_regbank;
255
256 switch ( reg & 0x0c )
257 {
258 case 0x00: return &m_xwa[regbank];
259 case 0x04: return &m_xbc[regbank];
260 case 0x08: return &m_xde[regbank];
261 case 0x0c: return &m_xhl[regbank];
262 }
263 break;
264 case 0xf0: /* index registers and sp */
265 switch ( reg & 0x0c )
266 {
267 case 0x00: return &m_xix;
268 case 0x04: return &m_xiy;
269 case 0x08: return &m_xiz;
270 /* TODO: Use correct SP */
271 case 0x0c: return &m_xssp;
272 }
273 break;
274 }
275
276 /* illegal/unknown register reference */
277 logerror( "Access to unknown tlcs-900 cpu register %02x\n", reg );
278 return &m_dummy;
279 }
280
281
get_reg8(uint8_t reg)282 uint8_t* tlcs900_device::get_reg8( uint8_t reg )
283 {
284 PAIR *r = get_reg( reg );
285
286 switch ( reg & 0x03 )
287 {
288 case 0x00: return &r->b.l;
289 case 0x01: return &r->b.h;
290 case 0x02: return &r->b.h2;
291 case 0x03: return &r->b.h3;
292 }
293
294 return &r->b.l;
295 }
296
297
get_reg16(uint8_t reg)298 uint16_t* tlcs900_device::get_reg16( uint8_t reg )
299 {
300 PAIR *r = get_reg( reg );
301
302 return ( reg & 0x02 ) ? &r->w.h : &r->w.l;
303 }
304
305
get_reg32(uint8_t reg)306 uint32_t* tlcs900_device::get_reg32( uint8_t reg )
307 {
308 PAIR *r = get_reg( reg );
309
310 return &r->d;
311 }
312
313
314
parity8(uint8_t a)315 void tlcs900_device::parity8( uint8_t a )
316 {
317 int i, j;
318
319 j = 0;
320 for ( i = 0; i < 8; i++ )
321 {
322 if ( a & 1 ) j++;
323 a >>= 1;
324 }
325 m_sr.b.l |= ( ( j & 1 ) ? 0 : FLAG_VF );
326 }
327
328
parity16(uint16_t a)329 void tlcs900_device::parity16( uint16_t a )
330 {
331 int i, j;
332
333 j = 0;
334 for ( i = 0; i < 16; i++ )
335 {
336 if ( a & 1 ) j++;
337 a >>= 1;
338 }
339 m_sr.b.l |= ( ( j & 1 ) ? 0 : FLAG_VF );
340 }
341
342
parity32(uint32_t a)343 void tlcs900_device::parity32( uint32_t a )
344 {
345 int i, j;
346
347 j = 0;
348 for ( i = 0; i < 32; i++ )
349 {
350 if ( a & 1 ) j++;
351 a >>= 1;
352 }
353 m_sr.b.l |= ( ( j & 1 ) ? 0 : FLAG_VF );
354 }
355
356
adc8(uint8_t a,uint8_t b)357 uint8_t tlcs900_device::adc8( uint8_t a, uint8_t b)
358 {
359 uint8_t cy = m_sr.b.l & FLAG_CF;
360 uint8_t result = a + b + cy;
361
362 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
363 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
364 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
365 ( ( ( result ^ a ) & ( result ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
366 ( ( ( result < a ) || ( ( result == a ) && cy ) ) ? FLAG_CF : 0 );
367
368 return result;
369 }
370
371
adc16(uint16_t a,uint16_t b)372 uint16_t tlcs900_device::adc16( uint16_t a, uint16_t b)
373 {
374 uint8_t cy = m_sr.b.l & FLAG_CF;
375 uint16_t result = a + b + cy;
376
377 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
378 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
379 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
380 ( ( ( result ^ a ) & ( result ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
381 ( ( ( result < a ) || ( ( result == a ) && cy ) ) ? FLAG_CF : 0 );
382
383 return result;
384 }
385
386
adc32(uint32_t a,uint32_t b)387 uint32_t tlcs900_device::adc32( uint32_t a, uint32_t b)
388 {
389 uint8_t cy = m_sr.b.l & FLAG_CF;
390 uint32_t result = a + b + cy;
391
392 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
393 m_sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
394 ( ( ( result ^ a ) & ( result ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
395 ( ( ( result < a ) || ( ( result == a ) && cy ) ) ? FLAG_CF : 0 );
396
397 return result;
398 }
399
400
add8(uint8_t a,uint8_t b)401 uint8_t tlcs900_device::add8( uint8_t a, uint8_t b)
402 {
403 uint8_t result = a + b;
404
405 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
406 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
407 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
408 ( ( ( result ^ a ) & ( result ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
409 ( ( result < a ) ? FLAG_CF : 0 );
410
411 return result;
412 }
413
414
add16(uint16_t a,uint16_t b)415 uint16_t tlcs900_device::add16( uint16_t a, uint16_t b)
416 {
417 uint16_t result = a + b;
418
419 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
420 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
421 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
422 ( ( ( result ^ a ) & ( result ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
423 ( ( result < a ) ? FLAG_CF : 0 );
424
425 return result;
426 }
427
428
add32(uint32_t a,uint32_t b)429 uint32_t tlcs900_device::add32( uint32_t a, uint32_t b)
430 {
431 uint32_t result = a + b;
432
433 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
434 m_sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
435 ( ( ( result ^ a ) & ( result ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
436 ( ( result < a ) ? FLAG_CF : 0 );
437
438 return result;
439 }
440
441
sbc8(uint8_t a,uint8_t b)442 uint8_t tlcs900_device::sbc8( uint8_t a, uint8_t b)
443 {
444 uint8_t cy = m_sr.b.l & FLAG_CF;
445 uint8_t result = a - b - cy;
446
447 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
448 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
449 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
450 ( ( ( result ^ a ) & ( a ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
451 ( ( ( result > a ) || ( cy && b == 0xFF ) ) ? FLAG_CF : 0 ) | FLAG_NF;
452
453 return result;
454 }
455
456
sbc16(uint16_t a,uint16_t b)457 uint16_t tlcs900_device::sbc16( uint16_t a, uint16_t b)
458 {
459 uint8_t cy = m_sr.b.l & FLAG_CF;
460 uint16_t result = a - b - cy;
461
462 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
463 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
464 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
465 ( ( ( result ^ a ) & ( a ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
466 ( ( ( result > a ) || ( cy && b == 0xFFFF ) ) ? FLAG_CF : 0 ) | FLAG_NF;
467
468 return result;
469 }
470
471
sbc32(uint32_t a,uint32_t b)472 uint32_t tlcs900_device::sbc32( uint32_t a, uint32_t b)
473 {
474 uint8_t cy = m_sr.b.l & FLAG_CF;
475 uint32_t result = a - b - cy;
476
477 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
478 m_sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
479 ( ( ( result ^ a ) & ( a ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
480 ( ( ( result > a ) || ( cy && b == 0xFFFFFFFF ) ) ? FLAG_CF : 0 ) | FLAG_NF;
481
482 return result;
483 }
484
485
sub8(uint8_t a,uint8_t b)486 uint8_t tlcs900_device::sub8( uint8_t a, uint8_t b)
487 {
488 uint8_t result = a - b;
489
490 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
491 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
492 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
493 ( ( ( result ^ a ) & ( a ^ b ) & 0x80 ) ? FLAG_VF : 0 ) |
494 ( ( result > a ) ? FLAG_CF : 0 ) | FLAG_NF;
495
496 return result;
497 }
498
499
sub16(uint16_t a,uint16_t b)500 uint16_t tlcs900_device::sub16( uint16_t a, uint16_t b)
501 {
502 uint16_t result = a - b;
503
504 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
505 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
506 ( ( ( a ^ b ) ^ result ) & FLAG_HF ) |
507 ( ( ( result ^ a ) & ( a ^ b ) & 0x8000 ) ? FLAG_VF : 0 ) |
508 ( ( result > a ) ? FLAG_CF : 0 ) | FLAG_NF;
509
510 return result;
511 }
512
513
sub32(uint32_t a,uint32_t b)514 uint32_t tlcs900_device::sub32( uint32_t a, uint32_t b)
515 {
516 uint32_t result = a - b;
517
518 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_CF);
519 m_sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) |
520 ( ( ( result ^ a ) & ( a ^ b ) & 0x80000000 ) ? FLAG_VF : 0 ) |
521 ( ( result > a ) ? FLAG_CF : 0 ) | FLAG_NF;
522
523 return result;
524 }
525
526
and8(uint8_t a,uint8_t b)527 uint8_t tlcs900_device::and8( uint8_t a, uint8_t b)
528 {
529 uint8_t result = a & b;
530
531 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
532 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) | FLAG_HF;
533
534 parity8( result );
535
536 return result;
537 }
538
539
and16(uint16_t a,uint16_t b)540 uint16_t tlcs900_device::and16( uint16_t a, uint16_t b)
541 {
542 uint16_t result = a & b;
543
544 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
545 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) | FLAG_HF;
546
547 parity16( result );
548
549 return result;
550 }
551
552
and32(uint32_t a,uint32_t b)553 uint32_t tlcs900_device::and32( uint32_t a, uint32_t b)
554 {
555 uint32_t result = a & b;
556
557 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
558 m_sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF ) | FLAG_HF;
559
560 return result;
561 }
562
563
or8(uint8_t a,uint8_t b)564 uint8_t tlcs900_device::or8( uint8_t a, uint8_t b)
565 {
566 uint8_t result = a | b;
567
568 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
569 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
570
571 parity8( result );
572
573 return result;
574 }
575
576
or16(uint16_t a,uint16_t b)577 uint16_t tlcs900_device::or16( uint16_t a, uint16_t b)
578 {
579 uint16_t result = a | b;
580
581 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
582 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
583
584 parity16( result );
585
586 return result;
587 }
588
589
or32(uint32_t a,uint32_t b)590 uint32_t tlcs900_device::or32( uint32_t a, uint32_t b)
591 {
592 uint32_t result = a | b;
593
594 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
595 m_sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
596
597 return result;
598 }
599
600
xor8(uint8_t a,uint8_t b)601 uint8_t tlcs900_device::xor8( uint8_t a, uint8_t b)
602 {
603 uint8_t result = a ^ b;
604
605 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
606 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
607
608 parity8( result );
609
610 return result;
611 }
612
613
xor16(uint16_t a,uint16_t b)614 uint16_t tlcs900_device::xor16( uint16_t a, uint16_t b)
615 {
616 uint16_t result = a ^ b;
617
618 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
619 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
620
621 parity16( result );
622
623 return result;
624 }
625
626
xor32(uint32_t a,uint32_t b)627 uint32_t tlcs900_device::xor32( uint32_t a, uint32_t b)
628 {
629 uint32_t result = a ^ b;
630
631 m_sr.b.l &= ~(FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF);
632 m_sr.b.l |= ( ( result >> 24 ) & FLAG_SF ) | ( result ? 0 : FLAG_ZF );
633
634 return result;
635 }
636
637
ldcf8(uint8_t a,uint8_t b)638 void tlcs900_device::ldcf8( uint8_t a, uint8_t b )
639 {
640 if ( b & ( 1 << ( a & 0x07 ) ) )
641 m_sr.b.l |= FLAG_CF;
642 else
643 m_sr.b.l &= ~ FLAG_CF;
644 }
645
646
ldcf16(uint8_t a,uint8_t b)647 void tlcs900_device::ldcf16( uint8_t a, uint8_t b )
648 {
649 if ( b & ( 1 << ( a & 0x0f ) ) )
650 m_sr.b.l |= FLAG_CF;
651 else
652 m_sr.b.l &= ~ FLAG_CF;
653 }
654
655
andcf8(uint8_t a,uint8_t b)656 void tlcs900_device::andcf8( uint8_t a, uint8_t b )
657 {
658 if ( ( b & ( 1 << ( a & 0x07 ) ) ) && ( m_sr.b.l & FLAG_CF ) )
659 m_sr.b.l |= FLAG_CF;
660 else
661 m_sr.b.l &= ~ FLAG_CF;
662 }
663
664
andcf16(uint8_t a,uint8_t b)665 void tlcs900_device::andcf16( uint8_t a, uint8_t b )
666 {
667 if ( ( b & ( 1 << ( a & 0x0f ) ) ) && ( m_sr.b.l & FLAG_CF ) )
668 m_sr.b.l |= FLAG_CF;
669 else
670 m_sr.b.l &= ~ FLAG_CF;
671 }
672
673
orcf8(uint8_t a,uint8_t b)674 void tlcs900_device::orcf8( uint8_t a, uint8_t b )
675 {
676 if ( b & ( 1 << ( a & 0x07 ) ) )
677 m_sr.b.l |= FLAG_CF;
678 }
679
680
orcf16(uint8_t a,uint8_t b)681 void tlcs900_device::orcf16( uint8_t a, uint8_t b )
682 {
683 if ( b & ( 1 << ( a & 0x0f ) ) )
684 m_sr.b.l |= FLAG_CF;
685 }
686
687
xorcf8(uint8_t a,uint8_t b)688 void tlcs900_device::xorcf8( uint8_t a, uint8_t b )
689 {
690 if ( b & ( 1 << ( a & 0x07 ) ) )
691 m_sr.b.l ^= FLAG_CF;
692 }
693
694
xorcf16(uint8_t a,uint8_t b)695 void tlcs900_device::xorcf16( uint8_t a, uint8_t b )
696 {
697 if ( b & ( 1 << ( a & 0x0f ) ) )
698 m_sr.b.l ^= FLAG_CF;
699 }
700
701
rl8(uint8_t a,uint8_t s)702 uint8_t tlcs900_device::rl8( uint8_t a, uint8_t s )
703 {
704 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
705
706 for (uint8_t n = count; n > 0; n--)
707 {
708 if ( a & 0x80 )
709 {
710 a = ( a << 1 ) | ( m_sr.b.l & FLAG_CF );
711 m_sr.b.l |= FLAG_CF;
712 }
713 else
714 {
715 a = ( a << 1 ) | ( m_sr.b.l & FLAG_CF );
716 m_sr.b.l &= ~ FLAG_CF;
717 }
718 }
719 m_cycles += tlcs900_shift_cycles(count);
720
721 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
722 m_sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
723 parity8( a );
724
725 return a;
726 }
727
728
rl16(uint16_t a,uint8_t s)729 uint16_t tlcs900_device::rl16( uint16_t a, uint8_t s )
730 {
731 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
732
733 for (uint8_t n = count; n > 0; n--)
734 {
735 if ( a & 0x8000 )
736 {
737 a = ( a << 1 ) | ( m_sr.b.l & FLAG_CF );
738 m_sr.b.l |= FLAG_CF;
739 }
740 else
741 {
742 a = ( a << 1 ) | ( m_sr.b.l & FLAG_CF );
743 m_sr.b.l &= ~ FLAG_CF;
744 }
745 }
746 m_cycles += tlcs900_shift_cycles(count);
747
748 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
749 m_sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
750 parity16( a );
751
752 return a;
753 }
754
755
rl32(uint32_t a,uint8_t s)756 uint32_t tlcs900_device::rl32( uint32_t a, uint8_t s )
757 {
758 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
759
760 for (uint8_t n = count; n > 0; n--)
761 {
762 if ( a & 0x80000000 )
763 {
764 a = ( a << 1 ) | ( m_sr.b.l & FLAG_CF );
765 m_sr.b.l |= FLAG_CF;
766 }
767 else
768 {
769 a = ( a << 1 ) | ( m_sr.b.l & FLAG_CF );
770 m_sr.b.l &= ~ FLAG_CF;
771 }
772 }
773 m_cycles += tlcs900_shift_cycles(count);
774
775 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
776 m_sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
777 parity32( a );
778
779 return a;
780 }
781
rlc8(uint8_t a,uint8_t s)782 uint8_t tlcs900_device::rlc8( uint8_t a, uint8_t s )
783 {
784 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
785
786 for (uint8_t n = count; n > 0; n--)
787 {
788 a = ( a << 1 ) | ( ( a & 0x80 ) ? 1 : 0 );
789 }
790 m_cycles += tlcs900_shift_cycles(count);
791
792 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
793 m_sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF ) | ( a & FLAG_CF );
794 parity8( a );
795
796 return a;
797 }
798
799
rlc16(uint16_t a,uint8_t s)800 uint16_t tlcs900_device::rlc16( uint16_t a, uint8_t s )
801 {
802 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
803
804 for (uint8_t n = count; n > 0; n--)
805 {
806 a = ( a << 1 ) | ( ( a & 0x8000 ) ? 1 : 0 );
807 }
808 m_cycles += tlcs900_shift_cycles(count);
809
810 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
811 m_sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF ) | ( a & FLAG_CF );
812 parity16( a );
813
814 return a;
815 }
816
817
rlc32(uint32_t a,uint8_t s)818 uint32_t tlcs900_device::rlc32( uint32_t a, uint8_t s )
819 {
820 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
821
822 for (uint8_t n = count; n > 0; n--)
823 {
824 a = ( a << 1 ) | ( ( a & 0x80000000 ) ? 1 : 0 );
825 }
826 m_cycles += tlcs900_shift_cycles(count);
827
828 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
829 m_sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF ) | ( a & FLAG_CF );
830 parity32( a );
831
832 return a;
833 }
834
835
rr8(uint8_t a,uint8_t s)836 uint8_t tlcs900_device::rr8( uint8_t a, uint8_t s )
837 {
838 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
839
840 for (uint8_t n = count; n > 0; n--)
841 {
842 if ( m_sr.b.l & FLAG_CF )
843 {
844 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
845 a = ( a >> 1 ) | 0x80;
846 }
847 else
848 {
849 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
850 a = ( a >> 1 );
851 }
852 }
853 m_cycles += tlcs900_shift_cycles(count);
854
855 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
856 m_sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
857 parity8( a );
858
859 return a;
860 }
861
862
rr16(uint16_t a,uint8_t s)863 uint16_t tlcs900_device::rr16( uint16_t a, uint8_t s )
864 {
865 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
866
867 for (uint8_t n = count; n > 0; n--)
868 {
869 if ( m_sr.b.l & FLAG_CF )
870 {
871 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
872 a = ( a >> 1 ) | 0x8000;
873 }
874 else
875 {
876 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
877 a = ( a >> 1 );
878 }
879 }
880 m_cycles += tlcs900_shift_cycles(count);
881
882 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
883 m_sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
884 parity16( a );
885
886 return a;
887 }
888
889
rr32(uint32_t a,uint8_t s)890 uint32_t tlcs900_device::rr32( uint32_t a, uint8_t s )
891 {
892 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
893
894 for (uint8_t n = count; n > 0; n--)
895 {
896 if ( m_sr.b.l & FLAG_CF )
897 {
898 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
899 a = ( a >> 1 ) | 0x80000000;
900 }
901 else
902 {
903 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
904 a = ( a >> 1 );
905 }
906 }
907 m_cycles += tlcs900_shift_cycles(count);
908
909 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
910 m_sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
911 parity32( a );
912
913 return a;
914 }
915
916
rrc8(uint8_t a,uint8_t s)917 uint8_t tlcs900_device::rrc8( uint8_t a, uint8_t s )
918 {
919 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
920
921 for (uint8_t n = count; n > 0; n--)
922 {
923 a = ( a >> 1 ) | ( ( a & 0x01 ) ? 0x80 : 0 );
924 }
925 m_cycles += tlcs900_shift_cycles(count);
926
927 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
928 m_sr.b.l |= ( ( a & FLAG_SF ) ? FLAG_CF | FLAG_SF : 0 ) | ( a ? 0 : FLAG_ZF );
929 parity8( a );
930
931 return a;
932 }
933
934
rrc16(uint16_t a,uint8_t s)935 uint16_t tlcs900_device::rrc16( uint16_t a, uint8_t s )
936 {
937 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
938
939 for (uint8_t n = count; n > 0; n--)
940 {
941 a = ( a >> 1 ) | ( ( a & 0x0001 ) ? 0x8000 : 0 );
942 }
943 m_cycles += tlcs900_shift_cycles(count);
944
945 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
946 m_sr.b.l |= ( ( ( a >> 8 ) & FLAG_SF ) ? FLAG_CF | FLAG_SF : 0 ) | ( a ? 0 : FLAG_ZF );
947 parity16( a );
948
949 return a;
950 }
951
952
rrc32(uint32_t a,uint8_t s)953 uint32_t tlcs900_device::rrc32( uint32_t a, uint8_t s )
954 {
955 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
956
957 for (uint8_t n = count; n > 0; n--)
958 {
959 a = ( a >> 1 ) | ( ( a & 0x00000001 ) ? 0x80000000 : 0 );
960 }
961 m_cycles += tlcs900_shift_cycles(count);
962
963 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
964 m_sr.b.l |= ( ( ( a >> 24 ) & FLAG_SF ) ? FLAG_CF | FLAG_SF : 0 ) | ( a ? 0 : FLAG_ZF );
965 parity32( a );
966
967 return a;
968 }
969
970
sla8(uint8_t a,uint8_t s)971 uint8_t tlcs900_device::sla8( uint8_t a, uint8_t s )
972 {
973 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
974
975 for (uint8_t n = count; n > 0; n--)
976 {
977 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( ( a & 0x80 ) ? FLAG_CF : 0 );
978 a = ( a << 1 );
979 }
980 m_cycles += tlcs900_shift_cycles(count);
981
982 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
983 m_sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
984 parity8( a );
985
986 return a;
987 }
988
989
sla16(uint16_t a,uint8_t s)990 uint16_t tlcs900_device::sla16( uint16_t a, uint8_t s )
991 {
992 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
993
994 for (uint8_t n = count; n > 0; n--)
995 {
996 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( ( a & 0x8000 ) ? FLAG_CF : 0 );
997 a = ( a << 1 );
998 }
999 m_cycles += tlcs900_shift_cycles(count);
1000
1001 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1002 m_sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1003 parity16( a );
1004
1005 return a;
1006 }
1007
1008
sla32(uint32_t a,uint8_t s)1009 uint32_t tlcs900_device::sla32( uint32_t a, uint8_t s )
1010 {
1011 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
1012
1013 for (uint8_t n = count; n > 0; n--)
1014 {
1015 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( ( a & 0x80000000 ) ? FLAG_CF : 0 );
1016 a = ( a << 1 );
1017 }
1018 m_cycles += tlcs900_shift_cycles(count);
1019
1020 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1021 m_sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1022 parity32( a );
1023
1024 return a;
1025 }
1026
1027
sra8(uint8_t a,uint8_t s)1028 uint8_t tlcs900_device::sra8( uint8_t a, uint8_t s )
1029 {
1030 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
1031
1032 for (uint8_t n = count; n > 0; n--)
1033 {
1034 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
1035 a = ( a & 0x80 ) | ( a >> 1 );
1036 }
1037 m_cycles += tlcs900_shift_cycles(count);
1038
1039 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1040 m_sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1041 parity8( a );
1042
1043 return a;
1044 }
1045
1046
sra16(uint16_t a,uint8_t s)1047 uint16_t tlcs900_device::sra16( uint16_t a, uint8_t s )
1048 {
1049 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
1050
1051 for (uint8_t n = count; n > 0; n--)
1052 {
1053 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
1054 a = ( a & 0x8000 ) | ( a >> 1 );
1055 }
1056 m_cycles += tlcs900_shift_cycles(count);
1057
1058 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1059 m_sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1060 parity16( a );
1061
1062 return a;
1063 }
1064
1065
sra32(uint32_t a,uint8_t s)1066 uint32_t tlcs900_device::sra32( uint32_t a, uint8_t s )
1067 {
1068 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
1069
1070 for (uint8_t n = count; n > 0; n--)
1071 {
1072 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
1073 a = ( a & 0x80000000 ) | ( a >> 1 );
1074 }
1075 m_cycles += tlcs900_shift_cycles(count);
1076
1077 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1078 m_sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1079 parity32( a );
1080
1081 return a;
1082 }
1083
1084
srl8(uint8_t a,uint8_t s)1085 uint8_t tlcs900_device::srl8( uint8_t a, uint8_t s )
1086 {
1087 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
1088
1089 for (uint8_t n = count; n > 0; n--)
1090 {
1091 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
1092 a = ( a >> 1 );
1093 }
1094 m_cycles += tlcs900_shift_cycles(count);
1095
1096 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1097 m_sr.b.l |= ( a & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1098 parity8( a );
1099
1100 return a;
1101 }
1102
1103
srl16(uint16_t a,uint8_t s)1104 uint16_t tlcs900_device::srl16( uint16_t a, uint8_t s )
1105 {
1106 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
1107
1108 for (uint8_t n = count; n > 0; n--)
1109 {
1110 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
1111 a = ( a >> 1 );
1112 }
1113 m_cycles += tlcs900_shift_cycles(count);
1114
1115 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1116 m_sr.b.l |= ( ( a >> 8 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1117 parity16( a );
1118
1119 return a;
1120 }
1121
1122
srl32(uint32_t a,uint8_t s)1123 uint32_t tlcs900_device::srl32( uint32_t a, uint8_t s )
1124 {
1125 uint8_t count = ( s & 0x0f ) ? ( s & 0x0f ) : 16;
1126
1127 for (uint8_t n = count; n > 0; n--)
1128 {
1129 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | ( a & FLAG_CF );
1130 a = ( a >> 1 );
1131 }
1132 m_cycles += tlcs900_shift_cycles(count);
1133
1134 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF );
1135 m_sr.b.l |= ( ( a >> 24 ) & FLAG_SF ) | ( a ? 0 : FLAG_ZF );
1136 parity32( a );
1137
1138 return a;
1139 }
1140
1141
div8(uint16_t a,uint8_t b)1142 uint16_t tlcs900_device::div8( uint16_t a, uint8_t b )
1143 {
1144 ldiv_t result;
1145
1146 if ( !b )
1147 {
1148 m_sr.b.l |= FLAG_VF;
1149 return ( a << 8 ) | ( ( a >> 8 ) ^ 0xff );
1150 }
1151
1152 if ( a >= ( 0x0200 * b ) ) {
1153 uint16_t diff = a - ( 0x0200 * b );
1154 uint16_t range = 0x100 - b;
1155
1156 result = ldiv( diff, range );
1157 result.quot = 0x1ff - result.quot;
1158 result.rem = result.rem + b;
1159 }
1160 else
1161 {
1162 result = ldiv( a, b );
1163 }
1164
1165 if ( result.quot > 0xff )
1166 m_sr.b.l |= FLAG_VF;
1167 else
1168 m_sr.b.l &= ~ FLAG_VF;
1169
1170 return ( result.quot & 0xff ) | ( ( result.rem & 0xff ) << 8 );
1171 }
1172
1173
div16(uint32_t a,uint16_t b)1174 uint32_t tlcs900_device::div16( uint32_t a, uint16_t b )
1175 {
1176 ldiv_t result;
1177
1178 if ( !b )
1179 {
1180 m_sr.b.l |= FLAG_VF;
1181 return ( a << 16 ) | ( ( a >> 16 ) ^ 0xffff );
1182 }
1183
1184 // if ( a >= ( 0x02000000 * b ) ) {
1185 // uint32_t diff = a - ( 0x02000000 * b );
1186 // uint32_t range = 0x1000000 - b;
1187 //
1188 // result = ldiv( diff, range );
1189 // result.quot = 0x1ffffff - result.quot;
1190 // result.rem = result.rem + b;
1191 // }
1192 // else
1193 // {
1194 result = ldiv( a, b );
1195 // }
1196
1197 if ( result.quot > 0xffff )
1198 m_sr.b.l |= FLAG_VF;
1199 else
1200 m_sr.b.l &= ~ FLAG_VF;
1201
1202 return ( result.quot & 0xffff ) | ( ( result.rem & 0xffff ) << 16 );
1203 }
1204
1205
divs8(int16_t a,int8_t b)1206 uint16_t tlcs900_device::divs8( int16_t a, int8_t b )
1207 {
1208 ldiv_t result;
1209
1210 if ( !b )
1211 {
1212 m_sr.b.l |= FLAG_VF;
1213 return ( a << 8 ) | ( ( a >> 8 ) ^ 0xff );
1214 }
1215
1216 result = ldiv( a, b );
1217
1218 if ( result.quot > 0xff )
1219 m_sr.b.l |= FLAG_VF;
1220 else
1221 m_sr.b.l &= ~ FLAG_VF;
1222
1223 return ( result.quot & 0xff ) | ( ( result.rem & 0xff ) << 8 );
1224 }
1225
1226
divs16(int32_t a,int16_t b)1227 uint32_t tlcs900_device::divs16( int32_t a, int16_t b )
1228 {
1229 ldiv_t result;
1230
1231 if ( !b )
1232 {
1233 m_sr.b.l |= FLAG_VF;
1234 return ( a << 16 ) | ( ( a >> 16 ) ^ 0xffff );
1235 }
1236
1237 result = ldiv( a, b );
1238
1239 if ( result.quot > 0xffff )
1240 m_sr.b.l |= FLAG_VF;
1241 else
1242 m_sr.b.l &= ~ FLAG_VF;
1243
1244 return ( result.quot & 0xffff ) | ( ( result.rem & 0xffff ) << 16 );
1245 }
1246
1247
op_ADCBMI()1248 void tlcs900_device::op_ADCBMI()
1249 {
1250 WRMEM( m_ea1.d, adc8( RDMEM( m_ea1.d ), m_imm2.b.l ) );
1251 }
1252
1253
op_ADCBMR()1254 void tlcs900_device::op_ADCBMR()
1255 {
1256 WRMEM( m_ea1.d, adc8( RDMEM( m_ea1.d ), *m_p2_reg8 ) );
1257 }
1258
1259
op_ADCBRI()1260 void tlcs900_device::op_ADCBRI()
1261 {
1262 *m_p1_reg8 = adc8( *m_p1_reg8, m_imm2.b.l );
1263 }
1264
1265
op_ADCBRM()1266 void tlcs900_device::op_ADCBRM()
1267 {
1268 *m_p1_reg8 = adc8( *m_p1_reg8, RDMEM( m_ea2.d ) );
1269 }
1270
1271
op_ADCBRR()1272 void tlcs900_device::op_ADCBRR()
1273 {
1274 *m_p1_reg8 = adc8( *m_p1_reg8, *m_p2_reg8 );
1275 }
1276
1277
op_ADCWMI()1278 void tlcs900_device::op_ADCWMI()
1279 {
1280 WRMEMW( m_ea1.d, adc16( RDMEMW( m_ea1.d ), m_imm2.w.l ) );
1281 }
1282
1283
op_ADCWMR()1284 void tlcs900_device::op_ADCWMR()
1285 {
1286 WRMEMW( m_ea1.d, adc16( RDMEMW( m_ea1.d ), *m_p2_reg16 ) );
1287 }
1288
1289
op_ADCWRI()1290 void tlcs900_device::op_ADCWRI()
1291 {
1292 *m_p1_reg16 = adc16( *m_p1_reg16, m_imm2.w.l );
1293 }
1294
1295
op_ADCWRM()1296 void tlcs900_device::op_ADCWRM()
1297 {
1298 *m_p1_reg16 = adc16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
1299 }
1300
1301
op_ADCWRR()1302 void tlcs900_device::op_ADCWRR()
1303 {
1304 *m_p1_reg16 = adc16( *m_p1_reg16, *m_p2_reg16 );
1305 }
1306
1307
op_ADCLMR()1308 void tlcs900_device::op_ADCLMR()
1309 {
1310 WRMEML( m_ea1.d, adc32( RDMEML( m_ea1.d ), *m_p2_reg32 ) );
1311 }
1312
1313
op_ADCLRI()1314 void tlcs900_device::op_ADCLRI()
1315 {
1316 *m_p1_reg32 = adc32( *m_p1_reg32, m_imm2.d );
1317 }
1318
1319
op_ADCLRM()1320 void tlcs900_device::op_ADCLRM()
1321 {
1322 *m_p1_reg32 = adc32( *m_p1_reg32, RDMEML( m_ea2.d ) );
1323 }
1324
1325
op_ADCLRR()1326 void tlcs900_device::op_ADCLRR()
1327 {
1328 *m_p1_reg32 = adc32( *m_p1_reg32, *m_p2_reg32 );
1329 }
1330
1331
op_ADDBMI()1332 void tlcs900_device::op_ADDBMI()
1333 {
1334 WRMEM( m_ea1.d, add8( RDMEM( m_ea1.d ), m_imm2.b.l ) );
1335 }
1336
1337
op_ADDBMR()1338 void tlcs900_device::op_ADDBMR()
1339 {
1340 WRMEM( m_ea1.d, add8( RDMEM( m_ea1.d ), *m_p2_reg8 ) );
1341 }
1342
1343
op_ADDBRI()1344 void tlcs900_device::op_ADDBRI()
1345 {
1346 *m_p1_reg8 = add8( *m_p1_reg8, m_imm2.b.l );
1347 }
1348
1349
op_ADDBRM()1350 void tlcs900_device::op_ADDBRM()
1351 {
1352 *m_p1_reg8 = add8( *m_p1_reg8, RDMEM( m_ea2.d ) );
1353 }
1354
1355
op_ADDBRR()1356 void tlcs900_device::op_ADDBRR()
1357 {
1358 *m_p1_reg8 = add8( *m_p1_reg8, *m_p2_reg8 );
1359 }
1360
1361
op_ADDWMI()1362 void tlcs900_device::op_ADDWMI()
1363 {
1364 WRMEMW( m_ea1.d, add16( RDMEMW( m_ea1.d ), m_imm2.w.l ) );
1365 }
1366
1367
op_ADDWMR()1368 void tlcs900_device::op_ADDWMR()
1369 {
1370 WRMEMW( m_ea1.d, add16( RDMEMW( m_ea1.d ), *m_p2_reg16 ) );
1371 }
1372
1373
op_ADDWRI()1374 void tlcs900_device::op_ADDWRI()
1375 {
1376 *m_p1_reg16 = add16( *m_p1_reg16, m_imm2.w.l );
1377 }
1378
1379
op_ADDWRM()1380 void tlcs900_device::op_ADDWRM()
1381 {
1382 *m_p1_reg16 = add16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
1383 }
1384
1385
op_ADDWRR()1386 void tlcs900_device::op_ADDWRR()
1387 {
1388 *m_p1_reg16 = add16( *m_p1_reg16, *m_p2_reg16 );
1389 }
1390
1391
op_ADDLMR()1392 void tlcs900_device::op_ADDLMR()
1393 {
1394 WRMEML( m_ea1.d, add32( RDMEML( m_ea1.d ), *m_p2_reg32 ) );
1395 }
1396
1397
op_ADDLRI()1398 void tlcs900_device::op_ADDLRI()
1399 {
1400 *m_p1_reg32 = add32( *m_p1_reg32, m_imm2.d );
1401 }
1402
1403
op_ADDLRM()1404 void tlcs900_device::op_ADDLRM()
1405 {
1406 *m_p1_reg32 = add32( *m_p1_reg32, RDMEML( m_ea2.d ) );
1407 }
1408
1409
op_ADDLRR()1410 void tlcs900_device::op_ADDLRR()
1411 {
1412 *m_p1_reg32 = add32( *m_p1_reg32, *m_p2_reg32 );
1413 }
1414
1415
op_ANDBMI()1416 void tlcs900_device::op_ANDBMI()
1417 {
1418 WRMEM( m_ea1.d, and8( RDMEM( m_ea1.d ), m_imm2.b.l ) );
1419 }
1420
1421
op_ANDBMR()1422 void tlcs900_device::op_ANDBMR()
1423 {
1424 WRMEM( m_ea1.d, and8( RDMEM( m_ea1.d ), *m_p2_reg8 ) );
1425 }
1426
1427
op_ANDBRI()1428 void tlcs900_device::op_ANDBRI()
1429 {
1430 *m_p1_reg8 = and8( *m_p1_reg8, m_imm2.b.l );
1431 }
1432
1433
op_ANDBRM()1434 void tlcs900_device::op_ANDBRM()
1435 {
1436 *m_p1_reg8 = and8( *m_p1_reg8, RDMEM( m_ea2.d ) );
1437 }
1438
1439
op_ANDBRR()1440 void tlcs900_device::op_ANDBRR()
1441 {
1442 *m_p1_reg8 = and8( *m_p1_reg8, *m_p2_reg8 );
1443 }
1444
1445
op_ANDWMI()1446 void tlcs900_device::op_ANDWMI()
1447 {
1448 WRMEMW( m_ea1.d, and16( RDMEMW( m_ea1.d ), m_imm2.w.l ) );
1449 }
1450
1451
op_ANDWMR()1452 void tlcs900_device::op_ANDWMR()
1453 {
1454 WRMEMW( m_ea1.d, and16( RDMEMW( m_ea1.d ), *m_p2_reg16 ) );
1455 }
1456
1457
op_ANDWRI()1458 void tlcs900_device::op_ANDWRI()
1459 {
1460 *m_p1_reg16 = and16( *m_p1_reg16, m_imm2.w.l );
1461 }
1462
1463
op_ANDWRM()1464 void tlcs900_device::op_ANDWRM()
1465 {
1466 *m_p1_reg16 = and16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
1467 }
1468
1469
op_ANDWRR()1470 void tlcs900_device::op_ANDWRR()
1471 {
1472 *m_p1_reg16 = and16( *m_p1_reg16, *m_p2_reg16 );
1473 }
1474
1475
op_ANDLMR()1476 void tlcs900_device::op_ANDLMR()
1477 {
1478 WRMEML( m_ea1.d, and32( RDMEML( m_ea1.d ), *m_p2_reg32 ) );
1479 }
1480
1481
op_ANDLRI()1482 void tlcs900_device::op_ANDLRI()
1483 {
1484 *m_p1_reg32 = and32( *m_p1_reg32, m_imm2.d );
1485 }
1486
1487
op_ANDLRM()1488 void tlcs900_device::op_ANDLRM()
1489 {
1490 *m_p1_reg32 = and32( *m_p1_reg32, RDMEML( m_ea2.d ) );
1491 }
1492
1493
op_ANDLRR()1494 void tlcs900_device::op_ANDLRR()
1495 {
1496 *m_p1_reg32 = and32( *m_p1_reg32, *m_p2_reg32 );
1497 }
1498
1499
op_ANDCFBIM()1500 void tlcs900_device::op_ANDCFBIM()
1501 {
1502 andcf8( m_imm1.b.l, RDMEM( m_ea2.d ) );
1503 }
1504
1505
op_ANDCFBIR()1506 void tlcs900_device::op_ANDCFBIR()
1507 {
1508 andcf8( m_imm1.b.l, *m_p2_reg8 );
1509 }
1510
1511
op_ANDCFBRM()1512 void tlcs900_device::op_ANDCFBRM()
1513 {
1514 andcf8( *m_p1_reg8, RDMEM( m_ea2.d ) );
1515 }
1516
1517
op_ANDCFBRR()1518 void tlcs900_device::op_ANDCFBRR()
1519 {
1520 andcf8( *m_p1_reg8, *m_p2_reg8 );
1521 }
1522
1523
op_ANDCFWIR()1524 void tlcs900_device::op_ANDCFWIR()
1525 {
1526 andcf16( m_imm1.b.l, *m_p2_reg16 );
1527 }
1528
1529
op_ANDCFWRR()1530 void tlcs900_device::op_ANDCFWRR()
1531 {
1532 andcf16( *m_p1_reg8, *m_p2_reg16 );
1533 }
1534
1535
op_BITBIM()1536 void tlcs900_device::op_BITBIM()
1537 {
1538 m_sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
1539 if ( RDMEM( m_ea2.d ) & ( 1 << ( m_imm1.b.l & 0x07 ) ) )
1540 m_sr.b.l |= FLAG_HF;
1541 else
1542 m_sr.b.l |= FLAG_HF | FLAG_ZF;
1543 }
1544
1545
op_BITBIR()1546 void tlcs900_device::op_BITBIR()
1547 {
1548 m_sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
1549 if ( *m_p2_reg8 & ( 1 << ( m_imm1.b.l & 0x0f ) ) )
1550 m_sr.b.l |= FLAG_HF;
1551 else
1552 m_sr.b.l |= FLAG_HF | FLAG_ZF;
1553 }
1554
1555
op_BITWIR()1556 void tlcs900_device::op_BITWIR()
1557 {
1558 m_sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
1559 if ( *m_p2_reg16 & ( 1 << ( m_imm1.b.l & 0x0f ) ) )
1560 m_sr.b.l |= FLAG_HF;
1561 else
1562 m_sr.b.l |= FLAG_HF | FLAG_ZF;
1563 }
1564
1565
op_BS1BRR()1566 void tlcs900_device::op_BS1BRR()
1567 {
1568 uint16_t r = *m_p2_reg16;
1569
1570 if ( r )
1571 {
1572 m_sr.b.l &= ~ FLAG_VF;
1573 *m_p1_reg8 = 15;
1574 while( r < 0x8000 )
1575 {
1576 r <<= 1;
1577 *m_p1_reg8 -= 1;
1578 }
1579 }
1580 else
1581 m_sr.b.l |= FLAG_VF;
1582 }
1583
1584
op_BS1FRR()1585 void tlcs900_device::op_BS1FRR()
1586 {
1587 uint16_t r = *m_p2_reg16;
1588
1589 if ( r )
1590 {
1591 m_sr.b.l &= ~ FLAG_VF;
1592 *m_p1_reg8 = 0;
1593 while( ! ( r & 0x0001 ) )
1594 {
1595 r >>= 1;
1596 *m_p1_reg8 += 1;
1597 }
1598 }
1599 else
1600 m_sr.b.l |= FLAG_VF;
1601 }
1602
1603
op_CALLI()1604 void tlcs900_device::op_CALLI()
1605 {
1606 m_xssp.d -= 4;
1607 WRMEML( m_xssp.d, m_pc.d );
1608 m_pc.d = m_imm1.d;
1609 m_prefetch_clear = true;
1610 }
1611
1612
op_CALLM()1613 void tlcs900_device::op_CALLM()
1614 {
1615 if ( condition_true( m_op ) )
1616 {
1617 m_xssp.d -= 4;
1618 WRMEML( m_xssp.d, m_pc.d );
1619 m_pc.d = m_ea2.d;
1620 m_cycles += tlcs900_call_true_cycles();
1621 m_prefetch_clear = true;
1622 }
1623 }
1624
1625
op_CALR()1626 void tlcs900_device::op_CALR()
1627 {
1628 m_xssp.d -= 4;
1629 WRMEML( m_xssp.d, m_pc.d );
1630 m_pc.d = m_ea1.d;
1631 m_prefetch_clear = true;
1632 }
1633
1634
op_CCF()1635 void tlcs900_device::op_CCF()
1636 {
1637 m_sr.b.l &= ~ FLAG_NF;
1638 m_sr.b.l ^= FLAG_CF;
1639 }
1640
1641
op_CHGBIM()1642 void tlcs900_device::op_CHGBIM()
1643 {
1644 WRMEM( m_ea2.d, RDMEM( m_ea2.d ) ^ ( 1 << ( m_imm1.b.l & 0x07 ) ) );
1645 }
1646
1647
op_CHGBIR()1648 void tlcs900_device::op_CHGBIR()
1649 {
1650 *m_p2_reg8 ^= ( 1 << ( m_imm1.b.l & 0x07 ) );
1651 }
1652
1653
op_CHGWIR()1654 void tlcs900_device::op_CHGWIR()
1655 {
1656 *m_p2_reg16 ^= ( 1 << ( m_imm1.b.l & 0x0f ) );
1657 }
1658
1659
op_CPBMI()1660 void tlcs900_device::op_CPBMI()
1661 {
1662 sub8( RDMEM( m_ea1.d ), m_imm2.b.l );
1663 }
1664
1665
op_CPBMR()1666 void tlcs900_device::op_CPBMR()
1667 {
1668 sub8( RDMEM( m_ea1.d ), *m_p2_reg8 );
1669 }
1670
1671
op_CPBRI()1672 void tlcs900_device::op_CPBRI()
1673 {
1674 sub8( *m_p1_reg8, m_imm2.b.l );
1675 }
1676
1677
op_CPBRM()1678 void tlcs900_device::op_CPBRM()
1679 {
1680 sub8( *m_p1_reg8, RDMEM( m_ea2.d ) );
1681 }
1682
1683
op_CPBRR()1684 void tlcs900_device::op_CPBRR()
1685 {
1686 sub8( *m_p1_reg8, *m_p2_reg8 );
1687 }
1688
1689
op_CPWMI()1690 void tlcs900_device::op_CPWMI()
1691 {
1692 sub16( RDMEMW( m_ea1.d ), m_imm2.w.l );
1693 }
1694
1695
op_CPWMR()1696 void tlcs900_device::op_CPWMR()
1697 {
1698 sub16( RDMEMW( m_ea1.d ), *m_p2_reg16 );
1699 }
1700
1701
op_CPWRI()1702 void tlcs900_device::op_CPWRI()
1703 {
1704 sub16( *m_p1_reg16, m_imm2.w.l );
1705 }
1706
1707
op_CPWRM()1708 void tlcs900_device::op_CPWRM()
1709 {
1710 sub16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
1711 }
1712
1713
op_CPWRR()1714 void tlcs900_device::op_CPWRR()
1715 {
1716 sub16( *m_p1_reg16, *m_p2_reg16 );
1717 }
1718
1719
op_CPLMR()1720 void tlcs900_device::op_CPLMR()
1721 {
1722 sub32( RDMEML( m_ea1.d ), *m_p2_reg32 );
1723 }
1724
1725
op_CPLRI()1726 void tlcs900_device::op_CPLRI()
1727 {
1728 sub32( *m_p1_reg32, m_imm2.d );
1729 }
1730
1731
op_CPLRM()1732 void tlcs900_device::op_CPLRM()
1733 {
1734 sub32( *m_p1_reg32, RDMEML( m_ea2.d ) );
1735 }
1736
1737
op_CPLRR()1738 void tlcs900_device::op_CPLRR()
1739 {
1740 sub32( *m_p1_reg32, *m_p2_reg32 );
1741 }
1742
1743
op_CPD()1744 void tlcs900_device::op_CPD()
1745 {
1746 uint8_t result = *get_reg8_current( 1 ) - RDMEM( *m_p2_reg32 );
1747 uint16_t *bc = get_reg16_current( 1 );
1748
1749 *m_p2_reg32 -= 1;
1750 *bc -= 1;
1751 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
1752 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
1753 ( *bc ? FLAG_VF : 0 );
1754 }
1755
1756
op_CPDR()1757 void tlcs900_device::op_CPDR()
1758 {
1759 op_CPD();
1760
1761 if ( ( m_sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
1762 {
1763 m_pc.d -= 2;
1764 m_cycles += tlcs900_ldxx_repeat_cycles();
1765 m_prefetch_clear = true;
1766 }
1767 }
1768
1769
op_CPDW()1770 void tlcs900_device::op_CPDW()
1771 {
1772 uint16_t result = *get_reg16_current( 0 ) - RDMEMW( *m_p2_reg32 );
1773 uint16_t *bc = get_reg16_current( 1 );
1774
1775 *m_p2_reg32 -= 2;
1776 *bc -= 1;
1777 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
1778 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
1779 ( *bc ? FLAG_VF : 0 );
1780 }
1781
1782
op_CPDRW()1783 void tlcs900_device::op_CPDRW()
1784 {
1785 op_CPDW();
1786
1787 if ( ( m_sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
1788 {
1789 m_pc.d -= 2;
1790 m_cycles += tlcs900_ldxx_repeat_cycles();
1791 m_prefetch_clear = true;
1792 }
1793 }
1794
1795
op_CPI()1796 void tlcs900_device::op_CPI()
1797 {
1798 uint8_t result = *get_reg8_current( 1 ) - RDMEM( *m_p2_reg32 );
1799 uint16_t *bc = get_reg16_current( 1 );
1800
1801 *m_p2_reg32 += 1;
1802 *bc -= 1;
1803 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
1804 m_sr.b.l |= ( result & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
1805 ( *bc ? FLAG_VF : 0 );
1806 }
1807
1808
op_CPIR()1809 void tlcs900_device::op_CPIR()
1810 {
1811 op_CPI();
1812
1813 if ( ( m_sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
1814 {
1815 m_pc.d -= 2;
1816 m_cycles += tlcs900_ldxx_repeat_cycles();
1817 m_prefetch_clear = true;
1818 }
1819 }
1820
1821
op_CPIW()1822 void tlcs900_device::op_CPIW()
1823 {
1824 uint16_t result = *get_reg16_current( 0 ) - RDMEMW( *m_p2_reg32 );
1825 uint16_t *bc = get_reg16_current( 1 );
1826
1827 *m_p2_reg32 += 2;
1828 *bc -= 1;
1829 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF );
1830 m_sr.b.l |= ( ( result >> 8 ) & FLAG_SF ) | ( result ? FLAG_NF : FLAG_NF | FLAG_ZF ) |
1831 ( *bc ? FLAG_VF : 0 );
1832 }
1833
1834
op_CPIRW()1835 void tlcs900_device::op_CPIRW()
1836 {
1837 op_CPIW();
1838
1839 if ( ( m_sr.b.l & ( FLAG_ZF | FLAG_VF ) ) == FLAG_VF )
1840 {
1841 m_pc.d -= 2;
1842 m_cycles += tlcs900_ldxx_repeat_cycles();
1843 m_prefetch_clear = true;
1844 }
1845 }
1846
1847
op_CPLBR()1848 void tlcs900_device::op_CPLBR()
1849 {
1850 *m_p1_reg8 = ~ *m_p1_reg8;
1851 m_sr.b.l |= FLAG_HF | FLAG_NF;
1852 }
1853
1854
op_CPLWR()1855 void tlcs900_device::op_CPLWR()
1856 {
1857 *m_p1_reg16 = ~ *m_p1_reg16;
1858 m_sr.b.l |= FLAG_HF | FLAG_NF;
1859 }
1860
1861
op_DAABR()1862 void tlcs900_device::op_DAABR()
1863 {
1864 uint8_t oldval = *m_p1_reg8;
1865 uint8_t fixval = 0;
1866 uint8_t carry = 0;
1867 uint8_t high = *m_p1_reg8 & 0xf0;
1868 uint8_t low = *m_p1_reg8 & 0x0f;
1869
1870 if ( m_sr.b.l & FLAG_CF )
1871 {
1872 if ( m_sr.b.l & FLAG_HF )
1873 {
1874 fixval = 0x66;
1875 }
1876 else
1877 {
1878 if ( low < 0x0a )
1879 fixval = 0x60;
1880 else
1881 fixval = 0x66;
1882 }
1883 carry = 1;
1884 }
1885 else
1886 {
1887 if ( m_sr.b.l & FLAG_HF )
1888 {
1889 if ( *m_p1_reg8 < 0x9a )
1890 fixval = 0x06;
1891 else
1892 fixval = 0x66;
1893 }
1894 else
1895 {
1896 if ( high < 0x90 && low > 0x09 )
1897 fixval = 0x06;
1898 else if ( high > 0x80 && low > 0x09 )
1899 fixval = 0x66;
1900 else if ( high > 0x90 && low < 0x0a )
1901 fixval = 0x60;
1902 }
1903 }
1904 m_sr.b.l &= ~ ( FLAG_VF | FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_CF );
1905 if ( m_sr.b.l & FLAG_NF )
1906 {
1907 /* after SUB, SBC, or NEG operation */
1908 *m_p1_reg8 -= fixval;
1909 m_sr.b.l |= ( ( *m_p1_reg8 > oldval || carry ) ? FLAG_CF : 0 );
1910 }
1911 else
1912 {
1913 /* after ADD or ADC operation */
1914 *m_p1_reg8 += fixval;
1915 m_sr.b.l |= ( ( *m_p1_reg8 < oldval || carry ) ? FLAG_CF : 0 );
1916 }
1917 m_sr.b.l |= ( *m_p1_reg8 & FLAG_SF ) | ( *m_p1_reg8 ? 0 : FLAG_ZF ) |
1918 ( ( ( oldval ^ fixval ) ^ *m_p1_reg8 ) & FLAG_HF );
1919
1920 parity8( *m_p1_reg8 );
1921 }
1922
1923
op_DB()1924 void tlcs900_device::op_DB()
1925 {
1926 logerror("%08x: invalid or illegal instruction\n", m_pc.d );
1927 }
1928
1929
op_DECBIM()1930 void tlcs900_device::op_DECBIM()
1931 {
1932 uint8_t cy = m_sr.b.l & FLAG_CF;
1933
1934 WRMEM( m_ea2.d, sub8( RDMEM( m_ea2.d ), m_imm1.b.l ? m_imm1.b.l : 8 ) );
1935 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | cy;
1936 }
1937
1938
op_DECBIR()1939 void tlcs900_device::op_DECBIR()
1940 {
1941 uint8_t cy = m_sr.b.l & FLAG_CF;
1942
1943 *m_p2_reg8 = sub8( *m_p2_reg8, m_imm1.b.l ? m_imm1.b.l : 8 );
1944 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | cy;
1945 }
1946
1947
op_DECWIM()1948 void tlcs900_device::op_DECWIM()
1949 {
1950 uint8_t cy = m_sr.b.l & FLAG_CF;
1951
1952 WRMEMW( m_ea2.d, sub16( RDMEMW( m_ea2.d ), m_imm1.b.l ? m_imm1.b.l : 8 ) );
1953 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | cy;
1954 }
1955
1956
op_DECWIR()1957 void tlcs900_device::op_DECWIR()
1958 {
1959 *m_p2_reg16 -= m_imm1.b.l ? m_imm1.b.l : 8;
1960 }
1961
1962
op_DECLIR()1963 void tlcs900_device::op_DECLIR()
1964 {
1965 *m_p2_reg32 -= m_imm1.b.l ? m_imm1.b.l : 8;
1966 }
1967
1968
op_DECF()1969 void tlcs900_device::op_DECF()
1970 {
1971 /* 0x03 for MAX mode, 0x07 for MIN mode */
1972 m_sr.b.h = ( m_sr.b.h & 0xf8 ) | ( ( m_sr.b.h - 1 ) & 0x07 );
1973 m_regbank = m_sr.b.h & 0x03;
1974 }
1975
1976
op_DIVBRI()1977 void tlcs900_device::op_DIVBRI()
1978 {
1979 *m_p1_reg16 = div8( *m_p1_reg16, m_imm2.b.l );
1980 }
1981
1982
op_DIVBRM()1983 void tlcs900_device::op_DIVBRM()
1984 {
1985 *m_p1_reg16 = div8( *m_p1_reg16, RDMEM( m_ea2.d ) );
1986 }
1987
1988
op_DIVBRR()1989 void tlcs900_device::op_DIVBRR()
1990 {
1991 *m_p1_reg16 = div8( *m_p1_reg16, *m_p2_reg8 );
1992 }
1993
1994
op_DIVWRI()1995 void tlcs900_device::op_DIVWRI()
1996 {
1997 *m_p1_reg32 = div16( *m_p1_reg32, m_imm2.w.l );
1998 }
1999
2000
op_DIVWRM()2001 void tlcs900_device::op_DIVWRM()
2002 {
2003 *m_p1_reg32 = div16( *m_p1_reg32, RDMEMW( m_ea2.d ) );
2004 }
2005
2006
op_DIVWRR()2007 void tlcs900_device::op_DIVWRR()
2008 {
2009 *m_p1_reg32 = div16( *m_p1_reg32, *m_p2_reg16 );
2010 }
2011
2012
op_DIVSBRI()2013 void tlcs900_device::op_DIVSBRI()
2014 {
2015 *m_p1_reg16 = divs8( *m_p1_reg16, m_imm2.b.l );
2016 }
2017
2018
op_DIVSBRM()2019 void tlcs900_device::op_DIVSBRM()
2020 {
2021 *m_p1_reg16 = divs8( *m_p1_reg16, RDMEM( m_ea2.d ) );
2022 }
2023
2024
op_DIVSBRR()2025 void tlcs900_device::op_DIVSBRR()
2026 {
2027 *m_p1_reg16 = divs8( *m_p1_reg16, *m_p2_reg8 );
2028 }
2029
2030
op_DIVSWRI()2031 void tlcs900_device::op_DIVSWRI()
2032 {
2033 *m_p1_reg32 = divs16( *m_p1_reg32, m_imm2.w.l );
2034 }
2035
2036
op_DIVSWRM()2037 void tlcs900_device::op_DIVSWRM()
2038 {
2039 *m_p1_reg32 = divs16( *m_p1_reg32, RDMEMW( m_ea2.d ) );
2040 }
2041
2042
op_DIVSWRR()2043 void tlcs900_device::op_DIVSWRR()
2044 {
2045 *m_p1_reg32 = divs16( *m_p1_reg32, *m_p2_reg16 );
2046 }
2047
2048
op_DJNZB()2049 void tlcs900_device::op_DJNZB()
2050 {
2051 *m_p1_reg8 -= 1;
2052 if ( *m_p1_reg8 )
2053 {
2054 m_pc.d = m_ea2.d;
2055 m_cycles += tlcs900_djnz_true_cycles();
2056 m_prefetch_clear = true;
2057 }
2058 }
2059
2060
op_DJNZW()2061 void tlcs900_device::op_DJNZW()
2062 {
2063 *m_p1_reg16 -= 1;
2064 if ( *m_p1_reg16 )
2065 {
2066 m_pc.d = m_ea2.d;
2067 m_cycles += tlcs900_djnz_true_cycles();
2068 m_prefetch_clear = true;
2069 }
2070 }
2071
2072
op_EI()2073 void tlcs900_device::op_EI()
2074 {
2075 m_sr.b.h = ( m_sr.b.h & 0x8f ) | ( ( m_imm1.b.l & 0x07 ) << 4 );
2076 m_check_irqs = 1;
2077 }
2078
2079
op_EXBMR()2080 void tlcs900_device::op_EXBMR()
2081 {
2082 uint8_t i = RDMEM( m_ea1.d );
2083
2084 WRMEM( m_ea1.d, *m_p2_reg8 );
2085 *m_p2_reg8 = i;
2086 }
2087
2088
op_EXBRR()2089 void tlcs900_device::op_EXBRR()
2090 {
2091 uint8_t i = *m_p2_reg8;
2092
2093 *m_p2_reg8 = *m_p1_reg8;
2094 *m_p1_reg8 = i;
2095 }
2096
2097
op_EXWMR()2098 void tlcs900_device::op_EXWMR()
2099 {
2100 uint16_t i = RDMEMW( m_ea1.d );
2101
2102 WRMEMW( m_ea1.d, *m_p2_reg16 );
2103 *m_p2_reg16 = i;
2104 }
2105
2106
op_EXWRR()2107 void tlcs900_device::op_EXWRR()
2108 {
2109 uint16_t i = *m_p2_reg16;
2110
2111 *m_p2_reg16 = *m_p1_reg16;
2112 *m_p1_reg16 = i;
2113 }
2114
2115
op_EXTSWR()2116 void tlcs900_device::op_EXTSWR()
2117 {
2118 if ( *m_p1_reg16 & 0x0080 )
2119 *m_p1_reg16 |= 0xff00;
2120 else
2121 *m_p1_reg16 &= 0x00ff;
2122 }
2123
2124
op_EXTSLR()2125 void tlcs900_device::op_EXTSLR()
2126 {
2127 if ( *m_p1_reg32 & 0x00008000 )
2128 *m_p1_reg32 |= 0xffff0000;
2129 else
2130 *m_p1_reg32 &= 0x0000ffff;
2131 }
2132
2133
op_EXTZWR()2134 void tlcs900_device::op_EXTZWR()
2135 {
2136 *m_p1_reg16 &= 0x00ff;
2137 }
2138
2139
op_EXTZLR()2140 void tlcs900_device::op_EXTZLR()
2141 {
2142 *m_p1_reg32 &= 0x0000ffff;
2143 }
2144
2145
op_HALT()2146 void tlcs900_device::op_HALT()
2147 {
2148 m_halted = 1;
2149 }
2150
2151
op_INCBIM()2152 void tlcs900_device::op_INCBIM()
2153 {
2154 uint8_t cy = m_sr.b.l & FLAG_CF;
2155
2156 WRMEM( m_ea2.d, add8( RDMEM( m_ea2.d ), m_imm1.b.l ? m_imm1.b.l : 8 ) );
2157 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | cy;
2158 }
2159
2160
op_INCBIR()2161 void tlcs900_device::op_INCBIR()
2162 {
2163 uint8_t cy = m_sr.b.l & FLAG_CF;
2164
2165 *m_p2_reg8 = add8( *m_p2_reg8, m_imm1.b.l ? m_imm1.b.l : 8 );
2166 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | cy;
2167 }
2168
2169
op_INCWIM()2170 void tlcs900_device::op_INCWIM()
2171 {
2172 uint8_t cy = m_sr.b.l & FLAG_CF;
2173
2174 WRMEMW( m_ea2.d, add16( RDMEMW( m_ea2.d ), m_imm1.b.l ? m_imm1.b.l : 8 ) );
2175 m_sr.b.l = ( m_sr.b.l & ~ FLAG_CF ) | cy;
2176 }
2177
2178
op_INCWIR()2179 void tlcs900_device::op_INCWIR()
2180 {
2181 *m_p2_reg16 += m_imm1.b.l ? m_imm1.b.l : 8;
2182 }
2183
2184
op_INCLIR()2185 void tlcs900_device::op_INCLIR()
2186 {
2187 *m_p2_reg32 += m_imm1.b.l ? m_imm1.b.l : 8;
2188 }
2189
2190
op_INCF()2191 void tlcs900_device::op_INCF()
2192 {
2193 /* 0x03 for MAX mode, 0x07 for MIN mode */
2194 m_sr.b.h = ( m_sr.b.h & 0xf8 ) | ( ( m_sr.b.h + 1 ) & 0x07 );
2195 m_regbank = m_sr.b.h & 0x03;
2196 }
2197
2198
op_JPI()2199 void tlcs900_device::op_JPI()
2200 {
2201 m_pc.d = m_imm1.d;
2202 m_prefetch_clear = true;
2203 }
2204
2205
op_JPM()2206 void tlcs900_device::op_JPM()
2207 {
2208 if ( condition_true( m_op ) )
2209 {
2210 m_pc.d = m_ea2.d;
2211 m_cycles += tlcs900_jp_true_cycles();
2212 m_prefetch_clear = true;
2213 }
2214 }
2215
2216
op_JR()2217 void tlcs900_device::op_JR()
2218 {
2219 if ( condition_true( m_op ) )
2220 {
2221 m_pc.d = m_ea2.d;
2222 m_cycles += tlcs900_jp_true_cycles();
2223 m_prefetch_clear = true;
2224 }
2225 }
2226
2227
op_JRL()2228 void tlcs900_device::op_JRL()
2229 {
2230 if ( condition_true( m_op ) )
2231 {
2232 m_pc.d = m_ea2.d;
2233 m_cycles += tlcs900_jp_true_cycles();
2234 m_prefetch_clear = true;
2235 }
2236 }
2237
2238
op_LDBMI()2239 void tlcs900_device::op_LDBMI()
2240 {
2241 WRMEM( m_ea1.d, m_imm2.b.l );
2242 }
2243
2244
op_LDBMM()2245 void tlcs900_device::op_LDBMM()
2246 {
2247 WRMEM( m_ea1.d, RDMEM( m_ea2.d ) );
2248 }
2249
2250
op_LDBMR()2251 void tlcs900_device::op_LDBMR()
2252 {
2253 WRMEM( m_ea1.d, *m_p2_reg8 );
2254 }
2255
2256
op_LDBRI()2257 void tlcs900_device::op_LDBRI()
2258 {
2259 *m_p1_reg8 = m_imm2.b.l;
2260 }
2261
2262
op_LDBRM()2263 void tlcs900_device::op_LDBRM()
2264 {
2265 *m_p1_reg8 = RDMEM( m_ea2.d );
2266 }
2267
2268
op_LDBRR()2269 void tlcs900_device::op_LDBRR()
2270 {
2271 *m_p1_reg8 = *m_p2_reg8;
2272 }
2273
2274
op_LDWMI()2275 void tlcs900_device::op_LDWMI()
2276 {
2277 WRMEMW( m_ea1.d, m_imm2.w.l );
2278 }
2279
2280
op_LDWMM()2281 void tlcs900_device::op_LDWMM()
2282 {
2283 WRMEMW( m_ea1.d, RDMEMW( m_ea2.d ) );
2284 }
2285
2286
op_LDWMR()2287 void tlcs900_device::op_LDWMR()
2288 {
2289 WRMEMW( m_ea1.d, *m_p2_reg16 );
2290 }
2291
2292
op_LDWRI()2293 void tlcs900_device::op_LDWRI()
2294 {
2295 *m_p1_reg16 = m_imm2.w.l;
2296 }
2297
2298
op_LDWRM()2299 void tlcs900_device::op_LDWRM()
2300 {
2301 *m_p1_reg16 = RDMEMW( m_ea2.d );
2302 }
2303
2304
op_LDWRR()2305 void tlcs900_device::op_LDWRR()
2306 {
2307 *m_p1_reg16 = *m_p2_reg16;
2308 }
2309
2310
op_LDLRI()2311 void tlcs900_device::op_LDLRI()
2312 {
2313 *m_p1_reg32 = m_imm2.d;
2314 }
2315
2316
op_LDLRM()2317 void tlcs900_device::op_LDLRM()
2318 {
2319 *m_p1_reg32 = RDMEML( m_ea2.d );
2320 }
2321
2322
op_LDLRR()2323 void tlcs900_device::op_LDLRR()
2324 {
2325 *m_p1_reg32 = *m_p2_reg32;
2326 }
2327
2328
op_LDLMR()2329 void tlcs900_device::op_LDLMR()
2330 {
2331 WRMEML( m_ea1.d, *m_p2_reg32 );
2332 }
2333
2334
op_LDAW()2335 void tlcs900_device::op_LDAW()
2336 {
2337 *m_p1_reg16 = m_ea2.w.l;
2338 }
2339
2340
op_LDAL()2341 void tlcs900_device::op_LDAL()
2342 {
2343 *m_p1_reg32 = m_ea2.d;
2344 }
2345
2346
op_LDCBRR()2347 void tlcs900_device::op_LDCBRR()
2348 {
2349 *m_p1_reg8 = *m_p2_reg8;
2350 }
2351
2352
op_LDCWRR()2353 void tlcs900_device::op_LDCWRR()
2354 {
2355 *m_p1_reg16 = *m_p2_reg16;
2356 }
2357
2358
op_LDCLRR()2359 void tlcs900_device::op_LDCLRR()
2360 {
2361 *m_p1_reg32 = *m_p2_reg32;
2362 }
2363
2364
op_LDCFBIM()2365 void tlcs900_device::op_LDCFBIM()
2366 {
2367 ldcf8( m_imm1.b.l, RDMEM( m_ea2.d ) );
2368 }
2369
2370
op_LDCFBIR()2371 void tlcs900_device::op_LDCFBIR()
2372 {
2373 ldcf8( m_imm1.b.l, *m_p2_reg8 );
2374 }
2375
2376
op_LDCFBRM()2377 void tlcs900_device::op_LDCFBRM()
2378 {
2379 ldcf8( *m_p1_reg8, RDMEM( m_ea2.d ) );
2380 }
2381
2382
op_LDCFBRR()2383 void tlcs900_device::op_LDCFBRR()
2384 {
2385 ldcf8( *m_p1_reg8, *m_p2_reg8 );
2386 }
2387
2388
op_LDCFWIR()2389 void tlcs900_device::op_LDCFWIR()
2390 {
2391 ldcf16( m_imm1.b.l, *m_p2_reg16 );
2392 }
2393
2394
op_LDCFWRR()2395 void tlcs900_device::op_LDCFWRR()
2396 {
2397 ldcf16( *m_p1_reg8, *m_p2_reg16 );
2398 }
2399
2400
op_LDD()2401 void tlcs900_device::op_LDD()
2402 {
2403 uint16_t *bc = get_reg16_current( 1 );
2404
2405 WRMEM( *m_p1_reg32, RDMEM( *m_p2_reg32 ) );
2406 *m_p1_reg32 -= 1;
2407 *m_p2_reg32 -= 1;
2408 *bc -= 1;
2409 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2410 if ( *bc )
2411 {
2412 m_sr.b.l |= FLAG_VF;
2413 }
2414 }
2415
2416
op_LDDR()2417 void tlcs900_device::op_LDDR()
2418 {
2419 uint16_t *bc = get_reg16_current( 1 );
2420
2421 WRMEM( *m_p1_reg32, RDMEM( *m_p2_reg32 ) );
2422 *m_p1_reg32 -= 1;
2423 *m_p2_reg32 -= 1;
2424 *bc -= 1;
2425 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2426 if ( *bc )
2427 {
2428 m_sr.b.l |= FLAG_VF;
2429 m_pc.d -= 2;
2430 m_cycles += tlcs900_ldxx_repeat_cycles();
2431 m_prefetch_clear = true;
2432 }
2433 }
2434
2435
op_LDDRW()2436 void tlcs900_device::op_LDDRW()
2437 {
2438 uint16_t *bc = get_reg16_current( 1 );
2439
2440 WRMEMW( *m_p1_reg32, RDMEMW( *m_p2_reg32 ) );
2441 *m_p1_reg32 -= 2;
2442 *m_p2_reg32 -= 2;
2443 *bc -= 1;
2444 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2445 if ( *bc )
2446 {
2447 m_sr.b.l |= FLAG_VF;
2448 m_pc.d -= 2;
2449 m_cycles += tlcs900_ldxx_repeat_cycles();
2450 m_prefetch_clear = true;
2451 }
2452 }
2453
2454
op_LDDW()2455 void tlcs900_device::op_LDDW()
2456 {
2457 uint16_t *bc = get_reg16_current( 1 );
2458
2459 WRMEMW( *m_p1_reg32, RDMEMW( *m_p2_reg32 ) );
2460 *m_p1_reg32 -= 2;
2461 *m_p2_reg32 -= 2;
2462 *bc -= 1;
2463 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2464 if ( *bc )
2465 {
2466 m_sr.b.l |= FLAG_VF;
2467 }
2468 }
2469
2470
op_LDF()2471 void tlcs900_device::op_LDF()
2472 {
2473 m_sr.b.h = ( m_sr.b.h & 0xf8 ) | ( m_imm1.b.l & 0x07 );
2474 m_regbank = m_imm1.b.l & 0x03;
2475 }
2476
2477
op_LDI()2478 void tlcs900_device::op_LDI()
2479 {
2480 uint16_t *bc = get_reg16_current( 1 );
2481
2482 WRMEM( *m_p1_reg32, RDMEM( *m_p2_reg32 ) );
2483 *m_p1_reg32 += 1;
2484 *m_p2_reg32 += 1;
2485 *bc -= 1;
2486 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2487 if ( *bc )
2488 {
2489 m_sr.b.l |= FLAG_VF;
2490 }
2491 }
2492
2493
op_LDIR()2494 void tlcs900_device::op_LDIR()
2495 {
2496 uint16_t *bc = get_reg16_current( 1 );
2497
2498 WRMEM( *m_p1_reg32, RDMEM( *m_p2_reg32 ) );
2499 *m_p1_reg32 += 1;
2500 *m_p2_reg32 += 1;
2501 *bc -= 1;
2502 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2503 if ( *bc )
2504 {
2505 m_sr.b.l |= FLAG_VF;
2506 m_pc.d -= 2;
2507 m_cycles += tlcs900_ldxx_repeat_cycles();
2508 m_prefetch_clear = true;
2509 }
2510 }
2511
2512
op_LDIRW()2513 void tlcs900_device::op_LDIRW()
2514 {
2515 uint16_t *bc = get_reg16_current( 1 );
2516
2517 WRMEMW( *m_p1_reg32, RDMEMW( *m_p2_reg32 ) );
2518 *m_p1_reg32 += 2;
2519 *m_p2_reg32 += 2;
2520 *bc -= 1;
2521 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2522 if ( *bc )
2523 {
2524 m_sr.b.l |= FLAG_VF;
2525 m_pc.d -= 2;
2526 m_cycles += tlcs900_ldxx_repeat_cycles();
2527 m_prefetch_clear = true;
2528 }
2529 }
2530
2531
op_LDIW()2532 void tlcs900_device::op_LDIW()
2533 {
2534 uint16_t *bc = get_reg16_current( 1 );
2535
2536 WRMEMW( *m_p1_reg32, RDMEMW( *m_p2_reg32 ) );
2537 *m_p1_reg32 += 2;
2538 *m_p2_reg32 += 2;
2539 *bc -= 1;
2540 m_sr.b.l &= ~ ( FLAG_HF | FLAG_VF | FLAG_NF );
2541 if ( *bc )
2542 {
2543 m_sr.b.l |= FLAG_VF;
2544 }
2545 }
2546
2547
op_LDX()2548 void tlcs900_device::op_LDX()
2549 {
2550 uint8_t a, b;
2551
2552 RDOP();
2553 a = RDOP();
2554 RDOP();
2555 b = RDOP();
2556 RDOP();
2557 WRMEM( a, b );
2558 }
2559
2560
op_LINK()2561 void tlcs900_device::op_LINK()
2562 {
2563 m_xssp.d -= 4;
2564 WRMEML( m_xssp.d, *m_p1_reg32 );
2565 *m_p1_reg32 = m_xssp.d;
2566 m_xssp.d += m_imm2.sw.l;
2567 }
2568
2569
op_MAX()2570 void tlcs900_device::op_MAX()
2571 {
2572 m_sr.b.h |= 0x08;
2573 }
2574
2575
op_MDEC1()2576 void tlcs900_device::op_MDEC1()
2577 {
2578 if ( ( *m_p2_reg16 & m_imm1.w.l ) == m_imm1.w.l )
2579 *m_p2_reg16 += m_imm1.w.l;
2580 else
2581 *m_p2_reg16 -= 1;
2582 }
2583
2584
op_MDEC2()2585 void tlcs900_device::op_MDEC2()
2586 {
2587 if ( ( *m_p2_reg16 & m_imm1.w.l ) == m_imm1.w.l )
2588 *m_p2_reg16 += m_imm1.w.l;
2589 else
2590 *m_p2_reg16 -= 2;
2591 }
2592
2593
op_MDEC4()2594 void tlcs900_device::op_MDEC4()
2595 {
2596 if ( ( *m_p2_reg16 & m_imm1.w.l ) == m_imm1.w.l )
2597 *m_p2_reg16 += m_imm1.w.l;
2598 else
2599 *m_p2_reg16 -= 4;
2600 }
2601
2602
op_MINC1()2603 void tlcs900_device::op_MINC1()
2604 {
2605 if ( ( *m_p2_reg16 & m_imm1.w.l ) == m_imm1.w.l )
2606 *m_p2_reg16 -= m_imm1.w.l;
2607 else
2608 *m_p2_reg16 += 1;
2609 }
2610
2611
op_MINC2()2612 void tlcs900_device::op_MINC2()
2613 {
2614 if ( ( *m_p2_reg16 & m_imm1.w.l ) == m_imm1.w.l )
2615 *m_p2_reg16 -= m_imm1.w.l;
2616 else
2617 *m_p2_reg16 += 2;
2618 }
2619
2620
op_MINC4()2621 void tlcs900_device::op_MINC4()
2622 {
2623 if ( ( *m_p2_reg16 & m_imm1.w.l ) == m_imm1.w.l )
2624 *m_p2_reg16 -= m_imm1.w.l;
2625 else
2626 *m_p2_reg16 += 4;
2627 }
2628
2629
op_MIRRW()2630 void tlcs900_device::op_MIRRW()
2631 {
2632 uint16_t r = *m_p1_reg16;
2633 uint16_t s = ( r & 0x01 );
2634 int i;
2635
2636
2637 for ( i = 0; i < 15; i++ )
2638 {
2639 r >>= 1;
2640 s <<= 1;
2641 s |= ( r & 0x01 );
2642 }
2643
2644 *m_p1_reg16 = s;
2645 }
2646
2647
op_MULBRI()2648 void tlcs900_device::op_MULBRI()
2649 {
2650 *m_p1_reg16 = ( *m_p1_reg16 & 0xff ) * m_imm2.b.l;
2651 }
2652
2653
op_MULBRM()2654 void tlcs900_device::op_MULBRM()
2655 {
2656 *m_p1_reg16 = ( *m_p1_reg16 & 0xff ) * RDMEM( m_ea2.d );
2657 }
2658
2659
op_MULBRR()2660 void tlcs900_device::op_MULBRR()
2661 {
2662 *m_p1_reg16 = ( *m_p1_reg16 & 0xff ) * *m_p2_reg8;
2663 }
2664
2665
op_MULWRI()2666 void tlcs900_device::op_MULWRI()
2667 {
2668 *m_p1_reg32 = ( *m_p1_reg32 & 0xffff ) * m_imm2.w.l;
2669 }
2670
2671
op_MULWRM()2672 void tlcs900_device::op_MULWRM()
2673 {
2674 *m_p1_reg32 = ( *m_p1_reg32 & 0xffff ) * RDMEMW( m_ea2.d );
2675 }
2676
2677
op_MULWRR()2678 void tlcs900_device::op_MULWRR()
2679 {
2680 *m_p1_reg32 = ( *m_p1_reg32 & 0xffff ) * *m_p2_reg16;
2681 }
2682
2683
op_MULAR()2684 void tlcs900_device::op_MULAR()
2685 {
2686 uint32_t *xde = get_reg32_current( 2 );
2687 uint32_t *xhl = get_reg32_current( 3 );
2688
2689 *m_p1_reg32 = *m_p1_reg32 + ( ((int16_t)RDMEMW( *xde )) * ((int16_t)RDMEMW( *xhl )) );
2690 *xhl -= 2;
2691
2692 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_VF );
2693 m_sr.b.l |= ( ( *m_p1_reg32 >> 24 ) & FLAG_SF ) | ( *m_p1_reg32 ? 0 : FLAG_ZF );
2694 }
2695
2696
op_MULSBRI()2697 void tlcs900_device::op_MULSBRI()
2698 {
2699 *m_p1_reg16 = (int8_t)( *m_p1_reg16 & 0xff ) * m_imm2.sb.l;
2700 }
2701
2702
op_MULSBRM()2703 void tlcs900_device::op_MULSBRM()
2704 {
2705 *m_p1_reg16 = (int8_t)( *m_p1_reg16 & 0xff ) * (int8_t)RDMEM( m_ea2.d );
2706 }
2707
2708
op_MULSBRR()2709 void tlcs900_device::op_MULSBRR()
2710 {
2711 *m_p1_reg16 = (int8_t)( *m_p1_reg16 & 0xff ) * (int8_t)*m_p2_reg8;
2712 }
2713
2714
op_MULSWRI()2715 void tlcs900_device::op_MULSWRI()
2716 {
2717 *m_p1_reg32 = (int16_t)( *m_p1_reg32 & 0xffff ) * m_imm2.sw.l;
2718 }
2719
2720
op_MULSWRM()2721 void tlcs900_device::op_MULSWRM()
2722 {
2723 *m_p1_reg32 = (int16_t)( *m_p1_reg32 & 0xffff ) * (int16_t)RDMEMW( m_ea2.d );
2724 }
2725
2726
op_MULSWRR()2727 void tlcs900_device::op_MULSWRR()
2728 {
2729 *m_p1_reg32 = (int16_t)( *m_p1_reg32 & 0xffff ) * (int16_t)*m_p2_reg16;
2730 }
2731
2732
op_NEGBR()2733 void tlcs900_device::op_NEGBR()
2734 {
2735 *m_p1_reg8 = sub8( 0, *m_p1_reg8 );
2736 }
2737
2738
op_NEGWR()2739 void tlcs900_device::op_NEGWR()
2740 {
2741 *m_p1_reg16 = sub16( 0, *m_p1_reg16 );
2742 }
2743
2744
op_NOP()2745 void tlcs900_device::op_NOP()
2746 {
2747 /* Do nothing */
2748 }
2749
2750
op_NORMAL()2751 void tlcs900_device::op_NORMAL()
2752 {
2753 m_sr.b.h &= 0x7F;
2754 }
2755
2756
op_ORBMI()2757 void tlcs900_device::op_ORBMI()
2758 {
2759 WRMEM( m_ea1.d, or8( RDMEM( m_ea1.d ), m_imm2.b.l ) );
2760 }
2761
2762
op_ORBMR()2763 void tlcs900_device::op_ORBMR()
2764 {
2765 WRMEM( m_ea1.d, or8( RDMEM( m_ea1.d ), *m_p2_reg8 ) );
2766 }
2767
2768
op_ORBRI()2769 void tlcs900_device::op_ORBRI()
2770 {
2771 *m_p1_reg8 = or8( *m_p1_reg8, m_imm2.b.l );
2772 }
2773
2774
op_ORBRM()2775 void tlcs900_device::op_ORBRM()
2776 {
2777 *m_p1_reg8 = or8( *m_p1_reg8, RDMEM( m_ea2.d ) );
2778 }
2779
2780
op_ORBRR()2781 void tlcs900_device::op_ORBRR()
2782 {
2783 *m_p1_reg8 = or8( *m_p1_reg8, *m_p2_reg8 );
2784 }
2785
2786
op_ORWMI()2787 void tlcs900_device::op_ORWMI()
2788 {
2789 WRMEMW( m_ea1.d, or16( RDMEMW( m_ea1.d ), m_imm2.w.l ) );
2790 }
2791
2792
op_ORWMR()2793 void tlcs900_device::op_ORWMR()
2794 {
2795 WRMEMW( m_ea1.d, or16( RDMEMW( m_ea1.d ), *m_p2_reg16 ) );
2796 }
2797
2798
op_ORWRI()2799 void tlcs900_device::op_ORWRI()
2800 {
2801 *m_p1_reg16 = or16( *m_p1_reg16, m_imm2.w.l );
2802 }
2803
2804
op_ORWRM()2805 void tlcs900_device::op_ORWRM()
2806 {
2807 *m_p1_reg16 = or16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
2808 }
2809
2810
op_ORWRR()2811 void tlcs900_device::op_ORWRR()
2812 {
2813 *m_p1_reg16 = or16( *m_p1_reg16, *m_p2_reg16 );
2814 }
2815
2816
op_ORLMR()2817 void tlcs900_device::op_ORLMR()
2818 {
2819 WRMEML( m_ea1.d, or32( RDMEML( m_ea1.d ), *m_p2_reg32 ) );
2820 }
2821
2822
op_ORLRI()2823 void tlcs900_device::op_ORLRI()
2824 {
2825 *m_p1_reg32 = or32( *m_p1_reg32, m_imm2.d );
2826 }
2827
2828
op_ORLRM()2829 void tlcs900_device::op_ORLRM()
2830 {
2831 *m_p1_reg32 = or32( *m_p1_reg32, RDMEML( m_ea2.d ) );
2832 }
2833
2834
op_ORLRR()2835 void tlcs900_device::op_ORLRR()
2836 {
2837 *m_p1_reg32 = or32( *m_p1_reg32, *m_p2_reg32 );
2838 }
2839
2840
op_ORCFBIM()2841 void tlcs900_device::op_ORCFBIM()
2842 {
2843 orcf8( m_imm1.b.l, RDMEM( m_ea2.d ) );
2844 }
2845
2846
op_ORCFBIR()2847 void tlcs900_device::op_ORCFBIR()
2848 {
2849 orcf8( m_imm1.b.l, *m_p2_reg8 );
2850 }
2851
2852
op_ORCFBRM()2853 void tlcs900_device::op_ORCFBRM()
2854 {
2855 orcf8( *m_p1_reg8, RDMEM( m_ea2.d ) );
2856 }
2857
2858
op_ORCFBRR()2859 void tlcs900_device::op_ORCFBRR()
2860 {
2861 orcf8( *m_p1_reg8, *m_p2_reg8 );
2862 }
2863
2864
op_ORCFWIR()2865 void tlcs900_device::op_ORCFWIR()
2866 {
2867 orcf16( m_imm1.b.l, *m_p2_reg16 );
2868 }
2869
2870
op_ORCFWRR()2871 void tlcs900_device::op_ORCFWRR()
2872 {
2873 orcf16( *m_p1_reg8, *m_p2_reg16 );
2874 }
2875
2876
op_PAAWR()2877 void tlcs900_device::op_PAAWR()
2878 {
2879 if ( *m_p1_reg16 & 1 )
2880 *m_p1_reg16 += 1;
2881 }
2882
2883
op_PAALR()2884 void tlcs900_device::op_PAALR()
2885 {
2886 if ( *m_p1_reg32 & 1 )
2887 *m_p1_reg32 += 1;
2888 }
2889
2890
op_POPBM()2891 void tlcs900_device::op_POPBM()
2892 {
2893 WRMEM( m_ea1.d, RDMEM( m_xssp.d ) );
2894 m_xssp.d += 1;
2895 }
2896
2897
op_POPBR()2898 void tlcs900_device::op_POPBR()
2899 {
2900 *m_p1_reg8 = RDMEM( m_xssp.d );
2901 m_xssp.d += 1;
2902 }
2903
2904
op_POPWM()2905 void tlcs900_device::op_POPWM()
2906 {
2907 WRMEMW( m_ea1.d, RDMEMW( m_xssp.d ) );
2908 m_xssp.d += 2;
2909 }
2910
2911
op_POPWR()2912 void tlcs900_device::op_POPWR()
2913 {
2914 *m_p1_reg16 = RDMEMW( m_xssp.d );
2915 m_xssp.d += 2;
2916 }
2917
2918
op_POPWSR()2919 void tlcs900_device::op_POPWSR()
2920 {
2921 op_POPWR();
2922 m_regbank = m_sr.b.h & 0x03;
2923 m_check_irqs = 1;
2924 }
2925
2926
op_POPLR()2927 void tlcs900_device::op_POPLR()
2928 {
2929 *m_p1_reg32 = RDMEML( m_xssp.d );
2930 m_xssp.d += 4;
2931 }
2932
2933
op_PUSHBI()2934 void tlcs900_device::op_PUSHBI()
2935 {
2936 m_xssp.d -= 1;
2937 WRMEM( m_xssp.d, m_imm1.b.l );
2938 }
2939
2940
op_PUSHBM()2941 void tlcs900_device::op_PUSHBM()
2942 {
2943 m_xssp.d -= 1;
2944 WRMEM( m_xssp.d, RDMEM( m_ea1.d ) );
2945 }
2946
2947
op_PUSHBR()2948 void tlcs900_device::op_PUSHBR()
2949 {
2950 m_xssp.d -= 1;
2951 WRMEM( m_xssp.d, *m_p1_reg8 );
2952 }
2953
2954
op_PUSHWI()2955 void tlcs900_device::op_PUSHWI()
2956 {
2957 m_xssp.d -= 2;
2958 WRMEMW( m_xssp.d, m_imm1.w.l );
2959 }
2960
2961
op_PUSHWM()2962 void tlcs900_device::op_PUSHWM()
2963 {
2964 m_xssp.d -= 2;
2965 WRMEMW( m_xssp.d, RDMEMW( m_ea1.d ) );
2966 }
2967
2968
op_PUSHWR()2969 void tlcs900_device::op_PUSHWR()
2970 {
2971 m_xssp.d -= 2;
2972 WRMEMW( m_xssp.d, *m_p1_reg16 );
2973 }
2974
2975
op_PUSHLR()2976 void tlcs900_device::op_PUSHLR()
2977 {
2978 m_xssp.d -= 4;
2979 WRMEML( m_xssp.d, *m_p1_reg32 );
2980 }
2981
2982
op_RCF()2983 void tlcs900_device::op_RCF()
2984 {
2985 m_sr.b.l &= ~ ( FLAG_HF | FLAG_NF | FLAG_CF );
2986 }
2987
2988
op_RESBIM()2989 void tlcs900_device::op_RESBIM()
2990 {
2991 WRMEM( m_ea2.d, RDMEM( m_ea2.d ) & ~( 1 << ( m_imm1.d & 0x07 ) ) );
2992 }
2993
2994
op_RESBIR()2995 void tlcs900_device::op_RESBIR()
2996 {
2997 *m_p2_reg8 = *m_p2_reg8 & ~( 1 << ( m_imm1.d & 0x07 ) );
2998 }
2999
3000
op_RESWIR()3001 void tlcs900_device::op_RESWIR()
3002 {
3003 *m_p2_reg16 = *m_p2_reg16 & ~( 1 << ( m_imm1.d & 0x0f ) );
3004 }
3005
3006
op_RET()3007 void tlcs900_device::op_RET()
3008 {
3009 m_pc.d = RDMEML( m_xssp.d );
3010 m_xssp.d += 4;
3011 m_prefetch_clear = true;
3012 }
3013
3014
op_RETCC()3015 void tlcs900_device::op_RETCC()
3016 {
3017 if ( condition_true( m_op ) )
3018 {
3019 m_pc.d = RDMEML( m_xssp.d );
3020 m_xssp.d += 4;
3021 m_cycles += tlcs900_call_true_cycles();
3022 m_prefetch_clear = true;
3023 }
3024 }
3025
3026
op_RETD()3027 void tlcs900_device::op_RETD()
3028 {
3029 m_pc.d = RDMEML( m_xssp.d );
3030 m_xssp.d += 4 + m_imm1.sw.l;
3031 m_prefetch_clear = true;
3032 }
3033
3034
op_RETI()3035 void tlcs900_device::op_RETI()
3036 {
3037 m_sr.w.l = RDMEMW( m_xssp.d );
3038 m_xssp.d += 2;
3039 m_pc.d = RDMEML( m_xssp.d );
3040 m_xssp.d += 4;
3041 m_regbank = m_sr.b.h & 0x03;
3042 m_check_irqs = 1;
3043 m_prefetch_clear = true;
3044 }
3045
3046
op_RLBM()3047 void tlcs900_device::op_RLBM()
3048 {
3049 WRMEM( m_ea2.d, rl8( RDMEM( m_ea2.d ), 1 ) );
3050 }
3051
3052
op_RLWM()3053 void tlcs900_device::op_RLWM()
3054 {
3055 WRMEMW( m_ea2.d, rl16( RDMEMW( m_ea2.d ), 1 ) );
3056 }
3057
3058
op_RLBIR()3059 void tlcs900_device::op_RLBIR()
3060 {
3061 *m_p2_reg8 = rl8( *m_p2_reg8, m_imm1.b.l );
3062 }
3063
3064
op_RLBRR()3065 void tlcs900_device::op_RLBRR()
3066 {
3067 *m_p2_reg8 = rl8( *m_p2_reg8, *m_p1_reg8 );
3068 }
3069
3070
op_RLWIR()3071 void tlcs900_device::op_RLWIR()
3072 {
3073 *m_p2_reg16 = rl16( *m_p2_reg16, m_imm1.b.l );
3074 }
3075
3076
op_RLWRR()3077 void tlcs900_device::op_RLWRR()
3078 {
3079 *m_p2_reg16 = rl16( *m_p2_reg16, *m_p1_reg8 );
3080 }
3081
3082
op_RLLIR()3083 void tlcs900_device::op_RLLIR()
3084 {
3085 *m_p2_reg32 = rl32( *m_p2_reg32, m_imm1.b.l );
3086 }
3087
3088
op_RLLRR()3089 void tlcs900_device::op_RLLRR()
3090 {
3091 *m_p2_reg32 = rl32( *m_p2_reg32, *m_p1_reg8 );
3092 }
3093
3094
op_RLCBM()3095 void tlcs900_device::op_RLCBM()
3096 {
3097 WRMEM( m_ea2.d, rlc8( RDMEM( m_ea2.d ), 1 ) );
3098 }
3099
3100
op_RLCWM()3101 void tlcs900_device::op_RLCWM()
3102 {
3103 WRMEMW( m_ea2.d, rlc16( RDMEMW( m_ea2.d ), 1 ) );
3104 }
3105
3106
op_RLCBIR()3107 void tlcs900_device::op_RLCBIR()
3108 {
3109 *m_p2_reg8 = rlc8( *m_p2_reg8, m_imm1.b.l );
3110 }
3111
3112
op_RLCBRR()3113 void tlcs900_device::op_RLCBRR()
3114 {
3115 *m_p2_reg8 = rlc8( *m_p2_reg8, *m_p1_reg8 );
3116 }
3117
3118
op_RLCWIR()3119 void tlcs900_device::op_RLCWIR()
3120 {
3121 *m_p2_reg16 = rlc16( *m_p2_reg16, m_imm1.b.l );
3122 }
3123
3124
op_RLCWRR()3125 void tlcs900_device::op_RLCWRR()
3126 {
3127 *m_p2_reg16 = rlc16( *m_p2_reg16, *m_p1_reg8 );
3128 }
3129
3130
op_RLCLIR()3131 void tlcs900_device::op_RLCLIR()
3132 {
3133 *m_p2_reg32 = rlc32( *m_p2_reg32, m_imm1.b.l );
3134 }
3135
3136
op_RLCLRR()3137 void tlcs900_device::op_RLCLRR()
3138 {
3139 *m_p2_reg32 = rlc32( *m_p2_reg32, *m_p1_reg8 );
3140 }
3141
3142
op_RLDRM()3143 void tlcs900_device::op_RLDRM()
3144 {
3145 uint8_t a = *m_p1_reg8 & 0x0f;
3146 uint8_t b = RDMEM( m_ea2.d );
3147
3148 *m_p1_reg8 = ( *m_p1_reg8 & 0xf0 ) | ( ( b & 0xf0 ) >> 4 );
3149 WRMEM( m_ea2.d, ( ( b & 0x0f ) << 4 ) | a );
3150 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
3151 m_sr.b.l |= ( *m_p1_reg8 & FLAG_SF ) | ( *m_p1_reg8 ? 0 : FLAG_ZF );
3152 parity8( *m_p1_reg8 );
3153 }
3154
3155
op_RRBM()3156 void tlcs900_device::op_RRBM()
3157 {
3158 WRMEM( m_ea2.d, rr8( RDMEM( m_ea2.d ), 1 ) );
3159 }
3160
3161
op_RRWM()3162 void tlcs900_device::op_RRWM()
3163 {
3164 WRMEMW( m_ea2.d, rr16( RDMEMW( m_ea2.d ), 1 ) );
3165 }
3166
3167
op_RRBIR()3168 void tlcs900_device::op_RRBIR()
3169 {
3170 *m_p2_reg8 = rr8( *m_p2_reg8, m_imm1.b.l );
3171 }
3172
3173
op_RRBRR()3174 void tlcs900_device::op_RRBRR()
3175 {
3176 *m_p2_reg8 = rr8( *m_p2_reg8, *m_p1_reg8 );
3177 }
3178
3179
op_RRWIR()3180 void tlcs900_device::op_RRWIR()
3181 {
3182 *m_p2_reg16 = rr16( *m_p2_reg16, m_imm1.b.l );
3183 }
3184
3185
op_RRWRR()3186 void tlcs900_device::op_RRWRR()
3187 {
3188 *m_p2_reg16 = rr16( *m_p2_reg16, *m_p1_reg8 );
3189 }
3190
3191
op_RRLIR()3192 void tlcs900_device::op_RRLIR()
3193 {
3194 *m_p2_reg32 = rr32( *m_p2_reg32, m_imm1.b.l );
3195 }
3196
3197
op_RRLRR()3198 void tlcs900_device::op_RRLRR()
3199 {
3200 *m_p2_reg32 = rr32( *m_p2_reg32, *m_p1_reg8 );
3201 }
3202
3203
op_RRCBM()3204 void tlcs900_device::op_RRCBM()
3205 {
3206 WRMEM( m_ea2.d, rrc8( RDMEM( m_ea2.d ), 1 ) );
3207 }
3208
3209
op_RRCWM()3210 void tlcs900_device::op_RRCWM()
3211 {
3212 WRMEMW( m_ea2.d, rrc16( RDMEMW( m_ea2.d ), 1 ) );
3213 }
3214
3215
op_RRCBIR()3216 void tlcs900_device::op_RRCBIR()
3217 {
3218 *m_p2_reg8 = rrc8( *m_p2_reg8, m_imm1.b.l );
3219 }
3220
3221
op_RRCBRR()3222 void tlcs900_device::op_RRCBRR()
3223 {
3224 *m_p2_reg8 = rrc8( *m_p2_reg8, *m_p1_reg8 );
3225 }
3226
3227
op_RRCWIR()3228 void tlcs900_device::op_RRCWIR()
3229 {
3230 *m_p2_reg16 = rrc16( *m_p2_reg16, m_imm1.b.l );
3231 }
3232
3233
op_RRCWRR()3234 void tlcs900_device::op_RRCWRR()
3235 {
3236 *m_p2_reg16 = rrc16( *m_p2_reg16, *m_p1_reg8 );
3237 }
3238
3239
op_RRCLIR()3240 void tlcs900_device::op_RRCLIR()
3241 {
3242 *m_p2_reg32 = rrc32( *m_p2_reg32, m_imm1.b.l );
3243 }
3244
3245
op_RRCLRR()3246 void tlcs900_device::op_RRCLRR()
3247 {
3248 *m_p2_reg32 = rrc32( *m_p2_reg32, *m_p1_reg8 );
3249 }
3250
3251
op_RRDRM()3252 void tlcs900_device::op_RRDRM()
3253 {
3254 uint8_t a = *m_p1_reg8 & 0x0f;
3255 uint8_t b = RDMEM( m_ea2.d );
3256
3257 *m_p1_reg8 = ( *m_p1_reg8 & 0xf0 ) | ( b & 0x0f );
3258 WRMEM( m_ea2.d, ( ( b & 0xf0 ) >> 4 ) | ( a << 4 ) );
3259 m_sr.b.l &= ~ ( FLAG_SF | FLAG_ZF | FLAG_HF | FLAG_VF | FLAG_NF | FLAG_CF );
3260 m_sr.b.l |= ( *m_p1_reg8 & FLAG_SF ) | ( *m_p1_reg8 ? 0 : FLAG_ZF );
3261 parity8( *m_p1_reg8 );
3262 }
3263
3264
op_SBCBMI()3265 void tlcs900_device::op_SBCBMI()
3266 {
3267 WRMEM( m_ea1.d, sbc8( RDMEM( m_ea1.d ), m_imm2.b.l ) );
3268 }
3269
3270
op_SBCBMR()3271 void tlcs900_device::op_SBCBMR()
3272 {
3273 WRMEM( m_ea1.d, sbc8( RDMEM( m_ea1.d ), *m_p2_reg8 ) );
3274 }
3275
3276
op_SBCBRI()3277 void tlcs900_device::op_SBCBRI()
3278 {
3279 *m_p1_reg8 = sbc8( *m_p1_reg8, m_imm2.b.l );
3280 }
3281
3282
op_SBCBRM()3283 void tlcs900_device::op_SBCBRM()
3284 {
3285 *m_p1_reg8 = sbc8( *m_p1_reg8, RDMEM( m_ea2.d ) );
3286 }
3287
3288
op_SBCBRR()3289 void tlcs900_device::op_SBCBRR()
3290 {
3291 *m_p1_reg8 = sbc8( *m_p1_reg8, *m_p2_reg8 );
3292 }
3293
3294
op_SBCWMI()3295 void tlcs900_device::op_SBCWMI()
3296 {
3297 WRMEMW( m_ea1.d, sbc16( RDMEMW( m_ea1.d ), m_imm2.w.l ) );
3298 }
3299
3300
op_SBCWMR()3301 void tlcs900_device::op_SBCWMR()
3302 {
3303 WRMEMW( m_ea1.d, sbc16( RDMEMW( m_ea1.d ), *m_p2_reg16 ) );
3304 }
3305
3306
op_SBCWRI()3307 void tlcs900_device::op_SBCWRI()
3308 {
3309 *m_p1_reg16 = sbc16( *m_p1_reg16, m_imm2.w.l );
3310 }
3311
3312
op_SBCWRM()3313 void tlcs900_device::op_SBCWRM()
3314 {
3315 *m_p1_reg16 = sbc16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
3316 }
3317
3318
op_SBCWRR()3319 void tlcs900_device::op_SBCWRR()
3320 {
3321 *m_p1_reg16 = sbc16( *m_p1_reg16, *m_p2_reg16 );
3322 }
3323
3324
op_SBCLMR()3325 void tlcs900_device::op_SBCLMR()
3326 {
3327 WRMEML( m_ea1.d, sbc32( RDMEML( m_ea1.d ), *m_p2_reg32 ) );
3328 }
3329
3330
op_SBCLRI()3331 void tlcs900_device::op_SBCLRI()
3332 {
3333 *m_p1_reg32 = sbc32( *m_p1_reg32, m_imm2.d );
3334 }
3335
3336
op_SBCLRM()3337 void tlcs900_device::op_SBCLRM()
3338 {
3339 *m_p1_reg32 = sbc32( *m_p1_reg32, RDMEML( m_ea2.d ) );
3340 }
3341
3342
op_SBCLRR()3343 void tlcs900_device::op_SBCLRR()
3344 {
3345 *m_p1_reg32 = sbc32( *m_p1_reg32, *m_p2_reg32 );
3346 }
3347
3348
op_SCCBR()3349 void tlcs900_device::op_SCCBR()
3350 {
3351 *m_p2_reg8 = condition_true( m_op ) ? 1 : 0;
3352 }
3353
3354
op_SCCWR()3355 void tlcs900_device::op_SCCWR()
3356 {
3357 *m_p2_reg16 = condition_true( m_op ) ? 1 : 0;
3358 }
3359
3360
op_SCF()3361 void tlcs900_device::op_SCF()
3362 {
3363 m_sr.b.l &= ~ ( FLAG_HF | FLAG_NF );
3364 m_sr.b.l |= FLAG_CF;
3365 }
3366
3367
op_SETBIM()3368 void tlcs900_device::op_SETBIM()
3369 {
3370 WRMEM( m_ea2.d, RDMEM( m_ea2.d ) | ( 1 << ( m_imm1.d & 0x07 ) ) );
3371 }
3372
3373
op_SETBIR()3374 void tlcs900_device::op_SETBIR()
3375 {
3376 *m_p2_reg8 = *m_p2_reg8 | ( 1 << ( m_imm1.d & 0x07 ) );
3377 }
3378
3379
op_SETWIR()3380 void tlcs900_device::op_SETWIR()
3381 {
3382 *m_p2_reg16 = *m_p2_reg16 | ( 1 << ( m_imm1.d & 0x0f ) );
3383 }
3384
3385
op_SLABM()3386 void tlcs900_device::op_SLABM()
3387 {
3388 WRMEM( m_ea2.d, sla8( RDMEM( m_ea2.d ), 1 ) );
3389 }
3390
3391
op_SLAWM()3392 void tlcs900_device::op_SLAWM()
3393 {
3394 WRMEMW( m_ea2.d, sla16( RDMEMW( m_ea2.d ), 1 ) );
3395 }
3396
3397
op_SLABIR()3398 void tlcs900_device::op_SLABIR()
3399 {
3400 *m_p2_reg8 = sla8( *m_p2_reg8, m_imm1.b.l );
3401 }
3402
3403
op_SLABRR()3404 void tlcs900_device::op_SLABRR()
3405 {
3406 *m_p2_reg8 = sla8( *m_p2_reg8, *m_p1_reg8 );
3407 }
3408
3409
op_SLAWIR()3410 void tlcs900_device::op_SLAWIR()
3411 {
3412 *m_p2_reg16 = sla16( *m_p2_reg16, m_imm1.b.l );
3413 }
3414
3415
op_SLAWRR()3416 void tlcs900_device::op_SLAWRR()
3417 {
3418 *m_p2_reg16 = sla16( *m_p2_reg16, *m_p1_reg8 );
3419 }
3420
3421
op_SLALIR()3422 void tlcs900_device::op_SLALIR()
3423 {
3424 *m_p2_reg32 = sla32( *m_p2_reg32, m_imm1.b.l );
3425 }
3426
3427
op_SLALRR()3428 void tlcs900_device::op_SLALRR()
3429 {
3430 *m_p2_reg32 = sla32( *m_p2_reg32, *m_p1_reg8 );
3431 }
3432
3433
op_SLLBM()3434 void tlcs900_device::op_SLLBM()
3435 {
3436 WRMEM( m_ea2.d, sla8( RDMEM( m_ea2.d ), 1 ) );
3437 }
3438
3439
op_SLLWM()3440 void tlcs900_device::op_SLLWM()
3441 {
3442 WRMEMW( m_ea2.d, sla16( RDMEMW( m_ea2.d ), 1 ) );
3443 }
3444
3445
op_SLLBIR()3446 void tlcs900_device::op_SLLBIR()
3447 {
3448 *m_p2_reg8 = sla8( *m_p2_reg8, m_imm1.b.l );
3449 }
3450
3451
op_SLLBRR()3452 void tlcs900_device::op_SLLBRR()
3453 {
3454 *m_p2_reg8 = sla8( *m_p2_reg8, *m_p1_reg8 );
3455 }
3456
3457
op_SLLWIR()3458 void tlcs900_device::op_SLLWIR()
3459 {
3460 *m_p2_reg16 = sla16( *m_p2_reg16, m_imm1.b.l );
3461 }
3462
3463
op_SLLWRR()3464 void tlcs900_device::op_SLLWRR()
3465 {
3466 *m_p2_reg16 = sla16( *m_p2_reg16, *m_p1_reg8 );
3467 }
3468
3469
op_SLLLIR()3470 void tlcs900_device::op_SLLLIR()
3471 {
3472 *m_p2_reg32 = sla32( *m_p2_reg32, m_imm1.b.l );
3473 }
3474
3475
op_SLLLRR()3476 void tlcs900_device::op_SLLLRR()
3477 {
3478 *m_p2_reg32 = sla32( *m_p2_reg32, *m_p1_reg8 );
3479 }
3480
3481
op_SRABM()3482 void tlcs900_device::op_SRABM()
3483 {
3484 WRMEM( m_ea2.d, sra8( RDMEM( m_ea2.d ), 1 ) );
3485 }
3486
3487
op_SRAWM()3488 void tlcs900_device::op_SRAWM()
3489 {
3490 WRMEMW( m_ea2.d, sra16( RDMEMW( m_ea2.d ), 1 ) );
3491 }
3492
3493
op_SRABIR()3494 void tlcs900_device::op_SRABIR()
3495 {
3496 *m_p2_reg8 = sra8( *m_p2_reg8, m_imm1.b.l );
3497 }
3498
3499
op_SRABRR()3500 void tlcs900_device::op_SRABRR()
3501 {
3502 *m_p2_reg8 = sra8( *m_p2_reg8, *m_p1_reg8 );
3503 }
3504
3505
op_SRAWIR()3506 void tlcs900_device::op_SRAWIR()
3507 {
3508 *m_p2_reg16 = sra16( *m_p2_reg16, m_imm1.b.l );
3509 }
3510
3511
op_SRAWRR()3512 void tlcs900_device::op_SRAWRR()
3513 {
3514 *m_p2_reg16 = sra16( *m_p2_reg16, *m_p1_reg8 );
3515 }
3516
3517
op_SRALIR()3518 void tlcs900_device::op_SRALIR()
3519 {
3520 *m_p2_reg32 = sra32( *m_p2_reg32, m_imm1.b.l );
3521 }
3522
3523
op_SRALRR()3524 void tlcs900_device::op_SRALRR()
3525 {
3526 *m_p2_reg32 = sra32( *m_p2_reg32, *m_p1_reg8 );
3527 }
3528
3529
op_SRLBM()3530 void tlcs900_device::op_SRLBM()
3531 {
3532 WRMEM( m_ea2.d, srl8( RDMEM( m_ea2.d ), 1 ) );
3533 }
3534
3535
op_SRLWM()3536 void tlcs900_device::op_SRLWM()
3537 {
3538 WRMEMW( m_ea2.d, srl16( RDMEMW( m_ea2.d ), 1 ) );
3539 }
3540
3541
op_SRLBIR()3542 void tlcs900_device::op_SRLBIR()
3543 {
3544 *m_p2_reg8 = srl8( *m_p2_reg8, m_imm1.b.l );
3545 }
3546
3547
op_SRLBRR()3548 void tlcs900_device::op_SRLBRR()
3549 {
3550 *m_p2_reg8 = srl8( *m_p2_reg8, *m_p1_reg8 );
3551 }
3552
3553
op_SRLWIR()3554 void tlcs900_device::op_SRLWIR()
3555 {
3556 *m_p2_reg16 = srl16( *m_p2_reg16, m_imm1.b.l );
3557 }
3558
3559
op_SRLWRR()3560 void tlcs900_device::op_SRLWRR()
3561 {
3562 *m_p2_reg16 = srl16( *m_p2_reg16, *m_p1_reg8 );
3563 }
3564
3565
op_SRLLIR()3566 void tlcs900_device::op_SRLLIR()
3567 {
3568 *m_p2_reg32 = srl32( *m_p2_reg32, m_imm1.b.l );
3569 }
3570
3571
op_SRLLRR()3572 void tlcs900_device::op_SRLLRR()
3573 {
3574 *m_p2_reg32 = srl32( *m_p2_reg32, *m_p1_reg8 );
3575 }
3576
3577
op_STCFBIM()3578 void tlcs900_device::op_STCFBIM()
3579 {
3580 if ( m_sr.b.l & FLAG_CF )
3581 WRMEM( m_ea2.d, RDMEM( m_ea2.d ) | ( 1 << ( m_imm1.b.l & 0x07 ) ) );
3582 else
3583 WRMEM( m_ea2.d, RDMEM( m_ea2.d ) & ~ ( 1 << ( m_imm1.b.l & 0x07 ) ) );
3584 }
3585
3586
op_STCFBIR()3587 void tlcs900_device::op_STCFBIR()
3588 {
3589 if ( m_sr.b.l & FLAG_CF )
3590 *m_p2_reg8 |= ( 1 << ( m_imm1.b.l & 0x07 ) );
3591 else
3592 *m_p2_reg8 &= ~ ( 1 << ( m_imm1.b.l & 0x07 ) );
3593 }
3594
3595
op_STCFBRM()3596 void tlcs900_device::op_STCFBRM()
3597 {
3598 if ( m_sr.b.l & FLAG_CF )
3599 WRMEM( m_ea2.d, RDMEM( m_ea2.d ) | ( 1 << ( *m_p1_reg8 & 0x07 ) ) );
3600 else
3601 WRMEM( m_ea2.d, RDMEM( m_ea2.d ) & ~ ( 1 << ( *m_p1_reg8 & 0x07 ) ) );
3602 }
3603
3604
op_STCFBRR()3605 void tlcs900_device::op_STCFBRR()
3606 {
3607 if ( m_sr.b.l & FLAG_CF )
3608 *m_p2_reg8 |= ( 1 << ( *m_p1_reg8 & 0x07 ) );
3609 else
3610 *m_p2_reg8 &= ~ ( 1 << ( *m_p1_reg8 & 0x07 ) );
3611 }
3612
3613
op_STCFWIR()3614 void tlcs900_device::op_STCFWIR()
3615 {
3616 if ( m_sr.b.l & FLAG_CF )
3617 *m_p2_reg16 |= ( 1 << ( m_imm1.b.l & 0x0f ) );
3618 else
3619 *m_p2_reg16 &= ~ ( 1 << ( m_imm1.b.l & 0x0f ) );
3620 }
3621
3622
op_STCFWRR()3623 void tlcs900_device::op_STCFWRR()
3624 {
3625 if ( m_sr.b.l & FLAG_CF )
3626 *m_p2_reg16 |= ( 1 << ( *m_p1_reg8 & 0x0f ) );
3627 else
3628 *m_p2_reg16 &= ~ ( 1 << ( *m_p1_reg8 & 0x0f ) );
3629 }
3630
3631
op_SUBBMI()3632 void tlcs900_device::op_SUBBMI()
3633 {
3634 WRMEM( m_ea1.d, sub8( RDMEM( m_ea1.d ), m_imm2.b.l ) );
3635 }
3636
3637
op_SUBBMR()3638 void tlcs900_device::op_SUBBMR()
3639 {
3640 WRMEM( m_ea1.d, sub8( RDMEM( m_ea1.d ), *m_p2_reg8 ) );
3641 }
3642
3643
op_SUBBRI()3644 void tlcs900_device::op_SUBBRI()
3645 {
3646 *m_p1_reg8 = sub8( *m_p1_reg8, m_imm2.b.l );
3647 }
3648
3649
op_SUBBRM()3650 void tlcs900_device::op_SUBBRM()
3651 {
3652 *m_p1_reg8 = sub8( *m_p1_reg8, RDMEM( m_ea2.d ) );
3653 }
3654
3655
op_SUBBRR()3656 void tlcs900_device::op_SUBBRR()
3657 {
3658 *m_p1_reg8 = sub8( *m_p1_reg8, *m_p2_reg8 );
3659 }
3660
3661
op_SUBWMI()3662 void tlcs900_device::op_SUBWMI()
3663 {
3664 WRMEMW( m_ea1.d, sub16( RDMEMW( m_ea1.d ), m_imm2.w.l ) );
3665 }
3666
3667
op_SUBWMR()3668 void tlcs900_device::op_SUBWMR()
3669 {
3670 WRMEMW( m_ea1.d, sub16( RDMEMW( m_ea1.d ), *m_p2_reg16 ) );
3671 }
3672
3673
op_SUBWRI()3674 void tlcs900_device::op_SUBWRI()
3675 {
3676 *m_p1_reg16 = sub16( *m_p1_reg16, m_imm2.w.l );
3677 }
3678
3679
op_SUBWRM()3680 void tlcs900_device::op_SUBWRM()
3681 {
3682 *m_p1_reg16 = sub16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
3683 }
3684
3685
op_SUBWRR()3686 void tlcs900_device::op_SUBWRR()
3687 {
3688 *m_p1_reg16 = sub16( *m_p1_reg16, *m_p2_reg16 );
3689 }
3690
3691
op_SUBLMR()3692 void tlcs900_device::op_SUBLMR()
3693 {
3694 WRMEML( m_ea1.d, sub32( RDMEML( m_ea1.d ), *m_p2_reg32 ) );
3695 }
3696
3697
op_SUBLRI()3698 void tlcs900_device::op_SUBLRI()
3699 {
3700 *m_p1_reg32 = sub32( *m_p1_reg32, m_imm2.d );
3701 }
3702
3703
op_SUBLRM()3704 void tlcs900_device::op_SUBLRM()
3705 {
3706 *m_p1_reg32 = sub32( *m_p1_reg32, RDMEML( m_ea2.d ) );
3707 }
3708
3709
op_SUBLRR()3710 void tlcs900_device::op_SUBLRR()
3711 {
3712 *m_p1_reg32 = sub32( *m_p1_reg32, *m_p2_reg32 );
3713 }
3714
3715
op_SWI()3716 void tlcs900_device::op_SWI()
3717 {
3718 m_xssp.d -= 4;
3719 WRMEML( m_xssp.d, m_pc.d );
3720 m_xssp.d -= 2;
3721 WRMEMW( m_xssp.d, m_sr.w.l );
3722 m_pc.d = RDMEML( 0x00ffff00 + 4 * m_imm1.b.l );
3723 m_prefetch_clear = true;
3724 }
3725
3726
op_SWI900()3727 void tlcs900_device::op_SWI900()
3728 {
3729 m_xssp.d -= 4;
3730 WRMEML( m_xssp.d, m_pc.d );
3731 m_xssp.d -= 2;
3732 WRMEMW( m_xssp.d, m_sr.w.l );
3733 m_pc.d = 0x00008000 + 0x10 * m_imm1.b.l;
3734 m_prefetch_clear = true;
3735 }
3736
3737
op_TSETBIM()3738 void tlcs900_device::op_TSETBIM()
3739 {
3740 uint8_t b = 1 << ( m_imm1.b.l & 0x07 );
3741 uint8_t a = RDMEM( m_ea2.d );
3742
3743 m_sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
3744 m_sr.b.l |= ( ( a & b ) ? 0 : FLAG_ZF ) | FLAG_HF;
3745 WRMEM( m_ea2.d, a | b );
3746 }
3747
3748
op_TSETBIR()3749 void tlcs900_device::op_TSETBIR()
3750 {
3751 uint8_t b = 1 << ( m_imm1.b.l & 0x07 );
3752
3753 m_sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
3754 m_sr.b.l |= ( ( *m_p2_reg8 & b ) ? 0 : FLAG_ZF ) | FLAG_HF;
3755 *m_p2_reg8 |= b;
3756 }
3757
3758
op_TSETWIR()3759 void tlcs900_device::op_TSETWIR()
3760 {
3761 uint16_t b = 1 << ( m_imm1.b.l & 0x0f );
3762
3763 m_sr.b.l &= ~ ( FLAG_ZF | FLAG_NF );
3764 m_sr.b.l |= ( ( *m_p2_reg16 & b ) ? 0 : FLAG_ZF ) | FLAG_HF;
3765 *m_p2_reg16 |= b;
3766 }
3767
3768
op_UNLK()3769 void tlcs900_device::op_UNLK()
3770 {
3771 m_xssp.d = *m_p1_reg32;
3772 *m_p1_reg32 = RDMEML( m_xssp.d );
3773 m_xssp.d += 4;
3774 }
3775
3776
op_XORBMI()3777 void tlcs900_device::op_XORBMI()
3778 {
3779 WRMEM( m_ea1.d, xor8( RDMEM( m_ea1.d ), m_imm2.b.l ) );
3780 }
3781
3782
op_XORBMR()3783 void tlcs900_device::op_XORBMR()
3784 {
3785 WRMEM( m_ea1.d, xor8( RDMEM( m_ea1.d ), *m_p2_reg8 ) );
3786 }
3787
3788
op_XORBRI()3789 void tlcs900_device::op_XORBRI()
3790 {
3791 *m_p1_reg8 = xor8( *m_p1_reg8, m_imm2.b.l );
3792 }
3793
3794
op_XORBRM()3795 void tlcs900_device::op_XORBRM()
3796 {
3797 *m_p1_reg8 = xor8( *m_p1_reg8, RDMEM( m_ea2.d ) );
3798 }
3799
3800
op_XORBRR()3801 void tlcs900_device::op_XORBRR()
3802 {
3803 *m_p1_reg8 = xor8( *m_p1_reg8, *m_p2_reg8 );
3804 }
3805
3806
op_XORWMI()3807 void tlcs900_device::op_XORWMI()
3808 {
3809 WRMEMW( m_ea1.d, xor16( RDMEMW( m_ea1.d ), m_imm2.w.l ) );
3810 }
3811
3812
op_XORWMR()3813 void tlcs900_device::op_XORWMR()
3814 {
3815 WRMEMW( m_ea1.d, xor16( RDMEMW( m_ea1.d ), *m_p2_reg16 ) );
3816 }
3817
3818
op_XORWRI()3819 void tlcs900_device::op_XORWRI()
3820 {
3821 *m_p1_reg16 = xor16( *m_p1_reg16, m_imm2.w.l );
3822 }
3823
3824
op_XORWRM()3825 void tlcs900_device::op_XORWRM()
3826 {
3827 *m_p1_reg16 = xor16( *m_p1_reg16, RDMEMW( m_ea2.d ) );
3828 }
3829
3830
op_XORWRR()3831 void tlcs900_device::op_XORWRR()
3832 {
3833 *m_p1_reg16 = xor16( *m_p1_reg16, *m_p2_reg16 );
3834 }
3835
3836
op_XORLMR()3837 void tlcs900_device::op_XORLMR()
3838 {
3839 WRMEML( m_ea1.d, xor32( RDMEML( m_ea1.d ), *m_p2_reg32 ) );
3840 }
3841
3842
op_XORLRI()3843 void tlcs900_device::op_XORLRI()
3844 {
3845 *m_p1_reg32 = xor32( *m_p1_reg32, m_imm2.d );
3846 }
3847
3848
op_XORLRM()3849 void tlcs900_device::op_XORLRM()
3850 {
3851 *m_p1_reg32 = xor32( *m_p1_reg32, RDMEML( m_ea2.d ) );
3852 }
3853
3854
op_XORLRR()3855 void tlcs900_device::op_XORLRR()
3856 {
3857 *m_p1_reg32 = xor32( *m_p1_reg32, *m_p2_reg32 );
3858 }
3859
3860
op_XORCFBIM()3861 void tlcs900_device::op_XORCFBIM()
3862 {
3863 xorcf8( m_imm1.b.l, RDMEM( m_ea2.d ) );
3864 }
3865
3866
op_XORCFBIR()3867 void tlcs900_device::op_XORCFBIR()
3868 {
3869 xorcf8( m_imm1.b.l, *m_p2_reg8 );
3870 }
3871
3872
op_XORCFBRM()3873 void tlcs900_device::op_XORCFBRM()
3874 {
3875 xorcf8( *m_p1_reg8, RDMEM( m_ea2.d ) );
3876 }
3877
3878
op_XORCFBRR()3879 void tlcs900_device::op_XORCFBRR()
3880 {
3881 xorcf8( *m_p1_reg8, *m_p2_reg8 );
3882 }
3883
3884
op_XORCFWIR()3885 void tlcs900_device::op_XORCFWIR()
3886 {
3887 xorcf16( m_imm1.b.l, *m_p2_reg16 );
3888 }
3889
3890
op_XORCFWRR()3891 void tlcs900_device::op_XORCFWRR()
3892 {
3893 xorcf16( *m_p1_reg8, *m_p2_reg16 );
3894 }
3895
3896
op_ZCF()3897 void tlcs900_device::op_ZCF()
3898 {
3899 m_sr.b.l &= ~ ( FLAG_NF | FLAG_CF );
3900 m_sr.b.l |= ( ( m_sr.b.l & FLAG_ZF ) ? 0 : FLAG_CF );
3901 }
3902
3903
prepare_operands(const tlcs900inst * inst)3904 void tlcs900_device::prepare_operands(const tlcs900inst *inst)
3905 {
3906 switch ( inst->operand1 )
3907 {
3908 case p_A:
3909 m_p1_reg8 = &m_xwa[m_regbank].b.l;
3910 break;
3911 case p_F:
3912 m_p1_reg8 = &m_sr.b.l;
3913 break;
3914 case p_SR:
3915 m_p1_reg16 = &m_sr.w.l;
3916 break;
3917 case p_C8:
3918 m_p1_reg8 = get_reg8_current( m_op );
3919 break;
3920 case p_C16:
3921 m_p1_reg16 = get_reg16_current( m_op );
3922 break;
3923 case p_MC16: /* For MUL and DIV operations */
3924 m_p1_reg16 = get_reg16_current( ( m_op >> 1 ) & 0x03 );
3925 break;
3926 case p_C32:
3927 m_p1_reg32 = get_reg32_current( m_op );
3928 break;
3929 case p_CR8:
3930 m_imm1.d = RDOP();
3931 switch( m_imm1.d )
3932 {
3933 case 0x22:
3934 m_p1_reg8 = &m_dmam[0].b.l;
3935 break;
3936 case 0x26:
3937 m_p1_reg8 = &m_dmam[1].b.l;
3938 break;
3939 case 0x2a:
3940 m_p1_reg8 = &m_dmam[2].b.l;
3941 break;
3942 case 0x2e:
3943 m_p1_reg8 = &m_dmam[3].b.l;
3944 break;
3945 default:
3946 m_p1_reg8 = &m_dummy.b.l;
3947 break;
3948 }
3949 break;
3950 case p_CR16:
3951 m_imm1.d = RDOP();
3952 switch( m_imm1.d )
3953 {
3954 case 0x20:
3955 m_p1_reg16 = &m_dmac[0].w.l;
3956 break;
3957 case 0x24:
3958 m_p1_reg16 = &m_dmac[1].w.l;
3959 break;
3960 case 0x28:
3961 m_p1_reg16 = &m_dmac[2].w.l;
3962 break;
3963 case 0x2c:
3964 m_p1_reg16 = &m_dmac[3].w.l;
3965 break;
3966 default:
3967 m_p1_reg16 = &m_dummy.w.l;
3968 break;
3969 }
3970 break;
3971 case p_CR32:
3972 m_imm1.d = RDOP();
3973 switch( m_imm1.d )
3974 {
3975 case 0x00:
3976 m_p1_reg32 = &m_dmas[0].d;
3977 break;
3978 case 0x04:
3979 m_p1_reg32 = &m_dmas[1].d;
3980 break;
3981 case 0x08:
3982 m_p1_reg32 = &m_dmas[2].d;
3983 break;
3984 case 0x0c:
3985 m_p1_reg32 = &m_dmas[3].d;
3986 break;
3987 case 0x10:
3988 m_p1_reg32 = &m_dmad[0].d;
3989 break;
3990 case 0x14:
3991 m_p1_reg32 = &m_dmad[1].d;
3992 break;
3993 case 0x18:
3994 m_p1_reg32 = &m_dmad[2].d;
3995 break;
3996 case 0x1c:
3997 m_p1_reg32 = &m_dmad[3].d;
3998 break;
3999 default:
4000 m_p1_reg32 = &m_dummy.d;
4001 break;
4002 }
4003 break;
4004 case p_D8:
4005 m_ea1.d = RDOP();
4006 m_ea1.d = m_pc.d + m_ea1.sb.l;
4007 break;
4008 case p_D16:
4009 m_ea1.d = RDOP();
4010 m_ea1.b.h = RDOP();
4011 m_ea1.d = m_pc.d + m_ea1.sw.l;
4012 break;
4013 case p_I3:
4014 m_imm1.d = m_op & 0x07;
4015 break;
4016 case p_I8:
4017 m_imm1.d = RDOP();
4018 break;
4019 case p_I16:
4020 m_imm1.d = RDOP();
4021 m_imm1.b.h = RDOP();
4022 break;
4023 case p_I24:
4024 m_imm1.d = RDOP();
4025 m_imm1.b.h = RDOP();
4026 m_imm1.b.h2 = RDOP();
4027 break;
4028 case p_I32:
4029 m_imm1.d = RDOP();
4030 m_imm1.b.h = RDOP();
4031 m_imm1.b.h2 = RDOP();
4032 m_imm1.b.h3 = RDOP();
4033 break;
4034 case p_M:
4035 m_ea1.d = m_ea2.d;
4036 break;
4037 case p_M8:
4038 m_ea1.d = RDOP();
4039 break;
4040 case p_M16:
4041 m_ea1.d = RDOP();
4042 m_ea1.b.h = RDOP();
4043 break;
4044 case p_R:
4045 m_p1_reg8 = m_p2_reg8;
4046 m_p1_reg16 = m_p2_reg16;
4047 m_p1_reg32 = m_p2_reg32;
4048 break;
4049 }
4050
4051 switch ( inst->operand2 )
4052 {
4053 case p_A:
4054 m_p2_reg8 = &m_xwa[m_regbank].b.l;
4055 break;
4056 case p_F: /* F' */
4057 m_p2_reg8 = &m_f2.b.l;
4058 break;
4059 case p_SR:
4060 m_p2_reg16 = &m_sr.w.l;
4061 break;
4062 case p_C8:
4063 m_p2_reg8 = get_reg8_current( m_op );
4064 break;
4065 case p_C16:
4066 m_p2_reg16 = get_reg16_current( m_op );
4067 break;
4068 case p_C32:
4069 m_p2_reg32 = get_reg32_current( m_op );
4070 break;
4071 case p_CR8:
4072 m_imm1.d = RDOP();
4073 switch( m_imm1.d )
4074 {
4075 case 0x22:
4076 m_p2_reg8 = &m_dmam[0].b.l;
4077 break;
4078 case 0x26:
4079 m_p2_reg8 = &m_dmam[1].b.l;
4080 break;
4081 case 0x2a:
4082 m_p2_reg8 = &m_dmam[2].b.l;
4083 break;
4084 case 0x2e:
4085 m_p2_reg8 = &m_dmam[3].b.l;
4086 break;
4087 default:
4088 m_p2_reg8 = &m_dummy.b.l;
4089 break;
4090 }
4091 break;
4092 case p_CR16:
4093 m_imm1.d = RDOP();
4094 switch( m_imm1.d )
4095 {
4096 case 0x20:
4097 m_p2_reg16 = &m_dmac[0].w.l;
4098 break;
4099 case 0x24:
4100 m_p2_reg16 = &m_dmac[1].w.l;
4101 break;
4102 case 0x28:
4103 m_p2_reg16 = &m_dmac[2].w.l;
4104 break;
4105 case 0x2c:
4106 m_p2_reg16 = &m_dmac[3].w.l;
4107 break;
4108 default:
4109 m_p2_reg16 = &m_dummy.w.l;
4110 break;
4111 }
4112 break;
4113 case p_CR32:
4114 m_imm1.d = RDOP();
4115 switch( m_imm1.d )
4116 {
4117 case 0x00:
4118 m_p2_reg32 = &m_dmas[0].d;
4119 break;
4120 case 0x04:
4121 m_p2_reg32 = &m_dmas[1].d;
4122 break;
4123 case 0x08:
4124 m_p2_reg32 = &m_dmas[2].d;
4125 break;
4126 case 0x0c:
4127 m_p2_reg32 = &m_dmas[3].d;
4128 break;
4129 case 0x10:
4130 m_p2_reg32 = &m_dmad[0].d;
4131 break;
4132 case 0x14:
4133 m_p2_reg32 = &m_dmad[1].d;
4134 break;
4135 case 0x18:
4136 m_p2_reg32 = &m_dmad[2].d;
4137 break;
4138 case 0x1c:
4139 m_p2_reg32 = &m_dmad[3].d;
4140 break;
4141 default:
4142 m_p2_reg32 = &m_dummy.d;
4143 break;
4144 }
4145 break;
4146 case p_D8:
4147 m_ea2.d = RDOP();
4148 m_ea2.d = m_pc.d + m_ea2.sb.l;
4149 break;
4150 case p_D16:
4151 m_ea2.d = RDOP();
4152 m_ea2.b.h = RDOP();
4153 m_ea2.d = m_pc.d + m_ea2.sw.l;
4154 break;
4155 case p_I3:
4156 m_imm2.d = m_op & 0x07;
4157 break;
4158 case p_I8:
4159 m_imm2.d = RDOP();
4160 break;
4161 case p_I16:
4162 m_imm2.d = RDOP();
4163 m_imm2.b.h = RDOP();
4164 break;
4165 case p_I32:
4166 m_imm2.d = RDOP();
4167 m_imm2.b.h = RDOP();
4168 m_imm2.b.h2 = RDOP();
4169 m_imm2.b.h3 = RDOP();
4170 break;
4171 case p_M8:
4172 m_ea2.d = RDOP();
4173 break;
4174 case p_M16:
4175 m_ea2.d = RDOP();
4176 m_ea2.b.h = RDOP();
4177 break;
4178 }
4179 }
4180
4181
4182 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_80[256] =
4183 {
4184 /* 00 - 1F */
4185 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4186 { &tlcs900_device::op_PUSHBM, p_M, 0, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_RLDRM, p_A, p_M, 12 }, { &tlcs900_device::op_RRDRM, p_A, p_M, 12 },
4187 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4188 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4189 { &tlcs900_device::op_LDI, 0, 0, 10 }, { &tlcs900_device::op_LDIR, 0, 0, 10 }, { &tlcs900_device::op_LDD, 0, 0, 10 }, { &tlcs900_device::op_LDDR, 0, 0, 10 },
4190 { &tlcs900_device::op_CPI, 0, 0, 8 }, { &tlcs900_device::op_CPIR, 0, 0, 10 }, { &tlcs900_device::op_CPD, 0, 0, 8 }, { &tlcs900_device::op_CPDR, 0, 0, 10 },
4191 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDBMM, p_M16, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4192 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4193
4194 /* 20 - 3F */
4195 { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 },
4196 { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 },
4197 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4198 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4199 { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 },
4200 { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 },
4201 { &tlcs900_device::op_ADDBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_ADCBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_SUBBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_SBCBMI, p_M, p_I8, 7 },
4202 { &tlcs900_device::op_ANDBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_XORBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_ORBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_CPBMI, p_M, p_I8, 6 },
4203
4204 /* 40 - 5F */
4205 { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 },
4206 { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 },
4207 { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 },
4208 { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 },
4209 { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 },
4210 { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 },
4211 { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 },
4212 { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 },
4213
4214 /* 60 - 7F */
4215 { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 },
4216 { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 },
4217 { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 },
4218 { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 },
4219 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4220 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4221 { &tlcs900_device::op_RLCBM, p_M, 0, 6 }, { &tlcs900_device::op_RRCBM, p_M, 0, 6 }, { &tlcs900_device::op_RLBM, p_M, 0, 6 }, { &tlcs900_device::op_RRBM, p_M, 0, 6 },
4222 { &tlcs900_device::op_SLABM, p_M, 0, 6 }, { &tlcs900_device::op_SRABM, p_M, 0, 6 }, { &tlcs900_device::op_SLLBM, p_M, 0, 6 }, { &tlcs900_device::op_SRLBM, p_M, 0, 6 },
4223
4224 /* 80 - 9F */
4225 { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 },
4226 { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 },
4227 { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 },
4228 { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 },
4229 { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 },
4230 { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 },
4231 { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 },
4232 { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 },
4233
4234 /* A0 - BF */
4235 { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 },
4236 { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 },
4237 { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 },
4238 { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 },
4239 { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 },
4240 { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 },
4241 { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 },
4242 { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 },
4243
4244 /* C0 - DF */
4245 { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 },
4246 { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 },
4247 { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 },
4248 { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 },
4249 { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 },
4250 { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 },
4251 { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 },
4252 { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 },
4253
4254 /* E0 - FF */
4255 { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 },
4256 { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 },
4257 { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 },
4258 { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 },
4259 { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 },
4260 { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 },
4261 { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 },
4262 { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 },
4263 };
4264
4265
4266 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_88[256] =
4267 {
4268 /* 00 - 1F */
4269 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4270 { &tlcs900_device::op_PUSHBM, p_M, 0, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_RLDRM, p_A, p_M, 12 }, { &tlcs900_device::op_RRDRM, p_A, p_M, 12 },
4271 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4272 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4273 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4274 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4275 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDBMM, p_M16, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4276 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4277
4278 /* 20 - 3F */
4279 { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 },
4280 { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 },
4281 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4282 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4283 { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 },
4284 { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 },
4285 { &tlcs900_device::op_ADDBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_ADCBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_SUBBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_SBCBMI, p_M, p_I8, 7 },
4286 { &tlcs900_device::op_ANDBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_XORBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_ORBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_CPBMI, p_M, p_I8, 6 },
4287
4288 /* 40 - 5F */
4289 { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 },
4290 { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 },
4291 { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 },
4292 { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 },
4293 { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 },
4294 { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 },
4295 { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 },
4296 { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 },
4297
4298 /* 60 - 7F */
4299 { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 },
4300 { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 },
4301 { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 },
4302 { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 },
4303 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4304 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4305 { &tlcs900_device::op_RLCBM, p_M, 0, 6 }, { &tlcs900_device::op_RRCBM, p_M, 0, 6 }, { &tlcs900_device::op_RLBM, p_M, 0, 6 }, { &tlcs900_device::op_RRBM, p_M, 0, 6 },
4306 { &tlcs900_device::op_SLABM, p_M, 0, 6 }, { &tlcs900_device::op_SRABM, p_M, 0, 6 }, { &tlcs900_device::op_SLLBM, p_M, 0, 6 }, { &tlcs900_device::op_SRLBM, p_M, 0, 6 },
4307
4308 /* 80 - 9F */
4309 { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 },
4310 { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 },
4311 { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 },
4312 { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 },
4313 { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 },
4314 { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 },
4315 { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 },
4316 { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 },
4317
4318 /* A0 - BF */
4319 { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 },
4320 { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 },
4321 { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 },
4322 { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 },
4323 { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 },
4324 { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 },
4325 { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 },
4326 { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 },
4327
4328 /* C0 - DF */
4329 { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 },
4330 { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 },
4331 { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 },
4332 { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 },
4333 { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 },
4334 { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 },
4335 { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 },
4336 { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 },
4337
4338 /* E0 - FF */
4339 { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 },
4340 { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 },
4341 { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 },
4342 { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 },
4343 { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 },
4344 { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 },
4345 { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 },
4346 { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 },
4347 };
4348
4349
4350 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_90[256] =
4351 {
4352 /* 00 - 1F */
4353 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4354 { &tlcs900_device::op_PUSHWM, p_M, 0, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4355 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4356 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4357 { &tlcs900_device::op_LDIW, 0, 0, 10 }, { &tlcs900_device::op_LDIRW, 0, 0, 10 }, { &tlcs900_device::op_LDDW, 0, 0, 10 }, { &tlcs900_device::op_LDDRW, 0, 0, 10 },
4358 { &tlcs900_device::op_CPIW, 0, 0, 8 }, { &tlcs900_device::op_CPIRW, 0, 0, 10 }, { &tlcs900_device::op_CPDW, 0, 0, 8 }, { &tlcs900_device::op_CPDRW, 0, 0, 10 },
4359 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMM, p_M16, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4360 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4361
4362 /* 20 - 3F */
4363 { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 },
4364 { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 },
4365 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4366 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4367 { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 },
4368 { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 },
4369 { &tlcs900_device::op_ADDWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_ADCWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_SUBWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_SBCWMI, p_M, p_I16, 8 },
4370 { &tlcs900_device::op_ANDWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_XORWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_ORWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_CPWMI, p_M, p_I16, 6 },
4371
4372 /* 40 - 5F */
4373 { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 },
4374 { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 },
4375 { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 },
4376 { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 },
4377 { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 },
4378 { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 },
4379 { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 },
4380 { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 },
4381
4382 /* 60 - 7F */
4383 { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 },
4384 { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 },
4385 { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 },
4386 { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 },
4387 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4388 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4389 { &tlcs900_device::op_RLCWM, p_M, 0, 6 }, { &tlcs900_device::op_RRCWM, p_M, 0, 6 }, { &tlcs900_device::op_RLWM, p_M, 0, 6 }, { &tlcs900_device::op_RRWM, p_M, 0, 6 },
4390 { &tlcs900_device::op_SLAWM, p_M, 0, 6 }, { &tlcs900_device::op_SRAWM, p_M, 0, 6 }, { &tlcs900_device::op_SLLWM, p_M, 0, 6 }, { &tlcs900_device::op_SRLWM, p_M, 0, 6 },
4391
4392 /* 80 - 9F */
4393 { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 },
4394 { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 },
4395 { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 },
4396 { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 },
4397 { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 },
4398 { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 },
4399 { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 },
4400 { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 },
4401
4402 /* A0 - BF */
4403 { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 },
4404 { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 },
4405 { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 },
4406 { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 },
4407 { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 },
4408 { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 },
4409 { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 },
4410 { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 },
4411
4412 /* C0 - DF */
4413 { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 },
4414 { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 },
4415 { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 },
4416 { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 },
4417 { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 },
4418 { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 },
4419 { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 },
4420 { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 },
4421
4422 /* E0 - FF */
4423 { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 },
4424 { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 },
4425 { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 },
4426 { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 },
4427 { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 },
4428 { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 },
4429 { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 },
4430 { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 },
4431 };
4432
4433
4434 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_98[256] =
4435 {
4436 /* 00 - 1F */
4437 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4438 { &tlcs900_device::op_PUSHWM, p_M, 0, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4439 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4440 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4441 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4442 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4443 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMM, p_M16, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4444 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4445
4446 /* 20 - 3F */
4447 { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 },
4448 { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 },
4449 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4450 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4451 { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 },
4452 { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 },
4453 { &tlcs900_device::op_ADDWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_ADCWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_SUBWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_SBCWMI, p_M, p_I16, 8 },
4454 { &tlcs900_device::op_ANDWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_XORWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_ORWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_CPWMI, p_M, p_I16, 6 },
4455
4456 /* 40 - 5F */
4457 { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 },
4458 { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 },
4459 { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 },
4460 { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 },
4461 { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 },
4462 { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 },
4463 { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 },
4464 { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 },
4465
4466 /* 60 - 7F */
4467 { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 },
4468 { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 },
4469 { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 },
4470 { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 },
4471 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4472 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4473 { &tlcs900_device::op_RLCWM, p_M, 0, 6 }, { &tlcs900_device::op_RRCWM, p_M, 0, 6 }, { &tlcs900_device::op_RLWM, p_M, 0, 6 }, { &tlcs900_device::op_RRWM, p_M, 0, 6 },
4474 { &tlcs900_device::op_SLAWM, p_M, 0, 6 }, { &tlcs900_device::op_SRAWM, p_M, 0, 6 }, { &tlcs900_device::op_SLLWM, p_M, 0, 6 }, { &tlcs900_device::op_SRLWM, p_M, 0, 6 },
4475
4476 /* 80 - 9F */
4477 { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 },
4478 { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 },
4479 { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 },
4480 { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 },
4481 { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 },
4482 { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 },
4483 { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 },
4484 { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 },
4485
4486 /* A0 - BF */
4487 { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 },
4488 { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 },
4489 { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 },
4490 { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 },
4491 { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 },
4492 { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 },
4493 { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 },
4494 { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 },
4495
4496 /* C0 - DF */
4497 { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 },
4498 { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 },
4499 { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 },
4500 { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 },
4501 { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 },
4502 { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 },
4503 { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 },
4504 { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 },
4505
4506 /* E0 - FF */
4507 { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 },
4508 { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 },
4509 { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 },
4510 { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 },
4511 { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 },
4512 { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 },
4513 { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 },
4514 { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 },
4515 };
4516
4517
4518 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_a0[256] =
4519 {
4520 /* 00 - 1F */
4521 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4522 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4523 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4524 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4525 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4526 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4527 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4528 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4529
4530 /* 20 - 3F */
4531 { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 },
4532 { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 },
4533 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4534 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4535 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4536 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4537 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4538 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4539
4540 /* 40 - 5F */
4541 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4542 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4543 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4544 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4545 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4546 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4547 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4548 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4549
4550 /* 60 - 7F */
4551 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4552 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4553 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4554 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4555 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4556 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4557 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4558 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4559
4560 /* 80 - 9F */
4561 { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 },
4562 { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 },
4563 { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 },
4564 { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 },
4565 { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 },
4566 { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 },
4567 { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 },
4568 { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 },
4569
4570 /* A0 - BF */
4571 { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 },
4572 { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 },
4573 { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 },
4574 { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 },
4575 { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 },
4576 { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 },
4577 { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 },
4578 { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 },
4579
4580 /* C0 - DF */
4581 { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 },
4582 { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 },
4583 { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 },
4584 { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 },
4585 { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 },
4586 { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 },
4587 { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 },
4588 { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 },
4589
4590 /* E0 - FF */
4591 { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 },
4592 { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 },
4593 { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 },
4594 { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 },
4595 { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 },
4596 { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 },
4597 { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 },
4598 { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 },
4599 };
4600
4601
4602 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_b0[256] =
4603 {
4604 /* 00 - 1F */
4605 { &tlcs900_device::op_LDBMI, p_M, p_I8, 5 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMI, p_M, p_I16, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4606 { &tlcs900_device::op_POPBM, p_M, 0, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_POPWM, p_M, 0, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4607 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4608 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4609 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4610 { &tlcs900_device::op_LDBMM, p_M, p_M16, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMM, p_M, p_M16, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4611 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4612 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4613
4614 /* 20 - 3F */
4615 { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 },
4616 { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 },
4617 { &tlcs900_device::op_ANDCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_ORCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_XORCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_LDCFBRM, p_A, p_M, 8 },
4618 { &tlcs900_device::op_STCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4619 { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 },
4620 { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 },
4621 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4622 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4623
4624 /* 40 - 5F */
4625 { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 },
4626 { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 },
4627 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4628 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4629 { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 },
4630 { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 },
4631 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4632 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4633
4634 /* 60 - 7F */
4635 { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 },
4636 { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 },
4637 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4638 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4639 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4640 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4641 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4642 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4643
4644 /* 80 - 9F */
4645 { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 },
4646 { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 },
4647 { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 },
4648 { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 },
4649 { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 },
4650 { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 },
4651 { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 },
4652 { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 },
4653
4654 /* A0 - BF */
4655 { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 },
4656 { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 },
4657 { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 },
4658 { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 },
4659 { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 },
4660 { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 },
4661 { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 },
4662 { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 },
4663
4664 /* C0 - DF */
4665 { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 },
4666 { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 },
4667 { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 },
4668 { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 },
4669 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4670 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4671 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4672 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4673
4674 /* E0 - FF */
4675 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4676 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4677 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4678 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4679 { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 },
4680 { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 },
4681 { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 },
4682 { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }, { &tlcs900_device::op_RETCC, p_CC, 0, 6 }
4683 };
4684
4685
4686 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_b8[256] =
4687 {
4688 /* 00 - 1F */
4689 { &tlcs900_device::op_LDBMI, p_M, p_I8, 5 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMI, p_M, p_I16, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4690 { &tlcs900_device::op_POPBM, p_M, 0, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_POPWM, p_M, 0, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4691 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4692 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4693 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4694 { &tlcs900_device::op_LDBMM, p_M, p_M16, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMM, p_M, p_M16, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4695 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4696 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4697
4698 /* 20 - 3F */
4699 { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 },
4700 { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 },
4701 { &tlcs900_device::op_ANDCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_ORCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_XORCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_LDCFBRM, p_A, p_M, 8 },
4702 { &tlcs900_device::op_STCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4703 { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 },
4704 { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 },
4705 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4706 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4707
4708 /* 40 - 5F */
4709 { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 },
4710 { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 },
4711 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4712 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4713 { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 },
4714 { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 },
4715 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4716 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4717
4718 /* 60 - 7F */
4719 { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 },
4720 { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 },
4721 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4722 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4723 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4724 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4725 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4726 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4727
4728 /* 80 - 9F */
4729 { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 },
4730 { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 },
4731 { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 },
4732 { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 },
4733 { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 },
4734 { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 },
4735 { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 },
4736 { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 },
4737
4738 /* A0 - BF */
4739 { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 },
4740 { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 },
4741 { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 },
4742 { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 },
4743 { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 },
4744 { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 },
4745 { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 },
4746 { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 },
4747
4748 /* C0 - DF */
4749 { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 },
4750 { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 },
4751 { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 },
4752 { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 },
4753 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4754 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4755 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4756 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
4757
4758 /* E0 - FF */
4759 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4760 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4761 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4762 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
4763 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4764 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4765 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4766 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }
4767 };
4768
4769
4770 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_c0[256] =
4771 {
4772 /* 00 - 1F */
4773 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4774 { &tlcs900_device::op_PUSHBM, p_M, 0, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_RLDRM, p_A, p_M, 12 }, { &tlcs900_device::op_RRDRM, p_A, p_M, 12 },
4775 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4776 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4777 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4778 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4779 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDBMM, p_M16, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4780 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4781
4782 /* 20 - 3F */
4783 { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 },
4784 { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_LDBRM, p_C8, p_M, 4 },
4785 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4786 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4787 { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 },
4788 { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_EXBMR, p_M, p_C8, 6 },
4789 { &tlcs900_device::op_ADDBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_ADCBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_SUBBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_SBCBMI, p_M, p_I8, 7 },
4790 { &tlcs900_device::op_ANDBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_XORBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_ORBMI, p_M, p_I8, 7 }, { &tlcs900_device::op_CPBMI, p_M, p_I8, 6 },
4791
4792 /* 40 - 5F */
4793 { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 },
4794 { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULBRM, p_MC16, p_M, 18 },
4795 { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 },
4796 { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 }, { &tlcs900_device::op_MULSBRM, p_MC16, p_M, 18 },
4797 { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 },
4798 { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 }, { &tlcs900_device::op_DIVBRM, p_MC16, p_M, 22 },
4799 { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 },
4800 { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 }, { &tlcs900_device::op_DIVSBRM, p_MC16, p_M, 24 },
4801
4802 /* 60 - 7F */
4803 { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 },
4804 { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCBIM, p_I3, p_M, 6 },
4805 { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 },
4806 { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECBIM, p_I3, p_M, 6 },
4807 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4808 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4809 { &tlcs900_device::op_RLCBM, p_M, 0, 6 }, { &tlcs900_device::op_RRCBM, p_M, 0, 6 }, { &tlcs900_device::op_RLBM, p_M, 0, 6 }, { &tlcs900_device::op_RRBM, p_M, 0, 6 },
4810 { &tlcs900_device::op_SLABM, p_M, 0, 6 }, { &tlcs900_device::op_SRABM, p_M, 0, 6 }, { &tlcs900_device::op_SLLBM, p_M, 0, 6 }, { &tlcs900_device::op_SRLBM, p_M, 0, 6 },
4811
4812 /* 80 - 9F */
4813 { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 },
4814 { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADDBRM, p_C8, p_M, 4 },
4815 { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 },
4816 { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADDBMR, p_M, p_C8, 6 },
4817 { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 },
4818 { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ADCBRM, p_C8, p_M, 4 },
4819 { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 },
4820 { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ADCBMR, p_M, p_C8, 6 },
4821
4822 /* A0 - BF */
4823 { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 },
4824 { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SUBBRM, p_C8, p_M, 4 },
4825 { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 },
4826 { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SUBBMR, p_M, p_C8, 6 },
4827 { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 },
4828 { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_SBCBRM, p_C8, p_M, 4 },
4829 { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 },
4830 { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_SBCBMR, p_M, p_C8, 6 },
4831
4832 /* C0 - DF */
4833 { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 },
4834 { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ANDBRM, p_C8, p_M, 4 },
4835 { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 },
4836 { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ANDBMR, p_M, p_C8, 6 },
4837 { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 },
4838 { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_XORBRM, p_C8, p_M, 4 },
4839 { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 },
4840 { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_XORBMR, p_M, p_C8, 6 },
4841
4842 /* E0 - FF */
4843 { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 },
4844 { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_ORBRM, p_C8, p_M, 4 },
4845 { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 },
4846 { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_ORBMR, p_M, p_C8, 6 },
4847 { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 },
4848 { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 }, { &tlcs900_device::op_CPBRM, p_C8, p_M, 4 },
4849 { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 },
4850 { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 }, { &tlcs900_device::op_CPBMR, p_M, p_C8, 6 },
4851 };
4852
4853
4854 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_c8[256] =
4855 {
4856 /* 00 - 1F */
4857 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDBRI, p_R, p_I8, 4 },
4858 { &tlcs900_device::op_PUSHBR, p_R, 0, 6 }, { &tlcs900_device::op_POPBR, p_R, 0, 6 }, { &tlcs900_device::op_CPLBR, p_R, 0, 4 }, { &tlcs900_device::op_NEGBR, p_R, 0, 5 },
4859 { &tlcs900_device::op_MULBRI, p_R, p_I8, 18 }, { &tlcs900_device::op_MULSBRI, p_R, p_I8, 18 }, { &tlcs900_device::op_DIVBRI, p_R, p_I8, 22 }, { &tlcs900_device::op_DIVSBRI, p_R, p_I8, 24 },
4860 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4861 { &tlcs900_device::op_DAABR, p_R, 0, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4862 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4863 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4864 { &tlcs900_device::op_DJNZB, p_R, p_D8, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4865
4866 /* 20 - 3F */
4867 { &tlcs900_device::op_ANDCFBIR, p_I8, p_R, 4 }, { &tlcs900_device::op_ORCFBIR, p_I8, p_R, 4 }, { &tlcs900_device::op_XORCFBIR, p_I8, p_R, 4 }, { &tlcs900_device::op_LDCFBIR, p_I8, p_R, 4 },
4868 { &tlcs900_device::op_STCFBIR, p_I8, p_R, 4 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4869 { &tlcs900_device::op_ANDCFBRR, p_A, p_R, 4 }, { &tlcs900_device::op_ORCFBRR, p_A, p_R, 4 }, { &tlcs900_device::op_XORCFBRR, p_A, p_R, 4 }, { &tlcs900_device::op_LDCFBRR, p_A, p_R, 4 },
4870 { &tlcs900_device::op_STCFBRR, p_A, p_R, 4 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDCBRR, p_CR8, p_R, 8 }, { &tlcs900_device::op_LDCBRR, p_R, p_CR8, 8 },
4871 { &tlcs900_device::op_RESBIR, p_I8, p_R, 4 }, { &tlcs900_device::op_SETBIR, p_I8, p_R, 4 }, { &tlcs900_device::op_CHGBIR, p_I8, p_R, 4 }, { &tlcs900_device::op_BITBIR, p_I8, p_R, 4 },
4872 { &tlcs900_device::op_TSETBIR, p_I8, p_R, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4873 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4874 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4875
4876 /* 40 - 5F */
4877 { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 },
4878 { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULBRR, p_MC16, p_R, 18 },
4879 { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 },
4880 { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 }, { &tlcs900_device::op_MULSBRR, p_MC16, p_R, 18 },
4881 { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 }, { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 }, { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 }, { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 },
4882 { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 }, { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 }, { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 }, { &tlcs900_device::op_DIVBRR, p_MC16, p_R, 22 },
4883 { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 }, { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 }, { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 }, { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 },
4884 { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 }, { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 }, { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 }, { &tlcs900_device::op_DIVSBRR, p_MC16, p_R, 24 },
4885
4886 /* 60 - 7F */
4887 { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 },
4888 { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCBIR, p_I3, p_R, 4 },
4889 { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 },
4890 { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECBIR, p_I3, p_R, 4 },
4891 { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 },
4892 { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 },
4893 { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 },
4894 { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCBR, p_CC, p_R, 6 },
4895
4896 /* 80 - 9F */
4897 { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 },
4898 { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADDBRR, p_C8, p_R, 4 },
4899 { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 },
4900 { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_LDBRR, p_C8, p_R, 4 },
4901 { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 },
4902 { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ADCBRR, p_C8, p_R, 4 },
4903 { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 }, { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 }, { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 }, { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 },
4904 { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 }, { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 }, { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 }, { &tlcs900_device::op_LDBRR, p_R, p_C8, 4 },
4905
4906 /* A0 - BF */
4907 { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 },
4908 { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SUBBRR, p_C8, p_R, 4 },
4909 { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 },
4910 { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDBRI, p_R, p_I3, 4 },
4911 { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 },
4912 { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_SBCBRR, p_C8, p_R, 4 },
4913 { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 }, { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 }, { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 }, { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 },
4914 { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 }, { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 }, { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 }, { &tlcs900_device::op_EXBRR, p_C8, p_R, 5 },
4915
4916 /* C0 - DF */
4917 { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 },
4918 { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ANDBRR, p_C8, p_R, 4 },
4919 { &tlcs900_device::op_ADDBRI, p_R, p_I8, 4 }, { &tlcs900_device::op_ADCBRI, p_R, p_I8, 4 }, { &tlcs900_device::op_SUBBRI, p_R, p_I8, 4 }, { &tlcs900_device::op_SBCBRI, p_R, p_I8, 4 },
4920 { &tlcs900_device::op_ANDBRI, p_R, p_I8, 4 }, { &tlcs900_device::op_XORBRI, p_R, p_I8, 4 }, { &tlcs900_device::op_ORBRI, p_R, p_I8, 4 }, { &tlcs900_device::op_CPBRI, p_R, p_I8, 4 },
4921 { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 },
4922 { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_XORBRR, p_C8, p_R, 4 },
4923 { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 },
4924 { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPBRI, p_R, p_I3, 4 },
4925
4926 /* E0 - FF */
4927 { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 },
4928 { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_ORBRR, p_C8, p_R, 4 },
4929 { &tlcs900_device::op_RLCBIR, p_I8, p_R, 6 }, { &tlcs900_device::op_RRCBIR, p_I8, p_R, 6 }, { &tlcs900_device::op_RLBIR, p_I8, p_R, 6 }, { &tlcs900_device::op_RRBIR, p_I8, p_R, 6 },
4930 { &tlcs900_device::op_SLABIR, p_I8, p_R, 6 }, { &tlcs900_device::op_SRABIR, p_I8, p_R, 6 }, { &tlcs900_device::op_SLLBIR, p_I8, p_R, 6 }, { &tlcs900_device::op_SRLBIR, p_I8, p_R, 6 },
4931 { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 },
4932 { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 }, { &tlcs900_device::op_CPBRR, p_C8, p_R, 4 },
4933 { &tlcs900_device::op_RLCBRR, p_A, p_R, 6 }, { &tlcs900_device::op_RRCBRR, p_A, p_R, 6 }, { &tlcs900_device::op_RLBRR, p_A, p_R, 6 }, { &tlcs900_device::op_RRBRR, p_A, p_R, 6 },
4934 { &tlcs900_device::op_SLABRR, p_A, p_R, 6 }, { &tlcs900_device::op_SRABRR, p_A, p_R, 6 }, { &tlcs900_device::op_SLLBRR, p_A, p_R, 6 }, { &tlcs900_device::op_SRLBRR, p_A, p_R, 6 }
4935 };
4936
4937
4938 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_d0[256] =
4939 {
4940 /* 00 - 1F */
4941 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4942 { &tlcs900_device::op_PUSHWM, p_M, 0, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4943 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4944 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4945 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4946 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4947 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMM, p_M16, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4948 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4949
4950 /* 20 - 3F */
4951 { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 },
4952 { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_LDWRM, p_C16, p_M, 4 },
4953 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4954 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4955 { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 },
4956 { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_EXWMR, p_M, p_C16, 6 },
4957 { &tlcs900_device::op_ADDWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_ADCWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_SUBWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_SBCWMI, p_M, p_I16, 8 },
4958 { &tlcs900_device::op_ANDWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_XORWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_ORWMI, p_M, p_I16, 8 }, { &tlcs900_device::op_CPWMI, p_M, p_I16, 6 },
4959
4960 /* 40 - 5F */
4961 { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 },
4962 { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULWRM, p_C32, p_M, 26 },
4963 { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 },
4964 { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 }, { &tlcs900_device::op_MULSWRM, p_C32, p_M, 26 },
4965 { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 },
4966 { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 }, { &tlcs900_device::op_DIVWRM, p_C32, p_M, 30 },
4967 { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 },
4968 { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 }, { &tlcs900_device::op_DIVSWRM, p_C32, p_M, 32 },
4969
4970 /* 60 - 7F */
4971 { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 },
4972 { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_INCWIM, p_I3, p_M, 6 },
4973 { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 },
4974 { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 }, { &tlcs900_device::op_DECWIM, p_I3, p_M, 6 },
4975 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4976 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
4977 { &tlcs900_device::op_RLCWM, p_M, 0, 6 }, { &tlcs900_device::op_RRCWM, p_M, 0, 6 }, { &tlcs900_device::op_RLWM, p_M, 0, 6 }, { &tlcs900_device::op_RRWM, p_M, 0, 6 },
4978 { &tlcs900_device::op_SLAWM, p_M, 0, 6 }, { &tlcs900_device::op_SRAWM, p_M, 0, 6 }, { &tlcs900_device::op_SLLWM, p_M, 0, 6 }, { &tlcs900_device::op_SRLWM, p_M, 0, 6 },
4979
4980 /* 80 - 9F */
4981 { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 },
4982 { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADDWRM, p_C16, p_M, 4 },
4983 { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 },
4984 { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADDWMR, p_M, p_C16, 6 },
4985 { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 },
4986 { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ADCWRM, p_C16, p_M, 4 },
4987 { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 },
4988 { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ADCWMR, p_M, p_C16, 6 },
4989
4990 /* A0 - BF */
4991 { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 },
4992 { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SUBWRM, p_C16, p_M, 4 },
4993 { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 },
4994 { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SUBWMR, p_M, p_C16, 6 },
4995 { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 },
4996 { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_SBCWRM, p_C16, p_M, 4 },
4997 { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 },
4998 { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_SBCWMR, p_M, p_C16, 6 },
4999
5000 /* C0 - DF */
5001 { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 },
5002 { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ANDWRM, p_C16, p_M, 4 },
5003 { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 },
5004 { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ANDWMR, p_M, p_C16, 6 },
5005 { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 },
5006 { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_XORWRM, p_C16, p_M, 4 },
5007 { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 },
5008 { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_XORWMR, p_M, p_C16, 6 },
5009
5010 /* E0 - FF */
5011 { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 },
5012 { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_ORWRM, p_C16, p_M, 4 },
5013 { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 },
5014 { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_ORWMR, p_M, p_C16, 6 },
5015 { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 },
5016 { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 }, { &tlcs900_device::op_CPWRM, p_C16, p_M, 4 },
5017 { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 },
5018 { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 }, { &tlcs900_device::op_CPWMR, p_M, p_C16, 6 },
5019 };
5020
5021
5022 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_d8[256] =
5023 {
5024 /* 00 - 1F */
5025 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWRI, p_R, p_I16, 4 },
5026 { &tlcs900_device::op_PUSHWR, p_R, 0, 5 }, { &tlcs900_device::op_POPWR, p_R, 0, 6 }, { &tlcs900_device::op_CPLWR, p_R, 0, 4 }, { &tlcs900_device::op_NEGWR, p_R, 0, 5 },
5027 { &tlcs900_device::op_MULWRI, p_R, p_I16, 26 }, { &tlcs900_device::op_MULSWRI, p_R, p_I16, 26 }, { &tlcs900_device::op_DIVWRI, p_R, p_I16, 30 }, { &tlcs900_device::op_DIVSWRI, p_R, p_I16, 32 },
5028 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_BS1FRR, p_A, p_R, 4 }, { &tlcs900_device::op_BS1BRR, p_A, p_R, 4 },
5029 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_EXTZWR, p_R, 0, 4 }, { &tlcs900_device::op_EXTSWR, p_R, 0, 5 },
5030 { &tlcs900_device::op_PAAWR, p_R, 0, 4 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_MIRRW, p_R, 0, 4 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5031 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_MULAR, p_R, 0, 31 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5032 { &tlcs900_device::op_DJNZW, p_R, p_D8, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5033
5034 /* 20 - 3F */
5035 { &tlcs900_device::op_ANDCFWIR, p_I8, p_R, 4 }, { &tlcs900_device::op_ORCFWIR, p_I8, p_R, 4 }, { &tlcs900_device::op_XORCFWIR, p_I8, p_R, 4 }, { &tlcs900_device::op_LDCFWIR, p_I8, p_R, 4 },
5036 { &tlcs900_device::op_STCFWIR, p_I8, p_R, 4 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5037 { &tlcs900_device::op_ANDCFWRR, p_A, p_R, 4 }, { &tlcs900_device::op_ORCFWRR, p_A, p_R, 4 }, { &tlcs900_device::op_XORCFWRR, p_A, p_R, 4 }, { &tlcs900_device::op_LDCFWRR, p_A, p_R, 4 },
5038 { &tlcs900_device::op_STCFWRR, p_A, p_R, 4 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDCWRR, p_CR16, p_R, 8 }, { &tlcs900_device::op_LDCWRR, p_R, p_CR16, 8 },
5039 { &tlcs900_device::op_RESWIR, p_I8, p_R, 4 }, { &tlcs900_device::op_SETWIR, p_I8, p_R, 4 }, { &tlcs900_device::op_CHGWIR, p_I8, p_R, 4 }, { &tlcs900_device::op_BITWIR, p_I8, p_R, 4 },
5040 { &tlcs900_device::op_TSETWIR, p_I8, p_R, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5041 { &tlcs900_device::op_MINC1, p_I16, p_R, 8 }, { &tlcs900_device::op_MINC2, p_I16, p_R, 8 }, { &tlcs900_device::op_MINC4, p_I16, p_R, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5042 { &tlcs900_device::op_MDEC1, p_I16, p_R, 7 }, { &tlcs900_device::op_MDEC2, p_I16, p_R, 7 }, { &tlcs900_device::op_MDEC4, p_I16, p_R, 7 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5043
5044 /* 40 - 5F */
5045 { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 },
5046 { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULWRR, p_C32, p_R, 26 },
5047 { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 },
5048 { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 }, { &tlcs900_device::op_MULSWRR, p_C32, p_R, 26 },
5049 { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 }, { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 }, { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 }, { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 },
5050 { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 }, { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 }, { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 }, { &tlcs900_device::op_DIVWRR, p_C32, p_R, 30 },
5051 { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 }, { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 }, { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 }, { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 },
5052 { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 }, { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 }, { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 }, { &tlcs900_device::op_DIVSWRR, p_C32, p_R, 32 },
5053
5054 /* 60 - 7F */
5055 { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 },
5056 { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCWIR, p_I3, p_R, 4 },
5057 { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 },
5058 { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECWIR, p_I3, p_R, 4 },
5059 { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 },
5060 { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 },
5061 { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 },
5062 { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 }, { &tlcs900_device::op_SCCWR, p_CC, p_R, 6 },
5063
5064 /* 80 - 9F */
5065 { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 },
5066 { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADDWRR, p_C16, p_R, 4 },
5067 { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 },
5068 { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_LDWRR, p_C16, p_R, 4 },
5069 { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 },
5070 { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ADCWRR, p_C16, p_R, 4 },
5071 { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 }, { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 }, { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 }, { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 },
5072 { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 }, { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 }, { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 }, { &tlcs900_device::op_LDWRR, p_R, p_C16, 4 },
5073
5074 /* A0 - BF */
5075 { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 },
5076 { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SUBWRR, p_C16, p_R, 4 },
5077 { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 },
5078 { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDWRI, p_R, p_I3, 4 },
5079 { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 },
5080 { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_SBCWRR, p_C16, p_R, 4 },
5081 { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 }, { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 }, { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 }, { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 },
5082 { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 }, { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 }, { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 }, { &tlcs900_device::op_EXWRR, p_C16, p_R, 5 },
5083
5084 /* C0 - DF */
5085 { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 },
5086 { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ANDWRR, p_C16, p_R, 4 },
5087 { &tlcs900_device::op_ADDWRI, p_R, p_I16, 4 }, { &tlcs900_device::op_ADCWRI, p_R, p_I16, 4 }, { &tlcs900_device::op_SUBWRI, p_R, p_I16, 4 }, { &tlcs900_device::op_SBCWRI, p_R, p_I16, 4 },
5088 { &tlcs900_device::op_ANDWRI, p_R, p_I16, 4 }, { &tlcs900_device::op_XORWRI, p_R, p_I16, 4 }, { &tlcs900_device::op_ORWRI, p_R, p_I16, 4 }, { &tlcs900_device::op_CPWRI, p_R, p_I16, 4 },
5089 { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 },
5090 { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_XORWRR, p_C16, p_R, 4 },
5091 { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 },
5092 { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 }, { &tlcs900_device::op_CPWRI, p_R, p_I3, 4 },
5093
5094 /* E0 - FF */
5095 { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 },
5096 { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_ORWRR, p_C16, p_R, 4 },
5097 { &tlcs900_device::op_RLCWIR, p_I8, p_R, 6 }, { &tlcs900_device::op_RRCWIR, p_I8, p_R, 6 }, { &tlcs900_device::op_RLWIR, p_I8, p_R, 6 }, { &tlcs900_device::op_RRWIR, p_I8, p_R, 6 },
5098 { &tlcs900_device::op_SLAWIR, p_I8, p_R, 6 }, { &tlcs900_device::op_SRAWIR, p_I8, p_R, 6 }, { &tlcs900_device::op_SLLWIR, p_I8, p_R, 6 }, { &tlcs900_device::op_SRLWIR, p_I8, p_R, 6 },
5099 { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 },
5100 { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 }, { &tlcs900_device::op_CPWRR, p_C16, p_R, 4 },
5101 { &tlcs900_device::op_RLCWRR, p_A, p_R, 6 }, { &tlcs900_device::op_RRCWRR, p_A, p_R, 6 }, { &tlcs900_device::op_RLWRR, p_A, p_R, 6 }, { &tlcs900_device::op_RRWRR, p_A, p_R, 6 },
5102 { &tlcs900_device::op_SLAWRR, p_A, p_R, 6 }, { &tlcs900_device::op_SRAWRR, p_A, p_R, 6 }, { &tlcs900_device::op_SLLWRR, p_A, p_R, 6 }, { &tlcs900_device::op_SRLWRR, p_A, p_R, 6 }
5103 };
5104
5105
5106 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_e0[256] =
5107 {
5108 /* 00 - 1F */
5109 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5110 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5111 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5112 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5113 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5114 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5115 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5116 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5117
5118 /* 20 - 3F */
5119 { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 },
5120 { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_LDLRM, p_C32, p_M, 6 },
5121 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5122 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5123 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5124 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5125 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5126 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5127
5128 /* 40 - 5F */
5129 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5130 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5131 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5132 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5133 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5134 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5135 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5136 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5137
5138 /* 60 - 7F */
5139 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5140 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5141 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5142 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5143 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5144 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5145 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5146 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5147
5148 /* 80 - 9F */
5149 { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 },
5150 { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADDLRM, p_C32, p_M, 6 },
5151 { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 },
5152 { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADDLMR, p_M, p_C32, 10 },
5153 { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 },
5154 { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ADCLRM, p_C32, p_M, 6 },
5155 { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 },
5156 { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ADCLMR, p_M, p_C32, 10 },
5157
5158 /* A0 - BF */
5159 { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 },
5160 { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SUBLRM, p_C32, p_M, 6 },
5161 { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 },
5162 { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SUBLMR, p_M, p_C32, 10 },
5163 { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 },
5164 { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_SBCLRM, p_C32, p_M, 6 },
5165 { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 },
5166 { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_SBCLMR, p_M, p_C32, 10 },
5167
5168 /* C0 - DF */
5169 { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 },
5170 { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ANDLRM, p_C32, p_M, 6 },
5171 { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 },
5172 { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ANDLMR, p_M, p_C32, 10 },
5173 { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 },
5174 { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_XORLRM, p_C32, p_M, 6 },
5175 { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 },
5176 { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_XORLMR, p_M, p_C32, 10 },
5177
5178 /* E0 - FF */
5179 { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 },
5180 { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_ORLRM, p_C32, p_M, 6 },
5181 { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 },
5182 { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 }, { &tlcs900_device::op_ORLMR, p_M, p_C32, 10 },
5183 { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 },
5184 { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 }, { &tlcs900_device::op_CPLRM, p_C32, p_M, 6 },
5185 { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 },
5186 { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_CPLMR, p_M, p_C32, 6 },
5187 };
5188
5189
5190 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_e8[256] =
5191 {
5192 /* 00 - 1F */
5193 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDLRI, p_R, p_I32, 6 },
5194 { &tlcs900_device::op_PUSHLR, p_R, 0, 7 }, { &tlcs900_device::op_POPLR, p_R, 0, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5195 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5196 { &tlcs900_device::op_LINK, p_R, p_I16, 10 }, { &tlcs900_device::op_UNLK, p_R, 0, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5197 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_EXTZLR, p_R, 0, 4 }, { &tlcs900_device::op_EXTSLR, p_R, 0, 5 },
5198 { &tlcs900_device::op_PAALR, p_R, 0, 4 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5199 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5200 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5201
5202 /* 20 - 3F */
5203 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5204 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5205 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5206 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDCLRR, p_CR32, p_R, 8 }, { &tlcs900_device::op_LDCLRR, p_R, p_CR32, 8 },
5207 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5208 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5209 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5210 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5211
5212 /* 40 - 5F */
5213 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5214 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5215 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5216 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5217 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5218 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5219 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5220 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5221
5222 /* 60 - 7F */
5223 { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 },
5224 { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_INCLIR, p_I3, p_R, 4 },
5225 { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 },
5226 { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 }, { &tlcs900_device::op_DECLIR, p_I3, p_R, 4 },
5227 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5228 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5229 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5230 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5231
5232 /* 80 - 9F */
5233 { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 },
5234 { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADDLRR, p_C32, p_R, 7 },
5235 { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 }, { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 }, { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 }, { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 },
5236 { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 }, { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 }, { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 }, { &tlcs900_device::op_LDLRR, p_C32, p_R, 4 },
5237 { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 },
5238 { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ADCLRR, p_C32, p_R, 7 },
5239 { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 }, { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 }, { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 }, { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 },
5240 { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 }, { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 }, { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 }, { &tlcs900_device::op_LDLRR, p_R, p_C32, 4 },
5241
5242 /* A0 - BF */
5243 { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 },
5244 { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SUBLRR, p_C32, p_R, 7 },
5245 { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 },
5246 { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 }, { &tlcs900_device::op_LDLRI, p_R, p_I3, 4 },
5247 { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 },
5248 { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_SBCLRR, p_C32, p_R, 7 },
5249 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5250 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5251
5252 /* C0 - DF */
5253 { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 },
5254 { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ANDLRR, p_C32, p_R, 7 },
5255 { &tlcs900_device::op_ADDLRI, p_R, p_I32, 7 }, { &tlcs900_device::op_ADCLRI, p_R, p_I32, 7 }, { &tlcs900_device::op_SUBLRI, p_R, p_I32, 7 }, { &tlcs900_device::op_SBCLRI, p_R, p_I32, 7 },
5256 { &tlcs900_device::op_ANDLRI, p_R, p_I32, 7 }, { &tlcs900_device::op_XORLRI, p_R, p_I32, 7 }, { &tlcs900_device::op_ORLRI, p_R, p_I32, 7 }, { &tlcs900_device::op_CPLRI, p_R, p_I32, 7 },
5257 { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 },
5258 { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_XORLRR, p_C32, p_R, 7 },
5259 { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 }, { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 }, { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 }, { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 },
5260 { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 }, { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 }, { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 }, { &tlcs900_device::op_CPLRI, p_R, p_I3, 6 },
5261
5262 /* E0 - FF */
5263 { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 },
5264 { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_ORLRR, p_C32, p_R, 7 },
5265 { &tlcs900_device::op_RLCLIR, p_I8, p_R, 8 }, { &tlcs900_device::op_RRCLIR, p_I8, p_R, 8 }, { &tlcs900_device::op_RLLIR, p_I8, p_R, 8 }, { &tlcs900_device::op_RRLIR, p_I8, p_R, 8 },
5266 { &tlcs900_device::op_SLALIR, p_I8, p_R, 8 }, { &tlcs900_device::op_SRALIR, p_I8, p_R, 8 }, { &tlcs900_device::op_SLLLIR, p_I8, p_R, 8 }, { &tlcs900_device::op_SRLLIR, p_I8, p_R, 8 },
5267 { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 },
5268 { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 }, { &tlcs900_device::op_CPLRR, p_C32, p_R, 7 },
5269 { &tlcs900_device::op_RLCLRR, p_A, p_R, 8 }, { &tlcs900_device::op_RRCLRR, p_A, p_R, 8 }, { &tlcs900_device::op_RLLRR, p_A, p_R, 8 }, { &tlcs900_device::op_RRLRR, p_A, p_R, 8 },
5270 { &tlcs900_device::op_SLALRR, p_A, p_R, 8 }, { &tlcs900_device::op_SRALRR, p_A, p_R, 8 }, { &tlcs900_device::op_SLLLRR, p_A, p_R, 8 }, { &tlcs900_device::op_SRLLRR, p_A, p_R, 8 }
5271 };
5272
5273
5274 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic_f0[256] =
5275 {
5276 /* 00 - 1F */
5277 { &tlcs900_device::op_LDBMI, p_M, p_I8, 5 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMI, p_M, p_I16, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5278 { &tlcs900_device::op_POPBM, p_M, 0, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_POPWM, p_M, 0, 6 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5279 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5280 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5281 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5282 { &tlcs900_device::op_LDBMM, p_M, p_M16, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_LDWMM, p_M, p_M16, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5283 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5284 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5285
5286 /* 20 - 3F */
5287 { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 },
5288 { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 }, { &tlcs900_device::op_LDAW, p_C16, p_M, 4 },
5289 { &tlcs900_device::op_ANDCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_ORCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_XORCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_LDCFBRM, p_A, p_M, 8 },
5290 { &tlcs900_device::op_STCFBRM, p_A, p_M, 8 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5291 { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 },
5292 { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 }, { &tlcs900_device::op_LDAL, p_C32, p_M, 4 },
5293 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5294 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5295
5296 /* 40 - 5F */
5297 { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 },
5298 { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 }, { &tlcs900_device::op_LDBMR, p_M, p_C8, 4 },
5299 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5300 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5301 { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 },
5302 { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 }, { &tlcs900_device::op_LDWMR, p_M, p_C16, 4 },
5303 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5304 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5305
5306 /* 60 - 7F */
5307 { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 },
5308 { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 }, { &tlcs900_device::op_LDLMR, p_M, p_C32, 6 },
5309 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5310 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5311 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5312 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5313 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5314 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5315
5316 /* 80 - 9F */
5317 { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 },
5318 { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ANDCFBIM, p_I3, p_M, 8 },
5319 { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 },
5320 { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_ORCFBIM, p_I3, p_M, 8 },
5321 { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 },
5322 { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_XORCFBIM, p_I3, p_M, 8 },
5323 { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 },
5324 { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_LDCFBIM, p_I3, p_M, 8 },
5325
5326 /* A0 - BF */
5327 { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 },
5328 { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_STCFBIM, p_I3, p_M, 8 },
5329 { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 },
5330 { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 }, { &tlcs900_device::op_TSETBIM, p_I3, p_M, 10 },
5331 { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 },
5332 { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_RESBIM, p_I3, p_M, 8 },
5333 { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 },
5334 { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_SETBIM, p_I3, p_M, 8 },
5335
5336 /* C0 - DF */
5337 { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 },
5338 { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_CHGBIM, p_I3, p_M, 8 },
5339 { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 },
5340 { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 }, { &tlcs900_device::op_BITBIM, p_I3, p_M, 8 },
5341 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
5342 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
5343 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
5344 { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 }, { &tlcs900_device::op_JPM, p_CC, p_M, 4 },
5345
5346 /* E0 - FF */
5347 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
5348 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
5349 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
5350 { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 }, { &tlcs900_device::op_CALLM, p_CC, p_M, 6 },
5351 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5352 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5353 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5354 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }
5355 };
5356
5357
5358 /* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP) used as source in byte operations */
op_80()5359 void tlcs900_device::op_80()
5360 {
5361 const tlcs900inst *inst;
5362
5363 /* For CPI/CPIR/CPD/CPDR/LDI/LDD/LDIR/LDDR operations */
5364 m_p1_reg32 = get_reg32_current( m_op - 1 );
5365 m_p2_reg32 = get_reg32_current( m_op );
5366
5367 m_ea2.d = *get_reg32_current( m_op );
5368 m_op = RDOP();
5369 inst = &m_mnemonic_80[m_op];
5370 prepare_operands( inst );
5371 (this->*inst->opfunc)();
5372 m_cycles += inst->cycles;
5373 }
5374
5375
5376 /* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as source in byte operations */
op_88()5377 void tlcs900_device::op_88()
5378 {
5379 const tlcs900inst *inst;
5380
5381 /* For CPI/CPIR/CPD/CPDR/LDI/LDD/LDIR/LDDR operations */
5382 m_p1_reg32 = get_reg32_current( m_op - 1 );
5383 m_p2_reg32 = get_reg32_current( m_op );
5384
5385 m_ea2.d = *get_reg32_current( m_op );
5386 m_op = RDOP();
5387 m_ea2.d += (int8_t)m_op;
5388 m_cycles += tlcs900_mem_index_cycles();
5389 m_op = RDOP();
5390 inst = &m_mnemonic_80[m_op];
5391 prepare_operands( inst );
5392 (this->*inst->opfunc)();
5393 m_cycles += inst->cycles;
5394 }
5395
5396
5397 /* (XWA/XBC/XDE/XHL/XIXI/XIY/XIZ/XSP) used as source in word operations */
op_90()5398 void tlcs900_device::op_90()
5399 {
5400 const tlcs900inst *inst;
5401
5402 /* For CPI/CPIR/CPD/CPDR/LDI/LDD/LDIR/LDDR operations */
5403 m_p1_reg32 = get_reg32_current( m_op - 1 );
5404 m_p2_reg32 = get_reg32_current( m_op );
5405
5406 m_ea2.d = *get_reg32_current( m_op );
5407 m_op = RDOP();
5408 inst = &m_mnemonic_90[m_op];
5409 prepare_operands( inst );
5410 (this->*inst->opfunc)();
5411 m_cycles += inst->cycles;
5412 }
5413
5414
5415 /* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as source in word operations */
op_98()5416 void tlcs900_device::op_98()
5417 {
5418 const tlcs900inst *inst;
5419
5420 m_ea2.d = *get_reg32_current( m_op );
5421 m_op = RDOP();
5422 m_ea2.d += (int8_t)m_op;
5423 m_cycles += tlcs900_mem_index_cycles();
5424 m_op = RDOP();
5425 inst = &m_mnemonic_98[m_op];
5426 prepare_operands( inst );
5427 (this->*inst->opfunc)();
5428 m_cycles += inst->cycles;
5429 }
5430
5431
5432 /* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP) used as source in long word operations */
op_A0()5433 void tlcs900_device::op_A0()
5434 {
5435 const tlcs900inst *inst;
5436
5437 m_ea2.d = *get_reg32_current( m_op );
5438 m_op = RDOP();
5439 inst = &m_mnemonic_a0[m_op];
5440 prepare_operands( inst );
5441 (this->*inst->opfunc)();
5442 m_cycles += inst->cycles;
5443 }
5444
5445
5446 /* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as source in long word operations */
op_A8()5447 void tlcs900_device::op_A8()
5448 {
5449 const tlcs900inst *inst;
5450
5451 m_ea2.d = *get_reg32_current( m_op );
5452 m_op = RDOP();
5453 m_ea2.d += (int8_t)m_op;
5454 m_cycles += tlcs900_mem_index_cycles();
5455 m_op = RDOP();
5456 inst = &m_mnemonic_a0[m_op];
5457 prepare_operands( inst );
5458 (this->*inst->opfunc)();
5459 m_cycles += inst->cycles;
5460 }
5461
5462
5463 /* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP) used as destination in operations */
op_B0()5464 void tlcs900_device::op_B0()
5465 {
5466 const tlcs900inst *inst;
5467
5468 m_ea2.d = *get_reg32_current( m_op );
5469 m_op = RDOP();
5470 inst = &m_mnemonic_b0[m_op];
5471 prepare_operands( inst );
5472 (this->*inst->opfunc)();
5473 m_cycles += inst->cycles;
5474 }
5475
5476
5477 /* (XWA/XBC/XDE/XHL/XIX/XIY/XIZ/XSP + d8) used as destination in operations */
op_B8()5478 void tlcs900_device::op_B8()
5479 {
5480 const tlcs900inst *inst;
5481
5482 m_ea2.d = *get_reg32_current( m_op );
5483 m_op = RDOP();
5484 m_ea2.d += (int8_t)m_op;
5485 m_cycles += tlcs900_mem_index_cycles();
5486 m_op = RDOP();
5487 inst = &m_mnemonic_b8[m_op];
5488 prepare_operands( inst );
5489 (this->*inst->opfunc)();
5490 m_cycles += inst->cycles;
5491 }
5492
5493
5494 /* memory used as source in byte operations */
op_C0()5495 void tlcs900_device::op_C0()
5496 {
5497 const tlcs900inst *inst;
5498 uint32_t *reg = nullptr;
5499
5500 switch ( m_op & 0x07 )
5501 {
5502 case 0x00: /* (n) */
5503 m_ea2.d = RDOP();
5504 m_cycles += tlcs900_mem_absolute_8_cycles();
5505 break;
5506
5507 case 0x01: /* (nn) */
5508 m_ea2.d = RDOP();
5509 m_ea2.b.h = RDOP();
5510 m_cycles += tlcs900_mem_absolute_16_cycles();
5511 break;
5512
5513 case 0x02: /* (nnn) */
5514 m_ea2.d = RDOP();
5515 m_ea2.b.h = RDOP();
5516 m_ea2.b.h2 = RDOP();
5517 m_cycles += tlcs900_mem_absolute_24_cycles();
5518 break;
5519
5520 case 0x03:
5521 m_op = RDOP();
5522 switch ( m_op & 0x03 )
5523 {
5524 /* (xrr) */
5525 case 0x00:
5526 m_ea2.d = *get_reg32( m_op );
5527 m_cycles += tlcs900_mem_gpr_indirect_cycles();
5528 break;
5529
5530 /* (xrr+d16) */
5531 case 0x01:
5532 m_ea2.b.l = RDOP();
5533 m_ea2.b.h = RDOP();
5534 m_ea2.d = *get_reg32( m_op ) + m_ea2.sw.l;
5535 m_cycles += tlcs900_mem_gpr_index_cycles();
5536 break;
5537
5538 /* unknown/illegal */
5539 case 0x02:
5540 break;
5541
5542 case 0x03:
5543 switch ( m_op )
5544 {
5545 /* (xrr+r8) */
5546 case 0x03:
5547 m_op = RDOP();
5548 m_ea2.d = *get_reg32( m_op );
5549 m_op = RDOP();
5550 m_ea2.d += (int8_t) *get_reg8( m_op );
5551 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5552 break;
5553
5554 /* (xrr+r16) */
5555 case 0x07:
5556 m_op = RDOP();
5557 m_ea2.d = *get_reg32( m_op );
5558 m_op = RDOP();
5559 m_ea2.d += (int16_t) *get_reg16( m_op );
5560 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5561 break;
5562
5563 /* (pc+d16) */
5564 case 0x13:
5565 m_ea2.b.l = RDOP();
5566 m_ea2.b.h = RDOP();
5567 m_ea2.d = m_pc.d + m_ea2.sw.l;
5568 m_cycles += tlcs900_mem_gpr_index_cycles();
5569 break;
5570 }
5571 }
5572 break;
5573
5574 case 0x04: /* (-xrr) */
5575 m_op = RDOP();
5576 reg = get_reg32( m_op );
5577 *reg -= ( 1 << ( m_op & 0x03 ) );
5578 m_ea2.d = *reg;
5579 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5580 break;
5581
5582 case 0x05: /* (xrr+) */
5583 m_op = RDOP();
5584 reg = get_reg32( m_op );
5585 m_ea2.d = *reg;
5586 *reg += ( 1 << ( m_op & 0x03 ) );
5587 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5588 break;
5589 }
5590 m_op = RDOP();
5591 inst = &m_mnemonic_c0[m_op];
5592 prepare_operands( inst );
5593 (this->*inst->opfunc)();
5594 m_cycles += inst->cycles;
5595 }
5596
5597
oC8()5598 void tlcs900_device::oC8()
5599 {
5600 const tlcs900inst *inst;
5601
5602 if ( m_op & 0x08 )
5603 {
5604 m_p2_reg8 = get_reg8_current( m_op );
5605 /* For MUL and DIV operations */
5606 m_p2_reg16 = get_reg16_current( ( m_op >> 1 ) & 0x03 );
5607 }
5608 else
5609 {
5610 m_op = RDOP();
5611 m_p2_reg8 = get_reg8( m_op );
5612 /* For MUL and DIV operations */
5613 m_p2_reg16 = get_reg16( m_op );
5614 }
5615 m_op = RDOP();
5616 inst = &m_mnemonic_c8[m_op];
5617 prepare_operands( inst );
5618 (this->*inst->opfunc)();
5619 m_cycles += inst->cycles;
5620 }
5621
5622
5623 /* memory used as source in word operations */
op_D0()5624 void tlcs900_device::op_D0()
5625 {
5626 const tlcs900inst *inst;
5627 uint32_t *reg = nullptr;
5628
5629 switch ( m_op & 0x07 )
5630 {
5631 case 0x00: /* (n) */
5632 m_ea2.d = RDOP();
5633 m_cycles += tlcs900_mem_absolute_8_cycles();
5634 break;
5635
5636 case 0x01: /* (nn) */
5637 m_ea2.d = RDOP();
5638 m_ea2.b.h = RDOP();
5639 m_cycles += tlcs900_mem_absolute_16_cycles();
5640 break;
5641
5642 case 0x02: /* (nnn) */
5643 m_ea2.d = RDOP();
5644 m_ea2.b.h = RDOP();
5645 m_ea2.b.h2 = RDOP();
5646 m_cycles += tlcs900_mem_absolute_24_cycles();
5647 break;
5648
5649 case 0x03:
5650 m_op = RDOP();
5651 switch ( m_op & 0x03 )
5652 {
5653 /* (xrr) */
5654 case 0x00:
5655 m_ea2.d = *get_reg32( m_op );
5656 m_cycles += tlcs900_mem_gpr_indirect_cycles();
5657 break;
5658
5659 /* (xrr+d16) */
5660 case 0x01:
5661 m_ea2.b.l = RDOP();
5662 m_ea2.b.h = RDOP();
5663 m_ea2.d = *get_reg32( m_op ) + m_ea2.sw.l;
5664 m_cycles += tlcs900_mem_gpr_index_cycles();
5665 break;
5666
5667 /* unknown/illegal */
5668 case 0x02:
5669 break;
5670
5671 case 0x03:
5672 switch ( m_op )
5673 {
5674 /* (xrr+r8) */
5675 case 0x03:
5676 m_op = RDOP();
5677 m_ea2.d = *get_reg32( m_op );
5678 m_op = RDOP();
5679 m_ea2.d += (int8_t) *get_reg8( m_op );
5680 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5681 break;
5682
5683 /* (xrr+r16) */
5684 case 0x07:
5685 m_op = RDOP();
5686 m_ea2.d = *get_reg32( m_op );
5687 m_op = RDOP();
5688 m_ea2.d += (int16_t) *get_reg16( m_op );
5689 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5690 break;
5691
5692 /* (pc+d16) */
5693 case 0x13:
5694 m_ea2.b.l = RDOP();
5695 m_ea2.b.h = RDOP();
5696 m_ea2.d = m_pc.d + m_ea2.sw.l;
5697 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5698 break;
5699 }
5700 }
5701 break;
5702
5703 case 0x04: /* (-xrr) */
5704 m_op = RDOP();
5705 reg = get_reg32( m_op );
5706 *reg -= ( 1 << ( m_op & 0x03 ) );
5707 m_ea2.d = *reg;
5708 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5709 break;
5710
5711 case 0x05: /* (xrr+) */
5712 m_op = RDOP();
5713 reg = get_reg32( m_op );
5714 m_ea2.d = *reg;
5715 *reg += ( 1 << ( m_op & 0x03 ) );
5716 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5717 break;
5718 }
5719 m_op = RDOP();
5720 inst = &m_mnemonic_d0[m_op];
5721 prepare_operands( inst );
5722 (this->*inst->opfunc)();
5723 m_cycles += inst->cycles;
5724 }
5725
5726
oD8()5727 void tlcs900_device::oD8()
5728 {
5729 const tlcs900inst *inst;
5730
5731 if ( m_op & 0x08 )
5732 {
5733 m_p2_reg16 = get_reg16_current( m_op );
5734 m_p2_reg32 = get_reg32_current( m_op );
5735 }
5736 else
5737 {
5738 m_op = RDOP();
5739 m_p2_reg16 = get_reg16( m_op );
5740 m_p2_reg32 = get_reg32( m_op );
5741 }
5742 m_op = RDOP();
5743 inst = &m_mnemonic_d8[m_op];
5744 prepare_operands( inst );
5745 (this->*inst->opfunc)();
5746 m_cycles += inst->cycles;
5747 }
5748
5749
5750 /* memory used as source in long word operations */
op_E0()5751 void tlcs900_device::op_E0()
5752 {
5753 const tlcs900inst *inst;
5754 uint32_t *reg = nullptr;
5755
5756 switch ( m_op & 0x07 )
5757 {
5758 case 0x00: /* (n) */
5759 m_ea2.d = RDOP();
5760 m_cycles += tlcs900_mem_absolute_8_cycles();
5761 break;
5762
5763 case 0x01: /* (nn) */
5764 m_ea2.d = RDOP();
5765 m_ea2.b.h = RDOP();
5766 m_cycles += tlcs900_mem_absolute_16_cycles();
5767 break;
5768
5769 case 0x02: /* (nnn) */
5770 m_ea2.d = RDOP();
5771 m_ea2.b.h = RDOP();
5772 m_ea2.b.h2 = RDOP();
5773 m_cycles += tlcs900_mem_absolute_24_cycles();
5774 break;
5775
5776 case 0x03:
5777 m_op = RDOP();
5778 switch ( m_op & 0x03 )
5779 {
5780 /* (xrr) */
5781 case 0x00:
5782 m_ea2.d = *get_reg32( m_op );
5783 m_cycles += tlcs900_mem_gpr_indirect_cycles();
5784 break;
5785
5786 /* (xrr+d16) */
5787 case 0x01:
5788 m_ea2.b.l = RDOP();
5789 m_ea2.b.h = RDOP();
5790 m_ea2.d = *get_reg32( m_op ) + m_ea2.sw.l;
5791 m_cycles += tlcs900_mem_gpr_index_cycles();
5792 break;
5793
5794 /* unknown/illegal */
5795 case 0x02:
5796 break;
5797
5798 case 0x03:
5799 switch ( m_op )
5800 {
5801 /* (xrr+r8) */
5802 case 0x03:
5803 m_op = RDOP();
5804 m_ea2.d = *get_reg32( m_op );
5805 m_op = RDOP();
5806 m_ea2.d += (int8_t) *get_reg8( m_op );
5807 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5808 break;
5809
5810 /* (xrr+r16) */
5811 case 0x07:
5812 m_op = RDOP();
5813 m_ea2.d = *get_reg32( m_op );
5814 m_op = RDOP();
5815 m_ea2.d += (int16_t) *get_reg16( m_op );
5816 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5817 break;
5818
5819 /* (pc+d16) */
5820 case 0x13:
5821 m_ea2.b.l = RDOP();
5822 m_ea2.b.h = RDOP();
5823 m_ea2.d = m_pc.d + m_ea2.sw.l;
5824 m_cycles += tlcs900_mem_gpr_index_cycles();
5825 break;
5826 }
5827 }
5828 break;
5829
5830 case 0x04: /* (-xrr) */
5831 m_op = RDOP();
5832 reg = get_reg32( m_op );
5833 *reg -= ( 1 << ( m_op & 0x03 ) );
5834 m_ea2.d = *reg;
5835 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5836 break;
5837
5838 case 0x05: /* (xrr+) */
5839 m_op = RDOP();
5840 reg = get_reg32( m_op );
5841 m_ea2.d = *reg;
5842 *reg += ( 1 << ( m_op & 0x03 ) );
5843 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5844 break;
5845 }
5846 m_op = RDOP();
5847 inst = &m_mnemonic_e0[m_op];
5848 prepare_operands( inst );
5849 (this->*inst->opfunc)();
5850 m_cycles += inst->cycles;
5851 }
5852
5853
op_E8()5854 void tlcs900_device::op_E8()
5855 {
5856 const tlcs900inst *inst;
5857
5858 if ( m_op & 0x08 )
5859 {
5860 m_p2_reg32 = get_reg32_current( m_op );
5861 }
5862 else
5863 {
5864 m_op = RDOP();
5865 m_p2_reg32 = get_reg32( m_op );
5866 }
5867 m_op = RDOP();
5868 inst = &m_mnemonic_e8[m_op];
5869 prepare_operands( inst );
5870 (this->*inst->opfunc)();
5871 m_cycles += inst->cycles;
5872 }
5873
5874
5875 /* memory used as destination operations */
op_F0()5876 void tlcs900_device::op_F0()
5877 {
5878 const tlcs900inst *inst;
5879 uint32_t *reg = nullptr;
5880
5881 switch ( m_op & 0x07 )
5882 {
5883 case 0x00: /* (n) */
5884 m_ea2.d = RDOP();
5885 m_cycles += tlcs900_mem_absolute_8_cycles();
5886 break;
5887
5888 case 0x01: /* (nn) */
5889 m_ea2.d = RDOP();
5890 m_ea2.b.h = RDOP();
5891 m_cycles += tlcs900_mem_absolute_16_cycles();
5892 break;
5893
5894 case 0x02: /* (nnn) */
5895 m_ea2.d = RDOP();
5896 m_ea2.b.h = RDOP();
5897 m_ea2.b.h2 = RDOP();
5898 m_cycles += tlcs900_mem_absolute_24_cycles();
5899 break;
5900
5901 case 0x03:
5902 m_op = RDOP();
5903 switch ( m_op & 0x03 )
5904 {
5905 /* (xrr) */
5906 case 0x00:
5907 m_ea2.d = *get_reg32( m_op );
5908 m_cycles += tlcs900_mem_gpr_indirect_cycles();
5909 break;
5910
5911 /* (xrr+d16) */
5912 case 0x01:
5913 m_ea2.b.l = RDOP();
5914 m_ea2.b.h = RDOP();
5915 m_ea2.d = *get_reg32( m_op ) + m_ea2.sw.l;
5916 m_cycles += tlcs900_mem_gpr_index_cycles();
5917 break;
5918
5919 /* unknown/illegal */
5920 case 0x02:
5921 break;
5922
5923 case 0x03:
5924 switch ( m_op )
5925 {
5926 /* (xrr+r8) */
5927 case 0x03:
5928 m_op = RDOP();
5929 m_ea2.d = *get_reg32( m_op );
5930 m_op = RDOP();
5931 m_ea2.d += (int8_t) *get_reg8( m_op );
5932 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5933 break;
5934
5935 /* (xrr+r16) */
5936 case 0x07:
5937 m_op = RDOP();
5938 m_ea2.d = *get_reg32( m_op );
5939 m_op = RDOP();
5940 m_ea2.d += (int16_t) *get_reg16( m_op );
5941 m_cycles += tlcs900_mem_gpr_reg_index_cycles();
5942 break;
5943
5944 /* (pc+d16) */
5945 case 0x13:
5946 m_ea2.b.l = RDOP();
5947 m_ea2.b.h = RDOP();
5948 m_ea2.d = m_pc.d + m_ea2.sw.l;
5949 m_cycles += tlcs900_mem_gpr_index_cycles();
5950 break;
5951 }
5952 }
5953 break;
5954
5955 case 0x04: /* (-xrr) */
5956 m_op = RDOP();
5957 reg = get_reg32( m_op );
5958 *reg -= ( 1 << ( m_op & 0x03 ) );
5959 m_ea2.d = *reg;
5960 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5961 break;
5962
5963 case 0x05: /* (xrr+) */
5964 m_op = RDOP();
5965 reg = get_reg32( m_op );
5966 m_ea2.d = *reg;
5967 *reg += ( 1 << ( m_op & 0x03 ) );
5968 m_cycles += tlcs900_mem_indirect_prepost_cycles();
5969 break;
5970 }
5971
5972 m_op = RDOP();
5973 inst = &m_mnemonic_f0[m_op];
5974 prepare_operands( inst );
5975 (this->*inst->opfunc)();
5976 m_cycles += inst->cycles;
5977 }
5978
5979
5980 const tlcs900_device::tlcs900inst tlcs900_device::s_mnemonic[256] =
5981 {
5982 /* 00 - 1F */
5983 { &tlcs900_device::op_NOP, 0, 0, 1 }, { &tlcs900_device::op_NORMAL, 0, 0, 4 }, { &tlcs900_device::op_PUSHWR, p_SR, 0, 4 }, { &tlcs900_device::op_POPWSR, p_SR, 0, 6 },
5984 { &tlcs900_device::op_MAX, 0, 0, 4 }, { &tlcs900_device::op_HALT, 0, 0, 8 }, { &tlcs900_device::op_EI, p_I8, 0, 5 }, { &tlcs900_device::op_RETI, 0, 0, 12 },
5985 { &tlcs900_device::op_LDBMI, p_M8, p_I8, 5 }, { &tlcs900_device::op_PUSHBI, p_I8, 0, 4 }, { &tlcs900_device::op_LDWMI, p_M8, p_I16, 6 }, { &tlcs900_device::op_PUSHWI, p_I16, 0, 5 },
5986 { &tlcs900_device::op_INCF, 0, 0, 2 }, { &tlcs900_device::op_DECF, 0, 0, 2 }, { &tlcs900_device::op_RET, 0, 0, 9 }, { &tlcs900_device::op_RETD, p_I16, 0, 9 },
5987 { &tlcs900_device::op_RCF, 0, 0, 2 }, { &tlcs900_device::op_SCF, 0, 0, 2 }, { &tlcs900_device::op_CCF, 0, 0, 2 }, { &tlcs900_device::op_ZCF, 0, 0, 2 },
5988 { &tlcs900_device::op_PUSHBR, p_A, 0, 3 }, { &tlcs900_device::op_POPBR, p_A, 0, 4 }, { &tlcs900_device::op_EXBRR, p_F, p_F, 2 }, { &tlcs900_device::op_LDF, p_I8, 0, 2 },
5989 { &tlcs900_device::op_PUSHBR, p_F, 0, 3 }, { &tlcs900_device::op_POPBR, p_F, 0, 4 }, { &tlcs900_device::op_JPI, p_I16, 0, 7 }, { &tlcs900_device::op_JPI, p_I24, 0, 7 },
5990 { &tlcs900_device::op_CALLI, p_I16, 0, 12 }, { &tlcs900_device::op_CALLI, p_I24, 0, 12 }, { &tlcs900_device::op_CALR, p_D16, 0, 12 }, { &tlcs900_device::op_DB, 0, 0, 1 },
5991
5992 /* 20 - 3F */
5993 { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 }, { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 }, { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 }, { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 },
5994 { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 }, { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 }, { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 }, { &tlcs900_device::op_LDBRI, p_C8, p_I8, 2 },
5995 { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 }, { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 }, { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 }, { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 },
5996 { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 }, { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 }, { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 }, { &tlcs900_device::op_PUSHWR, p_C16, 0, 3 },
5997 { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 }, { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 }, { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 }, { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 },
5998 { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 }, { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 }, { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 }, { &tlcs900_device::op_LDWRI, p_C16, p_I16, 3 },
5999 { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 }, { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 }, { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 }, { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 },
6000 { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 }, { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 }, { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 }, { &tlcs900_device::op_PUSHLR, p_C32, 0, 5 },
6001
6002 /* 40 - 5F */
6003 { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 }, { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 }, { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 }, { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 },
6004 { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 }, { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 }, { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 }, { &tlcs900_device::op_LDLRI, p_C32, p_I32, 5 },
6005 { &tlcs900_device::op_POPWR, p_C16, 0, 4 }, { &tlcs900_device::op_POPWR, p_C16, 0, 4 }, { &tlcs900_device::op_POPWR, p_C16, 0, 4 }, { &tlcs900_device::op_POPWR, p_C16, 0, 4 },
6006 { &tlcs900_device::op_POPWR, p_C16, 0, 4 }, { &tlcs900_device::op_POPWR, p_C16, 0, 4 }, { &tlcs900_device::op_POPWR, p_C16, 0, 4 }, { &tlcs900_device::op_POPWR, p_C16, 0, 4 },
6007 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
6008 { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 }, { &tlcs900_device::op_DB, 0, 0, 1 },
6009 { &tlcs900_device::op_POPLR, p_C32, 0, 6 }, { &tlcs900_device::op_POPLR, p_C32, 0, 6 }, { &tlcs900_device::op_POPLR, p_C32, 0, 6 }, { &tlcs900_device::op_POPLR, p_C32, 0, 6 },
6010 { &tlcs900_device::op_POPLR, p_C32, 0, 6 }, { &tlcs900_device::op_POPLR, p_C32, 0, 6 }, { &tlcs900_device::op_POPLR, p_C32, 0, 6 }, { &tlcs900_device::op_POPLR, p_C32, 0, 6 },
6011
6012 /* 60 - 7F */
6013 { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 },
6014 { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 },
6015 { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 },
6016 { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 }, { &tlcs900_device::op_JR, p_CC, p_D8, 4 },
6017 { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 },
6018 { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 },
6019 { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 },
6020 { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 }, { &tlcs900_device::op_JRL, p_CC, p_D16, 4 },
6021
6022 /* 80 - 9F */
6023 { &tlcs900_device::op_80, 0, 0, 0 }, { &tlcs900_device::op_80, 0, 0, 0 }, { &tlcs900_device::op_80, 0, 0, 0 }, { &tlcs900_device::op_80, 0, 0, 0 },
6024 { &tlcs900_device::op_80, 0, 0, 0 }, { &tlcs900_device::op_80, 0, 0, 0 }, { &tlcs900_device::op_80, 0, 0, 0 }, { &tlcs900_device::op_80, 0, 0, 0 },
6025 { &tlcs900_device::op_88, 0, 0, 0 }, { &tlcs900_device::op_88, 0, 0, 0 }, { &tlcs900_device::op_88, 0, 0, 0 }, { &tlcs900_device::op_88, 0, 0, 0 },
6026 { &tlcs900_device::op_88, 0, 0, 0 }, { &tlcs900_device::op_88, 0, 0, 0 }, { &tlcs900_device::op_88, 0, 0, 0 }, { &tlcs900_device::op_88, 0, 0, 0 },
6027 { &tlcs900_device::op_90, 0, 0, 0 }, { &tlcs900_device::op_90, 0, 0, 0 }, { &tlcs900_device::op_90, 0, 0, 0 }, { &tlcs900_device::op_90, 0, 0, 0 },
6028 { &tlcs900_device::op_90, 0, 0, 0 }, { &tlcs900_device::op_90, 0, 0, 0 }, { &tlcs900_device::op_90, 0, 0, 0 }, { &tlcs900_device::op_90, 0, 0, 0 },
6029 { &tlcs900_device::op_98, 0, 0, 0 }, { &tlcs900_device::op_98, 0, 0, 0 }, { &tlcs900_device::op_98, 0, 0, 0 }, { &tlcs900_device::op_98, 0, 0, 0 },
6030 { &tlcs900_device::op_98, 0, 0, 0 }, { &tlcs900_device::op_98, 0, 0, 0 }, { &tlcs900_device::op_98, 0, 0, 0 }, { &tlcs900_device::op_98, 0, 0, 0 },
6031
6032 /* A0 - BF */
6033 { &tlcs900_device::op_A0, 0, 0, 0 }, { &tlcs900_device::op_A0, 0, 0, 0 }, { &tlcs900_device::op_A0, 0, 0, 0 }, { &tlcs900_device::op_A0, 0, 0, 0 },
6034 { &tlcs900_device::op_A0, 0, 0, 0 }, { &tlcs900_device::op_A0, 0, 0, 0 }, { &tlcs900_device::op_A0, 0, 0, 0 }, { &tlcs900_device::op_A0, 0, 0, 0 },
6035 { &tlcs900_device::op_A8, 0, 0, 0 }, { &tlcs900_device::op_A8, 0, 0, 0 }, { &tlcs900_device::op_A8, 0, 0, 0 }, { &tlcs900_device::op_A8, 0, 0, 0 },
6036 { &tlcs900_device::op_A8, 0, 0, 0 }, { &tlcs900_device::op_A8, 0, 0, 0 }, { &tlcs900_device::op_A8, 0, 0, 0 }, { &tlcs900_device::op_A8, 0, 0, 0 },
6037 { &tlcs900_device::op_B0, 0, 0, 0 }, { &tlcs900_device::op_B0, 0, 0, 0 }, { &tlcs900_device::op_B0, 0, 0, 0 }, { &tlcs900_device::op_B0, 0, 0, 0 },
6038 { &tlcs900_device::op_B0, 0, 0, 0 }, { &tlcs900_device::op_B0, 0, 0, 0 }, { &tlcs900_device::op_B0, 0, 0, 0 }, { &tlcs900_device::op_B0, 0, 0, 0 },
6039 { &tlcs900_device::op_B8, 0, 0, 0 }, { &tlcs900_device::op_B8, 0, 0, 0 }, { &tlcs900_device::op_B8, 0, 0, 0 }, { &tlcs900_device::op_B8, 0, 0, 0 },
6040 { &tlcs900_device::op_B8, 0, 0, 0 }, { &tlcs900_device::op_B8, 0, 0, 0 }, { &tlcs900_device::op_B8, 0, 0, 0 }, { &tlcs900_device::op_B8, 0, 0, 0 },
6041
6042 /* C0 - DF */
6043 { &tlcs900_device::op_C0, 0, 0, 0 }, { &tlcs900_device::op_C0, 0, 0, 0 }, { &tlcs900_device::op_C0, 0, 0, 0 }, { &tlcs900_device::op_C0, 0, 0, 0 },
6044 { &tlcs900_device::op_C0, 0, 0, 0 }, { &tlcs900_device::op_C0, 0, 0, 0 }, { &tlcs900_device::op_DB, 0, 0, 0 }, { &tlcs900_device::oC8, 0, 0, 0 },
6045 { &tlcs900_device::oC8, 0, 0, 0 }, { &tlcs900_device::oC8, 0, 0, 0 }, { &tlcs900_device::oC8, 0, 0, 0 }, { &tlcs900_device::oC8, 0, 0, 0 },
6046 { &tlcs900_device::oC8, 0, 0, 0 }, { &tlcs900_device::oC8, 0, 0, 0 }, { &tlcs900_device::oC8, 0, 0, 0 }, { &tlcs900_device::oC8, 0, 0, 0 },
6047 { &tlcs900_device::op_D0, 0, 0, 0 }, { &tlcs900_device::op_D0, 0, 0, 0 }, { &tlcs900_device::op_D0, 0, 0, 0 }, { &tlcs900_device::op_D0, 0, 0, 0 },
6048 { &tlcs900_device::op_D0, 0, 0, 0 }, { &tlcs900_device::op_D0, 0, 0, 0 }, { &tlcs900_device::op_DB, 0, 0, 0 }, { &tlcs900_device::oD8, 0, 0, 0 },
6049 { &tlcs900_device::oD8, 0, 0, 0 }, { &tlcs900_device::oD8, 0, 0, 0 }, { &tlcs900_device::oD8, 0, 0, 0 }, { &tlcs900_device::oD8, 0, 0, 0 },
6050 { &tlcs900_device::oD8, 0, 0, 0 }, { &tlcs900_device::oD8, 0, 0, 0 }, { &tlcs900_device::oD8, 0, 0, 0 }, { &tlcs900_device::oD8, 0, 0, 0 },
6051
6052 /* E0 - FF */
6053 { &tlcs900_device::op_E0, 0, 0, 0 }, { &tlcs900_device::op_E0, 0, 0, 0 }, { &tlcs900_device::op_E0, 0, 0, 0 }, { &tlcs900_device::op_E0, 0, 0, 0 },
6054 { &tlcs900_device::op_E0, 0, 0, 0 }, { &tlcs900_device::op_E0, 0, 0, 0 }, { &tlcs900_device::op_DB, 0, 0, 0 }, { &tlcs900_device::op_E8, 0, 0, 0 },
6055 { &tlcs900_device::op_E8, 0, 0, 0 }, { &tlcs900_device::op_E8, 0, 0, 0 }, { &tlcs900_device::op_E8, 0, 0, 0 }, { &tlcs900_device::op_E8, 0, 0, 0 },
6056 { &tlcs900_device::op_E8, 0, 0, 0 }, { &tlcs900_device::op_E8, 0, 0, 0 }, { &tlcs900_device::op_E8, 0, 0, 0 }, { &tlcs900_device::op_E8, 0, 0, 0 },
6057 { &tlcs900_device::op_F0, 0, 0, 0 }, { &tlcs900_device::op_F0, 0, 0, 0 }, { &tlcs900_device::op_F0, 0, 0, 0 }, { &tlcs900_device::op_F0, 0, 0, 0 },
6058 { &tlcs900_device::op_F0, 0, 0, 0 }, { &tlcs900_device::op_F0, 0, 0, 0 }, { &tlcs900_device::op_DB, 0, 0, 0 }, { &tlcs900_device::op_LDX, 0, 0, 9 },
6059 { &tlcs900_device::op_SWI900, p_I3, 0, 16 }, { &tlcs900_device::op_SWI900, p_I3, 0, 16 }, { &tlcs900_device::op_SWI900, p_I3, 0, 16 }, { &tlcs900_device::op_SWI900, p_I3, 0, 16 },
6060 { &tlcs900_device::op_SWI900, p_I3, 0, 16 }, { &tlcs900_device::op_SWI900, p_I3, 0, 16 }, { &tlcs900_device::op_SWI900, p_I3, 0, 16 }, { &tlcs900_device::op_SWI900, p_I3, 0, 16 }
6061 };
6062