1 // license:BSD-3-Clause 2 // copyright-holders:Juergen Buchmueller,Ernesto Corvi 3 /***************************************************************************** 4 * 5 * z8000cpu.h 6 * Portable Z8000(2) emulator 7 * Macros and types used in z8000.c / z8000ops.inc / z8000tbl.inc 8 * 9 *****************************************************************************/ 10 11 /************************************************************************** 12 * This is the register file layout: 13 * 14 * BYTE WORD LONG QUAD 15 * msb lsb bits bits bits 16 * RH0 - RL0 R 0 15- 0 RR 0 31-16 RQ 0 63-48 17 * RH1 - RL1 R 1 15- 0 15- 0 47-32 18 * RH2 - RL2 R 2 15- 0 RR 2 31-16 31-16 19 * RH3 - RL3 R 3 15- 0 15- 0 15- 0 20 * RH4 - RL4 R 4 15- 0 RR 4 31-16 RQ 4 63-48 21 * RH5 - RL5 R 5 15- 0 15- 0 47-32 22 * RH6 - RL6 R 6 15- 0 RR 6 31-16 31-16 23 * RH7 - RL7 R 7 15- 0 15- 0 15- 0 24 * R 8 15- 0 RR 8 31-16 RQ 8 63-48 25 * R 9 15- 0 15- 0 47-32 26 * R10 15- 0 RR10 31-16 31-16 27 * R11 15- 0 15- 0 15- 0 28 * R12 15- 0 RR12 31-16 RQ12 63-48 29 * R13 15- 0 15- 0 47-32 30 * R14 15- 0 RR14 31-16 31-16 31 * R15 15- 0 15- 0 15- 0 32 * 33 * Note that for LSB_FIRST machines we have the case that the RR registers 34 * use the lower numbered R registers in the higher bit positions. 35 * And also the RQ registers use the lower numbered RR registers in the 36 * higher bit positions. 37 * That's the reason for the ordering in the following pointer table. 38 **************************************************************************/ 39 #define RB(n) m_regs.B[BYTE8_XOR_BE((((n) & 7) << 1) | (((n) & 8) >> 3))] 40 #define RW(n) m_regs.W[BYTE4_XOR_BE(n)] 41 #define RL(n) m_regs.L[BYTE_XOR_BE((n) >> 1)] 42 #define RQ(n) m_regs.Q[(n) >> 2] 43 44 /* the register used as stack pointer */ 45 #define SP (get_segmented_mode() ? 14 : 15) 46 47 /* these vectors are based on m_psap */ 48 #define RST (PSA_ADDR() + 0) /* start up m_fcw and m_pc */ 49 #define EPU (PSA_ADDR() + m_vector_mult * 0x0004) /* extension processor unit? trap */ 50 #define TRAP (PSA_ADDR() + m_vector_mult * 0x0008) /* privilege violation trap */ 51 #define SYSCALL (PSA_ADDR() + m_vector_mult * 0x000c) /* system call SC */ 52 #define SEGTRAP (PSA_ADDR() + m_vector_mult * 0x0010) /* segment trap */ 53 #define NMI (PSA_ADDR() + m_vector_mult * 0x0014) /* non maskable interrupt */ 54 #define NVI (PSA_ADDR() + m_vector_mult * 0x0018) /* non vectored interrupt */ 55 #define VI (PSA_ADDR() + m_vector_mult * 0x001c) /* vectored interrupt */ 56 #define VEC00 (PSA_ADDR() + m_vector_mult * 0x001e) /* vector n m_pc value */ 57 58 /* bits of the m_fcw */ 59 #define F_SEG 0x8000 /* segmented mode (Z8001 only) */ 60 #define F_S_N 0x4000 /* system / normal mode */ 61 #define F_EPU 0x2000 /* extension processor unit? */ 62 #define F_VIE 0x1000 /* vectored interrupt enable */ 63 #define F_NVIE 0x0800 /* non vectored interrupt enable */ 64 #define F_10 0x0400 /* unused */ 65 #define F_9 0x0200 /* unused */ 66 #define F_8 0x0100 /* unused */ 67 #define F_C 0x0080 /* carry flag */ 68 #define F_Z 0x0040 /* zero flag */ 69 #define F_S 0x0020 /* sign flag */ 70 #define F_PV 0x0010 /* parity/overflow flag */ 71 #define F_DA 0x0008 /* decimal adjust flag (0 add/adc, 1 sub/sbc) */ 72 #define F_H 0x0004 /* half carry flag (byte arithmetic only) */ 73 #define F_1 0x0002 /* unused */ 74 #define F_0 0x0001 /* unused */ 75 76 /* opcode word numbers in m_op[] array */ 77 #define OP0 0 78 #define OP1 1 79 #define OP2 2 80 81 /* nibble shift factors for an opcode word */ 82 /* left to right: 0x1340 -> NIB0=1, NIB1=3, NIB2=4, NIB3=0 */ 83 #define NIB0 12 84 #define NIB1 8 85 #define NIB2 4 86 #define NIB3 0 87 88 /* sign bit masks for byte, word and long */ 89 #define S08 0x80 90 #define S16 0x8000 91 #define S32 0x80000000 92 93 /* get a single flag bit 0/1 */ 94 #define GET_C ((m_fcw >> 7) & 1) 95 #define GET_Z ((m_fcw >> 6) & 1) 96 #define GET_S ((m_fcw >> 5) & 1) 97 #define GET_PV ((m_fcw >> 4) & 1) 98 #define GET_DA ((m_fcw >> 3) & 1) 99 #define GET_H ((m_fcw >> 2) & 1) 100 101 /* clear a single flag bit */ 102 #define CLR_C m_fcw &= ~F_C 103 #define CLR_Z m_fcw &= ~F_Z 104 #define CLR_S m_fcw &= ~F_S 105 #define CLR_P m_fcw &= ~F_PV 106 #define CLR_V m_fcw &= ~F_PV 107 #define CLR_DA m_fcw &= ~F_DA 108 #define CLR_H m_fcw &= ~F_H 109 110 /* clear a flag bit combination */ 111 #define CLR_CZS m_fcw &= ~(F_C|F_Z|F_S) 112 #define CLR_CZSP m_fcw &= ~(F_C|F_Z|F_S|F_PV) 113 #define CLR_CZSV m_fcw &= ~(F_C|F_Z|F_S|F_PV) 114 #define CLR_CZSVH m_fcw &= ~(F_C|F_Z|F_S|F_PV|F_H) 115 #define CLR_ZS m_fcw &= ~(F_Z|F_S) 116 #define CLR_ZSV m_fcw &= ~(F_Z|F_S|F_PV) 117 #define CLR_ZSP m_fcw &= ~(F_Z|F_S|F_PV) 118 119 /* set a single flag bit */ 120 #define SET_C m_fcw |= F_C 121 #define SET_Z m_fcw |= F_Z 122 #define SET_S m_fcw |= F_S 123 #define SET_P m_fcw |= F_PV 124 #define SET_V m_fcw |= F_PV 125 #define SET_DA m_fcw |= F_DA 126 #define SET_H m_fcw |= F_H 127 128 /* set a flag bit combination */ 129 #define SET_SC m_fcw |= F_C | F_S 130 131 /* check condition codes */ 132 #define CC0 (0) /* always false */ 133 #define CC1 (GET_PV^GET_S) /* less than */ 134 #define CC2 (GET_Z|(GET_PV^GET_S)) /* less than or equal */ 135 #define CC3 (GET_Z|GET_C) /* unsigned less than or equal */ 136 #define CC4 GET_PV /* parity even / overflow */ 137 #define CC5 GET_S /* minus (signed) */ 138 #define CC6 GET_Z /* zero / equal */ 139 #define CC7 GET_C /* carry / unsigned less than */ 140 141 #define CC8 (1) /* always true */ 142 #define CC9 !(GET_PV^GET_S) /* greater than or equal */ 143 #define CCA !(GET_Z|(GET_PV^GET_S)) /* greater than */ 144 #define CCB !(GET_Z|GET_C) /* unsigned greater than */ 145 #define CCC !GET_PV /* parity odd / no overflow */ 146 #define CCD !GET_S /* plus (not signed) */ 147 #define CCE !GET_Z /* not zero / not equal */ 148 #define CCF !GET_C /* not carry / unsigned greater than */ 149 150 /* get data from the opcode words */ 151 /* o is the opcode word offset */ 152 /* s is a nibble shift factor */ 153 #define GET_BIT(o) uint16_t bit = 1 << (get_operand(o) & 15) 154 #define GET_CCC(o,s) uint8_t cc = (get_operand(o) >> (s)) & 15 155 156 #define GET_DST(o,s) uint8_t dst = (get_operand(o) >> (s)) & 15 157 #define GET_SRC(o,s) uint8_t src = (get_operand(o) >> (s)) & 15 158 #define GET_IDX(o,s) uint8_t idx = (get_operand(o) >> (s)) & 15 159 #define GET_CNT(o,s) int8_t cnt = (get_operand(o) >> (s)) & 15 160 #define GET_IMM4(o,s) uint8_t imm4 = (get_operand(o) >> (s)) & 15 161 162 #define GET_I4M1(o,s) uint8_t i4p1 = ((get_operand(o) >> (s)) & 15) + 1 163 #define GET_IMM1(o,s) uint8_t imm1 = (get_operand(o) >> (s)) & 2 164 #define GET_IMM2(o,s) uint8_t imm2 = (get_operand(o) >> (s)) & 3 165 #define GET_IMM3(o,s) uint8_t imm3 = (get_operand(o) >> (s)) & 7 166 167 #define GET_IMM8(o) uint8_t imm8 = (uint8_t)get_operand(o) 168 169 // Be very careful with order of operations since get_operand has side effects 170 #define GET_IMM16(o) uint16_t imm16 = get_operand(o) 171 #define GET_IDX16(o) uint32_t idx16 = get_operand(o) 172 #define GET_IMM32 uint32_t imm32 = get_operand(1); imm32 = (imm32 << 16) + get_operand(2) 173 #define GET_DSP7 uint8_t dsp7 = get_operand(0) & 127 174 #define GET_DSP8 int8_t dsp8 = (int8_t)get_operand(0) 175 #define GET_DSP16 uint16_t tmp16 = get_operand(1); uint32_t dsp16 = addr_add(m_pc, (int16_t)tmp16) 176 #define GET_ADDR(o) uint32_t addr = (uint32_t)get_addr_operand(o) 177 #define GET_ADDR_RAW(o) uint32_t addr = (uint32_t)get_raw_addr_operand(o) 178