1 // license:BSD-3-Clause
2 // copyright-holders:Olivier Galibert
3 /***************************************************************************
4
5 NeXT
6
7 TODO:
8
9 - Hook up the sound output, it is shared with the keyboard port
10
11 - Implement more of the scc and its dma interactions so that the
12 start up test passes, but not before sound out is done (if the scc
13 test passes all the other test pass up to sound out which
14 infloops)
15
16 - Really implement the MO, it's only faking it for the startup test right now
17
18 - Fix the networking
19
20 - Find out why netbsd goes to hell even before loading the kernel
21
22 Memory map and other bits can be found here:
23 http://fxr.watson.org/fxr/source/arch/next68k/include/cpu.h?v=NETBSD5#L366
24
25 ****************************************************************************/
26
27
28 #include "emu.h"
29 #include "includes/next.h"
30
31 #include "bus/nscsi/cd.h"
32 #include "bus/nscsi/hd.h"
33 #include "screen.h"
34 #include "softlist.h"
35
36 #include "formats/mfi_dsk.h"
37 #include "formats/pc_dsk.h"
38
39
screen_update(screen_device & screen,bitmap_rgb32 & bitmap,const rectangle & cliprect)40 uint32_t next_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
41 {
42 // We don't handle partial updates, but we don't generate them either :-)
43 if(cliprect.min_x || cliprect.min_y || cliprect.max_x+1 != screen_sx || cliprect.max_y+1 != screen_sy)
44 return 0;
45
46 // 0,1,2,4=0b000000, 3=2c000000, 5,8,9=0c000000
47 // 1152x832 (0,1,2,3c,4)
48 // 1120x832 (8)
49 // 832x624 (5c,9c)
50 if(screen_color) {
51 const uint32_t *vr = vram;
52 for(int y=0; y<screen_sy; y++) {
53 uint32_t *pix = reinterpret_cast<uint32_t *>(bitmap.raw_pixptr(y));
54 for(int x=0; x<screen_sx; x+=2) {
55 uint32_t v = *vr++;
56 for(int xi=0; xi<2; xi++) {
57 uint16_t pen = (v >> (16-(xi*16))) & 0xffff;
58 uint32_t r = (pen & 0xf000) >> 12;
59 uint32_t g = (pen & 0x0f00) >> 8;
60 uint32_t b = (pen & 0x00f0) >> 4;
61 uint32_t col = (r << 20) | (r << 16) | (g << 12) | (g << 8) | (b << 4) | b;
62 *pix++ = col;
63 }
64 }
65 vr += screen_skip;
66 }
67 } else {
68 static uint32_t colors[4] = { 0xffffff, 0xaaaaaa, 0x555555, 0x000000 };
69 const uint32_t *vr = vram;
70 for(int y=0; y<screen_sy; y++) {
71 uint32_t *pix = reinterpret_cast<uint32_t *>(bitmap.raw_pixptr(y));
72 for(int x=0; x<screen_sx; x+=16) {
73 uint32_t v = *vr++;
74 for(int xi=0; xi<16; xi++)
75 *pix++ = colors[(v >> (30-(xi*2))) & 0x3];
76 }
77 vr += screen_skip;
78 }
79 }
80
81 return 0;
82 }
83
84 /* map ROM at 0x01000000-0x0101ffff? */
rom_map_r()85 uint32_t next_state::rom_map_r()
86 {
87 if(0 && !machine().side_effects_disabled())
88 printf("%08x ROM MAP?\n",maincpu->pc());
89 return 0x01000000;
90 }
91
scr2_r()92 uint32_t next_state::scr2_r()
93 {
94 if(0 && !machine().side_effects_disabled())
95 printf("%08x\n",maincpu->pc());
96 /*
97 x--- ---- ---- ---- ---- ---- ---- ---- dsp reset
98 -x-- ---- ---- ---- ---- ---- ---- ---- dsp block end
99 --x- ---- ---- ---- ---- ---- ---- ---- dsp unpacked
100 ---x ---- ---- ---- ---- ---- ---- ---- dsp mode b
101 ---- x--- ---- ---- ---- ---- ---- ---- dsp mode a
102 ---- -x-- ---- ---- ---- ---- ---- ---- remote int
103 ---- ---x ---- ---- ---- ---- ---- ---- local int
104 ---- ---- ---x ---- ---- ---- ---- ---- dram 256k
105 ---- ---- ---- ---x ---- ---- ---- ---- dram 1m
106 ---- ---- ---- ---- x--- ---- ---- ---- "timer on ipl7"
107 ---- ---- ---- ---- -xxx ---- ---- ---- rom waitstates
108 ---- ---- ---- ---- ---- x--- ---- ---- ROM 1M
109 ---- ---- ---- ---- ---- -x-- ---- ---- MCS1850 rtdata
110 ---- ---- ---- ---- ---- --x- ---- ---- MCS1850 rtclk
111 ---- ---- ---- ---- ---- ---x ---- ---- MCS1850 rtce
112 ---- ---- ---- ---- ---- ---- x--- ---- rom overlay
113 ---- ---- ---- ---- ---- ---- -x-- ---- dsp ie
114 ---- ---- ---- ---- ---- ---- --x- ---- mem en
115 ---- ---- ---- ---- ---- ---- ---- ---x led
116
117 68040-25, 100ns, 32M: 00000c80
118 68040-25, 100ns, 20M: 00ff0c80
119
120 */
121
122 uint32_t data = scr2 & 0xfffffbff;
123
124 data |= rtc->sdo_r() << 10;
125
126 return data;
127 }
128
scr2_w(offs_t offset,uint32_t data,uint32_t mem_mask)129 void next_state::scr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
130 {
131 if(0 && !machine().side_effects_disabled())
132 printf("scr2_w %08x (%08x)\n", data, maincpu->pc());
133 COMBINE_DATA(&scr2);
134
135 rtc->ce_w(BIT(scr2, 8));
136 rtc->sdi_w(BIT(scr2, 10));
137 rtc->sck_w(BIT(scr2, 9));
138 irq_set(0, scr2 & 0x01000000);
139 irq_set(1, scr2 & 0x02000000);
140 }
141
scr1_r()142 uint32_t next_state::scr1_r()
143 {
144 /*
145 xxxx ---- ---- ---- ---- ---- ---- ---- slot ID
146 ---- ---- xxxx xxxx ---- ---- ---- ---- DMA type
147 ---- ---- ---- ---- xxxx ---- ---- ---- machine type
148 ---- ---- ---- ---- ---- xxxx ---- ---- board revision
149 ---- ---- ---- ---- ---- ---- -xx- ---- video mem speed
150 ---- ---- ---- ---- ---- ---- ---x x--- mem speed
151 ---- ---- ---- ---- ---- ---- ---- -xxx cpu speed 16/20/25/33/40/50/66/80
152
153 machine types:
154 0 NeXT_CUBE
155 1 NeXT_WARP9
156 2 NeXT_X15
157 3 NeXT_WARP9C
158 4 NeXT_Turbo
159 5 NeXT_TurboC
160 6 Unknown
161 7 Unknown
162 8 NeXT_TurboCube
163 9 NeXT_TurboCubeC
164
165 68040-25: 00011102
166 68040-25: 00013002 (non-turbo, color)
167 */
168
169 return scr1;
170 }
171
172 // Interrupt subsystem
173 // source bit level
174 // nmi 31 7 *
175 // pfail 30 7
176 // timer 29 6 *
177 // enetxdma 28 6 *
178 // enetrdma 27 6 *
179 // scsidma 26 6 *
180 // diskdma 25 6
181 // prndma 24 6 *
182 // sndoutdma 23 6
183 // sndindma 22 6
184 // sccdma 21 6
185 // dspdma 20 6
186 // m2rdma 19 6
187 // r2mdma 18 6
188 // scc 17 5
189 // remote 16 5 *
190 // bus 15 5 *
191 // dsp4 14 4
192 // disk/cvid 13 3
193 // scsi 12 3 *
194 // printer 11 3
195 // enetx 10 3 *
196 // enetr 9 3
197 // soundovr 8 3 *
198 // phone 7 3 * -- floppy
199 // dsp3 6 3
200 // video 5 3
201 // monitor 4 3
202 // kbdmouse 3 3 *
203 // power 2 3 *
204 // softint1 1 2 *
205 // softint0 0 1 *
206
irq_set(int id,bool raise)207 void next_state::irq_set(int id, bool raise)
208 {
209 uint32_t mask = 1U << id;
210 uint32_t old_status = irq_status;
211 if(raise)
212 irq_status |= mask;
213 else
214 irq_status &= ~mask;
215 if(old_status != irq_status)
216 irq_check();
217 }
218
219
irq_status_r()220 uint32_t next_state::irq_status_r()
221 {
222 return irq_status;
223 }
224
irq_mask_r()225 uint32_t next_state::irq_mask_r()
226 {
227 return irq_mask;
228 }
229
irq_mask_w(offs_t offset,uint32_t data,uint32_t mem_mask)230 void next_state::irq_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask)
231 {
232 COMBINE_DATA(&irq_mask);
233 irq_check();
234 }
235
irq_check()236 void next_state::irq_check()
237 {
238 uint32_t act = irq_status & (irq_mask | 0x80000000);
239 int bit;
240 for(bit=31; bit >= 0 && !(act & (1U << bit)); bit--);
241
242 int level;
243 if (bit < 0) level = 0;
244 else if(bit < 1) level = 1;
245 else if(bit < 2) level = 2;
246 else if(bit < 14) level = 3;
247 else if(bit < 15) level = 4;
248 else if(bit < 18) level = 5;
249 else if(bit < 30) level = 6;
250 else level = 7;
251
252 logerror("IRQ info %08x/%08x - %d\n", irq_status, irq_mask, level);
253
254 if(level != irq_level) {
255 maincpu->set_input_line(irq_level, CLEAR_LINE);
256 maincpu->set_input_line(level, ASSERT_LINE);
257 irq_level = level;
258 }
259 }
260
261 char const *const next_state::dma_targets[0x20] = {
262 nullptr, "scsi", nullptr, nullptr, "soundout", "disk", nullptr, nullptr,
263 "soundin", "printer", nullptr, nullptr, "scc", "dsp", nullptr, nullptr,
264 "s-enetx", "enetx", nullptr, nullptr, "s-enetr", "enetr", nullptr, nullptr,
265 "video", nullptr, nullptr, nullptr, "r2m", "m2r", nullptr, nullptr
266 };
267
268 int const next_state::dma_irqs[0x20] = {
269 -1, 26, -1, -1, 23, 25, -1, -1, 22, 24, -1, -1, 21, 20, -1, -1,
270 -1, 28, -1, -1, -1, 27, -1, -1, 5, -1, -1, -1, 18, 19, -1, -1
271 };
272
273 bool const next_state::dma_has_saved[0x20] = {
274 false, false, false, false, false, false, false, false,
275 false, false, false, false, false, false, false, false,
276 false, true, false, false, false, true, false, false,
277 false, false, false, false, false, false, false, false,
278 };
279
dma_name(int slot)280 const char *next_state::dma_name(int slot)
281 {
282 static char buf[32];
283 if(dma_targets[slot])
284 return dma_targets[slot];
285 sprintf(buf, "<%02x>", slot);
286 return buf;
287 }
288
dma_drq_w(int slot,bool state)289 void next_state::dma_drq_w(int slot, bool state)
290 {
291 // fprintf(stderr, "DMA drq_w %d, %d\n", slot, state);
292 dma_slot &ds = dma_slots[slot];
293 ds.drq = state;
294 if(state && (ds.state & DMA_ENABLE)) {
295 address_space &space = maincpu->space(AS_PROGRAM);
296 if(ds.state & DMA_READ) {
297 while(ds.drq) {
298 dma_check_update(slot);
299 uint8_t val;
300 bool eof;
301 bool err;
302 dma_read(slot, val, eof, err);
303 if(err) {
304 ds.state = (ds.state & ~DMA_ENABLE) | DMA_BUSEXC;
305 logerror("DMA: bus error on read slot %d\n", slot);
306 return;
307 }
308 space.write_byte(ds.current++, val);
309 dma_check_end(slot, eof);
310 if(!(ds.state & DMA_ENABLE))
311 return;
312 }
313 } else {
314 while(ds.drq) {
315 dma_check_update(slot);
316 uint8_t val = space.read_byte(ds.current++);
317 bool eof = ds.current == (ds.limit & 0x7fffffff) && (ds.limit & 0x80000000);
318 bool err;
319 dma_write(slot, val, eof, err);
320 if(err) {
321 ds.state = (ds.state & ~DMA_ENABLE) | DMA_BUSEXC;
322 logerror("DMA: bus error on write slot %d\n", slot);
323 return;
324 }
325 dma_check_end(slot, false);
326 if(!(ds.state & DMA_ENABLE))
327 return;
328 }
329 }
330 }
331 }
332
dma_read(int slot,uint8_t & val,bool & eof,bool & err)333 void next_state::dma_read(int slot, uint8_t &val, bool &eof, bool &err)
334 {
335 err = false;
336 eof = false;
337 switch(slot) {
338 case 1:
339 if(fdc && fdc->get_drq()) {
340 val = fdc->dma_r();
341 if(eof) {
342 fdc->tc_w(true);
343 fdc->tc_w(false);
344 }
345 } else
346 val = scsi->dma_r();
347 break;
348
349 case 5:
350 val = mo->dma_r();
351 break;
352
353 case 21:
354 net->rx_dma_r(val, eof);
355 logerror("dma read net %02x %s\n", val, eof ? "eof" : "");
356 break;
357
358 default:
359 err = true;
360 val = 0;
361 break;
362 }
363 }
364
dma_write(int slot,uint8_t data,bool eof,bool & err)365 void next_state::dma_write(int slot, uint8_t data, bool eof, bool &err)
366 {
367 err = false;
368 switch(slot) {
369 case 1:
370 if(fdc && fdc->get_drq()) {
371 fdc->dma_w(data);
372 if(eof) {
373 fdc->tc_w(true);
374 fdc->tc_w(false);
375 }
376 } else
377 scsi->dma_w(data);
378 break;
379
380 case 4:
381 break;
382
383 case 5:
384 mo->dma_w(data);
385 break;
386
387 case 17:
388 net->tx_dma_w(data, eof);
389 break;
390
391 default:
392 err = true;
393 break;
394 }
395 }
396
dma_check_update(int slot)397 void next_state::dma_check_update(int slot)
398 {
399 dma_slot &ds = dma_slots[slot];
400 if(ds.restart) {
401 ds.current = ds.start;
402 ds.restart = false;
403 }
404 }
405
dma_end(int slot)406 void next_state::dma_end(int slot)
407 {
408 dma_slot &ds = dma_slots[slot];
409 if(dma_has_saved[slot]) {
410 dma_slot &ds1 = dma_slots[(slot-1) & 31];
411 ds1.current = ds.start;
412 ds1.limit = ds.current;
413 }
414
415 if(!ds.supdate)
416 ds.state &= ~DMA_ENABLE;
417 else {
418 ds.start = ds.chain_start;
419 ds.limit = ds.chain_limit;
420 ds.restart = true;
421 ds.supdate = false;
422 ds.state &= ~DMA_SUPDATE;
423 }
424 ds.state |= DMA_COMPLETE;
425 logerror("dma end slot %d irq %d\n", slot, dma_irqs[slot]);
426 if(dma_irqs[slot] >= 0)
427 irq_set(dma_irqs[slot], true);
428 }
429
dma_check_end(int slot,bool eof)430 void next_state::dma_check_end(int slot, bool eof)
431 {
432 dma_slot &ds = dma_slots[slot];
433 if(eof || ds.current == (ds.limit & 0x7fffffff))
434 dma_end(slot);
435 }
436
dma_regs_r(offs_t offset)437 uint32_t next_state::dma_regs_r(offs_t offset)
438 {
439 int slot = offset >> 2;
440 int reg = offset & 3;
441
442 uint32_t res;
443
444 switch(reg) {
445 case 0:
446 res = dma_slots[slot].current;
447 break;
448 case 1:
449 res = dma_slots[slot].limit;
450 break;
451 case 2:
452 res = dma_slots[slot].chain_start;
453 break;
454 case 3: default:
455 res = dma_slots[slot].chain_limit;
456 break;
457 }
458
459 const char *name = dma_name(slot);
460 logerror("dma_regs_r %s:%d %08x (%08x)\n", name, reg, res, maincpu->pc());
461
462 return res;
463 }
464
dma_regs_w(offs_t offset,uint32_t data)465 void next_state::dma_regs_w(offs_t offset, uint32_t data)
466 {
467 int slot = offset >> 2;
468 int reg = offset & 3;
469
470 const char *name = dma_name(slot);
471
472 logerror("dma_regs_w %s:%d %08x (%08x)\n", name, reg, data, maincpu->pc());
473 switch(reg) {
474 case 0:
475 dma_slots[slot].start = data;
476 dma_slots[slot].current = data;
477 break;
478 case 1:
479 dma_slots[slot].limit = data;
480 break;
481 case 2:
482 dma_slots[slot].chain_start = data;
483 break;
484 case 3:
485 dma_slots[slot].chain_limit = data;
486 break;
487 }
488 }
489
dma_ctrl_r(offs_t offset)490 uint32_t next_state::dma_ctrl_r(offs_t offset)
491 {
492 int slot = offset >> 2;
493 int reg = offset & 3;
494
495 const char *name = dma_name(slot);
496
497 if(maincpu->pc() != 0x409bb4e)
498 logerror("dma_ctrl_r %s:%d %02x (%08x)\n", name, reg, dma_slots[slot].state, maincpu->pc());
499
500 return reg ? 0 : dma_slots[slot].state << 24;
501 }
502
dma_ctrl_w(offs_t offset,uint32_t data,uint32_t mem_mask)503 void next_state::dma_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
504 {
505 int slot = offset >> 2;
506 int reg = offset & 3;
507 const char *name = dma_name(slot);
508 logerror("dma_ctrl_w %s:%d %08x @ %08x (%08x)\n", name, reg, data, mem_mask, maincpu->pc());
509 if(!reg) {
510 if(ACCESSING_BITS_16_23)
511 dma_do_ctrl_w(slot, data >> 16);
512 else if(ACCESSING_BITS_24_31)
513 dma_do_ctrl_w(slot, data >> 24);
514 }
515 }
516
dma_do_ctrl_w(int slot,uint8_t data)517 void next_state::dma_do_ctrl_w(int slot, uint8_t data)
518 {
519 const char *name = dma_name(slot);
520 #if 0
521 fprintf(stderr, "dma_ctrl_w %s %02x (%08x)\n", name, data, maincpu->pc());
522
523 fprintf(stderr, " ->%s%s%s%s%s%s%s\n",
524 data & DMA_SETENABLE ? " enable" : "",
525 data & DMA_SETSUPDATE ? " supdate" : "",
526 data & DMA_SETREAD ? " read" : "",
527 data & DMA_CLRCOMPLETE ? " complete" : "",
528 data & DMA_RESET ? " reset" : "",
529 data & DMA_INITBUF ? " initbuf" : "",
530 data & DMA_INITBUFTURBO ? " initbufturbo" : "");
531 #endif
532 if(data & DMA_SETENABLE)
533 logerror("dma enable %s %s %08x (%08x)\n", name, data & DMA_SETREAD ? "read" : "write", (dma_slots[slot].limit-dma_slots[slot].start) & 0x7fffffff, maincpu->pc());
534
535 dma_slot &ds = dma_slots[slot];
536 if(data & (DMA_RESET|DMA_INITBUF|DMA_INITBUFTURBO)) {
537 ds.state = 0;
538 if(dma_irqs[slot] >= 0)
539 irq_set(dma_irqs[slot], false);
540 }
541 if(data & DMA_SETSUPDATE) {
542 ds.state |= DMA_SUPDATE;
543 ds.supdate = true;
544 }
545 if(data & DMA_SETREAD)
546 ds.state |= DMA_READ;
547 if(data & DMA_CLRCOMPLETE) {
548 ds.state &= ~DMA_COMPLETE;
549 if(dma_irqs[slot] >= 0)
550 irq_set(dma_irqs[slot], false);
551 }
552 if(data & DMA_SETENABLE) {
553 ds.state |= DMA_ENABLE;
554 // fprintf(stderr, "dma slot %d drq=%s\n", slot, ds.drq ? "on" : "off");
555 if(ds.drq)
556 dma_drq_w(slot, ds.drq);
557 }
558 }
559
560 int const next_state::scsi_clocks[4] = { 10000000, 12000000, 20000000, 16000000 };
561
scsictrl_r(offs_t offset,uint32_t mem_mask)562 uint32_t next_state::scsictrl_r(offs_t offset, uint32_t mem_mask)
563 {
564 uint32_t res = (scsictrl << 24) | (scsistat << 16);
565 logerror("scsictrl_read %08x @ %08x (%08x)\n", res, mem_mask, maincpu->pc());
566 return res;
567 }
568
scsictrl_w(offs_t offset,uint32_t data,uint32_t mem_mask)569 void next_state::scsictrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
570 {
571 if(ACCESSING_BITS_24_31) {
572 scsictrl = data >> 24;
573 if(scsictrl & 0x02)
574 scsi->reset();
575 scsi->set_clock(scsi_clocks[scsictrl >> 6]);
576
577 logerror("SCSIctrl %dMHz int=%s dma=%s dmadir=%s%s%s dest=%s (%08x)\n",
578 scsi_clocks[scsictrl >> 6]/1000000,
579 scsictrl & 0x20 ? "on" : "off",
580 scsictrl & 0x10 ? "on" : "off",
581 scsictrl & 0x08 ? "read" : "write",
582 scsictrl & 0x04 ? " flush" : "",
583 scsictrl & 0x02 ? " reset" : "",
584 scsictrl & 0x01 ? "wd3392" : "ncr5390",
585 maincpu->pc());
586 }
587 if(ACCESSING_BITS_16_23) {
588 scsistat = data >> 16;
589 logerror("SCSIstat %02x (%08x)\n", data, maincpu->pc());
590 }
591 }
592
event_counter_r(offs_t offset,uint32_t mem_mask)593 uint32_t next_state::event_counter_r(offs_t offset, uint32_t mem_mask)
594 {
595 // Event counters, around that time, are usually fixed-frequency counters.
596 // This one being 1MHz seems to make sense
597
598 // The v74 rom seems pretty convinced that it's 20 bits only.
599
600 if(ACCESSING_BITS_24_31)
601 eventc_latch = machine().time().as_ticks(1000000) & 0xfffff;
602 return eventc_latch;
603 }
604
dsp_r()605 uint32_t next_state::dsp_r()
606 {
607 return 0x7fffffff;
608 }
609
fdc_control_w(uint32_t data)610 void next_state::fdc_control_w(uint32_t data)
611 {
612 logerror("FDC write %02x (%08x)\n", data >> 24, maincpu->pc());
613 }
614
fdc_control_r()615 uint32_t next_state::fdc_control_r()
616 {
617 // Type of floppy present
618 // 0 = no floppy in drive
619 // 1 = ed
620 // 2 = hd
621 // 3 = dd
622
623 // The rom strangely can't boot on anything else than ED, it has
624 // code for the other densities but forces ED for some mysterious
625 // reason. The kernel otoh behaves as expected.
626
627 if(fdc) {
628 floppy_image_device *fdev = floppy0->get_device();
629 if(fdev->exists()) {
630 uint32_t variant = fdev->get_variant();
631 switch(variant) {
632 case floppy_image::SSSD:
633 case floppy_image::SSDD:
634 case floppy_image::DSDD:
635 return 3 << 24;
636
637 case floppy_image::DSHD:
638 return 2 << 24;
639
640 case floppy_image::DSED:
641 return 1 << 24;
642 }
643 }
644 }
645
646 return 0 << 24;
647 }
648
phy_r(offs_t offset)649 uint32_t next_state::phy_r(offs_t offset)
650 {
651 logerror("phy_r %d %08x (%08x)\n", offset, phy[offset], maincpu->pc());
652 return phy[offset] | (0 << 24);
653 }
654
phy_w(offs_t offset,uint32_t data,uint32_t mem_mask)655 void next_state::phy_w(offs_t offset, uint32_t data, uint32_t mem_mask)
656 {
657 COMBINE_DATA(phy+offset);
658 logerror("phy_w %d %08x (%08x)\n", offset, phy[offset], maincpu->pc());
659 }
660
device_timer(emu_timer & timer,device_timer_id id,int param,void * ptr)661 void next_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
662 {
663 irq_set(29, true);
664 timer_data = timer_next_data;
665 if(timer_ctrl & 0x40000000)
666 timer_start();
667 else
668 timer_ctrl &= 0x7fffffff;
669 }
670
timer_data_r()671 uint32_t next_state::timer_data_r()
672 {
673 if(timer_ctrl & 0x80000000)
674 timer_update();
675 return timer_data;
676 }
677
timer_data_w(offs_t offset,uint32_t data,uint32_t mem_mask)678 void next_state::timer_data_w(offs_t offset, uint32_t data, uint32_t mem_mask)
679 {
680 if(timer_ctrl & 0x80000000) {
681 COMBINE_DATA(&timer_next_data);
682 timer_next_data &= 0xffff0000;
683 } else {
684 COMBINE_DATA(&timer_data);
685 timer_data &= 0xffff0000;
686 }
687 }
688
timer_ctrl_r()689 uint32_t next_state::timer_ctrl_r()
690 {
691 irq_set(29, false);
692 return timer_ctrl;
693 }
694
timer_ctrl_w(offs_t offset,uint32_t data,uint32_t mem_mask)695 void next_state::timer_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
696 {
697 bool oldact = timer_ctrl & 0x80000000;
698 COMBINE_DATA(&timer_ctrl);
699 bool newact = timer_ctrl & 0x80000000;
700 if(oldact != newact) {
701 if(oldact) {
702 timer_update();
703 irq_set(29, false);
704 } else {
705 timer_next_data = timer_data;
706 timer_start();
707 }
708 }
709 }
710
timer_update()711 void next_state::timer_update()
712 {
713 int delta = timer_vbase - (machine().time() - timer_tbase).as_ticks(1000000);
714 if(delta < 0)
715 delta = 0;
716 timer_data = delta << 16;
717 }
718
timer_start()719 void next_state::timer_start()
720 {
721 timer_tbase = machine().time();
722 timer_vbase = timer_data >> 16;
723 timer_tm->adjust(attotime::from_usec(timer_vbase));
724 }
725
WRITE_LINE_MEMBER(next_state::scc_irq)726 WRITE_LINE_MEMBER(next_state::scc_irq)
727 {
728 irq_set(17, state);
729 }
730
WRITE_LINE_MEMBER(next_state::keyboard_irq)731 WRITE_LINE_MEMBER(next_state::keyboard_irq)
732 {
733 irq_set(3, state);
734 }
735
WRITE_LINE_MEMBER(next_state::power_irq)736 WRITE_LINE_MEMBER(next_state::power_irq)
737 {
738 irq_set(2, state);
739 }
740
WRITE_LINE_MEMBER(next_state::nmi_irq)741 WRITE_LINE_MEMBER(next_state::nmi_irq)
742 {
743 irq_set(31, state);
744 }
745
WRITE_LINE_MEMBER(next_state::fdc_irq)746 WRITE_LINE_MEMBER(next_state::fdc_irq)
747 {
748 irq_set(7, state);
749 }
750
WRITE_LINE_MEMBER(next_state::fdc_drq)751 WRITE_LINE_MEMBER(next_state::fdc_drq)
752 {
753 dma_drq_w(1, state);
754 }
755
WRITE_LINE_MEMBER(next_state::net_tx_irq)756 WRITE_LINE_MEMBER(next_state::net_tx_irq)
757 {
758 irq_set(10, state);
759 }
760
WRITE_LINE_MEMBER(next_state::net_rx_irq)761 WRITE_LINE_MEMBER(next_state::net_rx_irq)
762 {
763 irq_set(9, state);
764 }
765
WRITE_LINE_MEMBER(next_state::net_tx_drq)766 WRITE_LINE_MEMBER(next_state::net_tx_drq)
767 {
768 dma_drq_w(17, state);
769 }
770
WRITE_LINE_MEMBER(next_state::net_rx_drq)771 WRITE_LINE_MEMBER(next_state::net_rx_drq)
772 {
773 dma_drq_w(21, state);
774 }
775
WRITE_LINE_MEMBER(next_state::mo_irq)776 WRITE_LINE_MEMBER(next_state::mo_irq)
777 {
778 irq_set(13, state);
779 }
780
WRITE_LINE_MEMBER(next_state::mo_drq)781 WRITE_LINE_MEMBER(next_state::mo_drq)
782 {
783 dma_drq_w(5, state);
784 }
785
WRITE_LINE_MEMBER(next_state::scsi_irq)786 WRITE_LINE_MEMBER(next_state::scsi_irq)
787 {
788 irq_set(12, state);
789 }
790
WRITE_LINE_MEMBER(next_state::scsi_drq)791 WRITE_LINE_MEMBER(next_state::scsi_drq)
792 {
793 dma_drq_w(1, state);
794 }
795
ramdac_w(offs_t offset,uint8_t data)796 void next_state::ramdac_w(offs_t offset, uint8_t data)
797 {
798 switch(offset) {
799 case 0:
800 switch(data) {
801 case 0x05:
802 if(screen_color)
803 irq_set(13, false);
804 else
805 irq_set(5, false);
806 vbl_enabled = false;
807 break;
808
809 case 0x06:
810 vbl_enabled = true;
811 break;
812
813 default:
814 fprintf(stderr, "ramdac_w %d, %02x\n", offset, data);
815 break;
816 }
817 break;
818
819 default:
820 fprintf(stderr, "ramdac_w %d, %02x\n", offset, data);
821 break;
822 }
823 }
824
setup(uint32_t _scr1,int size_x,int size_y,int skip,bool color)825 void next_state::setup(uint32_t _scr1, int size_x, int size_y, int skip, bool color)
826 {
827 scr1 = _scr1;
828 screen_sx = size_x;
829 screen_sy = size_y;
830 screen_skip = skip;
831 screen_color = color;
832 }
833
machine_start()834 void next_state::machine_start()
835 {
836 save_item(NAME(scr2));
837 save_item(NAME(irq_status));
838 save_item(NAME(irq_mask));
839 save_item(NAME(irq_level));
840 save_item(NAME(phy));
841 save_item(NAME(scsictrl));
842 save_item(NAME(scsistat));
843 save_item(NAME(timer_tbase));
844 save_item(NAME(timer_vbase));
845 save_item(NAME(timer_data));
846 save_item(NAME(timer_next_data));
847 save_item(NAME(timer_ctrl));
848 save_item(NAME(eventc_latch));
849 save_item(NAME(esp));
850
851 for(int i=0; i<0x20; i++) {
852 save_item(NAME(dma_slots[i].start), i);
853 save_item(NAME(dma_slots[i].limit), i);
854 save_item(NAME(dma_slots[i].chain_start), i);
855 save_item(NAME(dma_slots[i].chain_limit), i);
856 save_item(NAME(dma_slots[i].current), i);
857 save_item(NAME(dma_slots[i].state), i);
858 save_item(NAME(dma_slots[i].supdate), i);
859 save_item(NAME(dma_slots[i].restart), i);
860 save_item(NAME(dma_slots[i].drq), i);
861 }
862
863 timer_tm = timer_alloc(0);
864 }
865
machine_reset()866 void next_state::machine_reset()
867 {
868 scr2 = 0;
869 irq_status = 0;
870 irq_mask = 0;
871 irq_level = 0;
872 esp = 0;
873 scsictrl = 0;
874 scsistat = 0;
875 phy[0] = phy[1] = 0;
876 eventc_latch = 0;
877 timer_vbase = 0;
878 timer_data = 0;
879 timer_next_data = 0;
880 timer_ctrl = 0;
881 vbl_enabled = true;
882 dma_drq_w(4, true); // soundout
883 }
884
WRITE_LINE_MEMBER(next_state::vblank_w)885 WRITE_LINE_MEMBER(next_state::vblank_w)
886 {
887 if(vbl_enabled) {
888 if(screen_color)
889 irq_set(13, state);
890 else
891 irq_set(5, state);
892 }
893 }
894
next_mem(address_map & map)895 void next_state::next_mem(address_map &map)
896 {
897 map(0x00000000, 0x0001ffff).rom().region("user1", 0);
898 map(0x01000000, 0x0101ffff).rom().region("user1", 0);
899 map(0x02000000, 0x020001ff).mirror(0x300200).rw(FUNC(next_state::dma_ctrl_r), FUNC(next_state::dma_ctrl_w));
900 map(0x02004000, 0x020041ff).mirror(0x300200).rw(FUNC(next_state::dma_regs_r), FUNC(next_state::dma_regs_w));
901 map(0x02006000, 0x0200600f).mirror(0x300000).m(net, FUNC(mb8795_device::map));
902 // map(0x02006010, 0x02006013).mirror(0x300000); memory timing
903 map(0x02007000, 0x02007003).mirror(0x300000).r(FUNC(next_state::irq_status_r));
904 map(0x02007800, 0x02007803).mirror(0x300000).rw(FUNC(next_state::irq_mask_r), FUNC(next_state::irq_mask_w));
905 map(0x02008000, 0x02008003).mirror(0x300000).r(FUNC(next_state::dsp_r));
906 map(0x0200c000, 0x0200c003).mirror(0x300000).r(FUNC(next_state::scr1_r));
907 map(0x0200c800, 0x0200c803).mirror(0x300000).r(FUNC(next_state::rom_map_r));
908 map(0x0200d000, 0x0200d003).mirror(0x300000).rw(FUNC(next_state::scr2_r), FUNC(next_state::scr2_w));
909 // map(0x0200d800, 0x0200d803).mirror(0x300000); RMTINT
910 map(0x0200e000, 0x0200e00b).mirror(0x300000).m(keyboard, FUNC(nextkbd_device::amap));
911 // map(0x0200f000, 0x0200f003).mirror(0x300000); printer
912 // map(0x02010000, 0x02010003).mirror(0x300000); brightness
913 map(0x02012000, 0x0201201f).mirror(0x300000).m(mo, FUNC(nextmo_device::map));
914 map(0x02014000, 0x0201400f).mirror(0x300000).m(scsi, FUNC(ncr5390_device::map));
915 map(0x02014020, 0x02014023).mirror(0x300000).rw(FUNC(next_state::scsictrl_r), FUNC(next_state::scsictrl_w));
916 map(0x02016000, 0x02016003).mirror(0x300000).rw(FUNC(next_state::timer_data_r), FUNC(next_state::timer_data_w));
917 map(0x02016004, 0x02016007).mirror(0x300000).rw(FUNC(next_state::timer_ctrl_r), FUNC(next_state::timer_ctrl_w));
918 map(0x02018000, 0x02018003).mirror(0x300000).rw(scc, FUNC(scc8530_legacy_device::reg_r), FUNC(scc8530_legacy_device::reg_w));
919 // map(0x02018004, 0x02018007).mirror(0x300000); SCC CLK
920 // map(0x02018190, 0x02018197).mirror(0x300000); warp 9c DRAM timing
921 // map(0x02018198, 0x0201819f).mirror(0x300000); warp 9c VRAM timing
922 map(0x0201a000, 0x0201a003).mirror(0x300000).r(FUNC(next_state::event_counter_r)); // EVENTC
923 // map(0x020c0000, 0x020c0004).mirror(0x300000); BMAP
924 map(0x020c0030, 0x020c0037).mirror(0x300000).rw(FUNC(next_state::phy_r), FUNC(next_state::phy_w));
925 map(0x04000000, 0x07ffffff).ram(); //work ram
926 // map(0x0c000000, 0x0c03ffff) video RAM w A+B-AB function
927 // map(0x0d000000, 0x0d03ffff) video RAM w (1-A)B function
928 // map(0x0e000000, 0x0e03ffff) video RAM w ceil(A+B) function
929 // map(0x0f000000, 0x0f03ffff) video RAM w AB function
930 // map(0x10000000, 0x1003ffff) main RAM w A+B-AB function
931 // map(0x14000000, 0x1403ffff) main RAM w (1-A)B function
932 // map(0x18000000, 0x1803ffff) main RAM w ceil(A+B) function
933 // map(0x1c000000, 0x1c03ffff) main RAM w AB function
934 }
935
next_0b_m_nofdc_mem(address_map & map)936 void next_state::next_0b_m_nofdc_mem(address_map &map)
937 {
938 next_mem(map);
939 map(0x0b000000, 0x0b03ffff).ram().share("vram");
940 }
941
next_fdc_mem(address_map & map)942 void next_state::next_fdc_mem(address_map &map)
943 {
944 next_mem(map);
945 map(0x02014100, 0x02014107).mirror(0x300000).m(fdc, FUNC(n82077aa_device::map));
946 map(0x02014108, 0x0201410b).mirror(0x300000).rw(FUNC(next_state::fdc_control_r), FUNC(next_state::fdc_control_w));
947 }
948
next_0b_m_mem(address_map & map)949 void next_state::next_0b_m_mem(address_map &map)
950 {
951 next_fdc_mem(map);
952 map(0x0b000000, 0x0b03ffff).ram().share("vram");
953 }
954
next_0c_m_mem(address_map & map)955 void next_state::next_0c_m_mem(address_map &map)
956 {
957 next_fdc_mem(map);
958 map(0x0c000000, 0x0c1fffff).ram().share("vram");
959 }
960
next_0c_c_mem(address_map & map)961 void next_state::next_0c_c_mem(address_map &map)
962 {
963 next_fdc_mem(map);
964 map(0x0c000000, 0x0c1fffff).ram().share("vram");
965 map(0x02018180, 0x02018183).mirror(0x300000).w(FUNC(next_state::ramdac_w));
966 }
967
next_2c_c_mem(address_map & map)968 void next_state::next_2c_c_mem(address_map &map)
969 {
970 next_fdc_mem(map);
971 map(0x2c000000, 0x2c1fffff).ram().share("vram");
972 map(0x02018180, 0x02018183).mirror(0x300000).w(FUNC(next_state::ramdac_w));
973 }
974
975
976 /* Input ports */
INPUT_PORTS_START(next)977 static INPUT_PORTS_START( next )
978 INPUT_PORTS_END
979
980 FLOPPY_FORMATS_MEMBER( next_state::floppy_formats )
981 FLOPPY_PC_FORMAT
982 FLOPPY_FORMATS_END
983
984 static void next_floppies(device_slot_interface &device)
985 {
986 device.option_add("35ed", FLOPPY_35_ED);
987 }
988
next_scsi_devices(device_slot_interface & device)989 static void next_scsi_devices(device_slot_interface &device)
990 {
991 device.option_add("cdrom", NSCSI_CDROM);
992 device.option_add("harddisk", NSCSI_HARDDISK);
993 device.option_add_internal("ncr5390", NCR5390);
994 }
995
ncr5390(device_t * device)996 void next_state::ncr5390(device_t *device)
997 {
998 ncr5390_device &adapter = downcast<ncr5390_device &>(*device);
999
1000 adapter.set_clock(10000000);
1001 adapter.irq_handler_cb().set(*this, FUNC(next_state::scsi_irq));
1002 adapter.drq_handler_cb().set(*this, FUNC(next_state::scsi_drq));
1003 }
1004
next_base(machine_config & config)1005 void next_state::next_base(machine_config &config)
1006 {
1007 /* video hardware */
1008 screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
1009 screen.set_refresh_hz(60);
1010 screen.set_vblank_time(ATTOSECONDS_IN_USEC(2500)); /* not accurate */
1011 screen.set_screen_update(FUNC(next_state::screen_update));
1012 screen.set_size(1120, 900);
1013 screen.set_visarea(0, 1120-1, 0, 832-1);
1014 screen.screen_vblank().set(FUNC(next_state::vblank_w));
1015
1016 // devices
1017 NSCSI_BUS(config, "scsibus");
1018
1019 MCCS1850(config, rtc, XTAL(32'768));
1020
1021 SCC8530(config, scc, XTAL(25'000'000));
1022 scc->intrq_callback().set(FUNC(next_state::scc_irq));
1023
1024 NEXTKBD(config, keyboard, 0);
1025 keyboard->int_change_wr_callback().set(FUNC(next_state::keyboard_irq));
1026 keyboard->int_power_wr_callback().set(FUNC(next_state::power_irq));
1027 keyboard->int_nmi_wr_callback().set(FUNC(next_state::nmi_irq));
1028
1029 NSCSI_CONNECTOR(config, "scsibus:0", next_scsi_devices, "harddisk");
1030 NSCSI_CONNECTOR(config, "scsibus:1", next_scsi_devices, "cdrom");
1031 NSCSI_CONNECTOR(config, "scsibus:2", next_scsi_devices, nullptr);
1032 NSCSI_CONNECTOR(config, "scsibus:3", next_scsi_devices, nullptr);
1033 NSCSI_CONNECTOR(config, "scsibus:4", next_scsi_devices, nullptr);
1034 NSCSI_CONNECTOR(config, "scsibus:5", next_scsi_devices, nullptr);
1035 NSCSI_CONNECTOR(config, "scsibus:6", next_scsi_devices, nullptr);
1036 NSCSI_CONNECTOR(config, "scsibus:7", next_scsi_devices, "ncr5390", true).set_option_machine_config("ncr5390", [this] (device_t *device) { ncr5390(device); });
1037
1038 MB8795(config, net, 0);
1039 net->tx_irq().set(FUNC(next_state::net_tx_irq));
1040 net->rx_irq().set(FUNC(next_state::net_rx_irq));
1041 net->tx_drq().set(FUNC(next_state::net_tx_drq));
1042 net->rx_drq().set(FUNC(next_state::net_rx_drq));
1043
1044 NEXTMO(config, mo, 0);
1045 mo->irq_wr_callback().set(FUNC(next_state::mo_irq));
1046 mo->drq_wr_callback().set(FUNC(next_state::mo_drq));
1047 }
1048
next(machine_config & config)1049 void next_state::next(machine_config &config)
1050 {
1051 next_base(config);
1052 M68030(config, maincpu, XTAL(25'000'000));
1053 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_0b_m_nofdc_mem);
1054 }
1055
next_fdc_base(machine_config & config)1056 void next_state::next_fdc_base(machine_config &config)
1057 {
1058 next_base(config);
1059
1060 N82077AA(config, fdc, 24'000'000, n82077aa_device::mode_t::PS2);
1061 fdc->intrq_wr_callback().set(FUNC(next_state::fdc_irq));
1062 fdc->drq_wr_callback().set(FUNC(next_state::fdc_drq));
1063 FLOPPY_CONNECTOR(config, "fdc:0", next_floppies, "35ed", next_state::floppy_formats);
1064
1065 // software list
1066 SOFTWARE_LIST(config, "flop_list").set_original("next");
1067 }
1068
nexts(machine_config & config)1069 void next_state::nexts(machine_config &config)
1070 {
1071 next_fdc_base(config);
1072 M68040(config, maincpu, XTAL(25'000'000));
1073 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_0b_m_mem);
1074 }
1075
nexts2(machine_config & config)1076 void next_state::nexts2(machine_config &config)
1077 {
1078 next_fdc_base(config);
1079 M68040(config, maincpu, XTAL(25'000'000));
1080 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_0b_m_mem);
1081 }
1082
nextsc(machine_config & config)1083 void next_state::nextsc(machine_config &config)
1084 {
1085 next_fdc_base(config);
1086 M68040(config, maincpu, XTAL(25'000'000));
1087 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_2c_c_mem);
1088 }
1089
nextst(machine_config & config)1090 void next_state::nextst(machine_config &config)
1091 {
1092 next_fdc_base(config);
1093 M68040(config, maincpu, XTAL(33'000'000));
1094 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_0b_m_mem);
1095 }
1096
nextstc(machine_config & config)1097 void next_state::nextstc(machine_config &config)
1098 {
1099 next_fdc_base(config);
1100 M68040(config, maincpu, XTAL(33'000'000));
1101 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_0c_c_mem);
1102 subdevice<screen_device>("screen")->set_visarea(0, 832-1, 0, 624-1);
1103 }
1104
nextct(machine_config & config)1105 void next_state::nextct(machine_config &config)
1106 {
1107 next_fdc_base(config);
1108 M68040(config, maincpu, XTAL(33'000'000));
1109 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_0c_m_mem);
1110 }
1111
nextctc(machine_config & config)1112 void next_state::nextctc(machine_config &config)
1113 {
1114 next_fdc_base(config);
1115 M68040(config, maincpu, XTAL(33'000'000));
1116 maincpu->set_addrmap(AS_PROGRAM, &next_state::next_0c_c_mem);
1117 subdevice<screen_device>("screen")->set_visarea(0, 832-1, 0, 624-1);
1118 }
1119
1120 /* ROM definition */
1121 #define ROM_NEXT_V1 \
1122 ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \
1123 ROM_SYSTEM_BIOS( 0, "v12", "v1.2" ) /* MAC address/serial number word at 0xC: 005AD0 */ \
1124 ROMX_LOAD( "rev_1.2.bin", 0x0000, 0x10000, CRC(7070bd78) SHA1(e34418423da61545157e36b084e2068ad41c9e24), ROM_BIOS(0)) /* Label: "(C) 1990 NeXT, Inc. // All Rights Reserved. // Release 1.2 // 1142.02", underlabel exists but unknown */ \
1125 ROM_SYSTEM_BIOS( 1, "v10", "v1.0 v41" ) /* MAC address/serial number word at 0xC: 003090 */ \
1126 ROMX_LOAD( "rev_1.0_v41.bin", 0x0000, 0x10000, CRC(54df32b9) SHA1(06e3ecf09ab67a571186efd870e6b44028612371), ROM_BIOS(1)) /* Label: "(C) 1989 NeXT, Inc. // All Rights Reserved. // Release 1.0 // 1142.00", underlabel: "MYF // 1.0.41 // 0D5C" */ \
1127 ROM_SYSTEM_BIOS( 2, "v10p", "v1.0 v41 alternate" ) /* MAC address/serial number word at 0xC: 0023D9 */ \
1128 ROMX_LOAD( "rev_1.0_proto.bin", 0x0000, 0x10000, CRC(f44974f9) SHA1(09eaf9f5d47e379cfa0e4dc377758a97d2869ddc), ROM_BIOS(2)) /* Label: "(C) 1989 NeXT, Inc. // All Rights Reserved. // Release 1.0 // 1142.00", no underlabel */
1129
1130 #define ROM_NEXT_V2 \
1131 ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \
1132 ROM_SYSTEM_BIOS( 0, "v25", "v2.5 v66" ) /* MAC address/serial number word at 0xC: 00F302 */ \
1133 ROMX_LOAD( "rev_2.5_v66.bin", 0x0000, 0x20000, CRC(f47e0bfe) SHA1(b3534796abae238a0111299fc406a9349f7fee24), ROM_BIOS(0)) \
1134 ROM_SYSTEM_BIOS( 1, "v24", "v2.4 v65" ) /* MAC address/serial number word at 0xC: 00A634 */ \
1135 ROMX_LOAD( "rev_2.4_v65.bin", 0x0000, 0x20000, CRC(74e9e541) SHA1(67d195351288e90818336c3a84d55e6a070960d2), ROM_BIOS(1)) \
1136 ROM_SYSTEM_BIOS( 2, "v22", "v2.2 v63" ) /* MAC address/serial number word at 0xC: 00894C */ \
1137 ROMX_LOAD( "rev_2.2_v63.bin", 0x0000, 0x20000, CRC(739d7c07) SHA1(48ffe54cf2038782a92a0850337c5c6213c98571), ROM_BIOS(2)) /* Label: "(C) 1990 NeXT Computer, Inc. // All Rights Reserved. // Release 2.1 // 2918.AB" */ \
1138 ROM_SYSTEM_BIOS( 3, "v21", "v2.1 v59" ) /* MAC address/serial number word at 0xC: 0072FE */ \
1139 ROMX_LOAD( "rev_2.1_v59.bin", 0x0000, 0x20000, CRC(f20ef956) SHA1(09586c6de1ca73995f8c9b99870ee3cc9990933a), ROM_BIOS(3)) \
1140 ROM_SYSTEM_BIOS( 4, "v12", "v1.2 v58" ) /* MAC address/serial number word at 0xC: 006372 */ \
1141 ROMX_LOAD( "rev_1.2_v58.bin", 0x0000, 0x20000, CRC(b815b6a4) SHA1(97d8b09d03616e1487e69d26609487486db28090), ROM_BIOS(4)) /* Label: "V58 // (C) 1990 NeXT, Inc. // All Rights Reserved // Release 1.2 // 1142.02" */
1142
1143 #define ROM_NEXT_V3 \
1144 ROM_REGION32_BE( 0x20000, "user1", ROMREGION_ERASEFF ) \
1145 ROM_SYSTEM_BIOS( 0, "v33", "v3.3 v74" ) /* MAC address/serial number word at 0xC: 123456 */ \
1146 ROMX_LOAD( "rev_3.3_v74.bin", 0x0000, 0x20000, CRC(fbc3a2cd) SHA1(a9bef655f26f97562de366e4a33bb462e764c929), ROM_BIOS(0)) \
1147 ROM_SYSTEM_BIOS( 1, "v32", "v3.2 v72" ) /* MAC address/serial number word at 0xC: 012f31 */ \
1148 ROMX_LOAD( "rev_3.2_v72.bin", 0x0000, 0x20000, CRC(e750184f) SHA1(ccebf03ed090a79c36f761265ead6cd66fb04329), ROM_BIOS(1)) \
1149 ROM_SYSTEM_BIOS( 2, "v30", "v3.0 v70" ) /* MAC address/serial number word at 0xC: 0106e8 */ \
1150 ROMX_LOAD( "rev_3.0_v70.bin", 0x0000, 0x20000, CRC(37250453) SHA1(a7e42bd6a25c61903c8ca113d0b9a624325ee6cf), ROM_BIOS(2))
1151
1152
ROM_START(next)1153 ROM_START(next)
1154 ROM_NEXT_V1
1155 ROM_END
1156
1157 ROM_START(nexts)
1158 ROM_NEXT_V2
1159 ROM_END
1160
1161 ROM_START(nexts2)
1162 ROM_NEXT_V2
1163 ROM_END
1164
1165 ROM_START(nextsc)
1166 ROM_NEXT_V2
1167 ROM_END
1168
1169 ROM_START(nextst)
1170 ROM_NEXT_V3
1171 ROM_END
1172
1173 ROM_START(nextstc)
1174 ROM_NEXT_V3
1175 ROM_END
1176
1177 ROM_START(nextct)
1178 ROM_NEXT_V3
1179 ROM_END
1180
1181 ROM_START(nextctc)
1182 ROM_NEXT_V3
1183 ROM_END
1184
1185 void next_state::init_next()
1186 {
1187 setup(0x00010002, 1120, 832, 2, false);
1188 }
1189
init_nexts()1190 void next_state::init_nexts()
1191 {
1192 setup(0x00011002, 1120, 832, 2, false);
1193 }
1194
init_nexts2()1195 void next_state::init_nexts2()
1196 {
1197 setup(0x00012102, 1120, 832, 2, false);
1198 }
1199
init_nextsc()1200 void next_state::init_nextsc()
1201 {
1202 setup(0x00013102, 1120, 832, 16, true);
1203 }
1204
init_nextst()1205 void next_state::init_nextst()
1206 {
1207 setup(0x00014103, 1120, 832, 2, false);
1208 }
1209
init_nextstc()1210 void next_state::init_nextstc()
1211 {
1212 setup(0x00015103, 832, 624, 0, true);
1213 }
1214
init_nextct()1215 void next_state::init_nextct()
1216 {
1217 setup(0x00018103, 1120, 832, 0, false);
1218 }
1219
init_nextctc()1220 void next_state::init_nextctc()
1221 {
1222 setup(0x00019103, 832, 624, 0, true);
1223 }
1224
1225 /* Driver */
1226
1227 // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
1228 COMP( 1987, next, 0, 0, next, next, next_state, init_next, "Next Software Inc", "NeXT Cube", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1229 COMP( 1990, nexts, 0, 0, nexts, next, next_state, init_nexts, "Next Software Inc", "NeXTstation", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1230 COMP( 1990, nexts2, nexts, 0, nexts2, next, next_state, init_nexts2, "Next Software Inc", "NeXTstation (X15 variant)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1231 COMP( 1990, nextsc, nexts, 0, nextsc, next, next_state, init_nextsc, "Next Software Inc", "NeXTstation color", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1232 COMP( 1990, nextst, 0, 0, nextst, next, next_state, init_nextst, "Next Software Inc", "NeXTstation turbo", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1233 COMP( 1990, nextstc, nextst, 0, nextstc, next, next_state, init_nextstc, "Next Software Inc", "NeXTstation turbo color", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1234 COMP( ????, nextct, nextst, 0, nextct, next, next_state, init_nextct, "Next Software Inc", "NeXT Cube turbo", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1235 COMP( ????, nextctc, nextst, 0, nextctc, next, next_state, init_nextctc, "Next Software Inc", "NeXT Cube turbo color", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
1236