1 // license:BSD-3-Clause
2 // copyright-holders:Tomasz Slanina
3 /*
4 Super Eagle Shot
5 (c)1994 Seta (distributed by Visco)
6 -----------------------------------
7 driver by Tomasz Slanina
8
9
10 GOLF
11 E30-001A
12
13 CPU : Integrated Device IDT79R3051-25J 9407C (R3000A)
14 Sound+Objects : ST-0016
15 OSC : 50.0000MHz (X1) 42.9545MHz (X3)
16
17 ROMs:
18 SX004-01.PR0 - R3051 Main programs (MX27C4000)
19 SX004-02.PR1 |
20 SX004-03.PR2 |
21 SX004-04.PR3 /
22
23 SX004-05.RD0 - Data and Graphics (D23C8000SCZ)
24 SX004-06.RD1 /
25
26 SX004-07.ZPR - ST-0016 Program and Data (16M mask, read as 27c160)
27
28 GALs (not dumped):
29 SX004-08.27 (16V8B)
30 SX004-09.46 (16V8B)
31 SX004-10.59 (16V8B)
32 SX004-11.61 (22V10B)
33 SX004-12.62 (22V10B)
34 SX004-13.63 (22V10B)
35
36 Custom chips:
37 SETA ST-0015 60EN502F12 JAPAN 9415YAI (U18, 208pin PQFP, system controller)
38 SETA ST-0016 TC6187AF JAPAN 9348YAA (U68, 208pin PQFP, sound & object)
39
40 R3051 ST-0015 SX004-01 49.9545MHz ST-0016 5588-25
41 SX004-02 52B256-70 514256 514256
42 50MHz SX004-03 52B256-70 SX004-07
43 528257-70 514256-70 514256-70 SX004-04
44 528257-70 514256-70 514256-70 SX004-05
45 528257-70 514256-70 514256-70 SX004-06
46 514256-70 514256-70
47 NEC D6376
48
49 PCB Layout
50 ----------
51
52 GOLF E30-001A
53 |-------------------------------------------------------------|
54 | VOL |
55 | MB3714 |
56 | |
57 | D6376 PAL6 |
58 | PAL5 MB3790 |
59 | |
60 | |
61 | PAL4 TC528257|
62 |J PAL3 TC514256 |
63 |A PAL2 TC514256 TC528257|
64 |M TC514256 |
65 |M TC514256 TC528257|
66 |A PAL1 SX004-06.U35 TC514256 |
67 | TC514256 50MHz |
68 | SX004-05.U34 TC514256 |
69 | * LH52B256 TC514256 |-------| |
70 | SX004-07.U70 LH52B256 SX004-04.U33 | R3051 | |
71 | TC514256 TC514256 | | |
72 | 42.9545MHz SX004-03.U32 |-------| |
73 | |-------| |-------| |
74 |TC5588 |ST0016 | SX004-02.U31 |ST0015 | |
75 | | | | | |
76 |SW4 SW3 |-------| SX004-01.U30 |-------| |
77 |-------------------------------------------------------------|
78 Notes:
79 VOL : Master Volume Potentiometer
80 MB3714 : Fujitsu MB3714 Power Amp
81 D6376 : NEC uPD6376 2-channel 16-bit D/A convertor (SOIC16)
82 MB3790 : Power Monitoring IC with Reset and Watchdog Timer Function (SOIC16)
83 TC528257: Toshiba TC528257 32k x8 SRAM (SOJ28)
84 TC5588 : Toshiba TC5588 8k x8 SRAM (SOJ28)
85 TC514256: Toshiba TC514256 32k x8 SRAM (SOJ28)
86 LH52B256: Sharp LH52B256 32k x8 SRAM (SOP28)
87 R3051 : IDT 79R3051-25 CPU (PLCC84, Main CPU, R3000 core, running at 25MHz)
88 ST0015 : Seta ST-0015 Custom (QFP208)
89 ST0016 : Seta ST-0016 Custom (QFP208, Sub CPU with Z80 core)
90 note - 42.9545MHz OSC is tied to ST-0016 on pin 191, there's probably
91 internal divider. Actual chip might run at 7.159MHz (/6) or 14.31818MHz (/3)?
92 PAL1 : Lattice GAL16V8B (DIP20, labelled 'SX004-10')
93 PAL2 : Lattice GAL22V10B (DIP24, labelled 'SX004-11')
94 PAL3 : Lattice GAL22V10B (DIP24, labelled 'SX004-12')
95 PAL4 : Lattice GAL22V10B (DIP24, labelled 'SX004-13')
96 PAL5 : Lattice GAL16V8B (DIP20, labelled 'SX004-09')
97 PAL6 : Lattice GAL16V8B (DIP20, labelled 'SX004-08')
98 SW3 : 8 position Dip Switch
99 SW4 : 8 position Dip Switch
100 U30,U31,
101 U32,U33 : Macronix MX27C4000 512k x8 EPROM (DIP32, PCB labelled 'RPRO0', 'RPRO1', 'RPRO2', 'RPRO3')
102 U34,U35 : 8M mask ROM (DIP42, PCB labelled 'RD0', 'RD1')
103 U70 : 16M mask ROM (DIP42, PCB labelled 'ZPRO0')
104 * : Unpopulated position for 16M DIP42 mask ROM (PCB labelled 'ZPRO1')
105
106 */
107
108 #include "emu.h"
109 #include "emupal.h"
110 #include "machine/st0016.h"
111 #include "cpu/mips/mips1.h"
112 #include <algorithm>
113
114 class speglsht_state : public driver_device
115 {
116 public:
speglsht_state(const machine_config & mconfig,device_type type,const char * tag)117 speglsht_state(const machine_config &mconfig, device_type type, const char *tag)
118 : driver_device(mconfig, type, tag),
119 m_palette(*this, "palette"),
120 m_maincpu(*this,"maincpu"),
121 m_subcpu(*this, "sub"),
122 m_shared(*this, "shared"),
123 m_framebuffer(*this, "framebuffer"),
124 m_cop_ram(*this, "cop_ram"),
125 m_st0016_bank(*this, "st0016_bank")
126 { }
127
128 void speglsht(machine_config &config);
129
130 void init_speglsht();
131
132 private:
133 required_device<palette_device> m_palette;
134 required_device<st0016_cpu_device> m_maincpu;
135 required_device<r3051_device> m_subcpu;
136
137 required_shared_ptr<uint8_t> m_shared;
138 required_shared_ptr<uint32_t> m_framebuffer;
139 required_shared_ptr<uint32_t> m_cop_ram;
140
141 required_memory_bank m_st0016_bank;
142
143 std::unique_ptr<bitmap_ind16> m_bitmap;
144 uint32_t m_videoreg;
145
146 uint32_t shared_r(offs_t offset);
147 void shared_w(offs_t offset, uint32_t data);
148 void videoreg_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
149 void cop_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
150 uint32_t cop_r(offs_t offset);
151 uint32_t irq_ack_clear();
152
153 DECLARE_MACHINE_RESET(speglsht);
154 virtual void machine_start() override;
155 DECLARE_VIDEO_START(speglsht);
156 uint32_t screen_update_speglsht(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
157
158 void st0016_rom_bank_w(uint8_t data);
159 void speglsht_mem(address_map &map);
160 void st0016_io(address_map &map);
161 void st0016_mem(address_map &map);
162 };
163
164
st0016_mem(address_map & map)165 void speglsht_state::st0016_mem(address_map &map)
166 {
167 map(0x0000, 0x7fff).rom();
168 map(0x8000, 0xbfff).bankr("st0016_bank");
169 //map(0xc000, 0xcfff).rw(FUNC(speglsht_state::st0016_sprite_ram_r), FUNC(speglsht_state::st0016_sprite_ram_w));
170 //map(0xd000, 0xdfff).rw(FUNC(speglsht_state::st0016_sprite2_ram_r), FUNC(speglsht_state::st0016_sprite2_ram_w));
171 map(0xe000, 0xe7ff).ram();
172 map(0xe800, 0xe87f).ram();
173 //map(0xe900, 0xe9ff) // sound - internal
174 //map(0xea00, 0xebff).rw(FUNC(speglsht_state::st0016_palette_ram_r), FUNC(speglsht_state::st0016_palette_ram_w));
175 //map(0xec00, 0xec1f).rw(FUNC(speglsht_state::st0016_character_ram_r), FUNC(speglsht_state::st0016_character_ram_w));
176 map(0xf000, 0xffff).ram().share("shared");
177 }
178
machine_start()179 void speglsht_state::machine_start()
180 {
181 m_st0016_bank->configure_entries(0, 256, memregion("maincpu")->base(), 0x4000);
182 }
183
184 // common rombank? should go in machine/st0016 with larger address space exposed?
st0016_rom_bank_w(uint8_t data)185 void speglsht_state::st0016_rom_bank_w(uint8_t data)
186 {
187 m_st0016_bank->set_entry(data);
188 }
189
190
st0016_io(address_map & map)191 void speglsht_state::st0016_io(address_map &map)
192 {
193 map.global_mask(0xff);
194 //map(0x00, 0xbf).rw(FUNC(speglsht_state::st0016_vregs_r), FUNC(speglsht_state::st0016_vregs_w));
195 map(0xe1, 0xe1).w(FUNC(speglsht_state::st0016_rom_bank_w));
196 //map(0xe2, 0xe2).w(FUNC(speglsht_state::st0016_sprite_bank_w));
197 //map(0xe3, 0xe4).w(FUNC(speglsht_state::st0016_character_bank_w));
198 //map(0xe5, 0xe5).w(FUNC(speglsht_state::st0016_palette_bank_w));
199 map(0xe6, 0xe6).nopw();
200 map(0xe7, 0xe7).nopw();
201 //map(0xf0, 0xf0).r(FUNC(speglsht_state::st0016_dma_r));
202 }
203
shared_r(offs_t offset)204 uint32_t speglsht_state::shared_r(offs_t offset)
205 {
206 return m_shared[offset];
207 }
208
shared_w(offs_t offset,uint32_t data)209 void speglsht_state::shared_w(offs_t offset, uint32_t data)
210 {
211 m_shared[offset]=data&0xff;
212 }
213
videoreg_w(offs_t offset,uint32_t data,uint32_t mem_mask)214 void speglsht_state::videoreg_w(offs_t offset, uint32_t data, uint32_t mem_mask)
215 {
216 COMBINE_DATA(&m_videoreg);
217 }
218
219
cop_w(offs_t offset,uint32_t data,uint32_t mem_mask)220 void speglsht_state::cop_w(offs_t offset, uint32_t data, uint32_t mem_mask)
221 {
222 COMBINE_DATA(&m_cop_ram[offset]);
223
224 if(m_cop_ram[offset]&0x8000) //fix (sign)
225 {
226 m_cop_ram[offset]|=0xffff0000;
227 }
228 }
229
230 //matrix * vector
cop_r(offs_t offset)231 uint32_t speglsht_state::cop_r(offs_t offset)
232 {
233 int32_t *cop=(int32_t*)&m_cop_ram[0];
234
235 union
236 {
237 int32_t a;
238 uint32_t b;
239 }temp;
240
241 switch (offset)
242 {
243 case 0x40/4:
244 {
245 temp.a=((cop[0x3]*cop[0x0]+cop[0x4]*cop[0x1]+cop[0x5]*cop[0x2])>>14)+cop[0xc];
246 return temp.b;
247 }
248
249 case 0x44/4:
250 {
251 temp.a=((cop[0x6]*cop[0x0]+cop[0x7]*cop[0x1]+cop[0x8]*cop[0x2])>>14)+cop[0xd];
252 return temp.b;
253 }
254
255 case 0x48/4:
256 {
257 temp.a=((cop[0x9]*cop[0x0]+cop[0xa]*cop[0x1]+cop[0xb]*cop[0x2])>>14)+cop[0xe];
258 return temp.b;
259 }
260 }
261
262 return 0;
263 }
264
irq_ack_clear()265 uint32_t speglsht_state::irq_ack_clear()
266 {
267 m_subcpu->set_input_line(INPUT_LINE_IRQ4, CLEAR_LINE);
268 return 0;
269 }
270
speglsht_mem(address_map & map)271 void speglsht_state::speglsht_mem(address_map &map)
272 {
273 map(0x00000000, 0x000fffff).ram();
274 map(0x01000000, 0x01007fff).ram(); //tested - STATIC RAM
275 map(0x01600000, 0x0160004f).rw(FUNC(speglsht_state::cop_r), FUNC(speglsht_state::cop_w)).share("cop_ram");
276 map(0x01800200, 0x01800203).w(FUNC(speglsht_state::videoreg_w));
277 map(0x01800300, 0x01800303).portr("IN0");
278 map(0x01800400, 0x01800403).portr("IN1");
279 map(0x01a00000, 0x01afffff).ram().share("framebuffer");
280 map(0x01b00000, 0x01b07fff).ram(); //cleared ... video related ?
281 map(0x01c00000, 0x01dfffff).rom().region("subdata", 0);
282 map(0x0a000000, 0x0a003fff).rw(FUNC(speglsht_state::shared_r), FUNC(speglsht_state::shared_w));
283 map(0x0fc00000, 0x0fdfffff).rom().mirror(0x10000000).region("subprog", 0);
284 map(0x1eff0000, 0x1eff001f).ram();
285 map(0x1eff003c, 0x1eff003f).r(FUNC(speglsht_state::irq_ack_clear));
286 }
287
288 static INPUT_PORTS_START( speglsht )
289 PORT_START("IN0")
290 PORT_BIT( 0x000000ff, IP_ACTIVE_LOW, IPT_UNUSED )
291 PORT_BIT( 0x00000100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
292 PORT_BIT( 0x00000200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
293 PORT_BIT( 0x00000400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(2)
294 PORT_BIT( 0x00000800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(2)
295 PORT_BIT( 0x00001000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
296 PORT_BIT( 0x00002000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
297 PORT_BIT( 0x00004000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
298 PORT_BIT( 0x00008000, IP_ACTIVE_LOW, IPT_START2 )
299 PORT_BIT( 0xffff0000, IP_ACTIVE_LOW, IPT_UNUSED )
300
301 PORT_START("IN1")
DEF_STR(Coin_A)302 PORT_DIPNAME( 0x00000007, 0x00000007, DEF_STR( Coin_A ) ) PORT_DIPLOCATION("SW1:1,2,3")
303 PORT_DIPSETTING( 0x00000003, DEF_STR( 3C_1C ) )
304 PORT_DIPSETTING( 0x00000004, DEF_STR( 2C_1C ) )
305 PORT_DIPSETTING( 0x00000007, DEF_STR( 1C_1C ) )
306 PORT_DIPSETTING( 0x00000001, "1C/1C or 2C/3C" ) /* 1 coin/1 credit or 2 coins/3 credits */
307 PORT_DIPSETTING( 0x00000002, DEF_STR( 2C_3C ) )
308 PORT_DIPSETTING( 0x00000006, DEF_STR( 1C_2C ) )
309 PORT_DIPSETTING( 0x00000005, DEF_STR( 1C_3C ) )
310 PORT_DIPSETTING( 0x00000000, "2C Start/1C Continue" )
311 PORT_DIPNAME( 0x00000038, 0x00000038, DEF_STR( Coin_B ) ) PORT_DIPLOCATION("SW1:4,5,6")
312 PORT_DIPSETTING( 0x00000018, DEF_STR( 3C_1C ) )
313 PORT_DIPSETTING( 0x00000020, DEF_STR( 2C_1C ) )
314 PORT_DIPSETTING( 0x00000038, DEF_STR( 1C_1C ) )
315 PORT_DIPSETTING( 0x00000008, "1C/1C or 2C/3C" ) /* 1 coin/1 credit or 2 coins/3 credits */
316 PORT_DIPSETTING( 0x00000010, DEF_STR( 2C_3C ) )
317 PORT_DIPSETTING( 0x00000030, DEF_STR( 1C_2C ) )
318 PORT_DIPSETTING( 0x00000028, DEF_STR( 1C_3C ) )
319 PORT_DIPSETTING( 0x00000000, "2C Start/1C Continue" )
320 PORT_DIPUNUSED_DIPLOC( 0x00000040, 0x00000040, "SW1:7" )
321 PORT_DIPNAME( 0x00000080, 0x00000080, "Bonus for PAR Play" ) PORT_DIPLOCATION("SW1:8")
322 PORT_DIPSETTING( 0x00000080, DEF_STR( None ) )
323 PORT_DIPSETTING( 0x00000000, "Extra Hole" )
324 PORT_DIPNAME( 0x00000300, 0x00000300, DEF_STR( Difficulty ) ) PORT_DIPLOCATION("SW2:1,2")
325 PORT_DIPSETTING( 0x00000300, DEF_STR( Normal ) )
326 PORT_DIPSETTING( 0x00000200, DEF_STR( Easy ) )
327 PORT_DIPSETTING( 0x00000100, DEF_STR( Hard ) )
328 PORT_DIPSETTING( 0x00000000, DEF_STR( Very_Hard ) )
329 PORT_DIPNAME( 0x00000c00, 0x00000c00, "Number of Players" ) PORT_DIPLOCATION("SW2:3,4")
330 PORT_DIPSETTING( 0x00000c00, "3" )
331 PORT_DIPSETTING( 0x00000800, "4" )
332 PORT_DIPSETTING( 0x00000400, "2" )
333 PORT_DIPSETTING( 0x00000000, "1" )
334 PORT_DIPNAME( 0x00001000, 0x00000000, DEF_STR( Demo_Sounds ) ) PORT_DIPLOCATION("SW2:5")
335 PORT_DIPSETTING( 0x00001000, DEF_STR( Off ) )
336 PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
337 PORT_DIPNAME( 0x00002000, 0x00000000, "Control Panel" ) PORT_DIPLOCATION("SW2:6")
338 PORT_DIPSETTING( 0x00002000, "Double" )
339 PORT_DIPSETTING( 0x00000000, DEF_STR( Single ) )
340 PORT_DIPNAME( 0x00004000, 0x00000000, "Country" ) PORT_DIPLOCATION("SW2:7")
341 PORT_DIPSETTING( 0x00004000, DEF_STR( Japan ) )
342 PORT_DIPSETTING( 0x00000000, DEF_STR( USA ) )
343 PORT_DIPUNUSED_DIPLOC( 0x00008000, 0x00008000, "SW2:8" )
344 PORT_SERVICE_NO_TOGGLE( 0x00010000, IP_ACTIVE_HIGH )
345 PORT_BIT( 0x00020000, IP_ACTIVE_LOW, IPT_TILT )
346 PORT_BIT( 0x00040000, IP_ACTIVE_LOW, IPT_COIN1 )
347 PORT_BIT( 0x00080000, IP_ACTIVE_LOW, IPT_COIN2 )
348 PORT_BIT( 0x00100000, IP_ACTIVE_LOW, IPT_SERVICE1 )
349 PORT_BIT( 0x80a00000, IP_ACTIVE_LOW, IPT_UNUSED )
350 PORT_BIT( 0x00400000, IP_ACTIVE_LOW, IPT_START1 )
351 PORT_BIT( 0x01000000, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
352 PORT_BIT( 0x02000000, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
353 PORT_BIT( 0x04000000, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
354 PORT_BIT( 0x08000000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
355 PORT_BIT( 0x10000000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
356 PORT_BIT( 0x20000000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
357 PORT_BIT( 0x40000000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
358 INPUT_PORTS_END
359
360 static GFXDECODE_START( gfx_speglsht )
361 GFXDECODE_END
362
363
364 MACHINE_RESET_MEMBER(speglsht_state,speglsht)
365 {
366 std::fill(&m_shared[0],&m_shared[m_shared.bytes()],0);
367 }
368
VIDEO_START_MEMBER(speglsht_state,speglsht)369 VIDEO_START_MEMBER(speglsht_state,speglsht)
370 {
371 m_bitmap = std::make_unique<bitmap_ind16>(512, 512);
372 // VIDEO_START_CALL_MEMBER(st0016);
373 }
374
375 #define PLOT_PIXEL_RGB(x,y,r,g,b) if(y>=0 && x>=0 && x<512 && y<512) \
376 { \
377 bitmap.pix(y, x) = (b) | ((g)<<8) | ((r)<<16); \
378 }
379
screen_update_speglsht(screen_device & screen,bitmap_rgb32 & bitmap,const rectangle & cliprect)380 uint32_t speglsht_state::screen_update_speglsht(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
381 {
382 int dy=(m_videoreg&0x20)?(256*512):0; //visible frame
383
384 for(int y=0;y<256;y++)
385 {
386 for(int x=0;x<512;x++)
387 {
388 int tmp=dy+y*512+x;
389 PLOT_PIXEL_RGB(x-67,y-5,(m_framebuffer[tmp]>>0)&0xff,(m_framebuffer[tmp]>>8)&0xff,(m_framebuffer[tmp]>>16)&0xff);
390 }
391 }
392
393 //draw st0016 gfx to temporary bitmap (indexed 16)
394 m_bitmap->fill(0);
395 m_maincpu->draw_screen(screen, *m_bitmap, cliprect);
396
397 //copy temporary bitmap to rgb 32 bit bitmap
398 for(int y=cliprect.min_y; y<cliprect.max_y;y++)
399 {
400 uint16_t const *const srcline = &m_bitmap->pix(y);
401 for(int x=cliprect.min_x; x<cliprect.max_x;x++)
402 {
403 if(srcline[x])
404 {
405 rgb_t color = m_maincpu->palette().pen_color(srcline[x]);
406 PLOT_PIXEL_RGB(x,y,color.r(),color.g(),color.b());
407 }
408 }
409 }
410
411 return 0;
412 }
413
speglsht(machine_config & config)414 void speglsht_state::speglsht(machine_config &config)
415 {
416 /* basic machine hardware */
417 ST0016_CPU(config, m_maincpu, 8000000); /* 8 MHz ? */
418 m_maincpu->set_addrmap(AS_PROGRAM, &speglsht_state::st0016_mem);
419 m_maincpu->set_addrmap(AS_IO, &speglsht_state::st0016_io);
420 m_maincpu->set_vblank_int("screen", FUNC(speglsht_state::irq0_line_hold));
421
422 R3051(config, m_subcpu, 25000000);
423 m_subcpu->set_endianness(ENDIANNESS_LITTLE);
424 m_subcpu->set_addrmap(AS_PROGRAM, &speglsht_state::speglsht_mem);
425 m_subcpu->set_vblank_int("screen", FUNC(speglsht_state::irq4_line_assert));
426
427 config.set_maximum_quantum(attotime::from_hz(6000));
428 MCFG_MACHINE_RESET_OVERRIDE(speglsht_state,speglsht)
429
430 /* video hardware */
431 screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
432 screen.set_refresh_hz(60);
433 screen.set_vblank_time(ATTOSECONDS_IN_USEC(0));
434 screen.set_size(512, 512);
435 screen.set_visarea(0, 319, 8, 239-8);
436 screen.set_screen_update(FUNC(speglsht_state::screen_update_speglsht));
437
438 GFXDECODE(config, "gfxdecode", m_palette, gfx_speglsht);
439 PALETTE(config, m_palette).set_entries(16*16*4+1);
440
441 MCFG_VIDEO_START_OVERRIDE(speglsht_state,speglsht)
442 }
443
444 ROM_START( speglsht )
445 ROM_REGION( 0x400000, "maincpu", 0 )
446 ROM_LOAD( "sx004-07.u70", 0x000000, 0x200000, CRC(2d759cc4) SHA1(9fedd829190b2aab850b2f1088caaec91e8715dd) ) /* Noted as "ZPRO0" IE: Z80 (ST0016) Program 0 */
447 /* U71 unpopulated, Noted as ZPRO1 */
448
449 ROM_REGION32_LE( 0x200000, "subprog", 0 )
CRC(e46d2e57)450 ROM_LOAD32_BYTE( "sx004-04.u33", 0x00003, 0x80000, CRC(e46d2e57) SHA1(b1fb836ab2ce547dc2e8d1046d7ef835b87bb04e) ) /* Noted as "RPRO3" IE: R3000 Program 3 */
451 ROM_LOAD32_BYTE( "sx004-03.u32", 0x00002, 0x80000, CRC(c6ffb00e) SHA1(f57ef45bb5c690c3e63101a36835d2687abfcdbd) ) /* Noted as "RPRO2" */
452 ROM_LOAD32_BYTE( "sx004-02.u31", 0x00001, 0x80000, CRC(21eb46e4) SHA1(0ab21ed012c9a76e01c83b60c6f4670836dfa718) ) /* Noted as "RPRO1" */
453 ROM_LOAD32_BYTE( "sx004-01.u30", 0x00000, 0x80000, CRC(65646949) SHA1(74931c230f4e4b1008fbc5fba169292e216aa23b) ) /* Noted as "RPRO0" */
454
455 ROM_REGION32_LE( 0x200000, "subdata", 0)
456 ROM_LOAD32_WORD( "sx004-05.u34", 0x000000, 0x100000, CRC(f3c69468) SHA1(81daef6d0596cb67bb6f87b39874aae1b1ffe6a6) ) /* Noted as "RD0" IE: R3000 Data 0 */
457 ROM_LOAD32_WORD( "sx004-06.u35", 0x000002, 0x100000, CRC(5af78e44) SHA1(0131d50348fef80c2b100d74b7c967c6a710d548) ) /* Noted as "RD1" */
458 ROM_END
459
460
461 void speglsht_state::init_speglsht()
462 {
463 m_maincpu->set_game_flag(3);
464 }
465
466
467 GAME( 1994, speglsht, 0, speglsht, speglsht, speglsht_state, init_speglsht, ROT0, "Seta", "Super Eagle Shot", MACHINE_IMPERFECT_GRAPHICS )
468