1 // license:BSD-3-Clause
2 // copyright-holders:Miodrag Milanovic, R. Belmont
3 /***************************************************************************
4
5 sun3.c: preliminary driver for Sun 3 models
6
7 Sun-3 Models
8 ------------
9
10 3/160
11 Processor(s): 68020 @ 16.67MHz, 68881, Sun-3 MMU, 8 hardware
12 contexts, 2 MIPS
13 CPU: 501-1074/1096/1163/1164/1208
14 Chassis type: deskside
15 Bus: VME, 12 slots
16 Memory: 16M physical (documented), 256M virtual, 270ns cycle
17 Notes: First 68020-based Sun machine. Uses the 3004
18 "Carrera" CPU, which is used in most other Sun
19 3/1xx models and the 3/75. Sun supplied 4M
20 memory expansion boards; third parties had up to
21 32M on one card. SCSI optional. One variant of
22 the memory card holds a 6U VME SCSI board; there
23 is also a SCSI board which sits in slot 7 of the
24 backplane and runs the SCSI bus out the back of
25 the backplane to the internal disk/tape (slot 6
26 in very early backplanes). CPU has two serial
27 ports, Ethernet, keyboard. Type 3 keyboard plugs
28 into the CPU; Sun-3 mouse plugs into the
29 keyboard. Upgradeable to a 3/260 by replacing
30 CPU and memory boards.
31
32 3/75
33 Processor(s): 68020 @ 16.67MHz, 68881, Sun-3 MMU, 8 hardware
34 contexts, 2 MIPS
35 CPU: 501-1074/1094/1163/1164
36 Chassis type: wide pizza box
37 Bus: VME, 2 slot
38 Memory: 16M physical (documented), 256M virtual, 270ns cycle
39 Notes: Optional SCSI sits on memory expansion board in
40 second slot.
41
42 3/140
43 Processor(s): 68020 @ 16.67MHz, 68881, Sun-3 MMU, 8 hardware
44 contexts, 2 MIPS
45 CPU: 501-1074/1094/1163/1164/1208
46 Chassis type: deskside
47 Bus: VME, 3 slots
48 Memory: 16M physical (documented), 256M virtual, 270ns cycle
49
50 3/150
51 Processor(s): 68020 @ 16.67MHz, 68881, Sun-3 MMU, 8 hardware
52 contexts, 2 MIPS
53 CPU: 501-1074/1094/1163/1164/1208
54 Chassis type: deskside
55 Bus: VME, 6 slots
56 Memory: 16M physical (documented), 256M virtual, 270ns cycle
57
58 3/180
59 Processor(s): 68020 @ 16.67MHz, 68881, Sun-3 MMU, 8 hardware
60 contexts, 2 MIPS
61 CPU: 501-1074/1094/1163/1164/1208
62 Chassis type: rackmount
63 Bus: VME, 12 slots
64 Memory: 16M physical (documented), 256M virtual, 270ns cycle
65 Notes: Rackmount version of 3/160. Upgradeable to a
66 3/280 by replacing the CPU and memory boards.
67 Very early backplanes have the special SCSI
68 hookup on slot 6 rather than 7.
69
70 3/110
71 Processor(s): 68020
72 CPU: 501-1134/1209
73 Chassis type: deskside
74 Bus: VME, 3 slots
75 Notes: Similar to the "Carerra" CPU, but has 8-bit
76 color framebuffer (cgfour) on board and uses 1M
77 RAM chips for 4M on-CPU memory. Code-named
78 "Prism".
79
80 3/50
81 Processor(s): 68020 @ 15.7MHz, 68881 (socket for
82 501-1075/1133/1162, installed for 501-1207),
83 Sun-3 MMU, 8 hardware contexts, 1.5 MIPS
84 CPU: 501-1075/1133/1162/1207
85 Chassis type: wide pizza box
86 Bus: none
87 Memory: 4M physical (documented), 256M virtual, 270ns cycle
88 Notes: Cycle-stealing monochrome frame buffer. 4M
89 memory maximum stock, but third-party memory
90 expansion boards were sold, allowing up to at
91 least 12M. No bus or P4 connector. Onboard SCSI.
92 Thin coax or AUI Ethernet. Code-named "Model
93 25".
94
95 3/60
96 Processor(s): 68020 @ 20MHz, 68881 (stock), Sun-3 MMU,
97 8 hardware contexts, 3 MIPS
98 CPU: 501-1205/1322/1334/1345
99 Chassis type: wide pizza box
100 Bus: P4 connector (not same as P4 on 3/80)
101 Memory: 24M physical, 256M virtual, 200ns cycle
102 Notes: VRAM monochome frame buffer for 501-1205/1334.
103 Optional color frame buffer (can run mono and
104 color simultaneously) on P4 connector. Onboard
105 SCSI. SIMM memory (100ns 1M x 9 SIMMs). High
106 (1600 * 1100) or low (1152 * 900) resolution
107 mono selectable by jumper. Thin coax or AUI
108 Ethernet. Code-named "Ferrari". 4M stock on
109 501-1205/1322, 0M stock on 501-1322/1345.
110
111 3/60LE
112 Processor(s): 68020 @ 20MHz, 68881 (stock), Sun-3 MMU,
113 8 hardware contexts, 3 MIPS
114 CPU: 501-1378
115 Bus: P4 connector (not same as P4 on 3/80)
116 Memory: 12M physical, 256M virtual, 200ns cycle
117 Notes: A version of the 3/60 with no onboard
118 framebuffer and limited to 12M of RAM (4M of
119 256K SIMMs and 8M of 1M SIMMs).
120
121 3/260
122 Processor(s): 68020 @ 25MHz, 68881 @ 20MHz (stock), Sun-3 MMU,
123 8 hardware contexts, 4 MIPS
124 CPU: 501-1100/1206
125 Chassis type: deskside
126 Bus: VME, 12 slot
127 Memory: 64M (documented) physical with ECC, 256M virtual;
128 64K write-back cache, direct-mapped,
129 virtually-indexed and virtually-tagged, with
130 16-byte lines; 80ns cycle
131 Notes: Two serial ports, AUI Ethernet, keyboard, and
132 video on CPU. Video is mono, high-resolution
133 only. Sun supplied 8M memory boards. Sun 4/2xx
134 32M boards work up to 128M. First Sun with an
135 off-chip cache. Upgradeable to a 4/260 by
136 replacing the CPU board. Code-named "Sirius".
137
138 3/280
139 Processor(s): 68020 @ 25MHz, 68881 @ 20MHz (stock), Sun-3 MMU,
140 8 hardware contexts, 4 MIPS
141 CPU: 501-1100/1206
142 Chassis type: rackmount
143 Bus: VME, 12 slot
144 Memory: 64M (documented) physical with ECC, 256M virtual;
145 64K write-back cache, direct-mapped,
146 virtually-indexed and virtually-tagged, with
147 16-byte lines; 80ns cycle
148 Notes: Rackmount version of the 3/260. Upgradeable to a
149 4/280 by replacing the CPU board. Code-named
150 "Sirius".
151
152 3/E
153 Processor(s): 68020
154 CPU: 501-8028
155 Bus: VME
156 Notes: Single-board VME Sun-3, presumably for use as a
157 controller, not as a workstation. 6U form
158 factor. Serial and keyboard ports. External RAM,
159 framebuffer, and SCSI/ethernet boards
160 available.
161
162 3/60 ROM breakpoints of interest
163 fefb104 - bus error test
164 fefb18e - interrupt test
165 fefb1da - clock IRQ test
166 fefb344 - MMU page valid test
167 fefb3c4 - MMU read-only permissions test
168 fefb45e - parity test: no spurious NMI generated from normal parity operation
169 fefb50c - parity test: NMI is generated when we write with inverted parity and enable parity NMIs
170 fefb5c8 - size memory by bus error
171 fef581c - EPROM mapping check
172 fef02b2 - main screen turn on
173
174 3/260 ROM breakpoints of interest
175 fefcb34 - bpset to stop before each test
176 fefc0c2 - start of ECC test
177 fefc34a - start of mem_size, which queries ECC registers for each memory board
178
179 ****************************************************************************/
180
181 #include "emu.h"
182
183 #include "cpu/m68000/m68000.h"
184 #include "machine/bankdev.h"
185 #include "machine/nvram.h"
186 #include "machine/ram.h"
187 #include "machine/timekpr.h"
188 #include "machine/timer.h"
189 #include "machine/z80scc.h"
190 #include "machine/am79c90.h"
191 #include "machine/ncr5380n.h"
192 #include "bus/nscsi/cd.h"
193 #include "bus/nscsi/hd.h"
194
195 #include "bus/rs232/rs232.h"
196 #include "bus/sunkbd/sunkbd.h"
197 #include "bus/sunmouse/sunmouse.h"
198
199 #include "screen.h"
200
201
202 #define TIMEKEEPER_TAG "timekpr"
203 #define SCC1_TAG "scc1"
204 #define SCC2_TAG "scc2"
205 #define RS232A_TAG "rs232a"
206 #define RS232B_TAG "rs232b"
207 #define KEYBOARD_TAG "keyboard"
208 #define MOUSE_TAG "mouseport"
209
210 // page table entry constants
211 #define PM_VALID (0x80000000) // page is valid
212 #define PM_WRITEMASK (0x40000000) // writable?
213 #define PM_SYSMASK (0x20000000) // system use only?
214 #define PM_CACHE (0x10000000) // cachable?
215 #define PM_TYPEMASK (0x0c000000) // type mask
216 #define PM_ACCESSED (0x02000000) // accessed flag
217 #define PM_MODIFIED (0x01000000) // modified flag
218
219 #define BE_FPENABLE (0x04) // FPU not enabled
220 #define BE_FPBERR (0x08) // FPU encountered a bus error
221 #define BE_VMEBERR (0x10) // VME encountered a bus error
222 #define BE_TIMEOUT (0x20) // timeout - memory doesn't exist
223 #define BE_PROTERR (0x40) // protection failed on MMU page lookup
224 #define BE_INVALID (0x80) // invalid entry on MMU page lookup
225
226 class sun3_state : public driver_device
227 {
228 public:
sun3_state(const machine_config & mconfig,device_type type,const char * tag)229 sun3_state(const machine_config &mconfig, device_type type, const char *tag) :
230 driver_device(mconfig, type, tag),
231 m_maincpu(*this, "maincpu"),
232 m_scc1(*this, SCC1_TAG),
233 m_scc2(*this, SCC2_TAG),
234 m_scsibus(*this, "scsibus"),
235 m_scsi(*this, "scsibus:7:ncr5380"),
236 m_p_ram(*this, "p_ram"),
237 m_bw2_vram(*this, "bw2_vram"),
238 m_type0space(*this, "type0"),
239 m_type1space(*this, "type1"),
240 m_type2space(*this, "type2"),
241 m_type3space(*this, "type3"),
242 m_rom(*this, "user1"),
243 m_idprom(*this, "idprom"),
244 m_ram(*this, RAM_TAG),
245 m_lance(*this, "lance")
246 { }
247
248 void sun3(machine_config &config);
249 void sun3e(machine_config &config);
250 void sun3_60(machine_config &config);
251 void sun3200(machine_config &config);
252 void sun3_50(machine_config &config);
253
254 void ncr5380(device_t *device);
255
256 private:
257 required_device<m68020_device> m_maincpu;
258 required_device<z80scc_device> m_scc1;
259 required_device<z80scc_device> m_scc2;
260 required_device<nscsi_bus_device> m_scsibus;
261 required_device<ncr5380n_device> m_scsi;
262
263 virtual void machine_start() override;
264 virtual void machine_reset() override;
265
266 optional_shared_ptr<uint32_t> m_p_ram;
267 optional_shared_ptr<uint32_t> m_bw2_vram;
268 optional_device<address_map_bank_device> m_type0space, m_type1space, m_type2space, m_type3space;
269 required_memory_region m_rom, m_idprom;
270 required_device<ram_device> m_ram;
271 required_device<am79c90_device> m_lance;
272
273 uint32_t tl_mmu_r(offs_t offset, uint32_t mem_mask = ~0);
274 void tl_mmu_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
275 uint32_t ram_r(offs_t offset);
276 void ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
277 uint32_t parity_r(offs_t offset);
278 void parity_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
279 uint32_t ecc_r(offs_t offset);
280 void ecc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
281 uint32_t irqctrl_r();
282 void irqctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
283 uint8_t rtc7170_r(offs_t offset);
284 void rtc7170_w(offs_t offset, uint8_t data);
285
286 template <unsigned W, unsigned H>
287 uint32_t bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
288 uint32_t bw2_350_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
289
290 TIMER_DEVICE_CALLBACK_MEMBER(sun3_timer);
291
292 void sun3_mem(address_map &map);
293 void vmetype0space_map(address_map &map);
294 void vmetype0space_novram_map(address_map &map);
295 void vmetype1space_map(address_map &map);
296 void vmetype2space_map(address_map &map);
297 void vmetype3space_map(address_map &map);
298
299 uint32_t *m_rom_ptr, *m_ram_ptr;
300 uint8_t *m_idprom_ptr;
301 uint32_t m_enable, m_diag, m_dvma_enable, m_parregs[8], m_irqctrl, m_ecc[4];
302 uint8_t m_buserr;
303
304 uint32_t m_context;
305 uint8_t m_segmap[8][2048];
306 uint32_t m_pagemap[4096];
307 uint32_t m_ram_size, m_ram_size_words;
308 bool m_bInBusErr;
309
310 uint32_t m_cache_tags[0x4000], m_cache_data[0x4000];
311 };
312
sun_cdrom(device_t * device)313 static void sun_cdrom(device_t *device)
314 {
315 downcast<nscsi_cdrom_device &>(*device).set_block_size(512);
316 }
317
ncr5380(device_t * device)318 void sun3_state::ncr5380(device_t *device)
319 {
320 devcb_base *devcb;
321 (void)devcb;
322 // downcast<ncr5380n_device &>(*device).drq_handler().set(FUNC(sun3_state::drq_w));
323 }
324
scsi_devices(device_slot_interface & device)325 static void scsi_devices(device_slot_interface &device)
326 {
327 device.option_add("cdrom", NSCSI_CDROM);
328 device.option_add("harddisk", NSCSI_HARDDISK);
329 device.option_add_internal("ncr5380", NCR5380N);
330 device.set_option_machine_config("cdrom", sun_cdrom);
331 }
332
ram_r(offs_t offset)333 uint32_t sun3_state::ram_r(offs_t offset)
334 {
335 if (m_ecc[0] == 0x10c00000)
336 {
337 //printf("ECC testing, RAM read ofs %x\n", offset);
338 m_ecc[1] &= 0x00ffffff;
339
340 if (m_ecc[2] == 0x01000000) // single-bit error test
341 {
342 m_ecc[1] |= 0x8f000000; // put in the syndrome code the first ECC test wants
343
344 if (offset == 0)
345 {
346 return 0x80000000;
347 }
348 }
349 else if (m_ecc[2] == 0x01000200) // double-bit error test
350 {
351 m_ecc[1] |= 0xfc000000;
352 }
353 }
354
355 if (offset < m_ram_size_words) return m_ram_ptr[offset];
356
357 if (!m_bInBusErr)
358 {
359 //printf("ram_r: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc());
360 //fflush(stdout);
361 m_buserr = BE_TIMEOUT;
362 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
363 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
364 }
365
366 return 0xffffffff;
367 }
368
ram_w(offs_t offset,uint32_t data,uint32_t mem_mask)369 void sun3_state::ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
370 {
371 // if writing bad parity is enabled
372 if (((m_parregs[0] & 0x20000000) == 0x20000000) &&
373 (m_irqctrl & 0x01000000) &&
374 !(m_bInBusErr))
375 {
376 m_parregs[1] = offset<<2;
377 //printf("Generating parity error, mem_mask %08x\n", mem_mask);
378 switch (mem_mask)
379 {
380 case 0xff000000:
381 m_parregs[0] |= 0x08<<24;
382 break;
383
384 case 0x00ff0000:
385 m_parregs[1] += 1;
386 m_parregs[0] |= 0x04<<24;
387 break;
388
389 case 0x0000ff00:
390 m_parregs[1] += 2;
391 m_parregs[0] |= 0x02<<24;
392 break;
393
394 case 0x000000ff:
395 m_parregs[1] += 3;
396 m_parregs[0] |= 0x01<<24;
397 break;
398
399 case 0x0000ffff:
400 m_parregs[1] += 2;
401 m_parregs[0] |= 0x03<<24;
402 break;
403
404 case 0xffff0000:
405 m_parregs[0] |= 0x0c<<24;
406 break;
407
408 case 0xffffffff: // no address adjust, show all 4 lanes as problematic
409 m_parregs[0] |= 0x0f<<24;
410 break;
411 }
412
413 // indicate parity interrupt
414 m_parregs[0] |= 0x80000000;
415
416 // and can we take that now?
417 if (m_parregs[0] & 0x40000000)
418 {
419 m_bInBusErr = true; // prevent recursion
420 m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE);
421 }
422 }
423
424 if (offset < m_ram_size_words)
425 {
426 COMBINE_DATA(&m_ram_ptr[offset]);
427 return;
428 }
429
430 if (!m_bInBusErr)
431 {
432 //printf("ram_w: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc());
433 fflush(stdout);
434 m_buserr = BE_TIMEOUT;
435 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
436 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
437 }
438 }
439
tl_mmu_r(offs_t offset,uint32_t mem_mask)440 uint32_t sun3_state::tl_mmu_r(offs_t offset, uint32_t mem_mask)
441 {
442 uint8_t fc = m_maincpu->get_fc();
443
444 if ((fc == 3) && !machine().side_effects_disabled())
445 {
446 int page;
447
448 switch (offset >> 26)
449 {
450 case 0: // IDPROM
451 //printf("sun3: Read IDPROM at %x (mask %08x)\n", offset, mem_mask);
452 return m_idprom_ptr[(offset*4)] << 24 | m_idprom_ptr[(offset*4)+1]<<16 | m_idprom_ptr[(offset*4)+2]<<8 | m_idprom_ptr[(offset*4)+3];
453
454 case 1: // page map
455 page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
456 page += (offset >> 11) & 0xf;
457 //printf("sun3: Read page map at %x (entry %d)\n", offset<<1, page);
458 return m_pagemap[page];
459
460 case 2: // segment map
461 //printf("sun3: Read segment map at %x (entry %d, user ctx %d mask %x)\n", offset<<2, (offset & ~0x3c000000) >> 15, m_context & 7, mem_mask);
462 return m_segmap[m_context & 7][(offset >> 15) & 0x7ff]<<24;
463
464 case 3: // context reg
465 //printf("sun3: Read context reg\n");
466 return m_context<<24;
467
468 case 4: // enable reg
469 return m_enable;
470
471 case 5: // DVMA enable
472 return m_dvma_enable<<24;
473
474 case 6: // bus error
475 m_bInBusErr = false;
476 //printf("Reading bus error: %02x\n", m_buserr);
477 return m_buserr<<24;
478
479 case 7: // diagnostic reg
480 return 0;
481
482 case 8: // cache tags
483 //printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc());
484 return m_cache_tags[(offset & 0x3fff) >> 2];
485
486 case 9: // cache data
487 //printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc());
488 return m_cache_data[(offset & 0x3fff)];
489
490 case 10: // flush cache
491 return 0xffffffff;
492
493 case 11: // block copy
494 printf("sun3: read block copy @ %x, PC = %x\n", offset, m_maincpu->pc());
495 return 0xffffffff;
496
497 case 15: // UART bypass
498 //printf("sun3: read UART bypass @ %x, PC = %x, mask = %08x\n", offset, m_maincpu->pc(), mem_mask);
499 return 0xffffffff;
500 }
501 }
502
503 // boot mode?
504 if ((fc == M68K_FC_SUPERVISOR_PROGRAM) && !(m_enable & 0x80))
505 {
506 return m_rom_ptr[offset & 0x3fff];
507 }
508
509 // debugger hack
510 if (machine().side_effects_disabled() && (offset >= (0xfef0000>>2)) && (offset <= (0xfefffff>>2)))
511 {
512 return m_rom_ptr[offset & 0x3fff];
513 }
514
515 // it's translation time
516 uint8_t pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
517 uint32_t entry = (pmeg << 4) + ((offset >> 11) & 0xf);
518
519 //printf("sun3: Context = %d, pmeg = %d, offset >> 15 = %x, entry = %d, page = %d\n", m_context&7, pmeg, (offset >> 15) & 0x7ff, entry, (offset >> 11) & 0xf);
520
521 if (m_pagemap[entry] & PM_VALID)
522 {
523 if ((m_pagemap[entry] & PM_SYSMASK) && (fc < M68K_FC_SUPERVISOR_DATA))
524 {
525 m_buserr = BE_PROTERR;
526 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
527 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
528 m_bInBusErr = true;
529 return 0xffffffff;
530 }
531
532 m_pagemap[entry] |= PM_ACCESSED;
533
534 uint32_t tmp = (m_pagemap[entry] & 0x7ffff) << 11;
535 tmp |= (offset & 0x7ff);
536
537 //printf("pmeg %d, entry %d = %08x, virt %08x => tmp %08x\n", pmeg, entry, m_pagemap[entry], offset << 2, tmp);
538
539 // if (!machine().side_effects_disabled())
540 //printf("sun3: Translated addr: %08x, type %d (page %d page entry %08x, orig virt %08x, FC %d)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, entry, m_pagemap[entry], offset<<2, fc);
541
542 switch ((m_pagemap[entry] >> 26) & 3)
543 {
544 case 0: // type 0 space
545 return m_type0space->read32(tmp, mem_mask);
546
547 case 1: // type 1 space
548 // magic ROM bypass
549 if ((tmp >= (0x100000>>2)) && (tmp <= (0x10ffff>>2)))
550 {
551 return m_rom_ptr[offset & 0x3fff];
552 }
553 return m_type1space->read32(tmp, mem_mask);
554
555 case 2: // type 2 space
556 return m_type2space->read32(tmp, mem_mask);
557
558 case 3: // type 3 space
559 return m_type3space->read32(tmp, mem_mask);
560 }
561 }
562 else
563 {
564 // if (!machine().side_effects_disabled()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc());
565 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
566 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
567 m_buserr = BE_INVALID;
568 m_bInBusErr = true;
569 return 0xffffffff;
570 }
571
572 if (!machine().side_effects_disabled()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc(), offset>>15);
573
574 return 0xffffffff;
575 }
576
tl_mmu_w(offs_t offset,uint32_t data,uint32_t mem_mask)577 void sun3_state::tl_mmu_w(offs_t offset, uint32_t data, uint32_t mem_mask)
578 {
579 uint8_t fc = m_maincpu->get_fc();
580
581 //printf("sun3: Write %08x (FC %d, mask %08x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc(), offset<<1);
582
583 if (fc == 3) // control space
584 {
585 int page;
586
587 switch (offset >> 26)
588 {
589 case 0: // IDPROM
590 return;
591
592 case 1: // page map fefaf32
593 page = m_segmap[m_context & 7][(offset >> 15) & 0x7ff] << 4;
594 //printf("context = %d, segment = %d, PMEG = %d, add = %d\n", m_context & 7, (offset >> 15) & 0x7ff, page, (offset >> 11) & 0xf);
595 page += (offset >> 11) & 0xf;
596
597 //printf("sun3: Write %04x to page map at %x (entry %d), ", data, offset<<2, page);
598 COMBINE_DATA(&m_pagemap[page]);
599
600 //printf("entry now %08x (adr %08x PC=%x mask %x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 13, m_maincpu->pc(), mem_mask);
601 return;
602
603 case 2: // segment map
604 //printf("sun3: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x mask %x)\n", (data>>24) & 0xff, offset<<2, (offset & ~0x3c000000)>>15, m_context & 7, m_maincpu->pc(), mem_mask);
605 m_segmap[m_context & 7][(offset >> 15) & 0x7ff] = (data>>24) & 0xff;
606 //printf("segment map[%d][%d] now %x\n", m_context & 7, (offset & ~0x3c000000) >> 15, m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15] = (data>>24) & 0xff);
607 return;
608
609 case 3: // context reg
610 //printf("sun3: Write (%x) %x to context\n", data, data>>24);
611 m_context = data >> 24;
612 return;
613
614 case 4: // enable reg
615 //printf("sun3: Write %x to enable, PC=%x\n", data, m_maincpu->pc());
616 COMBINE_DATA(&m_enable);
617 return;
618
619 case 5: // DVMA enable
620 m_dvma_enable = data>>24;
621 return;
622
623 case 6: // bus error (read-only)
624 return;
625
626 case 7: // diagnostic reg
627 m_diag = data >> 24;
628 #if 0
629 printf("sun3: CPU LEDs to %02x (PC=%x) => ", ((data>>24) & 0xff) ^ 0xff, m_maincpu->pc());
630 for (int i = 0; i < 8; i++)
631 {
632 if (m_diag & (1<<i))
633 {
634 printf(".");
635 }
636 else
637 {
638 printf("*");
639 }
640 }
641 printf("\n");
642 #endif
643 return;
644
645 case 8: // cache tags
646 //printf("sun3: %08x to cache tags @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc(), mem_mask);
647 m_cache_tags[(offset & 0x3fff) >> 2] = data;
648 return;
649
650 case 9: // cache data
651 //printf("sun3: %08x to cache data @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc(), mem_mask);
652 m_cache_data[(offset & 0x3fff)] = data;
653 return;
654
655 case 10: // flush cache
656 return;
657
658 case 11: // block copy
659 printf("sun3: %08x to block copy @ %x, PC = %x\n", data, offset, m_maincpu->pc());
660 return;
661
662 case 15: // UART bypass
663 //printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc());
664 return;
665 }
666 }
667
668 // it's translation time
669 uint8_t pmeg = m_segmap[m_context & 7][(offset >> 15) & 0x7ff];
670 uint32_t entry = (pmeg << 4) + ((offset >> 11) & 0xf);
671
672 if (m_pagemap[entry] & PM_VALID)
673 {
674 if ((!(m_pagemap[entry] & PM_WRITEMASK)) ||
675 ((m_pagemap[entry] & PM_SYSMASK) && (fc < M68K_FC_SUPERVISOR_DATA)))
676 {
677 //printf("sun3: write protect MMU error (PC=%x)\n", m_maincpu->pc());
678 m_buserr = BE_PROTERR;
679 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
680 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
681 m_bInBusErr = true;
682 return;
683 }
684
685 m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED);
686
687 uint32_t tmp = (m_pagemap[entry] & 0x7ffff) << 11;
688 tmp |= (offset & 0x7ff);
689
690 //if (!machine().side_effects_disabled()) printf("sun3: Translated addr: %08x, type %d (page entry %08x, orig virt %08x)\n", tmp << 2, (m_pagemap[entry] >> 26) & 3, m_pagemap[entry], offset<<2);
691
692 switch ((m_pagemap[entry] >> 26) & 3)
693 {
694 case 0: // type 0
695 m_type0space->write32(tmp, data, mem_mask);
696 return;
697
698 case 1: // type 1
699 //printf("write device space @ %x\n", tmp<<1);
700 m_type1space->write32(tmp, data, mem_mask);
701 return;
702
703 case 2: // type 2
704 m_type2space->write32(tmp, data, mem_mask);
705 return;
706
707 case 3: // type 3
708 m_type3space->write32(tmp, data, mem_mask);
709 return;
710 }
711 }
712 else
713 {
714 //if (!machine().side_effects_disabled()) printf("sun3: pagemap entry not valid!\n");
715 m_buserr = BE_INVALID;
716 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
717 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
718 m_bInBusErr = true;
719 return;
720 }
721
722 logerror("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc(), offset<<2);
723 }
724
parity_r(offs_t offset)725 uint32_t sun3_state::parity_r(offs_t offset)
726 {
727 uint32_t rv = m_parregs[offset];
728
729 if (offset == 0) // clear interrupt if any
730 {
731 m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
732 m_parregs[offset] &= ~0x8f000000;
733 }
734
735 return rv;
736 }
737
parity_w(offs_t offset,uint32_t data,uint32_t mem_mask)738 void sun3_state::parity_w(offs_t offset, uint32_t data, uint32_t mem_mask)
739 {
740 //printf("sun3: %08x to parity registers @ %x (mask %08x)\n", data, offset, mem_mask);
741
742 if (offset == 0)
743 {
744 m_parregs[0] &= 0x8f000000;
745
746 if ((m_parregs[0] & 0x80000000) && (data & 0x40000000))
747 {
748 m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE);
749 }
750
751 m_parregs[0] |= (data & 0x70000000);
752 }
753 else
754 {
755 COMBINE_DATA(&m_parregs[offset]);
756 }
757 }
758
sun3_mem(address_map & map)759 void sun3_state::sun3_mem(address_map &map)
760 {
761 map(0x00000000, 0xffffffff).rw(FUNC(sun3_state::tl_mmu_r), FUNC(sun3_state::tl_mmu_w));
762 }
763
764 // type 0 device space
vmetype0space_map(address_map & map)765 void sun3_state::vmetype0space_map(address_map &map)
766 {
767 map(0x00000000, 0x08ffffff).rw(FUNC(sun3_state::ram_r), FUNC(sun3_state::ram_w));
768 map(0xfe400000, 0xfe41ffff).ram(); // not sure what's going on here (3/110)
769 map(0xff000000, 0xff03ffff).ram().share("bw2_vram");
770 }
771
772 // type 0 without VRAM (3/50)
vmetype0space_novram_map(address_map & map)773 void sun3_state::vmetype0space_novram_map(address_map &map)
774 {
775 map(0x00000000, 0x08ffffff).rw(FUNC(sun3_state::ram_r), FUNC(sun3_state::ram_w));
776 }
777
778 // type 1 device space
vmetype1space_map(address_map & map)779 void sun3_state::vmetype1space_map(address_map &map)
780 {
781 map(0x00000000, 0x0000000f).rw(m_scc1, FUNC(z80scc_device::ab_dc_r), FUNC(z80scc_device::ab_dc_w)).umask32(0xff00ff00);
782 map(0x00020000, 0x0002000f).rw(m_scc2, FUNC(z80scc_device::ab_dc_r), FUNC(z80scc_device::ab_dc_w)).umask32(0xff00ff00);
783 map(0x00040000, 0x000407ff).ram().share("nvram"); // type 2816 parallel EEPROM
784 map(0x00060000, 0x0006ffff).rw(FUNC(sun3_state::rtc7170_r), FUNC(sun3_state::rtc7170_w));
785 map(0x00080000, 0x0008000f).rw(FUNC(sun3_state::parity_r), FUNC(sun3_state::parity_w));
786 map(0x000a0000, 0x000a0003).rw(FUNC(sun3_state::irqctrl_r), FUNC(sun3_state::irqctrl_w));
787 map(0x00100000, 0x0010ffff).rom().region("user1", 0);
788 map(0x00120000, 0x00120003).rw(m_lance, FUNC(am79c90_device::regs_r), FUNC(am79c90_device::regs_w));
789 map(0x00140000, 0x00140007).rw(m_scsi, FUNC(ncr5380n_device::read), FUNC(ncr5380n_device::write)).umask32(0xffffffff);
790 map(0x001e0000, 0x001e00ff).rw(FUNC(sun3_state::ecc_r), FUNC(sun3_state::ecc_w));
791 }
792
793 // type 2 device space
vmetype2space_map(address_map & map)794 void sun3_state::vmetype2space_map(address_map &map)
795 {
796 }
797
798 // type 3 device space
vmetype3space_map(address_map & map)799 void sun3_state::vmetype3space_map(address_map &map)
800 {
801 }
802
irqctrl_r()803 uint32_t sun3_state::irqctrl_r()
804 {
805 return m_irqctrl;
806 }
807
irqctrl_w(offs_t offset,uint32_t data,uint32_t mem_mask)808 void sun3_state::irqctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
809 {
810 //printf("sun3: %08x to interrupt control (mask %08x)\n", data, mem_mask);
811 COMBINE_DATA(&m_irqctrl);
812
813 if (data & 0x01000000)
814 {
815 if (data & 0x02000000)
816 {
817 m_maincpu->set_input_line(M68K_IRQ_1, ASSERT_LINE);
818 }
819 if (data & 0x04000000)
820 {
821 m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
822 }
823 if (data & 0x08000000)
824 {
825 m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
826 }
827 }
828 else // master enable clear, clear all interrupts
829 {
830 m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
831 m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
832 m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
833 m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
834 m_maincpu->set_input_line(M68K_IRQ_5, CLEAR_LINE);
835 m_maincpu->set_input_line(M68K_IRQ_6, CLEAR_LINE);
836 m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
837 }
838 }
839
rtc7170_r(offs_t offset)840 uint8_t sun3_state::rtc7170_r(offs_t offset)
841 {
842 //printf("read 7170 @ %x, PC=%x\n", offset, m_maincpu->pc());
843
844 return 0xff;
845 }
846
rtc7170_w(offs_t offset,uint8_t data)847 void sun3_state::rtc7170_w(offs_t offset, uint8_t data)
848 {
849 //printf("%02x to 7170 @ %x\n", data, offset);
850
851 if ((offset == 0x11) && (data == 0x1c))
852 {
853 if ((m_irqctrl & 0x21000000) == 0x21000000)
854 {
855 m_maincpu->set_input_line(M68K_IRQ_5, ASSERT_LINE);
856 }
857 }
858 }
859
ecc_r(offs_t offset)860 uint32_t sun3_state::ecc_r(offs_t offset)
861 {
862 //printf("read ECC @ %x, PC=%x\n", offset, m_maincpu->pc());
863 // fefc34a
864 int mbram = (m_ram_size / (1024*1024));
865 int beoff = (mbram / 32) * 0x10;
866
867 //printf("offset %x MB %d beoff %x\n", offset, mbram, beoff);
868
869 if (offset >= beoff)
870 {
871 m_buserr = BE_TIMEOUT;
872 m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
873 m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
874 }
875
876 uint32_t rv = m_ecc[offset & 0xf];
877
878 if ((offset & 0xf) == 0) rv |= 0x06000000; // indicate each ECC board is 32MB, for 128MB total
879
880 return rv;
881 }
882
ecc_w(offs_t offset,uint32_t data,uint32_t mem_mask)883 void sun3_state::ecc_w(offs_t offset, uint32_t data, uint32_t mem_mask)
884 {
885 //printf("%08x to ecc @ %x, mask %08x\n", data, offset, mem_mask);
886
887 offset &= 0xf;
888 m_ecc[offset] = data;
889 }
890
TIMER_DEVICE_CALLBACK_MEMBER(sun3_state::sun3_timer)891 TIMER_DEVICE_CALLBACK_MEMBER(sun3_state::sun3_timer)
892 {
893 if ((m_irqctrl & 0x81000000) == 0x81000000)
894 {
895 //printf("NMI tick\n");
896 m_maincpu->set_input_line(M68K_IRQ_7, CLEAR_LINE);
897 m_maincpu->set_input_line(M68K_IRQ_7, ASSERT_LINE);
898 }
899 }
900
901 template <unsigned W, unsigned H>
bw2_update(screen_device & screen,bitmap_rgb32 & bitmap,const rectangle & cliprect)902 uint32_t sun3_state::bw2_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
903 {
904 static const uint32_t palette[2] = { 0, 0xffffff };
905 uint8_t const *const m_vram = (uint8_t *)m_bw2_vram.target();
906
907 for (int y = 0; y < H; y++)
908 {
909 uint32_t *scanline = &bitmap.pix(y);
910 for (int x = 0; x < W/8; x++)
911 {
912 uint8_t const pixels = m_vram[(y * (W/8)) + (BYTE4_XOR_BE(x))];
913
914 *scanline++ = palette[BIT(pixels, 7)];
915 *scanline++ = palette[BIT(pixels, 6)];
916 *scanline++ = palette[BIT(pixels, 5)];
917 *scanline++ = palette[BIT(pixels, 4)];
918 *scanline++ = palette[BIT(pixels, 3)];
919 *scanline++ = palette[BIT(pixels, 2)];
920 *scanline++ = palette[BIT(pixels, 1)];
921 *scanline++ = palette[BIT(pixels, 0)];
922 }
923 }
924 return 0;
925 }
926
bw2_350_update(screen_device & screen,bitmap_rgb32 & bitmap,const rectangle & cliprect)927 uint32_t sun3_state::bw2_350_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
928 {
929 static const uint32_t palette[2] = { 0, 0xffffff };
930 uint8_t const *const m_vram = (uint8_t *)&m_ram_ptr[(0x100000>>2)];
931
932 for (int y = 0; y < 900; y++)
933 {
934 uint32_t *scanline = &bitmap.pix(y);
935 for (int x = 0; x < 1152/8; x++)
936 {
937 uint8_t const pixels = m_vram[(y * (1152/8)) + (BYTE4_XOR_BE(x))];
938
939 *scanline++ = palette[BIT(pixels, 7)];
940 *scanline++ = palette[BIT(pixels, 6)];
941 *scanline++ = palette[BIT(pixels, 5)];
942 *scanline++ = palette[BIT(pixels, 4)];
943 *scanline++ = palette[BIT(pixels, 3)];
944 *scanline++ = palette[BIT(pixels, 2)];
945 *scanline++ = palette[BIT(pixels, 1)];
946 *scanline++ = palette[BIT(pixels, 0)];
947 }
948 }
949 return 0;
950 }
951
952 /* Input ports */
INPUT_PORTS_START(sun3)953 static INPUT_PORTS_START( sun3 )
954 INPUT_PORTS_END
955
956 void sun3_state::machine_start()
957 {
958 m_rom_ptr = (uint32_t *)m_rom->base();
959 m_ram_ptr = (uint32_t *)m_ram->pointer();
960 m_idprom_ptr = (uint8_t *)m_idprom->base();
961 m_ram_size = m_ram->size();
962 m_ram_size_words = m_ram_size >> 2;
963 }
964
machine_reset()965 void sun3_state::machine_reset()
966 {
967 m_enable = 0;
968 m_buserr = 0;
969 m_diag = 1;
970 m_dvma_enable = 0;
971 m_irqctrl = 0;
972 m_bInBusErr = false;
973 }
974
975 // The base Sun 3004 CPU board
sun3(machine_config & config)976 void sun3_state::sun3(machine_config &config)
977 {
978 /* basic machine hardware */
979 M68020(config, m_maincpu, 16670000);
980 m_maincpu->set_addrmap(AS_PROGRAM, &sun3_state::sun3_mem);
981
982 screen_device &bwtwo(SCREEN(config, "bwtwo", SCREEN_TYPE_RASTER));
983 bwtwo.set_screen_update(NAME((&sun3_state::bw2_update<1152, 900>)));
984 bwtwo.set_size(1600,1100);
985 bwtwo.set_visarea(0, 1152-1, 0, 900-1);
986 bwtwo.set_refresh_hz(72);
987
988 RAM(config, m_ram).set_default_size("4M").set_extra_options("6M,8M,12M,16M,20M,24M,28M,32M").set_default_value(0x00);
989
990 NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
991
992 // MMU Type 0 device space
993 ADDRESS_MAP_BANK(config, "type0").set_map(&sun3_state::vmetype0space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
994
995 // MMU Type 1 device space
996 ADDRESS_MAP_BANK(config, "type1").set_map(&sun3_state::vmetype1space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
997
998 // MMU Type 2 device space
999 ADDRESS_MAP_BANK(config, "type2").set_map(&sun3_state::vmetype2space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
1000
1001 // MMU Type 3 device space
1002 ADDRESS_MAP_BANK(config, "type3").set_map(&sun3_state::vmetype3space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
1003
1004 TIMER(config, "timer").configure_periodic(FUNC(sun3_state::sun3_timer), attotime::from_hz(100));
1005
1006 SCC8530N(config, m_scc1, 4.9152_MHz_XTAL);
1007 m_scc1->out_txda_callback().set(KEYBOARD_TAG, FUNC(sun_keyboard_port_device::write_txd));
1008 m_scc1->out_txdb_callback().set(MOUSE_TAG, FUNC(sun_mouse_port_device::write_txd));
1009
1010 SUNKBD_PORT(config, KEYBOARD_TAG, default_sun_keyboard_devices, "type3hle").rxd_handler().set(m_scc1, FUNC(z80scc_device::rxa_w));
1011
1012 SUNMOUSE_PORT(config, MOUSE_TAG, default_sun_mouse_devices, "hle1200").rxd_handler().set(m_scc1, FUNC(z80scc_device::rxb_w));
1013
1014 SCC8530N(config, m_scc2, 4.9152_MHz_XTAL);
1015 m_scc2->out_txda_callback().set(RS232A_TAG, FUNC(rs232_port_device::write_txd));
1016 m_scc2->out_txdb_callback().set(RS232B_TAG, FUNC(rs232_port_device::write_txd));
1017
1018 rs232_port_device &rs232a(RS232_PORT(config, RS232A_TAG, default_rs232_devices, nullptr));
1019 rs232a.rxd_handler().set(m_scc2, FUNC(z80scc_device::rxa_w));
1020 rs232a.dcd_handler().set(m_scc2, FUNC(z80scc_device::dcda_w));
1021 rs232a.cts_handler().set(m_scc2, FUNC(z80scc_device::ctsa_w));
1022
1023 rs232_port_device &rs232b(RS232_PORT(config, RS232B_TAG, default_rs232_devices, nullptr));
1024 rs232b.rxd_handler().set(m_scc2, FUNC(z80scc_device::rxb_w));
1025 rs232b.dcd_handler().set(m_scc2, FUNC(z80scc_device::dcdb_w));
1026 rs232b.cts_handler().set(m_scc2, FUNC(z80scc_device::ctsb_w));
1027
1028 AM79C90(config, m_lance, 10'000'000); // clock is a guess
1029
1030 NSCSI_BUS(config, "scsibus");
1031 NSCSI_CONNECTOR(config, "scsibus:0", scsi_devices, nullptr);
1032 NSCSI_CONNECTOR(config, "scsibus:1", scsi_devices, "harddisk");
1033 NSCSI_CONNECTOR(config, "scsibus:2", scsi_devices, nullptr);
1034 NSCSI_CONNECTOR(config, "scsibus:3", scsi_devices, nullptr);
1035 NSCSI_CONNECTOR(config, "scsibus:4", scsi_devices, nullptr);
1036 NSCSI_CONNECTOR(config, "scsibus:5", scsi_devices, nullptr);
1037 NSCSI_CONNECTOR(config, "scsibus:6", scsi_devices, "cdrom");
1038 NSCSI_CONNECTOR(config, "scsibus:7", scsi_devices, "ncr5380", true).set_option_machine_config("ncr5380", [this] (device_t *device) { ncr5380(device); });
1039 }
1040
1041 // Sun 3/60
sun3_60(machine_config & config)1042 void sun3_state::sun3_60(machine_config &config)
1043 {
1044 sun3(config);
1045 M68020(config.replace(), m_maincpu, 20000000);
1046 m_maincpu->set_addrmap(AS_PROGRAM, &sun3_state::sun3_mem);
1047
1048 screen_device &bwtwo(*subdevice<screen_device>("bwtwo"));
1049 bwtwo.set_screen_update(NAME((&sun3_state::bw2_update<1600, 1100>)));
1050 bwtwo.set_size(1600,1100);
1051 bwtwo.set_visarea(0, 1600-1, 0, 1100-1);
1052 bwtwo.set_refresh_hz(72);
1053 }
1054
1055 // Sun 3/E
sun3e(machine_config & config)1056 void sun3_state::sun3e(machine_config &config)
1057 {
1058 sun3(config);
1059
1060 M68020(config.replace(), m_maincpu, 20000000);
1061 m_maincpu->set_addrmap(AS_PROGRAM, &sun3_state::sun3_mem);
1062 }
1063
1064 // 3/260 and 3/280 (the Sun 3200 board)
sun3200(machine_config & config)1065 void sun3_state::sun3200(machine_config &config)
1066 {
1067 sun3(config);
1068 M68020(config.replace(), m_maincpu, 25000000);
1069 m_maincpu->set_addrmap(AS_PROGRAM, &sun3_state::sun3_mem);
1070
1071 screen_device &bwtwo(*subdevice<screen_device>("bwtwo"));
1072 bwtwo.set_screen_update(NAME((&sun3_state::bw2_update<1600, 1100>)));
1073 bwtwo.set_size(1600,1100);
1074 bwtwo.set_visarea(0, 1600-1, 0, 1100-1);
1075 bwtwo.set_refresh_hz(72);
1076
1077 m_ram->set_default_size("32M").set_extra_options("64M,96M,128M");
1078 }
1079
sun3_50(machine_config & config)1080 void sun3_state::sun3_50(machine_config &config)
1081 {
1082 /* basic machine hardware */
1083 M68020(config, m_maincpu, 15700000);
1084 m_maincpu->set_addrmap(AS_PROGRAM, &sun3_state::sun3_mem);
1085
1086 AM79C90(config, m_lance, 10'000'000); // clock is a guess
1087
1088 screen_device &bwtwo(SCREEN(config, "bwtwo", SCREEN_TYPE_RASTER));
1089 bwtwo.set_screen_update(FUNC(sun3_state::bw2_350_update));
1090 bwtwo.set_size(1600,1100);
1091 bwtwo.set_visarea(0, 1152-1, 0, 900-1);
1092 bwtwo.set_refresh_hz(72);
1093
1094 NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
1095
1096 TIMER(config, "timer").configure_periodic(FUNC(sun3_state::sun3_timer), attotime::from_hz(100));
1097
1098 RAM(config, m_ram).set_default_size("4M").set_default_value(0x00);
1099
1100 // MMU Type 0 device space
1101 ADDRESS_MAP_BANK(config, "type0").set_map(&sun3_state::vmetype0space_novram_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
1102
1103 // MMU Type 1 device space
1104 ADDRESS_MAP_BANK(config, "type1").set_map(&sun3_state::vmetype1space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
1105
1106 // MMU Type 2 device space
1107 ADDRESS_MAP_BANK(config, "type2").set_map(&sun3_state::vmetype2space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
1108
1109 // MMU Type 3 device space
1110 ADDRESS_MAP_BANK(config, "type3").set_map(&sun3_state::vmetype3space_map).set_options(ENDIANNESS_BIG, 32, 32, 0x80000000);
1111
1112 SCC8530N(config, m_scc1, 4.9152_MHz_XTAL);
1113 m_scc1->out_txda_callback().set(KEYBOARD_TAG, FUNC(sun_keyboard_port_device::write_txd));
1114 m_scc1->out_txdb_callback().set(MOUSE_TAG, FUNC(sun_mouse_port_device::write_txd));
1115
1116 SUNKBD_PORT(config, KEYBOARD_TAG, default_sun_keyboard_devices, "type3hle").rxd_handler().set(m_scc1, FUNC(z80scc_device::rxa_w));
1117
1118 SUNMOUSE_PORT(config, MOUSE_TAG, default_sun_mouse_devices, "hle1200").rxd_handler().set(m_scc1, FUNC(z80scc_device::rxb_w));
1119
1120 SCC8530N(config, m_scc2, 4.9152_MHz_XTAL);
1121 m_scc2->out_txda_callback().set(RS232A_TAG, FUNC(rs232_port_device::write_txd));
1122 m_scc2->out_txdb_callback().set(RS232B_TAG, FUNC(rs232_port_device::write_txd));
1123
1124 rs232_port_device &rs232a(RS232_PORT(config, RS232A_TAG, default_rs232_devices, nullptr));
1125 rs232a.rxd_handler().set(m_scc2, FUNC(z80scc_device::rxa_w));
1126 rs232a.dcd_handler().set(m_scc2, FUNC(z80scc_device::dcda_w));
1127 rs232a.cts_handler().set(m_scc2, FUNC(z80scc_device::ctsa_w));
1128
1129 rs232_port_device &rs232b(RS232_PORT(config, RS232B_TAG, default_rs232_devices, nullptr));
1130 rs232b.rxd_handler().set(m_scc2, FUNC(z80scc_device::rxb_w));
1131 rs232b.dcd_handler().set(m_scc2, FUNC(z80scc_device::dcdb_w));
1132 rs232b.cts_handler().set(m_scc2, FUNC(z80scc_device::ctsb_w));
1133
1134 NSCSI_BUS(config, "scsibus");
1135 NSCSI_CONNECTOR(config, "scsibus:0", scsi_devices, nullptr);
1136 NSCSI_CONNECTOR(config, "scsibus:1", scsi_devices, "harddisk");
1137 NSCSI_CONNECTOR(config, "scsibus:2", scsi_devices, nullptr);
1138 NSCSI_CONNECTOR(config, "scsibus:3", scsi_devices, nullptr);
1139 NSCSI_CONNECTOR(config, "scsibus:4", scsi_devices, nullptr);
1140 NSCSI_CONNECTOR(config, "scsibus:5", scsi_devices, nullptr);
1141 NSCSI_CONNECTOR(config, "scsibus:6", scsi_devices, "cdrom");
1142 NSCSI_CONNECTOR(config, "scsibus:7", scsi_devices, "ncr5380", true).set_option_machine_config("ncr5380", [this] (device_t *device) { ncr5380(device); });
1143 }
1144
1145 /* ROM definition */
1146
1147 ROM_START( sun3_50 )
1148 ROM_REGION32_BE( 0x10000, "user1", ROMREGION_ERASEFF )
1149 /*
1150 Sun 3/50 V1.2 Bootprom
1151 Sun 3/50 V1.4 Bootprom
1152 Sun 3/50 V1.6 Bootprom
1153 Sun 3/50 V1.8 Bootprom (Req. to load SunOS QIC-24 1/4" tapes)
1154 Sun 3/50 V2.0 Bootprom
1155 Sun 3/50 V2.1 Bootprom
1156 Sun 3/50 V2.3 Bootprom
1157 Sun 3/50 V2.5 Bootprom (Req. to load SunOS QIC-24 1/4" tapes from a Sun-2 Shoebox)
1158 Sun 3/50 V2.6 Bootprom
1159 Sun 3/50 V2.7 Bootprom
1160 Sun 3/50 V2.8 Bootprom
1161 */
1162 ROM_SYSTEM_BIOS(0, "rev28", "Rev 2.8")
1163 ROMX_LOAD( "sun3_50_v2.8", 0x0000, 0x10000, CRC(1ca6b0e8) SHA1(5773ac1c46399501d29d1758aa342862b03ec472), ROM_BIOS(0))
1164 ROM_SYSTEM_BIOS(1, "rev27", "Rev 2.7")
1165 ROMX_LOAD( "sun3_50_v2.7", 0x0000, 0x10000, CRC(7c4a9e20) SHA1(6dcd4883a170538050fd0e1f151fae413ec9ea52), ROM_BIOS(1))
1166 ROM_SYSTEM_BIOS(2, "rev26", "Rev 2.6")
1167 ROMX_LOAD( "sun3_50_v2.6", 0x0000, 0x10000, CRC(08abbb3b) SHA1(6bfb8d5c97d801cd7bb7d564de0e68a48fb807c4), ROM_BIOS(2))
1168 ROM_SYSTEM_BIOS(3, "rev23", "Rev 2.3")
1169 ROMX_LOAD( "sun3_50_v2.3", 0x0000, 0x10000, CRC(163500b3) SHA1(437c8d539e12d442ca6877566dbbe165d577fcab), ROM_BIOS(3))
1170 ROM_SYSTEM_BIOS(4, "rev16", "Rev 1.6")
1171 ROMX_LOAD( "sun3_50_v1.6", 0x0000, 0x10000, CRC(8be20826) SHA1(2a4d73fcb7fe0f0c83eb0f4c91d957b7bf88b7ed), ROM_BIOS(4))
1172
1173 ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
1174 ROM_LOAD( "sun3-50-idprom.bin", 0x000000, 0x000020, CRC(80610dbe) SHA1(0f37e31ed209b8905c5dc7c2663fa01a9b9baaba) )
1175 ROM_END
1176
1177 ROM_START( sun3_60 )
1178 ROM_REGION32_BE( 0x10000, "user1", ROMREGION_ERASEFF )
1179 /*
1180 Sun 3/60 V1.0 Bootprom
1181 Sun 3/60 V1.3 Bootprom
1182 Sun 3/60 V1.5 Bootprom
1183 Sun 3/60 V1.6 Bootprom (Req. to load SunOS QIC-24 1/4" tapes
1184 Sun 3/60 V1.9 Bootprom
1185 Sun 3/60 V2.8.3 Bootprom
1186 Sun 3/60 V3.0.1 Bootprom
1187 */
1188 ROM_SYSTEM_BIOS(0, "rev301", "Rev 3.0.1")
1189 ROMX_LOAD( "sun_3.60v3.0.1", 0x0000, 0x10000, CRC(e55dc1d8) SHA1(6e48414ce2139282e69f57612b20f7d5c475e74c), ROM_BIOS(0))
1190 ROM_SYSTEM_BIOS(1, "rev283", "Rev 2.8.3")
1191 ROMX_LOAD( "sun_3.60v2.8.3", 0x0000, 0x10000, CRC(de4ec54d) SHA1(e621a9c1a2a7df4975b12fa3a0d7f106383736ef), ROM_BIOS(1))
1192 ROM_SYSTEM_BIOS(2, "rev19", "Rev 1.9")
1193 ROMX_LOAD( "sun_3.60v1.9", 0x0000, 0x10000, CRC(32b6d3a9) SHA1(307756ba5698611d51059881057f8086956ce895), ROM_BIOS(2))
1194
1195 ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
1196 ROM_LOAD( "sun3-60-idprom.bin", 0x000000, 0x000020, CRC(117e766a) SHA1(f01547be0156bd4e06bbdee4c342d1b38c7646ae) )
1197 ROM_END
1198
1199 ROM_START( sun3_110 )
1200 ROM_REGION32_BE( 0x10000, "user1", ROMREGION_ERASEFF )
1201 /*
1202 Sun 3/110 V1.8 Bootprom
1203 Sun 3/110 V2.1 Bootprom
1204 Sun 3/110 V2.3 Bootprom
1205 Sun 3/110 V2.6 Bootprom
1206 Sun 3/110 V2.7 Bootprom
1207 Sun 3/110 V2.8 Bootprom
1208 Sun 3/110 V3.0 Bootprom
1209 */
1210 ROM_SYSTEM_BIOS(0, "rev30", "Rev 3.0")
1211 ROMX_LOAD( "sun3_110_v3.0", 0x0000, 0x10000, CRC(a193b26b) SHA1(0f54212ee3a5709f70e921069cca1ddb8c143b1b), ROM_BIOS(0))
1212
1213 ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
1214 ROM_LOAD( "sun3-110-idprom.bin", 0x000000, 0x000020, CRC(d6cd934a) SHA1(b0913708fe733250ef5c1289c10146dcef6d1a67) )
1215 ROM_END
1216
1217 ROM_START( sun3_150 )
1218 ROM_REGION32_BE( 0x10000, "user1", ROMREGION_ERASEFF )
1219 /*
1220 Sun 3/1[4,5,6,8]0 V1.3 Bootprom
1221 Sun 3/1[4,5,6,8]0 V1.4 Bootprom
1222 Sun 3/1[4,5,6,8]0 V1.5 Bootprom
1223 Sun 3/1[4,5,6,8]0 V1.8 Bootprom (Req. to load SunOS QIC-24 1/4" tapes)
1224 Sun 3/1[4,5,6,8]0 V2.1 Bootprom
1225 Sun 3/1[4,5,6,8]0 V2.1 Bootprom with Capricot Rimfire 3200/3400 support (b rf(0,0,0) works)
1226 Sun 3/1[4,5,6,8]0 V2.3 Bootprom
1227 Sun 3/1[4,5,6,8]0 V2.6 Bootprom (Req. to load SunOS QIC-24 1/4" tapes from a Sun-2 Shoebox and for Xylogics 7053)
1228 Sun 3/1[4,5,6,8]0 V2.7 Bootprom
1229 Sun 3/1[4,5,6,8]0 V2.8 Bootprom
1230 Sun 3/1[4,5,6,8]0 V2.8.4 Bootprom
1231 Sun 3/1[4,5,6,8]0 V3.0 Bootprom
1232 */
1233 ROM_SYSTEM_BIOS(0, "rev30", "Rev 3.0")
1234 ROMX_LOAD( "sun3_160_v3.0", 0x0000, 0x10000, CRC(fee6e4d6) SHA1(440d532e1848298dba0f043de710bb0b001fb675), ROM_BIOS(0))
1235 ROM_SYSTEM_BIOS(1, "rev284", "Rev 2.8.4")
1236 ROMX_LOAD( "sun3_160_v2.8.4", 0x0000, 0x10000, CRC(3befd013) SHA1(f642bb42200b794e6e32e2fe6c87d5c269c8656d), ROM_BIOS(1))
1237 ROM_SYSTEM_BIOS(2, "rev23", "Rev 2.3")
1238 ROMX_LOAD( "sun3_160_v2.3", 0x0000, 0x10000, CRC(09585745) SHA1(1de1725dd9e27f5a910989bbb5b51acfbdc1d70b), ROM_BIOS(2))
1239 ROM_SYSTEM_BIOS(3, "rev21rf", "Rev 2.1 RF")
1240 ROMX_LOAD( "sun3_160_v2.1_rf", 0x0000, 0x10000, CRC(5c7e9271) SHA1(5e4dbb50859a21f9e1d3e4a06c42494d13a9a8eb), ROM_BIOS(3))
1241 ROM_SYSTEM_BIOS(4, "rev15", "Rev 1.5")
1242 ROMX_LOAD( "sun3_160_v1.5", 0x0000, 0x10000, CRC(06daee37) SHA1(b9873cd48d78ad8e0c85d69966fc20c21cfc99aa), ROM_BIOS(4))
1243
1244
1245 ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
1246 ROM_LOAD( "sun3-150-idprom.bin", 0x000000, 0x000020, CRC(58956a93) SHA1(7334936dc945e05d63a94a33340e963a371672c9) )
1247 ROM_END
1248
1249 ROM_START( sun3_260 )
1250 ROM_REGION32_BE( 0x10000, "user1", ROMREGION_ERASEFF )
1251 /*
1252 Sun 3/260/280 V1.8 Bootprom
1253 Sun 3/260/280 V2.1 Bootprom ( 2x^G cause system to beep 'till reset)
1254 Sun 3/260/280 V2.3 Bootprom
1255 Sun 3/260/280 V2.6 Bootprom (Req. for Xylogics 7053)
1256 Sun 3/260/280 V2.7 Bootprom
1257 Sun 3/260/280 V2.8 Bootprom
1258 Sun 3/260/280 V2.8.4 Bootprom
1259 Sun 3/260/280 V3.0 Bootprom
1260 */
1261 ROM_SYSTEM_BIOS(0, "rev30", "Rev 3.0")
1262 ROMX_LOAD( "sun3_260_v3.0", 0x0000, 0x10000, CRC(f43ed1d3) SHA1(204880436bd087ede136f853610403d75e60bd75), ROM_BIOS(0))
1263 ROM_SYSTEM_BIOS(1, "rev27", "Rev 2.7")
1264 ROMX_LOAD( "sun3_260_v2.7", 0x0000, 0x10000, CRC(099fcaab) SHA1(4a5233c778676f48103bdd8bab03b4264686b4aa), ROM_BIOS(1))
1265 ROM_SYSTEM_BIOS(2, "rev26", "Rev 2.6")
1266 ROMX_LOAD( "sun3_260_v2.6", 0x0000, 0x10000, CRC(e8b17951) SHA1(e1fdef42670a349d99b0eca9c50c8566b8bb7c56), ROM_BIOS(2))
1267
1268 ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
1269 ROM_LOAD( "sun3-260-idprom.bin", 0x000000, 0x000020, CRC(d51794f3) SHA1(17930c773b6fe9a32819094ffaf69e5453d1ea4d) )
1270 ROM_END
1271
1272 ROM_START( sun3_e )
1273 ROM_REGION32_BE( 0x10000, "user1", ROMREGION_ERASEFF )
1274 ROM_SYSTEM_BIOS(0, "rev28", "Rev 3.2")
1275 ROMX_LOAD( "sun3_e.32", 0x0000, 0x10000, CRC(acedde7e) SHA1(1ab6ec28f4365a613a5e326c34cb37585c3f0ecc), ROM_BIOS(0))
1276
1277 ROM_REGION( 0x20, "idprom", ROMREGION_ERASEFF)
1278 ROM_LOAD( "sun3-e-idprom.bin", 0x000000, 0x000020, CRC(d1a92116) SHA1(4836f3188f2c3dd5ba49ab66e0b55caa6b1b1791) )
1279 ROM_END
1280
1281 // YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
1282 COMP( 198?, sun3_50, 0, 0, sun3_50, sun3, sun3_state, empty_init, "Sun Microsystems", "Sun 3/50", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // Model 25
1283 COMP( 1988, sun3_60, 0, 0, sun3_60, sun3, sun3_state, empty_init, "Sun Microsystems", "Sun 3/60", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // Ferrari
1284 COMP( 198?, sun3_110, 0, 0, sun3, sun3, sun3_state, empty_init, "Sun Microsystems", "Sun 3/110", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // Prism
1285 COMP( 1985, sun3_150, 0, 0, sun3, sun3, sun3_state, empty_init, "Sun Microsystems", "Sun 3/75/140/150/160/180", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // AKA Carrera
1286 COMP( 198?, sun3_260, 0, 0, sun3200, sun3, sun3_state, empty_init, "Sun Microsystems", "Sun 3/260/280", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // Prism
1287 COMP( 198?, sun3_e, 0, 0, sun3e, sun3, sun3_state, empty_init, "Sun Microsystems", "Sun 3/E", MACHINE_NOT_WORKING | MACHINE_NO_SOUND ) // Polaris
1288