1 // license:BSD-3-Clause
2 // copyright-holders:Angelo Salese, AJR
3 /***************************************************************************
4
5 Zenith Z-100
6
7 15/07/2011 Skeleton driver.
8
9 Commands:
10 Press DELETE to abort boot, then press H to list all the commands.
11
12 TODO:
13 - implement S-100 bus features;
14 - memory test hangs on the first pass;
15
16 ============================================================================
17
18 Z207A EQU 0B0H ; Z-207 disk controller base port
19 ; (See DEFZ207 to program controller)
20 Z217A EQU 0AEH ; Z-217 disk controller base port
21 ; (See DEFZ217 to program controller)
22 ZGRNSEG EQU 0E000H ; Segment of green video plane
23 ZREDSEG EQU 0D000H ; Segment of red video plane
24 ZBLUSEG EQU 0C000H ; Segment of blue video plane
25 ZVIDEO EQU 0D8H ; Video 68A21 port
26 ; PA0 -> enable red display
27 ; PA1 -> enable green display
28 ; PA2 -> enable blue display
29 ; PA3 -> not flash screen
30 ; PA4 -> not write multiple red
31 ; PA5 -> not write multiple green
32 ; PA6 -> not write multiple blue
33 ; PA7 -> disable video RAM
34 ; PB7-PB0 -> LA15-LA8
35 ; CA1 - not used
36 ; CA2 -> clear screen
37 ; CB1 - not used
38 ; CB2 -> value to write (0 or 1) on clear screen
39 ; (see DEF6821 to program the 6821)
40 ZCRTC EQU 0DCH ; Video 6845 CRT-C port
41 ; (see DEF6845 to program the 6845)
42 ZLPEN EQU 0DEH ; Light pen latch
43 ZLPEN_BIT EQU 00000111B ; Bit hit by pen
44 ZLPEN_ROW EQU 11110000B ; Row hit by pen
45 ZPIA EQU 0E0H ; Parallel printer plus light pen and
46 ; video vertical retrace 68A21 port
47 ; PA0 -> PDATA1
48 ; PA1 -> PDATA2
49 ; PA2 -> not STROBE
50 ; PA3 -> not INIT
51 ; PA4 <- VSYNC
52 ; PA5 -> clear VSYNC flip flop
53 ; PA6 <- light pen switch
54 ; PA7 -> clear light pen flip flop
55 ; PB0 <- BUSY
56 ; PB1 <- not ERROR
57 ; PB2 -> PDATA3
58 ; PB3 -> PDATA4
59 ; PB4 -> PDATA5
60 ; PB5 -> PDATA6
61 ; PB6 -> PDATA7
62 ; PB7 -> PDATA8
63 ; CA1 <- light pen hit (from flip flop)
64 ; CA2 <- VSYNC (from flip flop)
65 ; CB1 <- not ACKNLG
66 ; CB2 <- BUSY
67 ; (See DEF6821 to program the PIA)
68 ZTIMER EQU 0E4H ; Timer 8253 port
69 ZTIMEVAL EQU 2500 ; 100ms divide by N value
70 ; (See DEF8253 to program the 8253)
71 ZTIMERS EQU 0FBH ; Timer interrupt status port
72 ZTIMERS0 EQU 001H ; Timer 0 interrupt
73 ZTIMERS2 EQU 002H ; Timer 2 interrupt
74 ZSERA EQU 0E8H ; First 2661-2 serial port
75 ZSERB EQU 0ECH ; Second 2661-2 serial port
76 ; (See DEFEP2 to program 2661-2)
77 ZM8259A EQU 0F2H ; Master 8259A interrupt controller port
78 ZINTEI EQU 0 ; Parity error or S-100 pin 98 interrupt
79 ZINTPS EQU 1 ; Processor swap interrupt
80 ZINTTIM EQU 2 ; Timer interrupt
81 ZINTSLV EQU 3 ; Slave 8259A interrupt
82 ZINTSA EQU 4 ; Serial port A interrupt
83 ZINTSB EQU 5 ; Serial port B interrupt
84 ZINTKD EQU 6 ; Keyboard, Display, or Light pen interrupt
85 ZINTPP EQU 7 ; Parallel port interrupt
86 ; (See DEF8259A to program the 8259A)
87 ZM8259AI EQU 64 ; Base interrupt number for master
88 ZS8259A EQU 0F0H ; Secondary 8259A interrupt controller port
89 ZS8259AI EQU 72 ; Base interrupt number for slave
90 BIOSAI EQU ZS8259AI+8 ; Base of BIOS generated interrupts
91 ZKEYBRD EQU 0F4H ; Keyboard port
92 ZKEYBRDD EQU ZKEYBRD+0 ; Keyboard data port
93 ZKEYBRDC EQU ZKEYBRD+1 ; Keyboard command port
94 ZKEYRES EQU 0 ; Reset command
95 ZKEYARD EQU 1 ; Autorepeat on command
96 ZKEYARF EQU 2 ; Autorepeat off command
97 ZKEYKCO EQU 3 ; Key click on command
98 ZKEYKCF EQU 4 ; Key click off command
99 ZKEYCF EQU 5 ; Clear keyboard FIFO command
100 ZKEYCLK EQU 6 ; Generate a click sound command
101 ZKEYBEP EQU 7 ; Generate a beep sound command
102 ZKEYEK EQU 8 ; Enable keyboard command
103 ZKEYDK EQU 9 ; Disable keyboard command
104 ZKEYUDM EQU 10 ; Enter UP/DOWN mode command
105 ZKEYNSM EQU 11 ; Enter normal scan mode command
106 ZKEYEI EQU 12 ; Enable keyboard interrupts command
107 ZKEYDI EQU 13 ; Disable keyboard interrupts command
108 ZKEYBRDS EQU ZKEYBRD+1 ; Keyboard status port
109 ZKEYOBF EQU 001H ; Output buffer not empty
110 ZKEYIBF EQU 002H ; Input buffer full
111 ZMCL EQU 0FCH ; Memory control latch
112 ZMCLMS EQU 00000011B ; Map select mask
113 ZSM0 EQU 0 ; Map select 0
114 ZSM1 EQU 1 ; Map select 1
115 ZSM2 EQU 2 ; Map select 2
116 ZSM3 EQU 3 ; Map select 3
117 ZMCLRM EQU 00001100B ; Monitor ROM mapping mask
118 ZRM0 EQU 0*4 ; Power up mode - ROM everywhere on reads
119 ZRM1 EQU 1*4 ; ROM at top of every 64K page
120 ZRM2 EQU 2*4 ; ROM at top of 8088's addr space
121 ZRM3 EQU 3*4 ; Disable ROM
122 ZMCLPZ EQU 00010000B ; 0=Set Parity to the zero state
123 ZMCLPK EQU 00100000B ; 0=Disable parity checking circuity
124 ZMCLPF EQU 01000000B ; 0=Disable parity error flag
125 Z205BA EQU 098H ; Base address for Z-205 boards
126 Z205BMC EQU 8 ; Maximum of 8 Z-205 boards installed
127 ZHAL EQU 0FDH ; Hi-address latch
128 ZHAL85 EQU 0FFH ; 8085 Mask
129 ZHAL88 EQU 0F0H ; 8088 Mask
130 ZPSP EQU 0FEH ; Processor swap port
131 ZPSPPS EQU 10000000B ; Processor select (0=8085, 1=8088)
132 ZPSPPS5 EQU 00000000B ; Select 8085
133 ZPSPPS8 EQU 10000000B ; Select 8088
134 ZPSPSI EQU 00000010B ; Generate interrupt on swapping
135 ZPSPI8 EQU 00000001B ; 8088 processes all interrupts
136 ZDIPSW EQU 0FFH ; Configuration dip switches
137 ZDIPSWBOOT EQU 00000111B ; Boot device field
138 ZDIPSWAB EQU 00001000B ; 1=Auto boot(0=Manual boot)
139 ZDIPSWRES EQU 01110000B ; Reserved
140 ZDIPSWHZ EQU 10000000B ; 1=50Hz(0=60HZ)
141
142 ****************************************************************************/
143
144 #include "emu.h"
145 #include "cpu/i86/i86.h"
146 #include "cpu/i8085/i8085.h"
147 #include "cpu/mcs48/mcs48.h"
148 #include "bus/centronics/ctronics.h"
149 //#include "bus/rs232/rs232.h"
150 //#include "bus/s100/s100.h"
151 #include "imagedev/floppy.h"
152 #include "machine/74123.h"
153 #include "machine/6821pia.h"
154 #include "machine/input_merger.h"
155 #include "machine/pit8253.h"
156 #include "machine/pic8259.h"
157 #include "machine/rescap.h"
158 #include "machine/scn_pci.h"
159 #include "machine/wd_fdc.h"
160 #include "sound/beep.h"
161 #include "video/mc6845.h"
162 #include "emupal.h"
163 #include "screen.h"
164 #include "speaker.h"
165
166 class z100_state : public driver_device
167 {
168 public:
z100_state(const machine_config & mconfig,device_type type,const char * tag)169 z100_state(const machine_config &mconfig, device_type type, const char *tag)
170 : driver_device(mconfig, type, tag),
171 m_maincpu(*this, "maincpu"),
172 m_ram(*this, "ram"),
173 m_pia(*this, "pia%u", 0U),
174 m_picm(*this, "pic8259_master"),
175 m_pics(*this, "pic8259_slave"),
176 m_fdc(*this, "z207_fdc"),
177 m_floppies(*this, "z207_fdc:%u", 0U),
178 m_epci(*this, "epci%u", 0U),
179 m_keyclick(*this, "keyclick"),
180 m_keybeep(*this, "keybeep"),
181 m_beeper(*this, "beeper"),
182 m_crtc(*this, "crtc"),
183 m_palette(*this, "palette"),
184 m_vrmm(*this, "vrmm"),
185 m_vram_config(*this, "VRAM"),
186 m_keys(*this, "COL%u", 0U),
187 m_ctrl(*this, "CTRL"),
188 m_floppy(nullptr)
189 { }
190
191 void z100(machine_config &config);
192
193 DECLARE_INPUT_CHANGED_MEMBER(kbd_reset);
194
195 private:
196 virtual void machine_start() override;
197 virtual void machine_reset() override;
198 virtual void video_start() override;
199
200 uint8_t ram_r(offs_t offset);
201 void ram_w(offs_t offset, uint8_t data);
202 void memory_ctrl_w(uint8_t data);
203 offs_t vram_map(offs_t offset) const;
204 uint8_t z100_vram_r(offs_t offset);
205 void z100_vram_w(offs_t offset, uint8_t data);
206 void kbd_col_w(uint8_t data);
207 uint8_t kbd_rows_r();
208 DECLARE_READ_LINE_MEMBER(kbd_shift_row_r);
209 DECLARE_WRITE_LINE_MEMBER(beep_update);
210 void floppy_select_w(uint8_t data);
211 void floppy_motor_w(uint8_t data);
212 uint8_t tmr_status_r();
213 void tmr_status_w(uint8_t data);
214 DECLARE_WRITE_LINE_MEMBER(timer_flipflop0_w);
215 DECLARE_WRITE_LINE_MEMBER(timer_flipflop1_w);
216 DECLARE_WRITE_LINE_MEMBER(vidint_w);
217 DECLARE_WRITE_LINE_MEMBER(vidint_enable_w);
218
219 u8 get_slave_ack(offs_t offset);
220 void video_pia_A_w(u8 data);
221 void video_pia_B_w(u8 data);
222 DECLARE_WRITE_LINE_MEMBER(video_pia_CA2_w);
223 DECLARE_WRITE_LINE_MEMBER(video_pia_CB2_w);
224
225 MC6845_UPDATE_ROW(update_row);
226
227 void z100_io(address_map &map);
228 void z100_mem(address_map &map);
229
230 required_device<cpu_device> m_maincpu;
231 required_shared_ptr<uint8_t> m_ram;
232 required_device_array<pia6821_device, 2> m_pia;
233 required_device<pic8259_device> m_picm;
234 required_device<pic8259_device> m_pics;
235 required_device<fd1797_device> m_fdc;
236 required_device_array<floppy_connector, 4> m_floppies;
237 required_device_array<scn2661b_device, 2> m_epci;
238 required_device<ttl74123_device> m_keyclick;
239 required_device<ttl74123_device> m_keybeep;
240 required_device<beep_device> m_beeper;
241 required_device<mc6845_device> m_crtc;
242 required_device<palette_device> m_palette;
243 required_region_ptr<uint8_t> m_vrmm;
244 required_ioport m_vram_config;
245 required_ioport_array<16> m_keys;
246 required_ioport m_ctrl;
247
248 std::unique_ptr<uint8_t[]> m_gvram;
249 std::unique_ptr<uint32_t[]> m_parity;
250 uint8_t m_kbd_col;
251 uint8_t m_vram_enable;
252 uint8_t m_gbank;
253 uint8_t m_display_mask;
254 uint8_t m_flash;
255 uint8_t m_clr_val;
256 uint8_t m_tmr_status;
257 uint8_t m_start_addr;
258 bool m_vidint_enable;
259 uint8_t m_memory_ctrl;
260
261 floppy_image_device *m_floppy;
262 };
263
264
machine_start()265 void z100_state::machine_start()
266 {
267 m_parity = make_unique_clear<uint32_t[]>(m_ram.bytes() / 32);
268 }
269
video_start()270 void z100_state::video_start()
271 {
272 m_gvram = make_unique_clear<uint8_t[]>(0x30000);
273
274 m_vidint_enable = false;
275 }
276
ram_r(offs_t offset)277 uint8_t z100_state::ram_r(offs_t offset)
278 {
279 if (!machine().side_effects_disabled() && BIT(m_memory_ctrl, 5))
280 {
281 uint32_t parity = m_parity[offset >> 5];
282 if (BIT(parity, offset & 31))
283 m_picm->ir0_w(1);
284 }
285
286 return m_ram[offset];
287 }
288
ram_w(offs_t offset,uint8_t data)289 void z100_state::ram_w(offs_t offset, uint8_t data)
290 {
291 if (!machine().side_effects_disabled())
292 {
293 uint32_t &parity = m_parity[offset >> 5];
294 if (!BIT(m_memory_ctrl, 4) && BIT(population_count_32(data), 0))
295 parity |= 1 << (offset & 31);
296 else if (parity != 0)
297 parity &= ~(1 << (offset & 31));
298 }
299
300 m_ram[offset] = data;
301 }
302
memory_ctrl_w(uint8_t data)303 void z100_state::memory_ctrl_w(uint8_t data)
304 {
305 m_memory_ctrl = data & 0x3f;
306 if (!BIT(data, 5))
307 m_picm->ir0_w(0);
308 }
309
MC6845_UPDATE_ROW(z100_state::update_row)310 MC6845_UPDATE_ROW(z100_state::update_row)
311 {
312 uint32_t *const pix = &bitmap.pix(y);
313 const uint16_t amask = m_vram_config->read() ? 0xfff : 0x7ff;
314
315 for (int x = 0; x < x_count; x++)
316 {
317 for (int xi = 0; xi < 8; xi++)
318 {
319 int dot = 0;
320 if (m_flash)
321 {
322 dot = m_display_mask;
323 }
324 else
325 {
326 for (int i = 0; i < 3; i++)
327 dot |= ((m_gvram[((x + ma) & amask) << 4 | (ra & 0xf) | (0x10000*i)] >> (7-xi)) & 1) << i; // b, r, g
328
329 if (x == cursor_x)
330 dot ^= 7;
331
332 dot &= m_display_mask;
333 }
334
335 pix[x*8+xi] = m_palette->pen(dot);
336 }
337 }
338 }
339
vram_map(offs_t offset) const340 offs_t z100_state::vram_map(offs_t offset) const
341 {
342 // Translate logical address to physical address
343 return (offset & 0x30000) | (offset & 0x000f) << 4 | (offset & 0x0780) >> 7
344 | ((m_vrmm[(offset & 0xf800) >> 8 | (offset & 0x0070) >> 4] + m_start_addr) & (m_vram_config->read() ? 0xff : 0x7f)) << 8;
345 }
346
z100_vram_r(offs_t offset)347 uint8_t z100_state::z100_vram_r(offs_t offset)
348 {
349 return m_gvram[vram_map(offset)];
350 }
351
z100_vram_w(offs_t offset,uint8_t data)352 void z100_state::z100_vram_w(offs_t offset, uint8_t data)
353 {
354 if(m_vram_enable)
355 {
356 offset = vram_map(offset);
357 m_gvram[offset] = data;
358
359 for (int i = 0; i < 3; i++)
360 {
361 if (BIT(m_gbank, i))
362 m_gvram[((offset) & 0xffff)+0x10000*i] = data;
363 }
364 }
365 }
366
z100_mem(address_map & map)367 void z100_state::z100_mem(address_map &map)
368 {
369 map.unmap_value_high();
370 map(0x00000, 0x3ffff).rw(FUNC(z100_state::ram_r), FUNC(z100_state::ram_w)).share("ram"); // 128*2 KB RAM
371 // map(0xb0000,0xbffff).rom(); // expansion ROM
372 map(0xc0000, 0xeffff).rw(FUNC(z100_state::z100_vram_r), FUNC(z100_state::z100_vram_w)); // Blue / Red / Green
373 // map(0xf0000,0xf0fff) // network card (NET-100)
374 // map(0xf4000,0xf7fff) // MTRET-100 Firmware I expansion ROM
375 // map(0xf8000,0xfbfff) // MTRET-100 Firmware II expansion ROM check ID 0x4550
376 map(0xfc000, 0xfffff).rom().region("ipl", 0);
377 }
378
kbd_col_w(uint8_t data)379 void z100_state::kbd_col_w(uint8_t data)
380 {
381 m_kbd_col = data & 0x0f;
382
383 m_keyclick->b_w(BIT(data, 7));
384 m_keybeep->a_w((data & 0x82) == 0);
385 }
386
kbd_rows_r()387 uint8_t z100_state::kbd_rows_r()
388 {
389 if (m_kbd_col < 0x0c)
390 return m_keys[m_kbd_col]->read();
391
392 return 0xff;
393 }
394
READ_LINE_MEMBER(z100_state::kbd_shift_row_r)395 READ_LINE_MEMBER(z100_state::kbd_shift_row_r)
396 {
397 if ((m_kbd_col & 0x0c) == 0x0c)
398 return m_keys[m_kbd_col]->read();
399
400 return 1;
401 }
402
WRITE_LINE_MEMBER(z100_state::beep_update)403 WRITE_LINE_MEMBER(z100_state::beep_update)
404 {
405 m_beeper->set_state(m_keyclick->q_r() | m_keybeep->q_r());
406 }
407
408 // todo: side select?
409
floppy_select_w(uint8_t data)410 void z100_state::floppy_select_w(uint8_t data)
411 {
412 m_floppy = m_floppies[data & 0x03]->get_device();
413 m_fdc->set_floppy(m_floppy);
414 }
415
floppy_motor_w(uint8_t data)416 void z100_state::floppy_motor_w(uint8_t data)
417 {
418 if (m_floppy)
419 m_floppy->mon_w(!BIT(data, 1));
420 }
421
tmr_status_r()422 uint8_t z100_state::tmr_status_r()
423 {
424 return m_tmr_status;
425 }
426
tmr_status_w(uint8_t data)427 void z100_state::tmr_status_w(uint8_t data)
428 {
429 m_tmr_status &= data & 3;
430 if (m_tmr_status == 0)
431 m_picm->ir2_w(0);
432 }
433
WRITE_LINE_MEMBER(z100_state::timer_flipflop0_w)434 WRITE_LINE_MEMBER(z100_state::timer_flipflop0_w)
435 {
436 if (state)
437 {
438 m_tmr_status |= 1;
439 m_picm->ir2_w(1);
440 }
441 }
442
WRITE_LINE_MEMBER(z100_state::timer_flipflop1_w)443 WRITE_LINE_MEMBER(z100_state::timer_flipflop1_w)
444 {
445 if (state)
446 {
447 m_tmr_status |= 2;
448 m_picm->ir2_w(1);
449 }
450 }
451
WRITE_LINE_MEMBER(z100_state::vidint_w)452 WRITE_LINE_MEMBER(z100_state::vidint_w)
453 {
454 m_pia[1]->pa4_w(state);
455
456 if (state && m_vidint_enable)
457 m_pia[1]->ca2_w(1);
458 }
459
WRITE_LINE_MEMBER(z100_state::vidint_enable_w)460 WRITE_LINE_MEMBER(z100_state::vidint_enable_w)
461 {
462 m_vidint_enable = state;
463 if (!m_vidint_enable)
464 m_pia[1]->ca2_w(0);
465 }
466
z100_io(address_map & map)467 void z100_state::z100_io(address_map &map)
468 {
469 map.unmap_value_high();
470 map.global_mask(0xff);
471 // map(0x00, 0x3f) reserved for non-ZDS vendors
472 // map(0x40, 0x5f) secondary Multiport card (Z-204)
473 // map(0x60, 0x7f) primary Multiport card (Z-204)
474 // map(0x80, 0x83) development board
475 // map(0x98, 0x9f) Z-205 expansion memory boards
476 // map(0xa0, 0xa3) network card (NET-100)
477 // map(0xa4, 0xa7) gateway (reserved)
478 // map(0xac, 0xad) Z-217 secondary disk controller (winchester)
479 // map(0xae, 0xaf) Z-217 primary disk controller (winchester)
480 map(0xb0, 0xb3).rw(m_fdc, FUNC(fd1797_device::read), FUNC(fd1797_device::write));
481 map(0xb4, 0xb4).w(FUNC(z100_state::floppy_select_w));
482 map(0xb5, 0xb5).w(FUNC(z100_state::floppy_motor_w));
483 // z-207 secondary disk controller (wd1797)
484 // map(0xcd, 0xce) ET-100 CRT Controller
485 // map(0xd4, 0xd7) ET-100 Trainer Parallel I/O
486 map(0xd8, 0xdb).rw(m_pia[0], FUNC(pia6821_device::read), FUNC(pia6821_device::write)); //video board
487 map(0xdc, 0xdc).w(m_crtc, FUNC(mc6845_device::address_w));
488 map(0xdd, 0xdd).w(m_crtc, FUNC(mc6845_device::register_w));
489 // map(0xde, 0xde) light pen
490 map(0xe0, 0xe3).rw(m_pia[1], FUNC(pia6821_device::read), FUNC(pia6821_device::write)); //main board
491 map(0xe4, 0xe7).rw("pit", FUNC(pit8253_device::read), FUNC(pit8253_device::write));
492 map(0xe8, 0xeb).rw(m_epci[0], FUNC(scn2661b_device::read), FUNC(scn2661b_device::write));
493 map(0xec, 0xef).rw(m_epci[1], FUNC(scn2661b_device::read), FUNC(scn2661b_device::write));
494 map(0xf0, 0xf1).rw(m_pics, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
495 map(0xf2, 0xf3).rw(m_picm, FUNC(pic8259_device::read), FUNC(pic8259_device::write));
496 map(0xf4, 0xf5).rw("kbdc", FUNC(i8041a_device::upi41_master_r), FUNC(i8041a_device::upi41_master_w));
497 // map(0xf6, 0xf6) expansion ROM is present (bit 0, active low)
498 map(0xfb, 0xfb).rw(FUNC(z100_state::tmr_status_r), FUNC(z100_state::tmr_status_w));
499 map(0xfc, 0xfc).w(FUNC(z100_state::memory_ctrl_w));
500 // map(0xfd, 0xfd) Hi-address latch
501 // map(0xfe, 0xfe) Processor swap port
502 map(0xff, 0xff).portr("DSW101");
503 }
504
INPUT_CHANGED_MEMBER(z100_state::kbd_reset)505 INPUT_CHANGED_MEMBER(z100_state::kbd_reset)
506 {
507 if (m_ctrl->read() == 0)
508 reset();
509 }
510
511 /* Input ports */
512 INPUT_PORTS_START( z100 )
513 PORT_START("COL0") // 15
PORT_CODE(KEYCODE_A)514 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('a') PORT_CHAR('A') PORT_CODE(KEYCODE_A)
515 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('s') PORT_CHAR('S') PORT_CODE(KEYCODE_S)
516 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('d') PORT_CHAR('D') PORT_CODE(KEYCODE_D)
517 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('f') PORT_CHAR('F') PORT_CODE(KEYCODE_F)
518 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('g') PORT_CHAR('G') PORT_CODE(KEYCODE_G)
519 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('h') PORT_CHAR('H') PORT_CODE(KEYCODE_H)
520 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('j') PORT_CHAR('J') PORT_CODE(KEYCODE_J)
521 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('k') PORT_CHAR('K') PORT_CODE(KEYCODE_K)
522
523 PORT_START("COL1") // 11
524 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('q') PORT_CHAR('Q') PORT_CODE(KEYCODE_Q)
525 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('w') PORT_CHAR('W') PORT_CODE(KEYCODE_W)
526 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('e') PORT_CHAR('E') PORT_CODE(KEYCODE_E)
527 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('r') PORT_CHAR('R') PORT_CODE(KEYCODE_R)
528 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('t') PORT_CHAR('T') PORT_CODE(KEYCODE_T)
529 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('y') PORT_CHAR('Y') PORT_CODE(KEYCODE_Y)
530 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('u') PORT_CHAR('U') PORT_CODE(KEYCODE_U)
531 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('i') PORT_CHAR('I') PORT_CODE(KEYCODE_I)
532
533 PORT_START("COL2") // 16
534 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('z') PORT_CHAR('Z') PORT_CODE(KEYCODE_Z)
535 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('x') PORT_CHAR('X') PORT_CODE(KEYCODE_X)
536 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('c') PORT_CHAR('C') PORT_CODE(KEYCODE_C)
537 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('v') PORT_CHAR('V') PORT_CODE(KEYCODE_V)
538 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('b') PORT_CHAR('B') PORT_CODE(KEYCODE_B)
539 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('n') PORT_CHAR('N') PORT_CODE(KEYCODE_N)
540 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('m') PORT_CHAR('M') PORT_CODE(KEYCODE_M)
541 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('l') PORT_CHAR('L') PORT_CODE(KEYCODE_L)
542
543 PORT_START("COL3") // 13
544 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_UNUSED)
545 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_UNUSED)
546 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_UNUSED)
547 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_UNUSED)
548 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_UNUSED)
549 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('p') PORT_CHAR('P') PORT_CODE(KEYCODE_P)
550 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('o') PORT_CHAR('O') PORT_CODE(KEYCODE_O)
551 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNUSED)
552
553 PORT_START("COL4") // 9
554 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("F0")
555 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F1)) PORT_CODE(KEYCODE_F1)
556 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F2)) PORT_CODE(KEYCODE_F2)
557 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F3)) PORT_CODE(KEYCODE_F3)
558 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F4)) PORT_CODE(KEYCODE_F4)
559 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F5)) PORT_CODE(KEYCODE_F5)
560 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F6)) PORT_CODE(KEYCODE_F6)
561 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F7)) PORT_CODE(KEYCODE_F7)
562
563 PORT_START("COL5") // 12
564 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Del/Ins Char") PORT_CODE(KEYCODE_F14)
565 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Del/Ins Line") PORT_CODE(KEYCODE_F13)
566 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F12)) PORT_CODE(KEYCODE_F12)
567 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F11)) PORT_CODE(KEYCODE_F11)
568 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F10)) PORT_CODE(KEYCODE_F10)
569 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F9)) PORT_CODE(KEYCODE_F9)
570 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(F8)) PORT_CODE(KEYCODE_F8)
571 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_UNUSED)
572
573 PORT_START("COL6") // 17
574 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(HOME)) PORT_CODE(KEYCODE_HOME)
575 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(7_PAD)) PORT_CODE(KEYCODE_7_PAD)
576 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(4_PAD)) PORT_CODE(KEYCODE_4_PAD)
577 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(1_PAD)) PORT_CODE(KEYCODE_1_PAD)
578 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(RIGHT)) PORT_CODE(KEYCODE_RIGHT)
579 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(9_PAD)) PORT_CODE(KEYCODE_9_PAD)
580 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(6_PAD)) PORT_CODE(KEYCODE_6_PAD)
581 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(3_PAD)) PORT_CODE(KEYCODE_3_PAD)
582
583 PORT_START("COL7") // 18
584 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(LEFT)) PORT_CODE(KEYCODE_LEFT)
585 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(8_PAD)) PORT_CODE(KEYCODE_8_PAD)
586 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(5_PAD)) PORT_CODE(KEYCODE_5_PAD)
587 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(2_PAD)) PORT_CODE(KEYCODE_2_PAD)
588 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(UP)) PORT_CODE(KEYCODE_UP)
589 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(DOWN)) PORT_CODE(KEYCODE_DOWN)
590 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(MINUS_PAD)) PORT_CODE(KEYCODE_MINUS_PAD)
591 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(ENTER_PAD)) PORT_CODE(KEYCODE_ENTER_PAD)
592
593 PORT_START("COL8") // 3
594 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Break")
595 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Help")
596 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(' ') PORT_CODE(KEYCODE_SPACE)
597 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(0x0a) PORT_CODE(KEYCODE_RALT) PORT_NAME("Line Feed")
598 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('\\') PORT_CHAR('|') PORT_CODE(KEYCODE_BACKSLASH)
599 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(DEL)) PORT_CODE(KEYCODE_DEL) PORT_NAME("Delete")
600 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(0_PAD)) PORT_CODE(KEYCODE_0_PAD)
601 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(DEL_PAD)) PORT_CODE(KEYCODE_DEL_PAD)
602
603 PORT_START("COL9") // 7
604 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(0x1b) PORT_CODE(KEYCODE_ESC)
605 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(0x09) PORT_CODE(KEYCODE_TAB)
606 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(',') PORT_CHAR('<') PORT_CODE(KEYCODE_COMMA)
607 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(0x0d) PORT_CODE(KEYCODE_ENTER) PORT_NAME("Return")
608 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('/') PORT_CHAR('?') PORT_CODE(KEYCODE_SLASH)
609 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('.') PORT_CHAR('>') PORT_CODE(KEYCODE_STOP)
610 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(';') PORT_CHAR(':') PORT_CODE(KEYCODE_COLON)
611 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('\'') PORT_CHAR('"') PORT_CODE(KEYCODE_QUOTE)
612
613 PORT_START("COL10") // 10
614 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('1') PORT_CHAR('!') PORT_CODE(KEYCODE_1)
615 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('2') PORT_CHAR('@') PORT_CODE(KEYCODE_2)
616 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('3') PORT_CHAR('#') PORT_CODE(KEYCODE_3)
617 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('4') PORT_CHAR('$') PORT_CODE(KEYCODE_4)
618 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('5') PORT_CHAR('%') PORT_CODE(KEYCODE_5)
619 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('6') PORT_CHAR('^') PORT_CODE(KEYCODE_6)
620 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('7') PORT_CHAR('&') PORT_CODE(KEYCODE_7)
621 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('8') PORT_CHAR('*') PORT_CODE(KEYCODE_8)
622
623 PORT_START("COL11") // 14
624 PORT_BIT(0x80, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(0x08) PORT_CODE(KEYCODE_BACKSPACE) PORT_NAME("Back Space")
625 PORT_BIT(0x40, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('`') PORT_CHAR('~') PORT_CODE(KEYCODE_TILDE) // ~ key is between BS and =
626 PORT_BIT(0x20, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('=') PORT_CHAR('+') PORT_CODE(KEYCODE_EQUALS)
627 PORT_BIT(0x10, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('-') PORT_CHAR('_') PORT_CODE(KEYCODE_MINUS)
628 PORT_BIT(0x08, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('0') PORT_CHAR(')') PORT_CODE(KEYCODE_0)
629 PORT_BIT(0x04, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('9') PORT_CHAR('(') PORT_CODE(KEYCODE_9)
630 PORT_BIT(0x02, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR('[') PORT_CHAR('{') PORT_CODE(KEYCODE_OPENBRACE)
631 PORT_BIT(0x01, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(']') PORT_CHAR('}') PORT_CODE(KEYCODE_CLOSEBRACE)
632
633 PORT_START("COL12") // 5
634 PORT_BIT(1, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_SHIFT_1) PORT_CODE(KEYCODE_LSHIFT) PORT_NAME("Shift Left")
635
636 PORT_START("COL13") // 8
637 PORT_BIT(1, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_RSHIFT) PORT_NAME("Shift Right")
638
639 PORT_START("COL14") // 6
640 PORT_BIT(1, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CHAR(UCHAR_MAMEKEY(CAPSLOCK)) PORT_CODE(KEYCODE_CAPSLOCK)
641
642 PORT_START("COL15") // 1
643 PORT_BIT(1, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LALT) PORT_NAME("Fast Repeat")
644
645 PORT_START("CTRL") // 2 & 4
646 PORT_BIT(1, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_CODE(KEYCODE_LCONTROL) PORT_NAME("Ctrl") PORT_CHANGED_MEMBER(DEVICE_SELF, z100_state, kbd_reset, 0)
647 PORT_BIT(2, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Reset") PORT_CHANGED_MEMBER(DEVICE_SELF, z100_state, kbd_reset, 0)
648
649 PORT_START("DSW101")
650 PORT_DIPNAME( 0x07, 0x00, "Default Auto-boot Device" )
651 PORT_DIPSETTING( 0x00, "0" )
652 PORT_DIPSETTING( 0x01, "1" )
653 PORT_DIPSETTING( 0x02, "2" )
654 PORT_DIPSETTING( 0x03, "3" )
655 PORT_DIPSETTING( 0x04, "4" )
656 PORT_DIPSETTING( 0x05, "5" )
657 PORT_DIPSETTING( 0x06, "6" )
658 PORT_DIPSETTING( 0x07, "7" )
659 PORT_DIPNAME( 0x08, 0x08, "Auto-boot" )
660 PORT_DIPSETTING( 0x00, DEF_STR( No ) )
661 PORT_DIPSETTING( 0x08, DEF_STR( Yes ) )
662 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) // Reserved
663 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
664 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
665 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) // Reserved
666 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
667 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
668 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) // Reserved
669 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
670 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
671 PORT_DIPNAME( 0x80, 0x00, "Monitor" )
672 PORT_DIPSETTING( 0x80, "PAL 50 Hz" )
673 PORT_DIPSETTING( 0x00, "NTSC 60 Hz" )
674
675 PORT_START("CONFIG")
676 PORT_CONFNAME( 0x01, 0x01, "Video Board" )
677 PORT_CONFSETTING( 0x00, "Monochrome" )
678 PORT_CONFSETTING( 0x01, "Color" )
679
680 PORT_START("VRAM")
681 PORT_DIPNAME( 0x01, 0x01, "Video Memory" ) PORT_DIPLOCATION("J307:1")
682 PORT_DIPSETTING( 0x00, "32K" )
683 PORT_DIPSETTING( 0x01, "64K" )
684 INPUT_PORTS_END
685
686 u8 z100_state::get_slave_ack(offs_t offset)
687 {
688 if (offset==7) { // IRQ = 7
689 return m_pics->acknowledge();
690 }
691 return 0;
692 }
693
video_pia_A_w(u8 data)694 void z100_state::video_pia_A_w(u8 data)
695 {
696 /*
697 all bits are active low
698 x--- ---- -> disable video RAM
699 -x-- ---- -> not write multiple blue
700 --x- ---- -> not write multiple green
701 ---x ---- -> not write multiple red
702 ---- x--- -> not flash screen
703 ---- -x-- -> enable blue display
704 ---- --x- -> enable green display
705 ---- ---x -> enable red display
706 */
707
708 m_vram_enable = ((data & 0x80) >> 7) ^ 1;
709 m_gbank = bitswap<8>(((data & 0x70) >> 4) ^ 0x7,7,6,5,4,3,1,0,2);
710 m_flash = ((data & 8) >> 3) ^ 1;
711 m_display_mask = bitswap<8>((data & 7) ^ 7,7,6,5,4,3,1,0,2);
712 }
713
video_pia_B_w(u8 data)714 void z100_state::video_pia_B_w(u8 data)
715 {
716 m_start_addr = data;
717 }
718
719 /* clear screen */
WRITE_LINE_MEMBER(z100_state::video_pia_CA2_w)720 WRITE_LINE_MEMBER( z100_state::video_pia_CA2_w )
721 {
722 int i;
723
724 for(i=0; i<0x30000; i++)
725 m_gvram[i] = m_clr_val;
726 }
727
WRITE_LINE_MEMBER(z100_state::video_pia_CB2_w)728 WRITE_LINE_MEMBER( z100_state::video_pia_CB2_w )
729 {
730 m_clr_val = (state & 1) ? 0x00 : 0xff;
731 }
732
machine_reset()733 void z100_state::machine_reset()
734 {
735 int i;
736
737 if(ioport("CONFIG")->read() & 1)
738 {
739 for(i=0;i<8;i++)
740 m_palette->set_pen_color(i,pal1bit(i >> 1),pal1bit(i >> 2),pal1bit(i >> 0));
741 }
742 else
743 {
744 for(i=0;i<8;i++)
745 m_palette->set_pen_color(i,pal3bit(0),pal3bit(i),pal3bit(0));
746 }
747
748 memory_ctrl_w(0);
749 }
750
z100_floppies(device_slot_interface & device)751 static void z100_floppies(device_slot_interface &device)
752 {
753 device.option_add("dd", FLOPPY_525_DD);
754 }
755
z100(machine_config & config)756 void z100_state::z100(machine_config &config)
757 {
758 /* basic machine hardware */
759 I8088(config, m_maincpu, 15_MHz_XTAL / 3); // 5 MHz or 8 MHz depending on XTAL
760 m_maincpu->set_addrmap(AS_PROGRAM, &z100_state::z100_mem);
761 m_maincpu->set_addrmap(AS_IO, &z100_state::z100_io);
762 m_maincpu->set_irq_acknowledge_callback("pic8259_master", FUNC(pic8259_device::inta_cb));
763
764 I8085A(config, "cpu85", 10_MHz_XTAL).set_disable();
765
766 i8041a_device &kbdc(I8041A(config, "kbdc", 6_MHz_XTAL));
767 kbdc.p1_in_cb().set(FUNC(z100_state::kbd_rows_r));
768 kbdc.p2_out_cb().set(FUNC(z100_state::kbd_col_w));
769 kbdc.p2_out_cb().append("keydspyint", FUNC(input_merger_device::in_w<0>)).bit(4);
770 kbdc.t0_in_cb().set_ioport("CTRL").bit(0);
771 kbdc.t1_in_cb().set(FUNC(z100_state::kbd_shift_row_r));
772
773 TTL74123(config, m_keyclick, RES_K(150), CAP_U(.1));
774 m_keyclick->set_connection_type(TTL74123_NOT_GROUNDED_NO_DIODE);
775 m_keyclick->set_a_pin_value(0);
776 m_keyclick->set_b_pin_value(1);
777 m_keyclick->set_clear_pin_value(1);
778 m_keyclick->out_cb().set(FUNC(z100_state::beep_update));
779
780 TTL74123(config, m_keybeep, RES_K(220), CAP_U(2.2));
781 m_keybeep->set_connection_type(TTL74123_NOT_GROUNDED_NO_DIODE);
782 m_keybeep->set_b_pin_value(1);
783 m_keybeep->set_clear_pin_value(1);
784 m_keybeep->out_cb().set(FUNC(z100_state::beep_update));
785
786 SPEAKER(config, "mono").front_center();
787 BEEP(config, m_beeper, 1'000'000'000 / PERIOD_OF_555_ASTABLE_NSEC(RES_K(470), RES_K(470), CAP_U(.001)));
788 m_beeper->add_route(ALL_OUTPUTS, "mono", 0.50);
789
790 /* video hardware */
791 screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
792 screen.set_raw(14.112_MHz_XTAL, 912, 0, 640, 258, 0, 216);
793 screen.set_screen_update("crtc", FUNC(mc6845_device::screen_update));
794
795 PALETTE(config, m_palette).set_entries(8);
796
797 /* devices */
798 MC6845(config, m_crtc, 14.112_MHz_XTAL / 8); // 68A45
799 m_crtc->set_screen("screen");
800 m_crtc->set_show_border_area(false);
801 m_crtc->set_char_width(8);
802 m_crtc->set_update_row_callback(FUNC(z100_state::update_row));
803 m_crtc->out_vsync_callback().set(FUNC(z100_state::vidint_w));
804
805 PIC8259(config, m_picm);
806 m_picm->out_int_callback().set_inputline(m_maincpu, 0);
807 m_picm->in_sp_callback().set_constant(1);
808 m_picm->read_slave_ack_callback().set(FUNC(z100_state::get_slave_ack));
809
810 PIC8259(config, m_pics);
811 m_pics->out_int_callback().set(m_picm, FUNC(pic8259_device::ir3_w));
812 m_pics->in_sp_callback().set_constant(0);
813
814 pit8253_device &pit(PIT8253(config, "pit"));
815 pit.set_clk<0>(4_MHz_XTAL / 16);
816 pit.out_handler<0>().set(FUNC(z100_state::timer_flipflop0_w));
817 pit.out_handler<0>().append("pit", FUNC(pit8253_device::write_clk1));
818 pit.set_clk<2>(4_MHz_XTAL / 16);
819 pit.out_handler<2>().set(FUNC(z100_state::timer_flipflop1_w));
820
821 PIA6821(config, m_pia[0]);
822 m_pia[0]->writepa_handler().set(FUNC(z100_state::video_pia_A_w));
823 m_pia[0]->writepb_handler().set(FUNC(z100_state::video_pia_B_w));
824 m_pia[0]->ca2_handler().set(FUNC(z100_state::video_pia_CA2_w));
825 m_pia[0]->cb2_handler().set(FUNC(z100_state::video_pia_CB2_w));
826
827 PIA6821(config, m_pia[1]);
828 m_pia[1]->irqa_handler().set("keydspyint", FUNC(input_merger_device::in_w<1>));
829 m_pia[1]->irqb_handler().set(m_picm, FUNC(pic8259_device::ir7_w));
830 m_pia[1]->writepa_handler().set("centronics", FUNC(centronics_device::write_strobe)).bit(2);
831 m_pia[1]->writepa_handler().append("centronics", FUNC(centronics_device::write_data0)).bit(0);
832 m_pia[1]->writepa_handler().append("centronics", FUNC(centronics_device::write_data1)).bit(1);
833 m_pia[1]->writepa_handler().append("centronics", FUNC(centronics_device::write_init)).bit(3);
834 m_pia[1]->writepa_handler().append(FUNC(z100_state::vidint_enable_w)).bit(5);
835 m_pia[1]->writepb_handler().set("centronics", FUNC(centronics_device::write_data2)).bit(2);
836 m_pia[1]->writepb_handler().append("centronics", FUNC(centronics_device::write_data3)).bit(3);
837 m_pia[1]->writepb_handler().append("centronics", FUNC(centronics_device::write_data4)).bit(4);
838 m_pia[1]->writepb_handler().append("centronics", FUNC(centronics_device::write_data5)).bit(5);
839 m_pia[1]->writepb_handler().append("centronics", FUNC(centronics_device::write_data6)).bit(6);
840 m_pia[1]->writepb_handler().append("centronics", FUNC(centronics_device::write_data7)).bit(7);
841
842 centronics_device ¢ronics(CENTRONICS(config, "centronics", centronics_devices, nullptr));
843 centronics.ack_handler().set(m_pia[1], FUNC(pia6821_device::cb1_w)).invert();
844 centronics.busy_handler().set(m_pia[1], FUNC(pia6821_device::cb2_w));
845 centronics.busy_handler().append(m_pia[1], FUNC(pia6821_device::pb0_w));
846 centronics.perror_handler().set(m_pia[1], FUNC(pia6821_device::pb1_w));
847
848 input_merger_device &keydspyint(INPUT_MERGER_ANY_HIGH(config, "keydspyint"));
849 keydspyint.output_handler().set(m_picm, FUNC(pic8259_device::ir6_w));
850
851 FD1797(config, m_fdc, 4_MHz_XTAL / 4);
852
853 FLOPPY_CONNECTOR(config, m_floppies[0], z100_floppies, "dd", floppy_image_device::default_floppy_formats);
854 FLOPPY_CONNECTOR(config, m_floppies[1], z100_floppies, "dd", floppy_image_device::default_floppy_formats);
855 FLOPPY_CONNECTOR(config, m_floppies[2], z100_floppies, nullptr, floppy_image_device::default_floppy_formats);
856 FLOPPY_CONNECTOR(config, m_floppies[3], z100_floppies, nullptr, floppy_image_device::default_floppy_formats);
857
858 SCN2661B(config, m_epci[0], 4.9152_MHz_XTAL); // First 2661-2 serial port (printer)
859 m_epci[0]->txrdy_handler().set("epci0int", FUNC(input_merger_device::in_w<0>));
860 m_epci[0]->rxrdy_handler().set("epci0int", FUNC(input_merger_device::in_w<1>));
861
862 SCN2661B(config, m_epci[1], 4.9152_MHz_XTAL); // Second 2661-2 serial port (modem)
863 m_epci[1]->txrdy_handler().set("epci1int", FUNC(input_merger_device::in_w<0>));
864 m_epci[1]->rxrdy_handler().set("epci1int", FUNC(input_merger_device::in_w<1>));
865
866 input_merger_device &epci0int(INPUT_MERGER_ANY_HIGH(config, "epci0int"));
867 epci0int.output_handler().set(m_picm, FUNC(pic8259_device::ir4_w));
868
869 input_merger_device &epci1int(INPUT_MERGER_ANY_HIGH(config, "epci1int"));
870 epci1int.output_handler().set(m_picm, FUNC(pic8259_device::ir5_w));
871 }
872
873 /* ROM definition */
874 ROM_START( z100 )
875 ROM_REGION(0x4000, "ipl", 0)
876 ROM_LOAD("intel-d27128-1.bin", 0x0000, 0x4000, CRC(b21f0392) SHA1(69e492891cceb143a685315efe0752981a2d8143))
877
878 ROM_REGION(0x0400, "kbdc", 0) // 8041A keyboard controller
879 ROM_LOAD("444-109.u204", 0x0000, 0x0400, CRC(45181029) SHA1(0e89649364d25cf2d8669d2a293ee162e274cb64))
880
881 // All PROMs are typed in from Zenith technical manual listings rather than dumped from real devices, and are accordingly marked BAD_DUMP
882 ROM_REGION(0x0100, "iodec", 0) // 82S129 I/O Decoder PROM
883 ROM_LOAD("444-101.u179", 0x0000, 0x0100, CRC(c952be82) SHA1(0edf9265d302f8478a310858eb6a9352f0cda17b) BAD_DUMP)
884
885 ROM_REGION(0x0100, "memdec", 0) // 82S129 Memory Decoder PROM
886 ROM_LOAD("444-104.u111", 0x0000, 0x0100, CRC(46edd69d) SHA1(5d4bafeaa4593e419bf94dba9e44c8b2be58727b) BAD_DUMP)
887
888 ROM_REGION(0x0020, "status", 0) // 82S123 CPU Status Decode PROM
889 ROM_LOAD("444-105.u226", 0x0000, 0x0020, CRC(98b084e9) SHA1(d968b9a1b1d2ba3ed40036c2192c9960a6c15e99) BAD_DUMP)
890
891 ROM_REGION(0x0100, "vramsel", 0) // 82S129 Video RAM Select PROM
892 ROM_LOAD("444-102.u371", 0x0000, 0x0100, CRC(4558f540) SHA1(55c9bad87b111537a6d386a6eb405169fb47304c) BAD_DUMP)
893
894 ROM_REGION(0x0100, "viosel", 0) // 82S129 Video I/O Select PROM
895 ROM_LOAD("444-103.u369", 0x0000, 0x0100, CRC(854cef15) SHA1(836b244dac0085bcfe8006fde0c5f19982969236) BAD_DUMP)
896
897 ROM_REGION(0x0100, "vrmm", 0) // TBP18S22 Video RAM Mapping Module
898 ROM_LOAD("444-127.u370", 0x0000, 0x0100, CRC(ac386f6b) SHA1(2b62b939d704d90edf59923a8a1a51ef1902f4d7) BAD_DUMP)
899 ROM_END
900
901
902 /* Driver */
903
904 // YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS
905 COMP( 1982, z100, 0, 0, z100, z100, z100_state, empty_init, "Zenith Data Systems", "Z-100", MACHINE_NOT_WORKING )
906