1
2 /*
3 * O2EM Free Odyssey2 / Videopac+ Emulator
4 *
5 * Created by Daniel Boris <dboris@comcast.net> (c) 1997,1998
6 *
7 * Developed by Andre de la Rocha <adlroc@users.sourceforge.net>
8 *
9 * http://o2em.sourceforge.net
10 *
11 *
12 *
13 * 8048 microcontroller emulation
14 */
15
16
17 #include <stdio.h>
18 #include "types.h"
19 #include "vmachine.h"
20 #include "keyboard.h"
21 #include "voice.h"
22 #include "vdc.h"
23 #include "vpp.h"
24 #include "cpu.h"
25
26
27 Byte acc; /* Accumulator */
28 ADDRESS pc; /* Program counter */
29 long clk; /* clock */
30
31 Byte itimer; /* Internal timer */
32 Byte reg_pnt; /* pointer to register bank */
33 Byte timer_on; /* 0=timer off/1=timer on */
34 Byte count_on; /* 0=count off/1=count on */
35 Byte psw; /* Processor status word */
36 Byte sp; /* Stack pointer (part of psw) */
37
38 Byte p1; /* I/O port 1 */
39 Byte p2; /* I/O port 2 */
40 Byte xirq_pend; /* external IRQ pending */
41 Byte tirq_pend; /* timer IRQ pending */
42 Byte t_flag; /* Timer flag */
43
44 static ADDRESS lastpc;
45 static ADDRESS A11; /* PC bit 11 */
46 static ADDRESS A11ff;
47 static Byte bs; /* Register Bank (part of psw) */
48 static Byte f0; /* Flag Bit (part of psw) */
49 static Byte f1; /* Flag Bit 1 */
50 static Byte ac; /* Aux Carry (part of psw) */
51 static Byte cy; /* Carry flag (part of psw) */
52 static Byte xirq_en; /* external IRQ's enabled */
53 static Byte tirq_en; /* Timer IRQ enabled */
54 static Byte irq_ex; /* IRQ executing */
55
56 static int master_count;
57
58
59 #define push(d) {intRAM[sp++] = (d); if (sp > 23) sp = 8;}
60 #define pull() (sp--, (sp < 8)?(sp=23):0, intRAM[sp])
61 #define make_psw() {psw = (cy << 7) | ac | f0 | bs | 0x08; psw = psw | ((sp - 8) >> 1);}
62 #define illegal(o) {}
63 #define undef(i) {printf("** unimplemented instruction %x, %x**\n",i,pc);}
64 #define ROM(adr) (rom[(adr) & 0xfff])
65
66
init_cpu(void)67 void init_cpu(void){
68 pc=0;
69 sp=8;
70 bs=0;
71 p1=p2=0xFF;
72 ac=cy=f0=0;
73 A11=A11ff=0;
74 timer_on=0;
75 count_on=0;
76 reg_pnt=0;
77 tirq_en=xirq_en=irq_ex=xirq_pend=tirq_pend=0;
78 }
79
80
ext_IRQ(void)81 void ext_IRQ(void){
82 int_clk = 5; /* length of pulse on /INT */
83 if (xirq_en && !irq_ex) {
84 irq_ex=1;
85 xirq_pend=0;
86 clk+=2;
87 make_psw();
88 push(pc & 0xFF);
89 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
90 pc = 0x03;
91 A11ff=A11;
92 A11=0;
93 }
94 if (pendirq && (!xirq_en)) xirq_pend=1;
95 }
96
97
tim_IRQ(void)98 void tim_IRQ(void){
99 if (tirq_en && !irq_ex) {
100 irq_ex=2;
101 tirq_pend=0;
102 clk+=2;
103 make_psw();
104 push(pc & 0xFF);
105 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
106 pc = 0x07;
107 A11ff=A11;
108 A11=0;
109 }
110 if (pendirq && (!tirq_en)) tirq_pend=1;
111 }
112
113
make_psw_debug(void)114 void make_psw_debug(void){
115 make_psw();
116 }
117
118
119
cpu_exec(void)120 void cpu_exec(void) {
121 Byte op;
122 ADDRESS adr;
123 Byte dat;
124 int temp;
125
126 for (;;) {
127
128 clk=0;
129
130 lastpc=pc;
131 op=ROM(pc++);
132 switch (op) {
133 case 0x00: /* NOP */
134 clk++;
135 break;
136 case 0x01: /* ILL */
137 illegal(op);
138 clk++;
139 break;
140 case 0x02: /* OUTL BUS,A */
141 clk+=2;
142 undef(0x02);
143 break;
144 case 0x03: /* ADD A,#data */
145 clk+=2;
146 cy=ac=0;
147 dat=ROM(pc++);
148 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
149 temp=acc+dat;
150 if (temp > 0xFF) cy=1;
151 acc=(temp & 0xFF);
152 break;
153 case 0x04: /* JMP */
154 pc=ROM(pc) | A11;
155 clk+=2;
156 break;
157 case 0x05: /* EN I */
158 xirq_en=1;
159 clk++;
160 break;
161 case 0x06: /* ILL */
162 clk++;
163 illegal(op);
164 break;
165 case 0x07: /* DEC A */
166 acc--;
167 clk++;
168 break;
169 case 0x08: /* INS A,BUS*/
170 clk+=2;
171 acc=in_bus();
172 break;
173 case 0x09: /* IN A,Pp */
174 acc=p1;
175 clk+=2;
176 break;
177 case 0x0A: /* IN A,Pp */
178 acc=read_P2();
179 clk+=2;
180 break;
181 case 0x0B: /* ILL */
182 clk++;
183 illegal(op);
184 break;
185 case 0x0C: /* MOVD A,P4 */
186 clk+=2;
187 acc=read_PB(0);
188 break;
189 case 0x0D: /* MOVD A,P5 */
190 clk+=2;
191 acc=read_PB(1);
192 break;
193 case 0x0E: /* MOVD A,P6 */
194 clk+=2;
195 acc=read_PB(2);
196 break;
197 case 0x0F: /* MOVD A,P7 */
198 clk+=2;
199 acc=read_PB(3);
200 break;
201 case 0x10: /* INC @Ri */
202 intRAM[intRAM[reg_pnt] & 0x3F]++;
203 clk++;
204 break;
205 case 0x11: /* INC @Ri */
206 intRAM[intRAM[reg_pnt+1] & 0x3F]++;
207 clk++;
208 break;
209 case 0x12: /* JBb address */
210 clk+=2;
211 dat = ROM(pc);
212 if (acc & 0x01)
213 pc=(pc & 0xF00) | dat;
214 else
215 pc++;
216 break;
217 case 0x13: /* ADDC A,#data */
218 clk+=2;
219 dat=ROM(pc++);
220 ac=0;
221 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
222 temp=acc+dat+cy;
223 cy=0;
224 if (temp > 0xFF) cy=1;
225 acc=(temp & 0xFF);
226 break;
227
228 case 0x14: /* CALL */
229 make_psw();
230 adr = ROM(pc) | A11;
231 pc++;
232 clk+=2;
233 push(pc & 0xFF);
234 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
235 pc = adr;
236 break;
237 case 0x15: /* DIS I */
238 xirq_en=0;
239 clk++;
240 break;
241 case 0x16: /* JTF */
242 clk+=2;
243 dat = ROM(pc);
244 if (t_flag)
245 pc=(pc & 0xF00) | dat;
246 else
247 pc++;
248 t_flag=0;
249 break;
250 case 0x17: /* INC A */
251 acc++;
252 clk++;
253 break;
254 case 0x18: /* INC Rr */
255 intRAM[reg_pnt]++;
256 clk++;
257 break;
258 case 0x19: /* INC Rr */
259 intRAM[reg_pnt+1]++;
260 clk++;
261 break;
262 case 0x1A: /* INC Rr */
263 intRAM[reg_pnt+2]++;
264 clk++;
265 break;
266 case 0x1B: /* INC Rr */
267 intRAM[reg_pnt+3]++;
268 clk++;
269 break;
270 case 0x1C: /* INC Rr */
271 intRAM[reg_pnt+4]++;
272 clk++;
273 break;
274 case 0x1D: /* INC Rr */
275 intRAM[reg_pnt+5]++;
276 clk++;
277 break;
278 case 0x1E: /* INC Rr */
279 intRAM[reg_pnt+6]++;
280 clk++;
281 break;
282 case 0x1F: /* INC Rr */
283 intRAM[reg_pnt+7]++;
284 clk++;
285 break;
286 case 0x20: /* XCH A,@Ri */
287 clk++;
288 dat=acc;
289 acc=intRAM[intRAM[reg_pnt] & 0x3F];
290 intRAM[intRAM[reg_pnt] & 0x3F] = dat;
291 break;
292 case 0x21: /* XCH A,@Ri */
293 clk++;
294 dat=acc;
295 acc=intRAM[intRAM[reg_pnt+1] & 0x3F];
296 intRAM[intRAM[reg_pnt+1] & 0x3F] = dat;
297 break;
298 case 0x22: /* ILL */
299 clk++;
300 illegal(op);
301 break;
302 case 0x23: /* MOV a,#data */
303 clk+=2;
304 acc = ROM(pc++);
305 break;
306
307 case 0x24: /* JMP */
308 pc=ROM(pc) | 0x100 | A11;
309 clk+=2;
310 break;
311 case 0x25: /* EN TCNTI */
312 tirq_en=1;
313 clk++;
314 break;
315 case 0x26: /* JNT0 */
316 clk+=2;
317 dat = ROM(pc);
318 if (!get_voice_status())
319 pc=(pc & 0xF00) | dat;
320 else
321 pc++;
322 break;
323 case 0x27: /* CLR A */
324 clk++;
325 acc=0;
326 break;
327 case 0x28: /* XCH A,Rr */
328 dat=acc;
329 acc=intRAM[reg_pnt];
330 intRAM[reg_pnt]=dat;
331 clk++;
332 break;
333 case 0x29: /* XCH A,Rr */
334 dat=acc;
335 acc=intRAM[reg_pnt+1];
336 intRAM[reg_pnt+1]=dat;
337 clk++;
338 break;
339 case 0x2A: /* XCH A,Rr */
340 dat=acc;
341 acc=intRAM[reg_pnt+2];
342 intRAM[reg_pnt+2]=dat;
343 clk++;
344 break;
345 case 0x2B: /* XCH A,Rr */
346 dat=acc;
347 acc=intRAM[reg_pnt+3];
348 intRAM[reg_pnt+3]=dat;
349 clk++;
350 break;
351 case 0x2C: /* XCH A,Rr */
352 dat=acc;
353 acc=intRAM[reg_pnt+4];
354 intRAM[reg_pnt+4]=dat;
355 clk++;
356 break;
357 case 0x2D: /* XCH A,Rr */
358 dat=acc;
359 acc=intRAM[reg_pnt+5];
360 intRAM[reg_pnt+5]=dat;
361 clk++;
362 break;
363 case 0x2E: /* XCH A,Rr */
364 dat=acc;
365 acc=intRAM[reg_pnt+6];
366 intRAM[reg_pnt+6]=dat;
367 clk++;
368 break;
369 case 0x2F: /* XCH A,Rr */
370 dat=acc;
371 acc=intRAM[reg_pnt+7];
372 intRAM[reg_pnt+7]=dat;
373 clk++;
374 break;
375 case 0x30: /* XCHD A,@Ri */
376 clk++;
377 adr=intRAM[reg_pnt] & 0x3F;
378 dat=acc & 0x0F;
379 acc=acc & 0xF0;
380 acc=acc | (intRAM[adr] & 0x0F);
381 intRAM[adr] &= 0xF0;
382 intRAM[adr] |= dat;
383 break;
384 case 0x31: /* XCHD A,@Ri */
385 clk++;
386 adr=intRAM[reg_pnt+1] & 0x3F;
387 dat=acc & 0x0F;
388 acc=acc & 0xF0;
389 acc=acc | (intRAM[adr] & 0x0F);
390 intRAM[adr] &= 0xF0;
391 intRAM[adr] |= dat;
392 break;
393 case 0x32: /* JBb address */
394 clk+=2;
395 dat=ROM(pc);
396 if (acc & 0x02)
397 pc=(pc & 0xF00) | dat;
398 else
399 pc++;
400 break;
401 case 0x33: /* ILL */
402 clk++;
403 illegal(op);
404 break;
405 case 0x34: /* CALL */
406 make_psw();
407 adr = ROM(pc) | 0x100 | A11;
408 pc++;
409 clk+=2;
410 push(pc & 0xFF);
411 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
412 pc = adr;
413 break;
414 case 0x35: /* DIS TCNTI */
415 tirq_en=0;
416 tirq_pend=0;
417 clk++;
418 break;
419 case 0x36: /* JT0 */
420 clk+=2;
421 dat=ROM(pc);
422 if (get_voice_status())
423 pc=(pc & 0xF00) | dat;
424 else
425 pc++;
426 break;
427 case 0x37: /* CPL A */
428 acc = acc ^ 0xFF;
429 clk++;
430 break;
431 case 0x38: /* ILL */
432 clk++;
433 illegal(op);
434 break;
435 case 0x39: /* OUTL P1,A */
436 clk+=2;
437 write_p1(acc);
438 break;
439 case 0x3A: /* OUTL P2,A */
440 clk+=2;
441 p2=acc;
442 break;
443 case 0x3B: /* ILL */
444 clk++;
445 illegal(op);
446 break;
447 case 0x3C: /* MOVD P4,A */
448 clk+=2;
449 write_PB(0,acc);
450 break;
451 case 0x3D: /* MOVD P5,A */
452 clk+=2;
453 write_PB(1,acc);
454 break;
455 case 0x3E: /* MOVD P6,A */
456 clk+=2;
457 write_PB(2,acc);
458 break;
459 case 0x3F: /* MOVD P7,A */
460 clk+=2;
461 write_PB(3,acc);
462 break;
463 case 0x40: /* ORL A,@Ri */
464 clk++;
465 acc = acc | intRAM[intRAM[reg_pnt] & 0x3F];
466 break;
467 case 0x41: /* ORL A,@Ri */
468 clk++;
469 acc = acc | intRAM[intRAM[reg_pnt+1] & 0x3F];
470 break;
471 case 0x42: /* MOV A,T */
472 clk++;
473 acc = itimer;
474 break;
475 case 0x43: /* ORL A,#data */
476 clk+=2;
477 acc = acc | ROM(pc++);
478 break;
479 case 0x44: /* JMP */
480 pc=ROM(pc) | 0x200 | A11;
481 clk+=2;
482 break;
483 case 0x45: /* STRT CNT */
484 /* printf("START: %d=%d\n",master_clk/22,itimer); */
485 count_on=1;
486 clk++;
487 break;
488 case 0x46: /* JNT1 */
489 clk+=2;
490 dat = ROM(pc);
491 if (!read_t1())
492 pc=(pc & 0xF00) | dat;
493 else
494 pc++;
495 break;
496 case 0x47: /* SWAP A */
497 clk++;
498 dat=(acc & 0xF0) >> 4;
499 acc = acc << 4;
500 acc = acc | dat;
501 break;
502 case 0x48: /* ORL A,Rr */
503 clk++;
504 acc = acc | intRAM[reg_pnt];
505 break;
506 case 0x49: /* ORL A,Rr */
507 clk++;
508 acc = acc | intRAM[reg_pnt+1];
509 break;
510 case 0x4A: /* ORL A,Rr */
511 clk++;
512 acc = acc | intRAM[reg_pnt+2];
513 break;
514 case 0x4B: /* ORL A,Rr */
515 clk++;
516 acc = acc | intRAM[reg_pnt+3];
517 break;
518 case 0x4C: /* ORL A,Rr */
519 clk++;
520 acc = acc | intRAM[reg_pnt+4];
521 break;
522 case 0x4D: /* ORL A,Rr */
523 clk++;
524 acc = acc | intRAM[reg_pnt+5];
525 break;
526 case 0x4E: /* ORL A,Rr */
527 clk++;
528 acc = acc | intRAM[reg_pnt+6];
529 break;
530 case 0x4F: /* ORL A,Rr */
531 clk++;
532 acc = acc | intRAM[reg_pnt+7];
533 break;
534
535 case 0x50: /* ANL A,@Ri */
536 acc = acc & intRAM[intRAM[reg_pnt] & 0x3F];
537 clk++;
538 break;
539 case 0x51: /* ANL A,@Ri */
540 acc = acc & intRAM[intRAM[reg_pnt+1] & 0x3F];
541 clk++;
542 break;
543 case 0x52: /* JBb address */
544 clk+=2;
545 dat=ROM(pc);
546 if (acc & 0x04)
547 pc=(pc & 0xF00) | dat;
548 else
549 pc++;
550 break;
551 case 0x53: /* ANL A,#data */
552 clk+=2;
553 acc = acc & ROM(pc++);
554 break;
555 case 0x54: /* CALL */
556 make_psw();
557 adr = ROM(pc) | 0x200 | A11;
558 pc++;
559 clk+=2;
560 push(pc & 0xFF);
561 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
562 pc = adr;
563 break;
564 case 0x55: /* STRT T */
565 timer_on=1;
566 clk++;
567 break;
568 case 0x56: /* JT1 */
569 clk+=2;
570 dat = ROM(pc);
571 if (read_t1())
572 pc=(pc & 0xF00) | dat;
573 else
574 pc++;
575 break;
576 case 0x57: /* DA A */
577 clk++;
578 if (((acc & 0x0F) > 0x09) || ac) {
579 if (acc>0xf9) cy=1;
580 acc += 6;
581 }
582 dat = (acc & 0xF0) >> 4;
583 if ((dat > 9) || cy) {
584 dat+=6;
585 cy=1;
586 }
587 acc = (acc & 0x0F) | (dat << 4);
588 break;
589 case 0x58: /* ANL A,Rr */
590 clk++;
591 acc = acc & intRAM[reg_pnt];
592 break;
593 case 0x59: /* ANL A,Rr */
594 clk++;
595 acc = acc & intRAM[reg_pnt+1];
596 break;
597 case 0x5A: /* ANL A,Rr */
598 clk++;
599 acc = acc & intRAM[reg_pnt+2];
600 break;
601 case 0x5B: /* ANL A,Rr */
602 clk++;
603 acc = acc & intRAM[reg_pnt+3];
604 break;
605 case 0x5C: /* ANL A,Rr */
606 clk++;
607 acc = acc & intRAM[reg_pnt+4];
608 break;
609 case 0x5D: /* ANL A,Rr */
610 clk++;
611 acc = acc & intRAM[reg_pnt+5];
612 break;
613 case 0x5E: /* ANL A,Rr */
614 clk++;
615 acc = acc & intRAM[reg_pnt+6];
616 break;
617 case 0x5F: /* ANL A,Rr */
618 clk++;
619 acc = acc & intRAM[reg_pnt+7];
620 break;
621
622 case 0x60: /* ADD A,@Ri */
623 clk++;
624 cy=ac=0;
625 dat=intRAM[intRAM[reg_pnt] & 0x3F];
626 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
627 temp=acc+dat;
628 if (temp > 0xFF) cy=1;
629 acc=(temp & 0xFF);
630 break;
631 case 0x61: /* ADD A,@Ri */
632 clk++;
633 cy=ac=0;
634 dat=intRAM[intRAM[reg_pnt+1] & 0x3F];
635 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
636 temp=acc+dat;
637 if (temp > 0xFF) cy=1;
638 acc=(temp & 0xFF);
639 break;
640 case 0x62: /* MOV T,A */
641 clk++;
642 itimer=acc;
643 break;
644 case 0x63: /* ILL */
645 clk++;
646 illegal(op);
647 break;
648 case 0x64: /* JMP */
649 pc=ROM(pc) | 0x300 | A11;
650 clk+=2;
651 break;
652 case 0x65: /* STOP TCNT */
653 clk++;
654 /* printf("STOP %d\n",master_clk/22); */
655 count_on=timer_on=0;
656 break;
657 case 0x66: /* ILL */
658 clk++;
659 illegal(op);
660 break;
661 case 0x67: /* RRC A */
662 dat=cy;
663 cy=acc & 0x01;
664 acc = acc >> 1;
665 if (dat)
666 acc = acc | 0x80;
667 else
668 acc = acc & 0x7F;
669 clk++;
670 break;
671 case 0x68: /* ADD A,Rr */
672 clk++;
673 cy=ac=0;
674 dat=intRAM[reg_pnt];
675 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
676 temp=acc+dat;
677 if (temp > 0xFF) cy=1;
678 acc=(temp & 0xFF);
679 break;
680 case 0x69: /* ADD A,Rr */
681 clk++;
682 cy=ac=0;
683 dat=intRAM[reg_pnt+1];
684 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
685 temp=acc+dat;
686 if (temp > 0xFF) cy=1;
687 acc=(temp & 0xFF);
688 break;
689 case 0x6A: /* ADD A,Rr */
690 clk++;
691 cy=ac=0;
692 dat=intRAM[reg_pnt+2];
693 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
694 temp=acc+dat;
695 if (temp > 0xFF) cy=1;
696 acc=(temp & 0xFF);
697 break;
698 case 0x6B: /* ADD A,Rr */
699 clk++;
700 cy=ac=0;
701 dat=intRAM[reg_pnt+3];
702 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
703 temp=acc+dat;
704 if (temp > 0xFF) cy=1;
705 acc=(temp & 0xFF);
706 break;
707 case 0x6C: /* ADD A,Rr */
708 clk++;
709 cy=ac=0;
710 dat=intRAM[reg_pnt+4];
711 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
712 temp=acc+dat;
713 if (temp > 0xFF) cy=1;
714 acc=(temp & 0xFF);
715 break;
716 case 0x6D: /* ADD A,Rr */
717 clk++;
718 cy=ac=0;
719 dat=intRAM[reg_pnt+5];
720 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
721 temp=acc+dat;
722 if (temp > 0xFF) cy=1;
723 acc=(temp & 0xFF);
724 break;
725 case 0x6E: /* ADD A,Rr */
726 clk++;
727 cy=ac=0;
728 dat=intRAM[reg_pnt+6];
729 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
730 temp=acc+dat;
731 if (temp > 0xFF) cy=1;
732 acc=(temp & 0xFF);
733 break;
734 case 0x6F: /* ADD A,Rr */
735 clk++;
736 cy=ac=0;
737 dat=intRAM[reg_pnt+7];
738 if (((acc & 0x0f) + (dat & 0x0f)) > 0x0f) ac=0x40;
739 temp=acc+dat;
740 if (temp > 0xFF) cy=1;
741 acc=(temp & 0xFF);
742 break;
743 case 0x70: /* ADDC A,@Ri */
744 clk++;
745 ac=0;
746 dat=intRAM[intRAM[reg_pnt] & 0x3F];
747 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
748 temp=acc+dat+cy;
749 cy=0;
750 if (temp > 0xFF) cy=1;
751 acc=(temp & 0xFF);
752 break;
753 case 0x71: /* ADDC A,@Ri */
754 clk++;
755 ac=0;
756 dat=intRAM[intRAM[reg_pnt+1] & 0x3F];
757 if (((acc & 0x0f) + (dat & 0x0f) + cy) > 0x0f) ac=0x40;
758 temp=acc+dat+cy;
759 cy=0;
760 if (temp > 0xFF) cy=1;
761 acc=(temp & 0xFF);
762 break;
763
764 case 0x72: /* JBb address */
765 clk+=2;
766 dat=ROM(pc);
767 if (acc & 0x08)
768 pc=(pc & 0xF00) | dat;
769 else
770 pc++;
771 break;
772 case 0x73: /* ILL */
773 clk++;
774 illegal(op);
775 break;
776 case 0x74: /* CALL */
777 make_psw();
778 adr = ROM(pc) | 0x300 | A11;
779 pc++;
780 clk+=2;
781 push(pc & 0xFF);
782 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
783 pc = adr;
784 break;
785 case 0x75: /* EN CLK */
786 clk++;
787 undef(op);
788 break;
789 case 0x76: /* JF1 address */
790 clk+=2;
791 dat=ROM(pc);
792 if (f1)
793 pc=(pc & 0xF00) | dat;
794 else
795 pc++;
796 break;
797 case 0x77: /* RR A */
798 clk++;
799 dat=acc & 0x01;
800 acc = acc >> 1;
801 if (dat)
802 acc = acc | 0x80;
803 else
804 acc = acc & 0x7f;
805 break;
806
807 case 0x78: /* ADDC A,Rr */
808 clk++;
809 ac=0;
810 dat=intRAM[reg_pnt];
811 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
812 temp=acc+dat+cy;
813 cy=0;
814 if (temp > 0xFF) cy=1;
815 acc=(temp & 0xFF);
816 break;
817 case 0x79: /* ADDC A,Rr */
818 clk++;
819 ac=0;
820 dat=intRAM[reg_pnt+1];
821 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
822 temp=acc+dat+cy;
823 cy=0;
824 if (temp > 0xFF) cy=1;
825 acc=(temp & 0xFF);
826 break;
827 case 0x7A: /* ADDC A,Rr */
828 clk++;
829 ac=0;
830 dat=intRAM[reg_pnt+2];
831 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
832 temp=acc+dat+cy;
833 cy=0;
834 if (temp > 0xFF) cy=1;
835 acc=(temp & 0xFF);
836 break;
837 case 0x7B: /* ADDC A,Rr */
838 clk++;
839 ac=0;
840 dat=intRAM[reg_pnt+3];
841 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
842 temp=acc+dat+cy;
843 cy=0;
844 if (temp > 0xFF) cy=1;
845 acc=(temp & 0xFF);
846 break;
847 case 0x7C: /* ADDC A,Rr */
848 clk++;
849 ac=0;
850 dat=intRAM[reg_pnt+4];
851 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
852 temp=acc+dat+cy;
853 cy=0;
854 if (temp > 0xFF) cy=1;
855 acc=(temp & 0xFF);
856 break;
857 case 0x7D: /* ADDC A,Rr */
858 clk++;
859 ac=0;
860 dat=intRAM[reg_pnt+5];
861 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
862 temp=acc+dat+cy;
863 cy=0;
864 if (temp > 0xFF) cy=1;
865 acc=(temp & 0xFF);
866 break;
867 case 0x7E: /* ADDC A,Rr */
868 clk++;
869 ac=0;
870 dat=intRAM[reg_pnt+6];
871 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
872 temp=acc+dat+cy;
873 cy=0;
874 if (temp > 0xFF) cy=1;
875 acc=(temp & 0xFF);
876 break;
877 case 0x7F: /* ADDC A,Rr */
878 clk++;
879 ac=0;
880 dat=intRAM[reg_pnt+7];
881 if (((acc & 0x0f) + (dat & 0x0f)+cy) > 0x0f) ac=0x40;
882 temp=acc+dat+cy;
883 cy=0;
884 if (temp > 0xFF) cy=1;
885 acc=(temp & 0xFF);
886 break;
887
888 case 0x80: /* MOVX A,@Ri */
889 acc=ext_read(intRAM[reg_pnt]);
890 clk+=2;
891 break;
892 case 0x81: /* MOVX A,@Ri */
893 acc=ext_read(intRAM[reg_pnt+1]);
894 clk+=2;
895 break;
896 case 0x82: /* ILL */
897 clk++;
898 illegal(op);
899 break;
900 case 0x83: /* RET */
901 clk+=2;
902 pc = ((pull() & 0x0F) << 8);
903 pc = pc | pull();
904 break;
905 case 0x84: /* JMP */
906 pc=ROM(pc) | 0x400 | A11;
907 clk+=2;
908 break;
909 case 0x85: /* CLR F0 */
910 clk++;
911 f0=0;
912 break;
913 case 0x86: /* JNI address */
914 clk+=2;
915 dat=ROM(pc);
916 if (int_clk > 0)
917 pc=(pc & 0xF00) | dat;
918 else
919 pc++;
920 break;
921 case 0x87: /* ILL */
922 illegal(op);
923 clk++;
924 break;
925 case 0x88: /* BUS,#data */
926 clk+=2;
927 undef(op);
928 break;
929 case 0x89: /* ORL Pp,#data */
930 write_p1(p1 | ROM(pc++));
931 clk+=2;
932 break;
933 case 0x8A: /* ORL Pp,#data */
934 p2 = p2 | ROM(pc++);
935 clk+=2;
936 break;
937 case 0x8B: /* ILL */
938 illegal(op);
939 clk++;
940 break;
941 case 0x8C: /* ORLD P4,A */
942 write_PB(0,read_PB(0)|acc);
943 clk+=2;
944 break;
945 case 0x8D: /* ORLD P5,A */
946 write_PB(1,read_PB(1)|acc);
947 clk+=2;
948 break;
949 case 0x8E: /* ORLD P6,A */
950 write_PB(2,read_PB(2)|acc);
951 clk+=2;
952 break;
953 case 0x8F: /* ORLD P7,A */
954 write_PB(3,read_PB(3)|acc);
955 clk+=2;
956 break;
957 case 0x90: /* MOVX @Ri,A */
958 ext_write(acc,intRAM[reg_pnt]);
959 clk+=2;
960 break;
961 case 0x91: /* MOVX @Ri,A */
962 ext_write(acc,intRAM[reg_pnt+1]);
963 clk+=2;
964 break;
965 case 0x92: /* JBb address */
966 clk+=2;
967 dat=ROM(pc);
968 if (acc & 0x10)
969 pc=(pc & 0xF00) | dat;
970 else
971 pc++;
972 break;
973 case 0x93: /* RETR*/
974 /* printf("RETR %d\n",master_clk/22); */
975 clk+=2;
976 dat=pull();
977 pc = (dat & 0x0F) << 8;
978 cy = (dat & 0x80) >> 7;
979 ac = dat & 0x40;
980 f0 = dat & 0x20;
981 bs = dat & 0x10;
982 if (bs)
983 reg_pnt=24;
984 else
985 reg_pnt=0;
986 pc = pc | pull();
987 irq_ex=0;
988 A11=A11ff;
989 break;
990 case 0x94: /* CALL */
991 make_psw();
992 adr = ROM(pc) | 0x400 | A11;
993 pc++;
994 clk+=2;
995 push(pc & 0xFF);
996 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
997 pc = adr;
998 break;
999 case 0x95: /* CPL F0 */
1000 f0 = f0 ^ 0x20;
1001 clk++;
1002 break;
1003 case 0x96: /* JNZ address */
1004 clk+=2;
1005 dat=ROM(pc);
1006 if (acc != 0)
1007 pc=(pc & 0xF00) | dat;
1008 else
1009 pc++;
1010 break;
1011 case 0x97: /* CLR C */
1012 cy=0;
1013 clk++;
1014 break;
1015 case 0x98: /* ANL BUS,#data */
1016 clk+=2;
1017 undef(op);
1018 break;
1019 case 0x99: /* ANL Pp,#data */
1020 write_p1(p1 & ROM(pc++));
1021 clk+=2;
1022 break;
1023 case 0x9A: /* ANL Pp,#data */
1024 p2 = p2 & ROM(pc++);
1025 clk+=2;
1026 break;
1027 case 0x9B: /* ILL */
1028 illegal(op);
1029 clk++;
1030 break;
1031 case 0x9C: /* ANLD P4,A */
1032 write_PB(0,read_PB(0)&acc);
1033 clk+=2;
1034 break;
1035 case 0x9D: /* ANLD P5,A */
1036 write_PB(1,read_PB(1)&acc);
1037 clk+=2;
1038 break;
1039 case 0x9E: /* ANLD P6,A */
1040 write_PB(2,read_PB(2)&acc);
1041 clk+=2;
1042 break;
1043 case 0x9F: /* ANLD P7,A */
1044 write_PB(3,read_PB(3)&acc);
1045 clk+=2;
1046 break;
1047 case 0xA0: /* MOV @Ri,A */
1048 intRAM[intRAM[reg_pnt] & 0x3F]=acc;
1049 clk++;
1050 break;
1051 case 0xA1: /* MOV @Ri,A */
1052 intRAM[intRAM[reg_pnt+1] & 0x3F]=acc;
1053 clk++;
1054 break;
1055 case 0xA2: /* ILL */
1056 clk++;
1057 illegal(op);
1058 break;
1059 case 0xA3: /* MOVP A,@A */
1060 acc=ROM((pc & 0xF00) | acc);
1061 clk+=2;
1062 break;
1063 case 0xA4: /* JMP */
1064 pc=ROM(pc) | 0x500 | A11;
1065 clk+=2;
1066 break;
1067 case 0xA5: /* CLR F1 */
1068 clk++;
1069 f1=0;
1070 break;
1071 case 0xA6: /* ILL */
1072 illegal(op);
1073 clk++;
1074 break;
1075 case 0xA7: /* CPL C */
1076 cy = cy ^ 0x01;
1077 clk++;
1078 break;
1079 case 0xA8: /* MOV Rr,A */
1080 intRAM[reg_pnt] = acc;
1081 clk++;
1082 break;
1083 case 0xA9: /* MOV Rr,A */
1084 intRAM[reg_pnt+1] = acc;
1085 clk++;
1086 break;
1087 case 0xAA: /* MOV Rr,A */
1088 intRAM[reg_pnt+2] = acc;
1089 clk++;
1090 break;
1091 case 0xAB: /* MOV Rr,A */
1092 intRAM[reg_pnt+3] = acc;
1093 clk++;
1094 break;
1095 case 0xAC: /* MOV Rr,A */
1096 intRAM[reg_pnt+4] = acc;
1097 clk++;
1098 break;
1099 case 0xAD: /* MOV Rr,A */
1100 intRAM[reg_pnt+5] = acc;
1101 clk++;
1102 break;
1103 case 0xAE: /* MOV Rr,A */
1104 intRAM[reg_pnt+6] = acc;
1105 clk++;
1106 break;
1107 case 0xAF: /* MOV Rr,A */
1108 intRAM[reg_pnt+7] = acc;
1109 clk++;
1110 break;
1111 case 0xB0: /* MOV @Ri,#data */
1112 intRAM[intRAM[reg_pnt] & 0x3F]=ROM(pc++);
1113 clk+=2;
1114 break;
1115 case 0xB1: /* MOV @Ri,#data */
1116 intRAM[intRAM[reg_pnt+1] & 0x3F]=ROM(pc++);
1117 clk+=2;
1118 break;
1119 case 0xB2: /* JBb address */
1120 clk+=2;
1121 dat=ROM(pc);
1122 if (acc & 0x20)
1123 pc=(pc & 0xF00) | dat;
1124 else
1125 pc++;
1126 break;
1127 case 0xB3: /* JMPP @A */
1128 adr = (pc & 0xF00) | acc;
1129 pc=(pc & 0xF00) | ROM(adr);
1130 clk+=2;
1131 break;
1132 case 0xB4: /* CALL */
1133 make_psw();
1134 adr = ROM(pc) | 0x500 | A11;
1135 pc++;
1136 clk+=2;
1137 push(pc & 0xFF);
1138 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
1139 pc = adr;
1140 break;
1141 case 0xB5: /* CPL F1 */
1142 f1 = f1 ^ 0x01;
1143 clk++;
1144 break;
1145 case 0xB6: /* JF0 address */
1146 clk+=2;
1147 dat=ROM(pc);
1148 if (f0)
1149 pc=(pc & 0xF00) | dat;
1150 else
1151 pc++;
1152 break;
1153 case 0xB7: /* ILL */
1154 clk++;
1155 illegal(op);
1156 break;
1157 case 0xB8: /* MOV Rr,#data */
1158 intRAM[reg_pnt]=ROM(pc++);
1159 clk+=2;
1160 break;
1161 case 0xB9: /* MOV Rr,#data */
1162 intRAM[reg_pnt+1]=ROM(pc++);
1163 clk+=2;
1164 break;
1165 case 0xBA: /* MOV Rr,#data */
1166 intRAM[reg_pnt+2]=ROM(pc++);
1167 clk+=2;
1168 break;
1169 case 0xBB: /* MOV Rr,#data */
1170 intRAM[reg_pnt+3]=ROM(pc++);
1171 clk+=2;
1172 break;
1173 case 0xBC: /* MOV Rr,#data */
1174 intRAM[reg_pnt+4]=ROM(pc++);
1175 clk+=2;
1176 break;
1177 case 0xBD: /* MOV Rr,#data */
1178 intRAM[reg_pnt+5]=ROM(pc++);
1179 clk+=2;
1180 break;
1181 case 0xBE: /* MOV Rr,#data */
1182 intRAM[reg_pnt+6]=ROM(pc++);
1183 clk+=2;
1184 break;
1185 case 0xBF: /* MOV Rr,#data */
1186 intRAM[reg_pnt+7]=ROM(pc++);
1187 clk+=2;
1188 break;
1189 case 0xC0: /* ILL */
1190 illegal(op);
1191 clk++;
1192 break;
1193 case 0xC1: /* ILL */
1194 illegal(op);
1195 clk++;
1196 break;
1197 case 0xC2: /* ILL */
1198 illegal(op);
1199 clk++;
1200 break;
1201 case 0xC3: /* ILL */
1202 illegal(op);
1203 clk++;
1204 break;
1205 case 0xC4: /* JMP */
1206 pc=ROM(pc) | 0x600 | A11;
1207 clk+=2;
1208 break;
1209 case 0xC5: /* SEL RB0 */
1210 bs=reg_pnt=0;
1211 clk++;
1212 break;
1213 case 0xC6: /* JZ address */
1214 clk+=2;
1215 dat=ROM(pc);
1216 if (acc == 0)
1217 pc=(pc & 0xF00) | dat;
1218 else
1219 pc++;
1220 break;
1221 case 0xC7: /* MOV A,PSW */
1222 clk++;
1223 make_psw();
1224 acc=psw;
1225 break;
1226 case 0xC8: /* DEC Rr */
1227 intRAM[reg_pnt]--;
1228 clk++;
1229 break;
1230 case 0xC9: /* DEC Rr */
1231 intRAM[reg_pnt+1]--;
1232 clk++;
1233 break;
1234 case 0xCA: /* DEC Rr */
1235 intRAM[reg_pnt+2]--;
1236 clk++;
1237 break;
1238 case 0xCB: /* DEC Rr */
1239 intRAM[reg_pnt+3]--;
1240 clk++;
1241 break;
1242 case 0xCC: /* DEC Rr */
1243 intRAM[reg_pnt+4]--;
1244 clk++;
1245 break;
1246 case 0xCD: /* DEC Rr */
1247 intRAM[reg_pnt+5]--;
1248 clk++;
1249 break;
1250 case 0xCE: /* DEC Rr */
1251 intRAM[reg_pnt+6]--;
1252 clk++;
1253 break;
1254 case 0xCF: /* DEC Rr */
1255 intRAM[reg_pnt+7]--;
1256 clk++;
1257 break;
1258 case 0xD0: /* XRL A,@Ri */
1259 acc = acc ^ intRAM[intRAM[reg_pnt] & 0x3F];
1260 clk++;
1261 break;
1262 case 0xD1: /* XRL A,@Ri */
1263 acc = acc ^ intRAM[intRAM[reg_pnt+1] & 0x3F];
1264 clk++;
1265 break;
1266 case 0xD2: /* JBb address */
1267 clk+=2;
1268 dat = ROM(pc);
1269 if (acc & 0x40)
1270 pc=(pc & 0xF00) | dat;
1271 else
1272 pc++;
1273 break;
1274 case 0xD3: /* XRL A,#data */
1275 clk+=2;
1276 acc = acc ^ ROM(pc++);
1277 break;
1278 case 0xD4: /* CALL */
1279 make_psw();
1280 adr = ROM(pc) | 0x600 | A11;
1281 pc++;
1282 clk+=2;
1283 push(pc & 0xFF);
1284 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
1285 pc = adr;
1286 break;
1287 case 0xD5: /* SEL RB1 */
1288 bs=0x10;
1289 reg_pnt=24;
1290 clk++;
1291 break;
1292 case 0xD6: /* ILL */
1293 illegal(op);
1294 clk++;
1295 break;
1296 case 0xD7: /* MOV PSW,A */
1297 psw=acc;
1298 clk++;
1299 cy = (psw & 0x80) >> 7;
1300 ac = psw & 0x40;
1301 f0 = psw & 0x20;
1302 bs = psw & 0x10;
1303 if (bs)
1304 reg_pnt = 24;
1305 else
1306 reg_pnt = 0;
1307 sp = (psw & 0x07) << 1;
1308 sp+=8;
1309 break;
1310 case 0xD8: /* XRL A,Rr */
1311 acc = acc ^ intRAM[reg_pnt];
1312 clk++;
1313 break;
1314 case 0xD9: /* XRL A,Rr */
1315 acc = acc ^ intRAM[reg_pnt+1];
1316 clk++;
1317 break;
1318 case 0xDA: /* XRL A,Rr */
1319 acc = acc ^ intRAM[reg_pnt+2];
1320 clk++;
1321 break;
1322 case 0xDB: /* XRL A,Rr */
1323 acc = acc ^ intRAM[reg_pnt+3];
1324 clk++;
1325 break;
1326 case 0xDC: /* XRL A,Rr */
1327 acc = acc ^ intRAM[reg_pnt+4];
1328 clk++;
1329 break;
1330 case 0xDD: /* XRL A,Rr */
1331 acc = acc ^ intRAM[reg_pnt+5];
1332 clk++;
1333 break;
1334 case 0xDE: /* XRL A,Rr */
1335 acc = acc ^ intRAM[reg_pnt+6];
1336 clk++;
1337 break;
1338 case 0xDF: /* XRL A,Rr */
1339 acc = acc ^ intRAM[reg_pnt+7];
1340 clk++;
1341 break;
1342 case 0xE0: /* ILL */
1343 clk++;
1344 illegal(op);
1345 break;
1346 case 0xE1: /* ILL */
1347 clk++;
1348 illegal(op);
1349 break;
1350 case 0xE2: /* ILL */
1351 clk++;
1352 illegal(op);
1353 break;
1354 case 0xE3: /* MOVP3 A,@A */
1355
1356 adr = 0x300 | acc;
1357 acc=ROM(adr);
1358 clk+=2;
1359 break;
1360 case 0xE4: /* JMP */
1361 pc=ROM(pc) | 0x700 | A11;
1362 clk+=2;
1363 break;
1364 case 0xE5: /* SEL MB0 */
1365 A11=0;
1366 A11ff = 0;
1367 clk++;
1368 break;
1369 case 0xE6: /* JNC address */
1370 clk+=2;
1371 dat=ROM(pc);
1372 if (!cy)
1373 pc=(pc & 0xF00) | dat;
1374 else
1375 pc++;
1376 break;
1377 case 0xE7: /* RL A */
1378 clk++;
1379 dat=acc & 0x80;
1380 acc = acc << 1;
1381 if (dat)
1382 acc = acc | 0x01;
1383 else
1384 acc = acc & 0xFE;
1385 break;
1386 case 0xE8: /* DJNZ Rr,address */
1387 clk+=2;
1388 intRAM[reg_pnt]--;
1389 dat=ROM(pc);
1390 if (intRAM[reg_pnt] != 0) {
1391 pc = pc & 0xF00;
1392 pc = pc | dat;
1393 } else pc++;
1394 break;
1395 case 0xE9: /* DJNZ Rr,address */
1396 clk+=2;
1397 intRAM[reg_pnt+1]--;
1398 dat=ROM(pc);
1399 if (intRAM[reg_pnt+1] != 0) {
1400 pc = pc & 0xF00;
1401 pc = pc | dat;
1402 } else pc++;
1403 break;
1404 case 0xEA: /* DJNZ Rr,address */
1405 clk+=2;
1406 intRAM[reg_pnt+2]--;
1407 dat=ROM(pc);
1408 if (intRAM[reg_pnt+2] != 0) {
1409 pc = pc & 0xF00;
1410 pc = pc | dat;
1411 } else pc++;
1412 break;
1413 case 0xEB: /* DJNZ Rr,address */
1414 clk+=2;
1415 intRAM[reg_pnt+3]--;
1416 dat=ROM(pc);
1417 if (intRAM[reg_pnt+3] != 0) {
1418 pc = pc & 0xF00;
1419 pc = pc | dat;
1420 } else pc++;
1421 break;
1422 case 0xEC: /* DJNZ Rr,address */
1423 clk+=2;
1424 intRAM[reg_pnt+4]--;
1425 dat=ROM(pc);
1426 if (intRAM[reg_pnt+4] != 0) {
1427 pc = pc & 0xF00;
1428 pc = pc | dat;
1429 } else pc++;
1430 break;
1431 case 0xED: /* DJNZ Rr,address */
1432 clk+=2;
1433 intRAM[reg_pnt+5]--;
1434 dat=ROM(pc);
1435 if (intRAM[reg_pnt+5] != 0) {
1436 pc = pc & 0xF00;
1437 pc = pc | dat;
1438 } else pc++;
1439 break;
1440 case 0xEE: /* DJNZ Rr,address */
1441 clk+=2;
1442 intRAM[reg_pnt+6]--;
1443 dat=ROM(pc);
1444 if (intRAM[reg_pnt+6] != 0) {
1445 pc = pc & 0xF00;
1446 pc = pc | dat;
1447 } else pc++;
1448 break;
1449 case 0xEF: /* DJNZ Rr,address */
1450 clk+=2;
1451 intRAM[reg_pnt+7]--;
1452 dat=ROM(pc);
1453 if (intRAM[reg_pnt+7] != 0) {
1454 pc = pc & 0xF00;
1455 pc = pc | dat;
1456 } else pc++;
1457 break;
1458 case 0xF0: /* MOV A,@Ri */
1459 clk++;
1460 acc=intRAM[intRAM[reg_pnt] & 0x3F];
1461 break;
1462 case 0xF1: /* MOV A,@Ri */
1463 clk++;
1464 acc=intRAM[intRAM[reg_pnt + 1] & 0x3F];
1465 break;
1466 case 0xF2: /* JBb address */
1467 clk+=2;
1468 dat=ROM(pc);
1469 if (acc & 0x80)
1470 pc=(pc & 0xF00) | dat;
1471 else
1472 pc++;
1473 break;
1474 case 0xF3: /* ILL */
1475 illegal(op);
1476 clk++;
1477 break;
1478 case 0xF4: /* CALL */
1479 clk+=2;
1480 make_psw();
1481 adr = ROM(pc) | 0x700 | A11;
1482 pc++;
1483 push(pc & 0xFF);
1484 push(((pc & 0xF00) >> 8) | (psw & 0xF0));
1485 pc = adr;
1486 break;
1487 case 0xF5: /* SEL MB1 */
1488 if (irq_ex) {
1489 A11ff = 0x800;
1490 }
1491 else
1492 {
1493 A11=0x800;
1494 A11ff = 0x800;
1495 }
1496 clk++;
1497 break;
1498 case 0xF6: /* JC address */
1499 clk+=2;
1500 dat=ROM(pc);
1501 if (cy)
1502 pc=(pc & 0xF00) | dat;
1503 else
1504 pc++;
1505 break;
1506 case 0xF7: /* RLC A */
1507 dat=cy;
1508 cy=(acc & 0x80) >> 7;
1509 acc = acc << 1;
1510 if (dat)
1511 acc = acc | 0x01;
1512 else
1513 acc = acc & 0xFE;
1514 clk++;
1515 break;
1516 case 0xF8: /* MOV A,Rr */
1517 clk++;
1518 acc = intRAM[reg_pnt];
1519 break;
1520 case 0xF9: /* MOV A,Rr */
1521 clk++;
1522 acc = intRAM[reg_pnt + 1];
1523 break;
1524 case 0xFA: /* MOV A,Rr */
1525 clk++;
1526 acc = intRAM[reg_pnt + 2];
1527 break;
1528 case 0xFB: /* MOV A,Rr */
1529 clk++;
1530 acc = intRAM[reg_pnt + 3];
1531 break;
1532 case 0xFC: /* MOV A,Rr */
1533 clk++;
1534 acc = intRAM[reg_pnt + 4];
1535 break;
1536 case 0xFD: /* MOV A,Rr */
1537 clk++;
1538 acc = intRAM[reg_pnt + 5];
1539 break;
1540 case 0xFE: /* MOV A,Rr */
1541 clk++;
1542 acc = intRAM[reg_pnt + 6];
1543 break;
1544 case 0xFF: /* MOV A,Rr */
1545 clk++;
1546 acc = intRAM[reg_pnt + 7];
1547 break;
1548 }
1549
1550
1551 master_clk+=clk;
1552 h_clk+=clk;
1553 clk_counter+=clk;
1554
1555 /* flag for JNI */
1556 if (int_clk > clk)
1557 int_clk -= clk;
1558 else
1559 int_clk = 0;
1560
1561 /* pending IRQs */
1562 if (xirq_pend) ext_IRQ();
1563 if (tirq_pend) tim_IRQ();
1564
1565 if (h_clk > LINECNT-1) {
1566 h_clk-=LINECNT;
1567 if (enahirq && (VDCwrite[0xA0] & 0x01)) ext_IRQ();
1568 if (count_on && mstate == 0) {
1569 itimer++;
1570 if (itimer == 0) {
1571 t_flag=1;
1572 tim_IRQ();
1573 draw_region();
1574 }
1575 }
1576 }
1577
1578 if (timer_on) {
1579 master_count+=clk;
1580 if (master_count > 31) {
1581 master_count-=31;
1582 itimer++;
1583 if (itimer == 0) {
1584 t_flag=1;
1585 tim_IRQ();
1586 }
1587 }
1588 }
1589
1590 if ((mstate==0) && (master_clk > VBLCLK)) handle_vbl();
1591
1592 if ((mstate==1) && (master_clk > evblclk)) {
1593 handle_evbl();
1594 break;
1595 }
1596
1597 if (app_data.debug) break;
1598 }
1599
1600 }
1601
1602