1 // Copyright (c) 2012- PPSSPP Project. 2 3 // This program is free software: you can redistribute it and/or modify 4 // it under the terms of the GNU General Public License as published by 5 // the Free Software Foundation, version 2.0 or later versions. 6 7 // This program is distributed in the hope that it will be useful, 8 // but WITHOUT ANY WARRANTY; without even the implied warranty of 9 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 // GNU General Public License 2.0 for more details. 11 12 // A copy of the GPL 2.0 should have been included with the program. 13 // If not, see http://www.gnu.org/licenses/ 14 15 // Official git repository and contact information can be found at 16 // https://github.com/hrydgard/ppsspp and http://www.ppsspp.org/. 17 18 #include "ppsspp_config.h" 19 #if PPSSPP_ARCH(ARM) 20 21 #include <cmath> 22 #include "Common/CPUDetect.h" 23 #include "Common/Data/Convert/SmallDataConvert.h" 24 #include "Common/Math/math_util.h" 25 26 #include "Core/Compatibility.h" 27 #include "Core/Config.h" 28 #include "Core/MemMap.h" 29 #include "Core/Reporting.h" 30 #include "Core/System.h" 31 #include "Core/MIPS/MIPS.h" 32 #include "Core/MIPS/MIPSTables.h" 33 #include "Core/MIPS/MIPSAnalyst.h" 34 #include "Core/MIPS/MIPSCodeUtils.h" 35 36 #include "Core/MIPS/ARM/ArmJit.h" 37 #include "Core/MIPS/ARM/ArmRegCache.h" 38 39 // Cool NEON references: 40 // http://www.delmarnorth.com/microwave/requirements/neon-test-tutorial.pdf 41 42 // All functions should have CONDITIONAL_DISABLE, so we can narrow things down to a file quickly. 43 // Currently known non working ones should have DISABLE. 44 45 // #define CONDITIONAL_DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; } 46 #define CONDITIONAL_DISABLE(flag) if (jo.Disabled(JitDisable::flag)) { Comp_Generic(op); return; } 47 #define DISABLE { fpr.ReleaseSpillLocksAndDiscardTemps(); Comp_Generic(op); return; } 48 49 #define NEON_IF_AVAILABLE(func) { if (jo.useNEONVFPU) { func(op); return; } } 50 #define _RS MIPS_GET_RS(op) 51 #define _RT MIPS_GET_RT(op) 52 #define _RD MIPS_GET_RD(op) 53 #define _FS MIPS_GET_FS(op) 54 #define _FT MIPS_GET_FT(op) 55 #define _FD MIPS_GET_FD(op) 56 #define _SA MIPS_GET_SA(op) 57 #define _POS ((op>> 6) & 0x1F) 58 #define _SIZE ((op>>11) & 0x1F) 59 #define _IMM16 (signed short)(op & 0xFFFF) 60 #define _IMM26 (op & 0x03FFFFFF) 61 62 namespace MIPSComp 63 { 64 using namespace ArmGen; 65 using namespace ArmJitConstants; 66 67 // Vector regs can overlap in all sorts of swizzled ways. 68 // This does allow a single overlap in sregs[i]. IsOverlapSafeAllowS(int dreg,int di,int sn,u8 sregs[],int tn=0,u8 tregs[]=NULL)69 static bool IsOverlapSafeAllowS(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL) 70 { 71 for (int i = 0; i < sn; ++i) 72 { 73 if (sregs[i] == dreg && i != di) 74 return false; 75 } 76 for (int i = 0; i < tn; ++i) 77 { 78 if (tregs[i] == dreg) 79 return false; 80 } 81 82 // Hurray, no overlap, we can write directly. 83 return true; 84 } 85 IsOverlapSafe(int dreg,int di,int sn,u8 sregs[],int tn=0,u8 tregs[]=NULL)86 static bool IsOverlapSafe(int dreg, int di, int sn, u8 sregs[], int tn = 0, u8 tregs[] = NULL) 87 { 88 return IsOverlapSafeAllowS(dreg, di, sn, sregs, tn, tregs) && sregs[di] != dreg; 89 } 90 Comp_VPFX(MIPSOpcode op)91 void ArmJit::Comp_VPFX(MIPSOpcode op) 92 { 93 CONDITIONAL_DISABLE(VFPU_XFER); 94 int data = op & 0xFFFFF; 95 int regnum = (op >> 24) & 3; 96 switch (regnum) { 97 case 0: // S 98 js.prefixS = data; 99 js.prefixSFlag = JitState::PREFIX_KNOWN_DIRTY; 100 break; 101 case 1: // T 102 js.prefixT = data; 103 js.prefixTFlag = JitState::PREFIX_KNOWN_DIRTY; 104 break; 105 case 2: // D 106 js.prefixD = data & 0x00000FFF; 107 js.prefixDFlag = JitState::PREFIX_KNOWN_DIRTY; 108 break; 109 default: 110 ERROR_LOG(CPU, "VPFX - bad regnum %i : data=%08x", regnum, data); 111 break; 112 } 113 } 114 ApplyPrefixST(u8 * vregs,u32 prefix,VectorSize sz)115 void ArmJit::ApplyPrefixST(u8 *vregs, u32 prefix, VectorSize sz) { 116 if (prefix == 0xE4) 117 return; 118 119 int n = GetNumVectorElements(sz); 120 u8 origV[4]; 121 static const float constantArray[8] = {0.f, 1.f, 2.f, 0.5f, 3.f, 1.f/3.f, 0.25f, 1.f/6.f}; 122 123 for (int i = 0; i < n; i++) 124 origV[i] = vregs[i]; 125 126 for (int i = 0; i < n; i++) { 127 int regnum = (prefix >> (i*2)) & 3; 128 int abs = (prefix >> (8+i)) & 1; 129 int negate = (prefix >> (16+i)) & 1; 130 int constants = (prefix >> (12+i)) & 1; 131 132 // Unchanged, hurray. 133 if (!constants && regnum == i && !abs && !negate) 134 continue; 135 136 // This puts the value into a temp reg, so we won't write the modified value back. 137 vregs[i] = fpr.GetTempV(); 138 if (!constants) { 139 fpr.MapDirtyInV(vregs[i], origV[regnum]); 140 fpr.SpillLockV(vregs[i]); 141 142 // Prefix may say "z, z, z, z" but if this is a pair, we force to x. 143 // TODO: But some ops seem to use const 0 instead? 144 if (regnum >= n) { 145 WARN_LOG(CPU, "JIT: Invalid VFPU swizzle: %08x : %d / %d at PC = %08x (%s)", prefix, regnum, n, GetCompilerPC(), MIPSDisasmAt(GetCompilerPC())); 146 regnum = 0; 147 } 148 149 if (abs) { 150 VABS(fpr.V(vregs[i]), fpr.V(origV[regnum])); 151 if (negate) 152 VNEG(fpr.V(vregs[i]), fpr.V(vregs[i])); 153 } else { 154 if (negate) 155 VNEG(fpr.V(vregs[i]), fpr.V(origV[regnum])); 156 else 157 VMOV(fpr.V(vregs[i]), fpr.V(origV[regnum])); 158 } 159 } else { 160 fpr.MapRegV(vregs[i], MAP_DIRTY | MAP_NOINIT); 161 fpr.SpillLockV(vregs[i]); 162 MOVI2F(fpr.V(vregs[i]), constantArray[regnum + (abs<<2)], SCRATCHREG1, negate != 0); 163 } 164 } 165 } 166 GetVectorRegsPrefixD(u8 * regs,VectorSize sz,int vectorReg)167 void ArmJit::GetVectorRegsPrefixD(u8 *regs, VectorSize sz, int vectorReg) { 168 _assert_(js.prefixDFlag & JitState::PREFIX_KNOWN); 169 170 GetVectorRegs(regs, sz, vectorReg); 171 if (js.prefixD == 0) 172 return; 173 174 int n = GetNumVectorElements(sz); 175 for (int i = 0; i < n; i++) { 176 // Hopefully this is rare, we'll just write it into a reg we drop. 177 if (js.VfpuWriteMask(i)) 178 regs[i] = fpr.GetTempV(); 179 } 180 } 181 ApplyPrefixD(const u8 * vregs,VectorSize sz)182 void ArmJit::ApplyPrefixD(const u8 *vregs, VectorSize sz) { 183 _assert_(js.prefixDFlag & JitState::PREFIX_KNOWN); 184 if (!js.prefixD) 185 return; 186 187 int n = GetNumVectorElements(sz); 188 for (int i = 0; i < n; i++) { 189 if (js.VfpuWriteMask(i)) 190 continue; 191 192 int sat = (js.prefixD >> (i * 2)) & 3; 193 if (sat == 1) { 194 // clamped = x < 0 ? (x > 1 ? 1 : x) : x [0, 1] 195 fpr.MapRegV(vregs[i], MAP_DIRTY); 196 197 MOVI2F(S0, 0.0f, SCRATCHREG1); 198 MOVI2F(S1, 1.0f, SCRATCHREG1); 199 VCMP(fpr.V(vregs[i]), S0); 200 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 201 SetCC(CC_LS); 202 VMOV(fpr.V(vregs[i]), S0); 203 SetCC(CC_AL); 204 VCMP(fpr.V(vregs[i]), S1); 205 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 206 SetCC(CC_GT); 207 VMOV(fpr.V(vregs[i]), S1); 208 SetCC(CC_AL); 209 } else if (sat == 3) { 210 // clamped = x < -1 ? (x > 1 ? 1 : x) : x [-1, 1] 211 fpr.MapRegV(vregs[i], MAP_DIRTY); 212 213 MOVI2F(S0, -1.0f, SCRATCHREG1); 214 MOVI2F(S1, 1.0f, SCRATCHREG1); 215 VCMP(fpr.V(vregs[i]), S0); 216 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 217 SetCC(CC_LO); 218 VMOV(fpr.V(vregs[i]), S0); 219 SetCC(CC_AL); 220 VCMP(fpr.V(vregs[i]), S1); 221 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 222 SetCC(CC_GT); 223 VMOV(fpr.V(vregs[i]), S1); 224 SetCC(CC_AL); 225 } 226 } 227 } 228 Comp_SV(MIPSOpcode op)229 void ArmJit::Comp_SV(MIPSOpcode op) { 230 NEON_IF_AVAILABLE(CompNEON_SV); 231 CONDITIONAL_DISABLE(LSU_VFPU); 232 CheckMemoryBreakpoint(); 233 234 s32 offset = (signed short)(op & 0xFFFC); 235 int vt = ((op >> 16) & 0x1f) | ((op & 3) << 5); 236 MIPSGPReg rs = _RS; 237 238 bool doCheck = false; 239 switch (op >> 26) 240 { 241 case 50: //lv.s // VI(vt) = Memory::Read_U32(addr); 242 { 243 if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) { 244 gpr.MapRegAsPointer(rs); 245 fpr.MapRegV(vt, MAP_NOINIT | MAP_DIRTY); 246 VLDR(fpr.V(vt), gpr.RPtr(rs), offset); 247 break; 248 } 249 250 // CC might be set by slow path below, so load regs first. 251 fpr.MapRegV(vt, MAP_DIRTY | MAP_NOINIT); 252 if (gpr.IsImm(rs)) { 253 u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF; 254 gpr.SetRegImm(R0, addr + (u32)Memory::base); 255 } else { 256 gpr.MapReg(rs); 257 if (g_Config.bFastMemory) { 258 SetR0ToEffectiveAddress(rs, offset); 259 } else { 260 SetCCAndR0ForSafeAddress(rs, offset, SCRATCHREG2); 261 doCheck = true; 262 } 263 ADD(R0, R0, MEMBASEREG); 264 } 265 #ifdef __ARM_ARCH_7S__ 266 FixupBranch skip; 267 if (doCheck) { 268 skip = B_CC(CC_EQ); 269 } 270 VLDR(fpr.V(vt), R0, 0); 271 if (doCheck) { 272 SetJumpTarget(skip); 273 SetCC(CC_AL); 274 } 275 #else 276 VLDR(fpr.V(vt), R0, 0); 277 if (doCheck) { 278 SetCC(CC_EQ); 279 MOVI2F(fpr.V(vt), 0.0f, SCRATCHREG1); 280 SetCC(CC_AL); 281 } 282 #endif 283 } 284 break; 285 286 case 58: //sv.s // Memory::Write_U32(VI(vt), addr); 287 { 288 if (!gpr.IsImm(rs) && jo.cachePointers && g_Config.bFastMemory && (offset & 3) == 0 && offset < 0x400 && offset > -0x400) { 289 gpr.MapRegAsPointer(rs); 290 fpr.MapRegV(vt, 0); 291 VSTR(fpr.V(vt), gpr.RPtr(rs), offset); 292 break; 293 } 294 295 // CC might be set by slow path below, so load regs first. 296 fpr.MapRegV(vt); 297 if (gpr.IsImm(rs)) { 298 u32 addr = (offset + gpr.GetImm(rs)) & 0x3FFFFFFF; 299 gpr.SetRegImm(R0, addr + (u32)Memory::base); 300 } else { 301 gpr.MapReg(rs); 302 if (g_Config.bFastMemory) { 303 SetR0ToEffectiveAddress(rs, offset); 304 } else { 305 SetCCAndR0ForSafeAddress(rs, offset, SCRATCHREG2); 306 doCheck = true; 307 } 308 ADD(R0, R0, MEMBASEREG); 309 } 310 #ifdef __ARM_ARCH_7S__ 311 FixupBranch skip; 312 if (doCheck) { 313 skip = B_CC(CC_EQ); 314 } 315 VSTR(fpr.V(vt), R0, 0); 316 if (doCheck) { 317 SetJumpTarget(skip); 318 SetCC(CC_AL); 319 } 320 #else 321 VSTR(fpr.V(vt), R0, 0); 322 if (doCheck) { 323 SetCC(CC_AL); 324 } 325 #endif 326 } 327 break; 328 329 330 default: 331 DISABLE; 332 } 333 } 334 Comp_SVQ(MIPSOpcode op)335 void ArmJit::Comp_SVQ(MIPSOpcode op) 336 { 337 NEON_IF_AVAILABLE(CompNEON_SVQ); 338 CONDITIONAL_DISABLE(LSU_VFPU); 339 CheckMemoryBreakpoint(); 340 341 int imm = (signed short)(op&0xFFFC); 342 int vt = (((op >> 16) & 0x1f)) | ((op&1) << 5); 343 MIPSGPReg rs = _RS; 344 345 bool doCheck = false; 346 switch (op >> 26) 347 { 348 case 54: //lv.q 349 { 350 // CC might be set by slow path below, so load regs first. 351 u8 vregs[4]; 352 GetVectorRegs(vregs, V_Quad, vt); 353 fpr.MapRegsAndSpillLockV(vregs, V_Quad, MAP_DIRTY | MAP_NOINIT); 354 355 if (gpr.IsImm(rs)) { 356 u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF; 357 gpr.SetRegImm(R0, addr + (u32)Memory::base); 358 } else { 359 gpr.MapReg(rs); 360 if (g_Config.bFastMemory) { 361 SetR0ToEffectiveAddress(rs, imm); 362 } else { 363 SetCCAndR0ForSafeAddress(rs, imm, SCRATCHREG2); 364 doCheck = true; 365 } 366 ADD(R0, R0, MEMBASEREG); 367 } 368 369 #ifdef __ARM_ARCH_7S__ 370 FixupBranch skip; 371 if (doCheck) { 372 skip = B_CC(CC_EQ); 373 } 374 375 bool consecutive = true; 376 for (int i = 0; i < 3 && consecutive; i++) 377 if ((fpr.V(vregs[i]) + 1) != fpr.V(vregs[i+1])) 378 consecutive = false; 379 if (consecutive) { 380 VLDMIA(R0, false, fpr.V(vregs[0]), 4); 381 } else { 382 for (int i = 0; i < 4; i++) 383 VLDR(fpr.V(vregs[i]), R0, i * 4); 384 } 385 386 if (doCheck) { 387 SetJumpTarget(skip); 388 SetCC(CC_AL); 389 } 390 #else 391 bool consecutive = true; 392 for (int i = 0; i < 3 && consecutive; i++) 393 if ((fpr.V(vregs[i]) + 1) != fpr.V(vregs[i+1])) 394 consecutive = false; 395 if (consecutive) { 396 VLDMIA(R0, false, fpr.V(vregs[0]), 4); 397 } else { 398 for (int i = 0; i < 4; i++) 399 VLDR(fpr.V(vregs[i]), R0, i * 4); 400 } 401 402 if (doCheck) { 403 SetCC(CC_EQ); 404 MOVI2R(SCRATCHREG1, 0); 405 for (int i = 0; i < 4; i++) 406 VMOV(fpr.V(vregs[i]), SCRATCHREG1); 407 SetCC(CC_AL); 408 } 409 #endif 410 } 411 break; 412 413 case 62: //sv.q 414 { 415 // CC might be set by slow path below, so load regs first. 416 u8 vregs[4]; 417 GetVectorRegs(vregs, V_Quad, vt); 418 fpr.MapRegsAndSpillLockV(vregs, V_Quad, 0); 419 420 if (gpr.IsImm(rs)) { 421 u32 addr = (imm + gpr.GetImm(rs)) & 0x3FFFFFFF; 422 gpr.SetRegImm(R0, addr + (u32)Memory::base); 423 } else { 424 gpr.MapReg(rs); 425 if (g_Config.bFastMemory) { 426 SetR0ToEffectiveAddress(rs, imm); 427 } else { 428 SetCCAndR0ForSafeAddress(rs, imm, SCRATCHREG2); 429 doCheck = true; 430 } 431 ADD(R0, R0, MEMBASEREG); 432 } 433 434 #ifdef __ARM_ARCH_7S__ 435 FixupBranch skip; 436 if (doCheck) { 437 skip = B_CC(CC_EQ); 438 } 439 440 bool consecutive = true; 441 for (int i = 0; i < 3 && consecutive; i++) 442 if ((fpr.V(vregs[i]) + 1) != fpr.V(vregs[i+1])) 443 consecutive = false; 444 if (consecutive) { 445 VSTMIA(R0, false, fpr.V(vregs[0]), 4); 446 } else { 447 for (int i = 0; i < 4; i++) 448 VSTR(fpr.V(vregs[i]), R0, i * 4); 449 } 450 451 if (doCheck) { 452 SetJumpTarget(skip); 453 SetCC(CC_AL); 454 } 455 #else 456 bool consecutive = true; 457 for (int i = 0; i < 3 && consecutive; i++) 458 if ((fpr.V(vregs[i]) + 1) != fpr.V(vregs[i+1])) 459 consecutive = false; 460 if (consecutive) { 461 VSTMIA(R0, false, fpr.V(vregs[0]), 4); 462 } else { 463 for (int i = 0; i < 4; i++) 464 VSTR(fpr.V(vregs[i]), R0, i * 4); 465 } 466 467 if (doCheck) { 468 SetCC(CC_AL); 469 } 470 #endif 471 } 472 break; 473 474 default: 475 DISABLE; 476 break; 477 } 478 fpr.ReleaseSpillLocksAndDiscardTemps(); 479 } 480 Comp_VVectorInit(MIPSOpcode op)481 void ArmJit::Comp_VVectorInit(MIPSOpcode op) 482 { 483 NEON_IF_AVAILABLE(CompNEON_VVectorInit); 484 CONDITIONAL_DISABLE(VFPU_XFER); 485 // WARNING: No prefix support! 486 if (js.HasUnknownPrefix()) { 487 DISABLE; 488 } 489 490 switch ((op >> 16) & 0xF) 491 { 492 case 6: // v=zeros; break; //vzero 493 MOVI2F(S0, 0.0f, SCRATCHREG1); 494 break; 495 case 7: // v=ones; break; //vone 496 MOVI2F(S0, 1.0f, SCRATCHREG1); 497 break; 498 default: 499 DISABLE; 500 break; 501 } 502 503 VectorSize sz = GetVecSize(op); 504 int n = GetNumVectorElements(sz); 505 506 u8 dregs[4]; 507 GetVectorRegsPrefixD(dregs, sz, _VD); 508 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_NOINIT | MAP_DIRTY); 509 510 for (int i = 0; i < n; ++i) 511 VMOV(fpr.V(dregs[i]), S0); 512 513 ApplyPrefixD(dregs, sz); 514 515 fpr.ReleaseSpillLocksAndDiscardTemps(); 516 } 517 Comp_VIdt(MIPSOpcode op)518 void ArmJit::Comp_VIdt(MIPSOpcode op) { 519 NEON_IF_AVAILABLE(CompNEON_VIdt); 520 521 CONDITIONAL_DISABLE(VFPU_XFER); 522 if (js.HasUnknownPrefix()) { 523 DISABLE; 524 } 525 526 int vd = _VD; 527 VectorSize sz = GetVecSize(op); 528 int n = GetNumVectorElements(sz); 529 MOVI2F(S0, 0.0f, SCRATCHREG1); 530 MOVI2F(S1, 1.0f, SCRATCHREG1); 531 u8 dregs[4]; 532 GetVectorRegsPrefixD(dregs, sz, _VD); 533 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_NOINIT | MAP_DIRTY); 534 switch (sz) 535 { 536 case V_Pair: 537 VMOV(fpr.V(dregs[0]), (vd&1)==0 ? S1 : S0); 538 VMOV(fpr.V(dregs[1]), (vd&1)==1 ? S1 : S0); 539 break; 540 case V_Quad: 541 VMOV(fpr.V(dregs[0]), (vd&3)==0 ? S1 : S0); 542 VMOV(fpr.V(dregs[1]), (vd&3)==1 ? S1 : S0); 543 VMOV(fpr.V(dregs[2]), (vd&3)==2 ? S1 : S0); 544 VMOV(fpr.V(dregs[3]), (vd&3)==3 ? S1 : S0); 545 break; 546 default: 547 _dbg_assert_msg_(false,"Trying to interpret instruction that can't be interpreted"); 548 break; 549 } 550 551 ApplyPrefixD(dregs, sz); 552 553 fpr.ReleaseSpillLocksAndDiscardTemps(); 554 } 555 Comp_VMatrixInit(MIPSOpcode op)556 void ArmJit::Comp_VMatrixInit(MIPSOpcode op) 557 { 558 NEON_IF_AVAILABLE(CompNEON_VMatrixInit); 559 CONDITIONAL_DISABLE(VFPU_XFER); 560 if (js.HasUnknownPrefix()) { 561 // Don't think matrix init ops care about prefixes. 562 // DISABLE; 563 } 564 565 MatrixSize sz = GetMtxSize(op); 566 int n = GetMatrixSide(sz); 567 568 u8 dregs[16]; 569 GetMatrixRegs(dregs, sz, _VD); 570 571 switch ((op >> 16) & 0xF) { 572 case 3: // vmidt 573 MOVI2F(S0, 0.0f, SCRATCHREG1); 574 MOVI2F(S1, 1.0f, SCRATCHREG1); 575 for (int a = 0; a < n; a++) { 576 for (int b = 0; b < n; b++) { 577 fpr.MapRegV(dregs[a * 4 + b], MAP_DIRTY | MAP_NOINIT); 578 VMOV(fpr.V(dregs[a * 4 + b]), a == b ? S1 : S0); 579 } 580 } 581 break; 582 case 6: // vmzero 583 MOVI2F(S0, 0.0f, SCRATCHREG1); 584 for (int a = 0; a < n; a++) { 585 for (int b = 0; b < n; b++) { 586 fpr.MapRegV(dregs[a * 4 + b], MAP_DIRTY | MAP_NOINIT); 587 VMOV(fpr.V(dregs[a * 4 + b]), S0); 588 } 589 } 590 break; 591 case 7: // vmone 592 MOVI2F(S1, 1.0f, SCRATCHREG1); 593 for (int a = 0; a < n; a++) { 594 for (int b = 0; b < n; b++) { 595 fpr.MapRegV(dregs[a * 4 + b], MAP_DIRTY | MAP_NOINIT); 596 VMOV(fpr.V(dregs[a * 4 + b]), S1); 597 } 598 } 599 break; 600 } 601 602 fpr.ReleaseSpillLocksAndDiscardTemps(); 603 } 604 Comp_VHdp(MIPSOpcode op)605 void ArmJit::Comp_VHdp(MIPSOpcode op) { 606 NEON_IF_AVAILABLE(CompNEON_VHdp); 607 CONDITIONAL_DISABLE(VFPU_VEC); 608 if (js.HasUnknownPrefix()) { 609 DISABLE; 610 } 611 612 int vd = _VD; 613 int vs = _VS; 614 int vt = _VT; 615 VectorSize sz = GetVecSize(op); 616 617 // TODO: Force read one of them into regs? probably not. 618 u8 sregs[4], tregs[4], dregs[1]; 619 GetVectorRegsPrefixS(sregs, sz, vs); 620 GetVectorRegsPrefixT(tregs, sz, vt); 621 GetVectorRegsPrefixD(dregs, V_Single, vd); 622 623 // TODO: applyprefixST here somehow (shuffle, etc...) 624 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 625 fpr.MapRegsAndSpillLockV(tregs, sz, 0); 626 VMUL(S0, fpr.V(sregs[0]), fpr.V(tregs[0])); 627 628 int n = GetNumVectorElements(sz); 629 for (int i = 1; i < n; i++) { 630 // sum += s[i]*t[i]; 631 if (i == n - 1) { 632 VADD(S0, S0, fpr.V(tregs[i])); 633 } else { 634 VMLA(S0, fpr.V(sregs[i]), fpr.V(tregs[i])); 635 } 636 } 637 fpr.ReleaseSpillLocksAndDiscardTemps(); 638 639 fpr.MapRegV(dregs[0], MAP_NOINIT | MAP_DIRTY); 640 641 VMOV(fpr.V(dregs[0]), S0); 642 ApplyPrefixD(dregs, V_Single); 643 fpr.ReleaseSpillLocksAndDiscardTemps(); 644 } 645 646 alignas(16) static const float vavg_table[4] = { 1.0f, 1.0f / 2.0f, 1.0f / 3.0f, 1.0f / 4.0f }; 647 Comp_Vhoriz(MIPSOpcode op)648 void ArmJit::Comp_Vhoriz(MIPSOpcode op) { 649 NEON_IF_AVAILABLE(CompNEON_Vhoriz); 650 CONDITIONAL_DISABLE(VFPU_VEC); 651 if (js.HasUnknownPrefix()) { 652 DISABLE; 653 } 654 655 int vd = _VD; 656 int vs = _VS; 657 int vt = _VT; 658 VectorSize sz = GetVecSize(op); 659 660 // TODO: Force read one of them into regs? probably not. 661 u8 sregs[4], dregs[1]; 662 GetVectorRegsPrefixS(sregs, sz, vs); 663 GetVectorRegsPrefixD(dregs, V_Single, vd); 664 665 // TODO: applyprefixST here somehow (shuffle, etc...) 666 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 667 668 int n = GetNumVectorElements(sz); 669 670 bool is_vavg = ((op >> 16) & 0x1f) == 7; 671 if (is_vavg) { 672 MOVI2F(S1, vavg_table[n - 1], R0); 673 } 674 // Have to start at +0.000 for the correct sign. 675 MOVI2F(S0, 0.0f, SCRATCHREG1); 676 for (int i = 0; i < n; i++) { 677 // sum += s[i]; 678 VADD(S0, S0, fpr.V(sregs[i])); 679 } 680 681 fpr.MapRegV(dregs[0], MAP_NOINIT | MAP_DIRTY); 682 if (is_vavg) { 683 VMUL(fpr.V(dregs[0]), S0, S1); 684 } else { 685 VMOV(fpr.V(dregs[0]), S0); 686 } 687 ApplyPrefixD(dregs, V_Single); 688 fpr.ReleaseSpillLocksAndDiscardTemps(); 689 } 690 Comp_VDot(MIPSOpcode op)691 void ArmJit::Comp_VDot(MIPSOpcode op) { 692 NEON_IF_AVAILABLE(CompNEON_VDot); 693 CONDITIONAL_DISABLE(VFPU_VEC); 694 if (js.HasUnknownPrefix()) { 695 DISABLE; 696 } 697 698 int vd = _VD; 699 int vs = _VS; 700 int vt = _VT; 701 VectorSize sz = GetVecSize(op); 702 703 // TODO: Force read one of them into regs? probably not. 704 u8 sregs[4], tregs[4], dregs[1]; 705 GetVectorRegsPrefixS(sregs, sz, vs); 706 GetVectorRegsPrefixT(tregs, sz, vt); 707 GetVectorRegsPrefixD(dregs, V_Single, vd); 708 709 // TODO: applyprefixST here somehow (shuffle, etc...) 710 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 711 fpr.MapRegsAndSpillLockV(tregs, sz, 0); 712 VMUL(S0, fpr.V(sregs[0]), fpr.V(tregs[0])); 713 714 int n = GetNumVectorElements(sz); 715 for (int i = 1; i < n; i++) { 716 // sum += s[i]*t[i]; 717 VMLA(S0, fpr.V(sregs[i]), fpr.V(tregs[i])); 718 } 719 fpr.ReleaseSpillLocksAndDiscardTemps(); 720 721 fpr.MapRegV(dregs[0], MAP_NOINIT | MAP_DIRTY); 722 723 VMOV(fpr.V(dregs[0]), S0); 724 ApplyPrefixD(dregs, V_Single); 725 fpr.ReleaseSpillLocksAndDiscardTemps(); 726 } 727 Comp_VecDo3(MIPSOpcode op)728 void ArmJit::Comp_VecDo3(MIPSOpcode op) { 729 NEON_IF_AVAILABLE(CompNEON_VecDo3); 730 CONDITIONAL_DISABLE(VFPU_VEC); 731 if (js.HasUnknownPrefix()) { 732 DISABLE; 733 } 734 735 int vd = _VD; 736 int vs = _VS; 737 int vt = _VT; 738 739 VectorSize sz = GetVecSize(op); 740 int n = GetNumVectorElements(sz); 741 742 u8 sregs[4], tregs[4], dregs[4]; 743 GetVectorRegsPrefixS(sregs, sz, _VS); 744 GetVectorRegsPrefixT(tregs, sz, _VT); 745 GetVectorRegsPrefixD(dregs, sz, _VD); 746 747 MIPSReg tempregs[4]; 748 for (int i = 0; i < n; i++) { 749 if (!IsOverlapSafe(dregs[i], i, n, sregs, n, tregs)) { 750 tempregs[i] = fpr.GetTempV(); 751 } else { 752 tempregs[i] = dregs[i]; 753 } 754 } 755 756 // Map first, then work. This will allow us to use VLDMIA more often 757 // (when we add the appropriate map function) and the instruction ordering 758 // will improve. 759 // Note that mapping like this (instead of first all sregs, first all tregs etc) 760 // reduces the amount of continuous registers a lot :( 761 for (int i = 0; i < n; i++) { 762 fpr.MapDirtyInInV(tempregs[i], sregs[i], tregs[i]); 763 fpr.SpillLockV(tempregs[i]); 764 fpr.SpillLockV(sregs[i]); 765 fpr.SpillLockV(tregs[i]); 766 } 767 768 for (int i = 0; i < n; i++) { 769 switch (op >> 26) { 770 case 24: //VFPU0 771 switch ((op >> 23)&7) { 772 case 0: // d[i] = s[i] + t[i]; break; //vadd 773 VADD(fpr.V(tempregs[i]), fpr.V(sregs[i]), fpr.V(tregs[i])); 774 break; 775 case 1: // d[i] = s[i] - t[i]; break; //vsub 776 VSUB(fpr.V(tempregs[i]), fpr.V(sregs[i]), fpr.V(tregs[i])); 777 break; 778 case 7: // d[i] = s[i] / t[i]; break; //vdiv 779 VDIV(fpr.V(tempregs[i]), fpr.V(sregs[i]), fpr.V(tregs[i])); 780 break; 781 default: 782 DISABLE; 783 } 784 break; 785 case 25: //VFPU1 786 switch ((op >> 23) & 7) { 787 case 0: // d[i] = s[i] * t[i]; break; //vmul 788 VMUL(fpr.V(tempregs[i]), fpr.V(sregs[i]), fpr.V(tregs[i])); 789 break; 790 default: 791 DISABLE; 792 } 793 break; 794 // Unfortunately there is no VMIN/VMAX on ARM without NEON. 795 case 27: //VFPU3 796 switch ((op >> 23) & 7) { 797 case 2: // vmin 798 { 799 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 800 VMRS_APSR(); 801 FixupBranch skipNAN = B_CC(CC_VC); 802 VMOV(SCRATCHREG1, fpr.V(sregs[i])); 803 VMOV(SCRATCHREG2, fpr.V(tregs[i])); 804 // If both are negative, we reverse the comparison. We want the highest mantissa then. 805 // Also, between -NAN and -5.0, we want -NAN to be less. 806 TST(SCRATCHREG1, SCRATCHREG2); 807 FixupBranch cmpPositive = B_CC(CC_PL); 808 CMP(SCRATCHREG2, SCRATCHREG1); 809 FixupBranch skipPositive = B(); 810 SetJumpTarget(cmpPositive); 811 CMP(SCRATCHREG1, SCRATCHREG2); 812 SetJumpTarget(skipPositive); 813 SetCC(CC_AL); 814 SetJumpTarget(skipNAN); 815 SetCC(CC_LT); 816 VMOV(fpr.V(tempregs[i]), fpr.V(sregs[i])); 817 SetCC(CC_GE); 818 VMOV(fpr.V(tempregs[i]), fpr.V(tregs[i])); 819 SetCC(CC_AL); 820 break; 821 } 822 case 3: // vmax 823 { 824 VCMP(fpr.V(tregs[i]), fpr.V(sregs[i])); 825 VMRS_APSR(); 826 FixupBranch skipNAN = B_CC(CC_VC); 827 VMOV(SCRATCHREG1, fpr.V(sregs[i])); 828 VMOV(SCRATCHREG2, fpr.V(tregs[i])); 829 // If both are negative, we reverse the comparison. We want the lowest mantissa then. 830 // Also, between -NAN and -5.0, we want -5.0 to be greater. 831 TST(SCRATCHREG2, SCRATCHREG1); 832 FixupBranch cmpPositive = B_CC(CC_PL); 833 CMP(SCRATCHREG1, SCRATCHREG2); 834 FixupBranch skipPositive = B(); 835 SetJumpTarget(cmpPositive); 836 CMP(SCRATCHREG2, SCRATCHREG1); 837 SetJumpTarget(skipPositive); 838 SetCC(CC_AL); 839 SetJumpTarget(skipNAN); 840 SetCC(CC_LT); 841 VMOV(fpr.V(tempregs[i]), fpr.V(sregs[i])); 842 SetCC(CC_GE); 843 VMOV(fpr.V(tempregs[i]), fpr.V(tregs[i])); 844 SetCC(CC_AL); 845 break; 846 } 847 case 6: // vsge 848 DISABLE; // pending testing 849 VCMP(fpr.V(tregs[i]), fpr.V(sregs[i])); 850 VMRS_APSR(); 851 // Unordered is always 0. 852 SetCC(CC_GE); 853 MOVI2F(fpr.V(tempregs[i]), 1.0f, SCRATCHREG1); 854 SetCC(CC_LT); 855 MOVI2F(fpr.V(tempregs[i]), 0.0f, SCRATCHREG1); 856 SetCC(CC_AL); 857 break; 858 case 7: // vslt 859 DISABLE; // pending testing 860 VCMP(fpr.V(tregs[i]), fpr.V(sregs[i])); 861 VMRS_APSR(); 862 // Unordered is always 0. 863 SetCC(CC_LO); 864 MOVI2F(fpr.V(tempregs[i]), 1.0f, SCRATCHREG1); 865 SetCC(CC_HS); 866 MOVI2F(fpr.V(tempregs[i]), 0.0f, SCRATCHREG1); 867 SetCC(CC_AL); 868 break; 869 } 870 break; 871 872 default: 873 DISABLE; 874 } 875 } 876 877 for (int i = 0; i < n; i++) { 878 if (dregs[i] != tempregs[i]) { 879 fpr.MapDirtyInV(dregs[i], tempregs[i]); 880 VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); 881 } 882 } 883 ApplyPrefixD(dregs, sz); 884 885 fpr.ReleaseSpillLocksAndDiscardTemps(); 886 } 887 Comp_VV2Op(MIPSOpcode op)888 void ArmJit::Comp_VV2Op(MIPSOpcode op) { 889 NEON_IF_AVAILABLE(CompNEON_VV2Op); 890 CONDITIONAL_DISABLE(VFPU_VEC); 891 if (js.HasUnknownPrefix()) { 892 DISABLE; 893 } 894 895 // Pre-processing: Eliminate silly no-op VMOVs, common in Wipeout Pure 896 if (((op >> 16) & 0x1f) == 0 && _VS == _VD && js.HasNoPrefix()) { 897 return; 898 } 899 900 // Catch the disabled operations immediately so we don't map registers unnecessarily later. 901 // Move these down to the big switch below as they are implemented. 902 switch ((op >> 16) & 0x1f) { 903 case 18: // d[i] = sinf((float)M_PI_2 * s[i]); break; //vsin 904 DISABLE; 905 break; 906 case 19: // d[i] = cosf((float)M_PI_2 * s[i]); break; //vcos 907 DISABLE; 908 break; 909 case 20: // d[i] = powf(2.0f, s[i]); break; //vexp2 910 DISABLE; 911 break; 912 case 21: // d[i] = logf(s[i])/log(2.0f); break; //vlog2 913 DISABLE; 914 break; 915 case 26: // d[i] = -sinf((float)M_PI_2 * s[i]); break; // vnsin 916 DISABLE; 917 break; 918 case 28: // d[i] = 1.0f / expf(s[i] * (float)M_LOG2E); break; // vrexp2 919 DISABLE; 920 break; 921 default: 922 ; 923 } 924 925 VectorSize sz = GetVecSize(op); 926 int n = GetNumVectorElements(sz); 927 928 u8 sregs[4], dregs[4]; 929 GetVectorRegsPrefixS(sregs, sz, _VS); 930 GetVectorRegsPrefixD(dregs, sz, _VD); 931 932 MIPSReg tempregs[4]; 933 for (int i = 0; i < n; ++i) { 934 if (!IsOverlapSafe(dregs[i], i, n, sregs)) { 935 tempregs[i] = fpr.GetTempV(); 936 } else { 937 tempregs[i] = dregs[i]; 938 } 939 } 940 941 // Get some extra temps, used by vasin only. 942 ARMReg t2 = INVALID_REG, t3 = INVALID_REG, t4 = INVALID_REG; 943 if (((op >> 16) & 0x1f) == 23) { 944 // Only get here on vasin. 945 int t[3] = { fpr.GetTempV(), fpr.GetTempV(), fpr.GetTempV() }; 946 fpr.MapRegV(t[0], MAP_NOINIT); 947 fpr.MapRegV(t[1], MAP_NOINIT); 948 fpr.MapRegV(t[2], MAP_NOINIT); 949 t2 = fpr.V(t[0]); 950 t3 = fpr.V(t[1]); 951 t4 = fpr.V(t[2]); 952 } 953 954 // Pre map the registers to get better instruction ordering. 955 // Note that mapping like this (instead of first all sregs, first all tempregs etc) 956 // reduces the amount of continuous registers a lot :( 957 for (int i = 0; i < n; i++) { 958 fpr.MapDirtyInV(tempregs[i], sregs[i]); 959 fpr.SpillLockV(tempregs[i]); 960 fpr.SpillLockV(sregs[i]); 961 } 962 963 // Warning: sregs[i] and tempxregs[i] may be the same reg. 964 // Helps for vmov, hurts for vrcp, etc. 965 for (int i = 0; i < n; i++) { 966 switch ((op >> 16) & 0x1f) { 967 case 0: // d[i] = s[i]; break; //vmov 968 // Probably for swizzle. 969 VMOV(fpr.V(tempregs[i]), fpr.V(sregs[i])); 970 break; 971 case 1: // d[i] = fabsf(s[i]); break; //vabs 972 VABS(fpr.V(tempregs[i]), fpr.V(sregs[i])); 973 break; 974 case 2: // d[i] = -s[i]; break; //vneg 975 VNEG(fpr.V(tempregs[i]), fpr.V(sregs[i])); 976 break; 977 case 4: // if (s[i] < 0) d[i] = 0; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat0 978 if (i == 0) { 979 MOVI2F(S0, 0.0f, SCRATCHREG1); 980 MOVI2F(S1, 1.0f, SCRATCHREG1); 981 } 982 VCMP(fpr.V(sregs[i]), S0); 983 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 984 VMOV(fpr.V(tempregs[i]), fpr.V(sregs[i])); 985 SetCC(CC_LS); 986 VMOV(fpr.V(tempregs[i]), S0); 987 SetCC(CC_AL); 988 VCMP(fpr.V(sregs[i]), S1); 989 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 990 SetCC(CC_GT); 991 VMOV(fpr.V(tempregs[i]), S1); 992 SetCC(CC_AL); 993 break; 994 case 5: // if (s[i] < -1.0f) d[i] = -1.0f; else {if(s[i] > 1.0f) d[i] = 1.0f; else d[i] = s[i];} break; // vsat1 995 if (i == 0) { 996 MOVI2F(S0, -1.0f, SCRATCHREG1); 997 MOVI2F(S1, 1.0f, SCRATCHREG1); 998 } 999 VCMP(fpr.V(sregs[i]), S0); 1000 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 1001 VMOV(fpr.V(tempregs[i]), fpr.V(sregs[i])); 1002 SetCC(CC_LO); 1003 VMOV(fpr.V(tempregs[i]), S0); 1004 SetCC(CC_AL); 1005 VCMP(fpr.V(sregs[i]), S1); 1006 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 1007 SetCC(CC_GT); 1008 VMOV(fpr.V(tempregs[i]), S1); 1009 SetCC(CC_AL); 1010 break; 1011 case 16: // d[i] = 1.0f / s[i]; break; //vrcp 1012 if (i == 0) { 1013 MOVI2F(S0, 1.0f, SCRATCHREG1); 1014 } 1015 VDIV(fpr.V(tempregs[i]), S0, fpr.V(sregs[i])); 1016 break; 1017 case 17: // d[i] = 1.0f / sqrtf(s[i]); break; //vrsq 1018 if (i == 0) { 1019 MOVI2F(S0, 1.0f, SCRATCHREG1); 1020 } 1021 VSQRT(S1, fpr.V(sregs[i])); 1022 VDIV(fpr.V(tempregs[i]), S0, S1); 1023 break; 1024 case 22: // d[i] = sqrtf(s[i]); break; //vsqrt 1025 VSQRT(fpr.V(tempregs[i]), fpr.V(sregs[i])); 1026 VABS(fpr.V(tempregs[i]), fpr.V(tempregs[i])); 1027 break; 1028 case 23: // d[i] = asinf(s[i] * (float)M_2_PI); break; //vasin 1029 // Seems to work well enough but can disable if it becomes a problem. 1030 // Should be easy enough to translate to NEON. There we can load all the constants 1031 // in one go of course. 1032 VCMP(fpr.V(sregs[i])); // flags = sign(sregs[i]) 1033 VMRS_APSR(); 1034 MOVI2F(S0, 1.0f, SCRATCHREG1); 1035 VABS(t4, fpr.V(sregs[i])); // t4 = |sregs[i]| 1036 VSUB(t3, S0, t4); 1037 VSQRT(t3, t3); // t3 = sqrt(1 - |sregs[i]|) 1038 MOVI2F(S1, -0.0187293f, SCRATCHREG1); 1039 MOVI2F(t2, 0.0742610f, SCRATCHREG1); 1040 VMLA(t2, t4, S1); 1041 MOVI2F(S1, -0.2121144f, SCRATCHREG1); 1042 VMLA(S1, t4, t2); 1043 MOVI2F(t2, 1.5707288f, SCRATCHREG1); 1044 VMLA(t2, t4, S1); 1045 MOVI2F(fpr.V(tempregs[i]), M_PI / 2, SCRATCHREG1); 1046 VMLS(fpr.V(tempregs[i]), t2, t3); // tr[i] = M_PI / 2 - t2 * t3 1047 { 1048 FixupBranch br = B_CC(CC_GE); 1049 VNEG(fpr.V(tempregs[i]), fpr.V(tempregs[i])); 1050 SetJumpTarget(br); 1051 } 1052 // Correction factor for PSP range. Could be baked into the calculation above? 1053 MOVI2F(S1, 1.0f / (M_PI / 2), SCRATCHREG1); 1054 VMUL(fpr.V(tempregs[i]), fpr.V(tempregs[i]), S1); 1055 break; 1056 case 24: // d[i] = -1.0f / s[i]; break; // vnrcp 1057 if (i == 0) { 1058 MOVI2F(S0, -1.0f, SCRATCHREG1); 1059 } 1060 VDIV(fpr.V(tempregs[i]), S0, fpr.V(sregs[i])); 1061 break; 1062 default: 1063 ERROR_LOG(JIT, "case missing in vfpu vv2op"); 1064 DISABLE; 1065 break; 1066 } 1067 } 1068 1069 for (int i = 0; i < n; ++i) { 1070 if (dregs[i] != tempregs[i]) { 1071 fpr.MapDirtyInV(dregs[i], tempregs[i]); 1072 VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); 1073 } 1074 } 1075 1076 ApplyPrefixD(dregs, sz); 1077 1078 fpr.ReleaseSpillLocksAndDiscardTemps(); 1079 } 1080 Comp_Vi2f(MIPSOpcode op)1081 void ArmJit::Comp_Vi2f(MIPSOpcode op) { 1082 NEON_IF_AVAILABLE(CompNEON_Vi2f); 1083 CONDITIONAL_DISABLE(VFPU_VEC); 1084 if (js.HasUnknownPrefix()) { 1085 DISABLE; 1086 } 1087 1088 VectorSize sz = GetVecSize(op); 1089 int n = GetNumVectorElements(sz); 1090 1091 int imm = (op >> 16) & 0x1f; 1092 const float mult = 1.0f / (float)(1UL << imm); 1093 1094 u8 sregs[4], dregs[4]; 1095 GetVectorRegsPrefixS(sregs, sz, _VS); 1096 GetVectorRegsPrefixD(dregs, sz, _VD); 1097 1098 MIPSReg tempregs[4]; 1099 for (int i = 0; i < n; ++i) { 1100 if (!IsOverlapSafe(dregs[i], i, n, sregs)) { 1101 tempregs[i] = fpr.GetTempV(); 1102 } else { 1103 tempregs[i] = dregs[i]; 1104 } 1105 } 1106 1107 if (mult != 1.0f) 1108 MOVI2F(S0, mult, SCRATCHREG1); 1109 1110 for (int i = 0; i < n; i++) { 1111 fpr.MapDirtyInV(tempregs[i], sregs[i]); 1112 VCVT(fpr.V(tempregs[i]), fpr.V(sregs[i]), TO_FLOAT | IS_SIGNED); 1113 if (mult != 1.0f) 1114 VMUL(fpr.V(tempregs[i]), fpr.V(tempregs[i]), S0); 1115 } 1116 1117 for (int i = 0; i < n; ++i) { 1118 if (dregs[i] != tempregs[i]) { 1119 fpr.MapDirtyInV(dregs[i], tempregs[i]); 1120 VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); 1121 } 1122 } 1123 1124 ApplyPrefixD(dregs, sz); 1125 fpr.ReleaseSpillLocksAndDiscardTemps(); 1126 } 1127 Comp_Vh2f(MIPSOpcode op)1128 void ArmJit::Comp_Vh2f(MIPSOpcode op) { 1129 NEON_IF_AVAILABLE(CompNEON_Vh2f); 1130 CONDITIONAL_DISABLE(VFPU_VEC); 1131 if (js.HasUnknownPrefix()) { 1132 DISABLE; 1133 } 1134 1135 if (!cpu_info.bNEON) { 1136 DISABLE; 1137 } 1138 1139 // This multi-VCVT.F32.F16 is only available in the VFPv4 extension. 1140 // The VFPv3 one is VCVTB, VCVTT which we don't yet have support for. 1141 if (!(cpu_info.bHalf && cpu_info.bVFPv4)) { 1142 // No hardware support for half-to-float, fallback to interpreter 1143 // TODO: Translate the fast SSE solution to standard integer/VFP stuff 1144 // for the weaker CPUs. 1145 DISABLE; 1146 } 1147 1148 u8 sregs[4], dregs[4]; 1149 VectorSize sz = GetVecSize(op); 1150 VectorSize outSz; 1151 1152 switch (sz) { 1153 case V_Single: 1154 outSz = V_Pair; 1155 break; 1156 case V_Pair: 1157 outSz = V_Quad; 1158 break; 1159 default: 1160 DISABLE; 1161 } 1162 1163 int n = GetNumVectorElements(sz); 1164 int nOut = n * 2; 1165 GetVectorRegsPrefixS(sregs, sz, _VS); 1166 GetVectorRegsPrefixD(dregs, outSz, _VD); 1167 1168 static const ARMReg tmp[4] = { S0, S1, S2, S3 }; 1169 1170 for (int i = 0; i < n; i++) { 1171 fpr.MapRegV(sregs[i], sz); 1172 VMOV(tmp[i], fpr.V(sregs[i])); 1173 } 1174 1175 // This always converts four 16-bit floats in D0 to four 32-bit floats 1176 // in Q0. If we are dealing with a pair here, we just ignore the upper two outputs. 1177 // There are also a couple of other instructions that do it one at a time but doesn't 1178 // seem worth the trouble. 1179 VCVTF32F16(Q0, D0); 1180 1181 for (int i = 0; i < nOut; i++) { 1182 fpr.MapRegV(dregs[i], MAP_DIRTY | MAP_NOINIT); 1183 VMOV(fpr.V(dregs[i]), tmp[i]); 1184 } 1185 1186 ApplyPrefixD(dregs, sz); 1187 fpr.ReleaseSpillLocksAndDiscardTemps(); 1188 } 1189 Comp_Vf2i(MIPSOpcode op)1190 void ArmJit::Comp_Vf2i(MIPSOpcode op) { 1191 NEON_IF_AVAILABLE(CompNEON_Vf2i); 1192 CONDITIONAL_DISABLE(VFPU_VEC); 1193 1194 if (js.HasUnknownPrefix()) { 1195 DISABLE; 1196 } 1197 DISABLE; 1198 1199 VectorSize sz = GetVecSize(op); 1200 int n = GetNumVectorElements(sz); 1201 1202 int imm = (op >> 16) & 0x1f; 1203 float mult = (float)(1ULL << imm); 1204 1205 switch ((op >> 21) & 0x1f) 1206 { 1207 case 17: 1208 break; //z - truncate. Easy to support. 1209 case 16: 1210 case 18: 1211 case 19: 1212 DISABLE; 1213 break; 1214 } 1215 1216 u8 sregs[4], dregs[4]; 1217 GetVectorRegsPrefixS(sregs, sz, _VS); 1218 GetVectorRegsPrefixD(dregs, sz, _VD); 1219 1220 MIPSReg tempregs[4]; 1221 for (int i = 0; i < n; ++i) { 1222 if (!IsOverlapSafe(dregs[i], i, n, sregs)) { 1223 tempregs[i] = fpr.GetTempV(); 1224 } else { 1225 tempregs[i] = dregs[i]; 1226 } 1227 } 1228 1229 if (mult != 1.0f) 1230 MOVI2F(S1, mult, SCRATCHREG1); 1231 1232 for (int i = 0; i < n; i++) { 1233 fpr.MapDirtyInV(tempregs[i], sregs[i]); 1234 switch ((op >> 21) & 0x1f) { 1235 case 16: /* TODO */ break; //n 1236 case 17: 1237 if (mult != 1.0f) { 1238 VMUL(S0, fpr.V(sregs[i]), S1); 1239 VCVT(fpr.V(tempregs[i]), S0, TO_INT | ROUND_TO_ZERO); 1240 } else { 1241 VCVT(fpr.V(tempregs[i]), fpr.V(sregs[i]), TO_INT | ROUND_TO_ZERO); 1242 } 1243 break; 1244 case 18: /* TODO */ break; //u 1245 case 19: /* TODO */ break; //d 1246 } 1247 } 1248 1249 for (int i = 0; i < n; ++i) { 1250 if (dregs[i] != tempregs[i]) { 1251 fpr.MapDirtyInV(dregs[i], tempregs[i]); 1252 VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); 1253 } 1254 } 1255 1256 ApplyPrefixD(dregs, sz); 1257 fpr.ReleaseSpillLocksAndDiscardTemps(); 1258 } 1259 Comp_Mftv(MIPSOpcode op)1260 void ArmJit::Comp_Mftv(MIPSOpcode op) { 1261 NEON_IF_AVAILABLE(CompNEON_Mftv); 1262 CONDITIONAL_DISABLE(VFPU_XFER); 1263 1264 int imm = op & 0xFF; 1265 MIPSGPReg rt = _RT; 1266 switch ((op >> 21) & 0x1f) { 1267 case 3: //mfv / mfvc 1268 // rt = 0, imm = 255 appears to be used as a CPU interlock by some games. 1269 if (rt != 0) { 1270 if (imm < 128) { //R(rt) = VI(imm); 1271 fpr.MapRegV(imm, 0); 1272 gpr.MapReg(rt, MAP_NOINIT | MAP_DIRTY); 1273 VMOV(gpr.R(rt), fpr.V(imm)); 1274 } else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc 1275 if (imm - 128 == VFPU_CTRL_CC) { 1276 if (gpr.IsImm(MIPS_REG_VFPUCC)) { 1277 gpr.SetImm(rt, gpr.GetImm(MIPS_REG_VFPUCC)); 1278 } else { 1279 gpr.MapDirtyIn(rt, MIPS_REG_VFPUCC); 1280 MOV(gpr.R(rt), gpr.R(MIPS_REG_VFPUCC)); 1281 } 1282 } else { 1283 // In case we have a saved prefix. 1284 FlushPrefixV(); 1285 gpr.MapReg(rt, MAP_NOINIT | MAP_DIRTY); 1286 LDR(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128)); 1287 } 1288 } else { 1289 //ERROR - maybe need to make this value too an "interlock" value? 1290 ERROR_LOG(CPU, "mfv - invalid register %i", imm); 1291 } 1292 } 1293 break; 1294 1295 case 7: // mtv 1296 if (imm < 128) { 1297 gpr.MapReg(rt); 1298 fpr.MapRegV(imm, MAP_DIRTY | MAP_NOINIT); 1299 VMOV(fpr.V(imm), gpr.R(rt)); 1300 } else if (imm < 128 + VFPU_CTRL_MAX) { //mtvc //currentMIPS->vfpuCtrl[imm - 128] = R(rt); 1301 if (imm - 128 == VFPU_CTRL_CC) { 1302 if (gpr.IsImm(rt)) { 1303 gpr.SetImm(MIPS_REG_VFPUCC, gpr.GetImm(rt)); 1304 } else { 1305 gpr.MapDirtyIn(MIPS_REG_VFPUCC, rt); 1306 MOV(gpr.R(MIPS_REG_VFPUCC), gpr.R(rt)); 1307 } 1308 } else { 1309 gpr.MapReg(rt); 1310 STR(gpr.R(rt), CTXREG, offsetof(MIPSState, vfpuCtrl) + 4 * (imm - 128)); 1311 } 1312 1313 // TODO: Optimization if rt is Imm? 1314 // Set these BEFORE disable! 1315 if (imm - 128 == VFPU_CTRL_SPREFIX) { 1316 js.prefixSFlag = JitState::PREFIX_UNKNOWN; 1317 } else if (imm - 128 == VFPU_CTRL_TPREFIX) { 1318 js.prefixTFlag = JitState::PREFIX_UNKNOWN; 1319 } else if (imm - 128 == VFPU_CTRL_DPREFIX) { 1320 js.prefixDFlag = JitState::PREFIX_UNKNOWN; 1321 } 1322 } else { 1323 //ERROR 1324 _dbg_assert_msg_(false,"mtv - invalid register"); 1325 } 1326 break; 1327 1328 default: 1329 DISABLE; 1330 } 1331 1332 fpr.ReleaseSpillLocksAndDiscardTemps(); 1333 } 1334 Comp_Vmfvc(MIPSOpcode op)1335 void ArmJit::Comp_Vmfvc(MIPSOpcode op) { 1336 NEON_IF_AVAILABLE(CompNEON_Vmtvc); 1337 CONDITIONAL_DISABLE(VFPU_XFER); 1338 1339 int vd = _VD; 1340 int imm = (op >> 8) & 0x7F; 1341 if (imm < VFPU_CTRL_MAX) { 1342 fpr.MapRegV(vd); 1343 if (imm == VFPU_CTRL_CC) { 1344 gpr.MapReg(MIPS_REG_VFPUCC, 0); 1345 VMOV(fpr.V(vd), gpr.R(MIPS_REG_VFPUCC)); 1346 } else { 1347 ADDI2R(SCRATCHREG1, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + imm * 4, SCRATCHREG2); 1348 VLDR(fpr.V(vd), SCRATCHREG1, 0); 1349 } 1350 fpr.ReleaseSpillLocksAndDiscardTemps(); 1351 } else { 1352 fpr.MapRegV(vd); 1353 MOVI2F(fpr.V(vd), 0.0f, SCRATCHREG1); 1354 } 1355 } 1356 Comp_Vmtvc(MIPSOpcode op)1357 void ArmJit::Comp_Vmtvc(MIPSOpcode op) { 1358 NEON_IF_AVAILABLE(CompNEON_Vmtvc); 1359 CONDITIONAL_DISABLE(VFPU_XFER); 1360 1361 int vs = _VS; 1362 int imm = op & 0x7F; 1363 if (imm < VFPU_CTRL_MAX) { 1364 fpr.MapRegV(vs); 1365 if (imm == VFPU_CTRL_CC) { 1366 gpr.MapReg(MIPS_REG_VFPUCC, MAP_DIRTY | MAP_NOINIT); 1367 VMOV(gpr.R(MIPS_REG_VFPUCC), fpr.V(vs)); 1368 } else { 1369 ADDI2R(SCRATCHREG1, CTXREG, offsetof(MIPSState, vfpuCtrl[0]) + imm * 4, SCRATCHREG2); 1370 VSTR(fpr.V(vs), SCRATCHREG1, 0); 1371 } 1372 fpr.ReleaseSpillLocksAndDiscardTemps(); 1373 1374 if (imm == VFPU_CTRL_SPREFIX) { 1375 js.prefixSFlag = JitState::PREFIX_UNKNOWN; 1376 } else if (imm == VFPU_CTRL_TPREFIX) { 1377 js.prefixTFlag = JitState::PREFIX_UNKNOWN; 1378 } else if (imm == VFPU_CTRL_DPREFIX) { 1379 js.prefixDFlag = JitState::PREFIX_UNKNOWN; 1380 } 1381 } 1382 } 1383 Comp_Vmmov(MIPSOpcode op)1384 void ArmJit::Comp_Vmmov(MIPSOpcode op) { 1385 NEON_IF_AVAILABLE(CompNEON_Vmmov); 1386 CONDITIONAL_DISABLE(VFPU_MTX_VMMOV); 1387 1388 // This probably ignores prefixes for all sane intents and purposes. 1389 if (_VS == _VD) { 1390 // A lot of these no-op matrix moves in Wipeout... Just drop the instruction entirely. 1391 return; 1392 } 1393 1394 MatrixSize sz = GetMtxSize(op); 1395 int n = GetMatrixSide(sz); 1396 1397 u8 sregs[16], dregs[16]; 1398 GetMatrixRegs(sregs, sz, _VS); 1399 GetMatrixRegs(dregs, sz, _VD); 1400 1401 // Rough overlap check. 1402 bool overlap = false; 1403 if (GetMtx(_VS) == GetMtx(_VD)) { 1404 // Potential overlap (guaranteed for 3x3 or more). 1405 overlap = true; 1406 } 1407 1408 if (overlap) { 1409 // Not so common, fallback. 1410 DISABLE; 1411 } else { 1412 for (int a = 0; a < n; a++) { 1413 for (int b = 0; b < n; b++) { 1414 fpr.MapDirtyInV(dregs[a * 4 + b], sregs[a * 4 + b]); 1415 VMOV(fpr.V(dregs[a * 4 + b]), fpr.V(sregs[a * 4 + b])); 1416 } 1417 } 1418 fpr.ReleaseSpillLocksAndDiscardTemps(); 1419 } 1420 } 1421 Comp_VScl(MIPSOpcode op)1422 void ArmJit::Comp_VScl(MIPSOpcode op) { 1423 NEON_IF_AVAILABLE(CompNEON_VScl); 1424 CONDITIONAL_DISABLE(VFPU_VEC); 1425 if (js.HasUnknownPrefix()) { 1426 DISABLE; 1427 } 1428 1429 VectorSize sz = GetVecSize(op); 1430 int n = GetNumVectorElements(sz); 1431 1432 u8 sregs[4], dregs[4], treg; 1433 GetVectorRegsPrefixS(sregs, sz, _VS); 1434 // TODO: Prefixes seem strange... 1435 GetVectorRegsPrefixT(&treg, V_Single, _VT); 1436 GetVectorRegsPrefixD(dregs, sz, _VD); 1437 1438 // Move to S0 early, so we don't have to worry about overlap with scale. 1439 fpr.LoadToRegV(S0, treg); 1440 1441 // For prefixes to work, we just have to ensure that none of the output registers spill 1442 // and that there's no overlap. 1443 MIPSReg tempregs[4]; 1444 for (int i = 0; i < n; ++i) { 1445 if (!IsOverlapSafe(dregs[i], i, n, sregs)) { 1446 // Need to use temp regs 1447 tempregs[i] = fpr.GetTempV(); 1448 } else { 1449 tempregs[i] = dregs[i]; 1450 } 1451 } 1452 1453 // The meat of the function! 1454 for (int i = 0; i < n; i++) { 1455 fpr.MapDirtyInV(tempregs[i], sregs[i]); 1456 VMUL(fpr.V(tempregs[i]), fpr.V(sregs[i]), S0); 1457 } 1458 1459 for (int i = 0; i < n; i++) { 1460 // All must be mapped for prefixes to work. 1461 if (dregs[i] != tempregs[i]) { 1462 fpr.MapDirtyInV(dregs[i], tempregs[i]); 1463 VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); 1464 } 1465 } 1466 1467 ApplyPrefixD(dregs, sz); 1468 1469 fpr.ReleaseSpillLocksAndDiscardTemps(); 1470 } 1471 Comp_Vmmul(MIPSOpcode op)1472 void ArmJit::Comp_Vmmul(MIPSOpcode op) { 1473 CONDITIONAL_DISABLE(VFPU_MTX_VMMUL); 1474 if (!js.HasNoPrefix()) { 1475 DISABLE; 1476 } 1477 NEON_IF_AVAILABLE(CompNEON_Vmmul); 1478 1479 if (PSP_CoreParameter().compat.flags().MoreAccurateVMMUL) { 1480 // Fall back to interpreter, which has the accurate implementation. 1481 // Later we might do something more optimized here. 1482 DISABLE; 1483 } 1484 1485 MatrixSize sz = GetMtxSize(op); 1486 int n = GetMatrixSide(sz); 1487 1488 u8 sregs[16], tregs[16], dregs[16]; 1489 GetMatrixRegs(sregs, sz, _VS); 1490 GetMatrixRegs(tregs, sz, _VT); 1491 GetMatrixRegs(dregs, sz, _VD); 1492 1493 // Rough overlap check. 1494 bool overlap = false; 1495 if (GetMtx(_VS) == GetMtx(_VD) || GetMtx(_VT) == GetMtx(_VD)) { 1496 // Potential overlap (guaranteed for 3x3 or more). 1497 overlap = true; 1498 } 1499 1500 if (overlap) { 1501 DISABLE; 1502 } else { 1503 for (int a = 0; a < n; a++) { 1504 for (int b = 0; b < n; b++) { 1505 fpr.MapInInV(sregs[b * 4], tregs[a * 4]); 1506 VMUL(S0, fpr.V(sregs[b * 4]), fpr.V(tregs[a * 4])); 1507 for (int c = 1; c < n; c++) { 1508 fpr.MapInInV(sregs[b * 4 + c], tregs[a * 4 + c]); 1509 VMLA(S0, fpr.V(sregs[b * 4 + c]), fpr.V(tregs[a * 4 + c])); 1510 } 1511 fpr.MapRegV(dregs[a * 4 + b], MAP_DIRTY | MAP_NOINIT); 1512 VMOV(fpr.V(dregs[a * 4 + b]), S0); 1513 } 1514 } 1515 fpr.ReleaseSpillLocksAndDiscardTemps(); 1516 } 1517 } 1518 Comp_Vmscl(MIPSOpcode op)1519 void ArmJit::Comp_Vmscl(MIPSOpcode op) { 1520 NEON_IF_AVAILABLE(CompNEON_Vmscl); 1521 DISABLE; 1522 } 1523 Comp_Vtfm(MIPSOpcode op)1524 void ArmJit::Comp_Vtfm(MIPSOpcode op) { 1525 NEON_IF_AVAILABLE(CompNEON_Vtfm); 1526 CONDITIONAL_DISABLE(VFPU_MTX_VTFM); 1527 if (js.HasUnknownPrefix()) { 1528 DISABLE; 1529 } 1530 1531 // TODO: This probably ignores prefixes? Or maybe uses D? 1532 1533 VectorSize sz = GetVecSize(op); 1534 MatrixSize msz = GetMtxSize(op); 1535 int n = GetNumVectorElements(sz); 1536 int ins = (op >> 23) & 7; 1537 1538 bool homogenous = false; 1539 if (n == ins) { 1540 n++; 1541 sz = (VectorSize)((int)(sz) + 1); 1542 msz = (MatrixSize)((int)(msz) + 1); 1543 homogenous = true; 1544 } 1545 // Otherwise, n should already be ins + 1. 1546 else if (n != ins + 1) { 1547 DISABLE; 1548 } 1549 1550 u8 sregs[16], dregs[4], tregs[4]; 1551 GetMatrixRegs(sregs, msz, _VS); 1552 GetVectorRegs(tregs, sz, _VT); 1553 GetVectorRegs(dregs, sz, _VD); 1554 1555 // TODO: test overlap, optimize. 1556 int tempregs[4]; 1557 for (int i = 0; i < n; i++) { 1558 fpr.MapInInV(sregs[i * 4], tregs[0]); 1559 VMUL(S0, fpr.V(sregs[i * 4]), fpr.V(tregs[0])); 1560 for (int k = 1; k < n; k++) { 1561 if (!homogenous || k != n - 1) { 1562 fpr.MapInInV(sregs[i * 4 + k], tregs[k]); 1563 VMLA(S0, fpr.V(sregs[i * 4 + k]), fpr.V(tregs[k])); 1564 } else { 1565 fpr.MapRegV(sregs[i * 4 + k]); 1566 VADD(S0, S0, fpr.V(sregs[i * 4 + k])); 1567 } 1568 } 1569 1570 int temp = fpr.GetTempV(); 1571 fpr.MapRegV(temp, MAP_NOINIT | MAP_DIRTY); 1572 fpr.SpillLockV(temp); 1573 VMOV(fpr.V(temp), S0); 1574 tempregs[i] = temp; 1575 } 1576 for (int i = 0; i < n; i++) { 1577 u8 temp = tempregs[i]; 1578 fpr.MapRegV(dregs[i], MAP_NOINIT | MAP_DIRTY); 1579 VMOV(fpr.V(dregs[i]), fpr.V(temp)); 1580 } 1581 1582 fpr.ReleaseSpillLocksAndDiscardTemps(); 1583 } 1584 Comp_VCrs(MIPSOpcode op)1585 void ArmJit::Comp_VCrs(MIPSOpcode op) { 1586 NEON_IF_AVAILABLE(CompNEON_VCrs); 1587 DISABLE; 1588 } 1589 Comp_VDet(MIPSOpcode op)1590 void ArmJit::Comp_VDet(MIPSOpcode op) { 1591 NEON_IF_AVAILABLE(CompNEON_VDet); 1592 DISABLE; 1593 } 1594 Comp_Vi2x(MIPSOpcode op)1595 void ArmJit::Comp_Vi2x(MIPSOpcode op) { 1596 NEON_IF_AVAILABLE(CompNEON_Vi2x); 1597 CONDITIONAL_DISABLE(VFPU_VEC); 1598 if (js.HasUnknownPrefix()) { 1599 DISABLE; 1600 } 1601 1602 if (!cpu_info.bNEON) { 1603 DISABLE; 1604 } 1605 1606 int bits = ((op >> 16) & 2) == 0 ? 8 : 16; // vi2uc/vi2c (0/1), vi2us/vi2s (2/3) 1607 bool unsignedOp = ((op >> 16) & 1) == 0; // vi2uc (0), vi2us (2) 1608 1609 if (unsignedOp) { 1610 // Requires a tricky clamp operation that we can't do without more temps, see below 1611 DISABLE; 1612 } 1613 1614 // These instructions pack pairs or quads of integers into 32 bits. 1615 // The unsigned (u) versions skip the sign bit when packing. 1616 VectorSize sz = GetVecSize(op); 1617 VectorSize outsize; 1618 if (bits == 8) { 1619 outsize = V_Single; 1620 if (sz != V_Quad) { 1621 DISABLE; 1622 } 1623 } else { 1624 switch (sz) { 1625 case V_Pair: 1626 outsize = V_Single; 1627 break; 1628 case V_Quad: 1629 outsize = V_Pair; 1630 break; 1631 default: 1632 DISABLE; 1633 } 1634 } 1635 1636 u8 sregs[4], dregs[4]; 1637 GetVectorRegsPrefixS(sregs, sz, _VS); 1638 GetVectorRegsPrefixD(dregs, outsize, _VD); 1639 1640 // First, let's assemble the sregs into lanes of either D0 (pair) or Q0 (quad). 1641 bool quad = sz == V_Quad; 1642 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 1643 VMOV(S0, fpr.V(sregs[0])); 1644 VMOV(S1, fpr.V(sregs[1])); 1645 if (quad) { 1646 VMOV(S2, fpr.V(sregs[2])); 1647 VMOV(S3, fpr.V(sregs[3])); 1648 } 1649 1650 // TODO: For "u" type ops, we clamp to zero and shift off the sign bit first. 1651 // Need some temp regs to do that efficiently, right? 1652 1653 // At this point, we simply need to collect the high bits of each 32-bit lane into one register. 1654 if (bits == 8) { 1655 // Really want to do a VSHRN(..., 24) but that can't be encoded. So we synthesize it. 1656 VSHR(I_32, Q0, Q0, 16); 1657 VSHRN(I_32, D0, Q0, 8); 1658 VMOVN(I_16, D0, Q0); 1659 } else { 1660 VSHRN(I_32, D0, Q0, 16); 1661 } 1662 1663 fpr.MapRegsAndSpillLockV(dregs, outsize, MAP_DIRTY|MAP_NOINIT); 1664 VMOV(fpr.V(dregs[0]), S0); 1665 if (outsize == V_Pair) { 1666 VMOV(fpr.V(dregs[1]), S1); 1667 } 1668 1669 ApplyPrefixD(dregs, outsize); 1670 fpr.ReleaseSpillLocksAndDiscardTemps(); 1671 } 1672 Comp_Vx2i(MIPSOpcode op)1673 void ArmJit::Comp_Vx2i(MIPSOpcode op) { 1674 NEON_IF_AVAILABLE(CompNEON_Vx2i); 1675 CONDITIONAL_DISABLE(VFPU_VEC); 1676 if (js.HasUnknownPrefix()) { 1677 DISABLE; 1678 } 1679 1680 int bits = ((op >> 16) & 2) == 0 ? 8 : 16; // vuc2i/vc2i (0/1), vus2i/vs2i (2/3) 1681 bool unsignedOp = ((op >> 16) & 1) == 0; // vuc2i (0), vus2i (2) 1682 1683 if (bits == 8 && unsignedOp) { 1684 // vuc2i is odd and needs temp registers for implementation. 1685 DISABLE; 1686 } 1687 // vs2i or vus2i unpack pairs of 16-bit integers into 32-bit integers, with the values 1688 // at the top. vus2i shifts it an extra bit right afterward. 1689 // vc2i and vuc2i unpack quads of 8-bit integers into 32-bit integers, with the values 1690 // at the top too. vuc2i is a bit special (see below.) 1691 // Let's do this similarly as h2f - we do a solution that works for both singles and pairs 1692 // then use it for both. 1693 1694 VectorSize sz = GetVecSize(op); 1695 VectorSize outsize; 1696 if (bits == 8) { 1697 outsize = V_Quad; 1698 } else { 1699 switch (sz) { 1700 case V_Single: 1701 outsize = V_Pair; 1702 break; 1703 case V_Pair: 1704 outsize = V_Quad; 1705 break; 1706 default: 1707 DISABLE; 1708 } 1709 } 1710 1711 u8 sregs[4], dregs[4]; 1712 GetVectorRegsPrefixS(sregs, sz, _VS); 1713 GetVectorRegsPrefixD(dregs, outsize, _VD); 1714 1715 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 1716 if (sz == V_Single) { 1717 VMOV(S0, fpr.V(sregs[0])); 1718 } else if (sz == V_Pair) { 1719 VMOV(S0, fpr.V(sregs[0])); 1720 VMOV(S1, fpr.V(sregs[1])); 1721 } else if (bits == 8) { 1722 // For some reason, sz is quad on vc2i. 1723 VMOV(S0, fpr.V(sregs[0])); 1724 } 1725 1726 1727 if (bits == 16) { 1728 // Simply expand, to upper bits. 1729 VSHLL(I_16, Q0, D0, 16); 1730 } else if (bits == 8) { 1731 if (unsignedOp) { 1732 // vuc2i is a bit special. It spreads out the bits like this: 1733 // s[0] = 0xDDCCBBAA -> d[0] = (0xAAAAAAAA >> 1), d[1] = (0xBBBBBBBB >> 1), etc. 1734 // TODO 1735 } else { 1736 VSHLL(I_8, Q0, D0, 8); 1737 VSHLL(I_16, Q0, D0, 16); 1738 } 1739 } 1740 1741 // At this point we have the regs in the 4 lanes. 1742 // In the "u" mode, we need to shift it out of the sign bit. 1743 if (unsignedOp) { 1744 ArmGen::ARMReg reg = (outsize == V_Quad) ? Q0 : D0; 1745 VSHR(I_32 | I_UNSIGNED, reg, reg, 1); 1746 } 1747 1748 fpr.MapRegsAndSpillLockV(dregs, outsize, MAP_NOINIT); 1749 1750 VMOV(fpr.V(dregs[0]), S0); 1751 VMOV(fpr.V(dregs[1]), S1); 1752 if (outsize == V_Quad) { 1753 VMOV(fpr.V(dregs[2]), S2); 1754 VMOV(fpr.V(dregs[3]), S3); 1755 } 1756 1757 ApplyPrefixD(dregs, outsize); 1758 fpr.ReleaseSpillLocksAndDiscardTemps(); 1759 } 1760 Comp_VCrossQuat(MIPSOpcode op)1761 void ArmJit::Comp_VCrossQuat(MIPSOpcode op) { 1762 NEON_IF_AVAILABLE(CompNEON_VCrossQuat); 1763 // This op does not support prefixes anyway. 1764 CONDITIONAL_DISABLE(VFPU_VEC); 1765 if (js.HasUnknownPrefix()) 1766 DISABLE; 1767 1768 VectorSize sz = GetVecSize(op); 1769 int n = GetNumVectorElements(sz); 1770 1771 u8 sregs[4], tregs[4], dregs[4]; 1772 GetVectorRegs(sregs, sz, _VS); 1773 GetVectorRegs(tregs, sz, _VT); 1774 GetVectorRegs(dregs, sz, _VD); 1775 1776 // Map everything into registers. 1777 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 1778 fpr.MapRegsAndSpillLockV(tregs, sz, 0); 1779 1780 if (sz == V_Triple) { 1781 MIPSReg temp3 = fpr.GetTempV(); 1782 fpr.MapRegV(temp3, MAP_DIRTY | MAP_NOINIT); 1783 // Cross product vcrsp.t 1784 1785 // Compute X 1786 VMUL(S0, fpr.V(sregs[1]), fpr.V(tregs[2])); 1787 VMLS(S0, fpr.V(sregs[2]), fpr.V(tregs[1])); 1788 1789 // Compute Y 1790 VMUL(S1, fpr.V(sregs[2]), fpr.V(tregs[0])); 1791 VMLS(S1, fpr.V(sregs[0]), fpr.V(tregs[2])); 1792 1793 // Compute Z 1794 VMUL(fpr.V(temp3), fpr.V(sregs[0]), fpr.V(tregs[1])); 1795 VMLS(fpr.V(temp3), fpr.V(sregs[1]), fpr.V(tregs[0])); 1796 1797 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_NOINIT); 1798 VMOV(fpr.V(dregs[0]), S0); 1799 VMOV(fpr.V(dregs[1]), S1); 1800 VMOV(fpr.V(dregs[2]), fpr.V(temp3)); 1801 } else if (sz == V_Quad) { 1802 MIPSReg temp3 = fpr.GetTempV(); 1803 MIPSReg temp4 = fpr.GetTempV(); 1804 fpr.MapRegV(temp3, MAP_DIRTY | MAP_NOINIT); 1805 fpr.MapRegV(temp4, MAP_DIRTY | MAP_NOINIT); 1806 1807 // Quaternion product vqmul.q untested 1808 // d[0] = s[0] * t[3] + s[1] * t[2] - s[2] * t[1] + s[3] * t[0]; 1809 VMUL(S0, fpr.V(sregs[0]), fpr.V(tregs[3])); 1810 VMLA(S0, fpr.V(sregs[1]), fpr.V(tregs[2])); 1811 VMLS(S0, fpr.V(sregs[2]), fpr.V(tregs[1])); 1812 VMLA(S0, fpr.V(sregs[3]), fpr.V(tregs[0])); 1813 1814 //d[1] = -s[0] * t[2] + s[1] * t[3] + s[2] * t[0] + s[3] * t[1]; 1815 VNMUL(S1, fpr.V(sregs[0]), fpr.V(tregs[2])); 1816 VMLA(S1, fpr.V(sregs[1]), fpr.V(tregs[3])); 1817 VMLA(S1, fpr.V(sregs[2]), fpr.V(tregs[0])); 1818 VMLA(S1, fpr.V(sregs[3]), fpr.V(tregs[1])); 1819 1820 //d[2] = s[0] * t[1] - s[1] * t[0] + s[2] * t[3] + s[3] * t[2]; 1821 VMUL(fpr.V(temp3), fpr.V(sregs[0]), fpr.V(tregs[1])); 1822 VMLS(fpr.V(temp3), fpr.V(sregs[1]), fpr.V(tregs[0])); 1823 VMLA(fpr.V(temp3), fpr.V(sregs[2]), fpr.V(tregs[3])); 1824 VMLA(fpr.V(temp3), fpr.V(sregs[3]), fpr.V(tregs[2])); 1825 1826 //d[3] = -s[0] * t[0] - s[1] * t[1] - s[2] * t[2] + s[3] * t[3]; 1827 VNMUL(fpr.V(temp4), fpr.V(sregs[0]), fpr.V(tregs[0])); 1828 VMLS(fpr.V(temp4), fpr.V(sregs[1]), fpr.V(tregs[1])); 1829 VMLS(fpr.V(temp4), fpr.V(sregs[2]), fpr.V(tregs[2])); 1830 VMLA(fpr.V(temp4), fpr.V(sregs[3]), fpr.V(tregs[3])); 1831 1832 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_NOINIT); 1833 VMOV(fpr.V(dregs[0]), S0); 1834 VMOV(fpr.V(dregs[1]), S1); 1835 VMOV(fpr.V(dregs[2]), fpr.V(temp3)); 1836 VMOV(fpr.V(dregs[3]), fpr.V(temp4)); 1837 } 1838 1839 fpr.ReleaseSpillLocksAndDiscardTemps(); 1840 } 1841 Comp_Vcmp(MIPSOpcode op)1842 void ArmJit::Comp_Vcmp(MIPSOpcode op) { 1843 NEON_IF_AVAILABLE(CompNEON_Vcmp); 1844 CONDITIONAL_DISABLE(VFPU_COMP); 1845 if (js.HasUnknownPrefix()) 1846 DISABLE; 1847 1848 VectorSize sz = GetVecSize(op); 1849 int n = GetNumVectorElements(sz); 1850 1851 VCondition cond = (VCondition)(op & 0xF); 1852 1853 u8 sregs[4], tregs[4]; 1854 GetVectorRegsPrefixS(sregs, sz, _VS); 1855 GetVectorRegsPrefixT(tregs, sz, _VT); 1856 1857 // Some, we just fall back to the interpreter. 1858 // ES is just really equivalent to (value & 0x7F800000) == 0x7F800000. 1859 1860 switch (cond) { 1861 case VC_EI: // c = my_isinf(s[i]); break; 1862 case VC_NI: // c = !my_isinf(s[i]); break; 1863 DISABLE; 1864 case VC_ES: // c = my_isnan(s[i]) || my_isinf(s[i]); break; // Tekken Dark Resurrection 1865 case VC_NS: // c = !my_isnan(s[i]) && !my_isinf(s[i]); break; 1866 case VC_EN: // c = my_isnan(s[i]); break; 1867 case VC_NN: // c = !my_isnan(s[i]); break; 1868 if (_VS != _VT) 1869 DISABLE; 1870 break; 1871 1872 case VC_EZ: 1873 case VC_NZ: 1874 break; 1875 default: 1876 ; 1877 } 1878 1879 // First, let's get the trivial ones. 1880 int affected_bits = (1 << 4) | (1 << 5); // 4 and 5 1881 1882 MOVI2R(SCRATCHREG1, 0); 1883 for (int i = 0; i < n; ++i) { 1884 // Let's only handle the easy ones, and fall back on the interpreter for the rest. 1885 CCFlags flag = CC_AL; 1886 switch (cond) { 1887 case VC_FL: // c = 0; 1888 break; 1889 1890 case VC_TR: // c = 1 1891 if (i == 0) { 1892 if (n == 1) { 1893 MOVI2R(SCRATCHREG1, 0x31); 1894 } else { 1895 MOVI2R(SCRATCHREG1, 1 << i); 1896 } 1897 } else { 1898 ORR(SCRATCHREG1, SCRATCHREG1, 1 << i); 1899 } 1900 break; 1901 1902 case VC_ES: // c = my_isnan(s[i]) || my_isinf(s[i]); break; // Tekken Dark Resurrection 1903 case VC_NS: // c = !(my_isnan(s[i]) || my_isinf(s[i])); break; 1904 // For these, we use the integer ALU as there is no support on ARM for testing for INF. 1905 // Testing for nan or inf is the same as testing for &= 0x7F800000 == 0x7F800000. 1906 // We need an extra temporary register so we store away SCRATCHREG1. 1907 STR(SCRATCHREG1, CTXREG, offsetof(MIPSState, temp)); 1908 fpr.MapRegV(sregs[i], 0); 1909 MOVI2R(SCRATCHREG1, 0x7F800000); 1910 VMOV(SCRATCHREG2, fpr.V(sregs[i])); 1911 AND(SCRATCHREG2, SCRATCHREG2, SCRATCHREG1); 1912 CMP(SCRATCHREG2, SCRATCHREG1); // (SCRATCHREG2 & 0x7F800000) == 0x7F800000 1913 flag = cond == VC_ES ? CC_EQ : CC_NEQ; 1914 LDR(SCRATCHREG1, CTXREG, offsetof(MIPSState, temp)); 1915 break; 1916 1917 case VC_EN: // c = my_isnan(s[i]); break; // Tekken 6 1918 // Should we involve T? Where I found this used, it compared a register with itself so should be fine. 1919 fpr.MapInInV(sregs[i], tregs[i]); 1920 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1921 VMRS_APSR(); 1922 flag = CC_VS; // overflow = unordered : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdhcfbc.html 1923 break; 1924 1925 case VC_NN: // c = !my_isnan(s[i]); break; 1926 // Should we involve T? Where I found this used, it compared a register with itself so should be fine. 1927 fpr.MapInInV(sregs[i], tregs[i]); 1928 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1929 VMRS_APSR(); 1930 flag = CC_VC; // !overflow = !unordered : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0204j/Chdhcfbc.html 1931 break; 1932 1933 case VC_EQ: // c = s[i] == t[i] 1934 fpr.MapInInV(sregs[i], tregs[i]); 1935 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1936 VMRS_APSR(); 1937 flag = CC_EQ; 1938 break; 1939 1940 case VC_LT: // c = s[i] < t[i] 1941 fpr.MapInInV(sregs[i], tregs[i]); 1942 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1943 VMRS_APSR(); 1944 flag = CC_LO; 1945 break; 1946 1947 case VC_LE: // c = s[i] <= t[i]; 1948 fpr.MapInInV(sregs[i], tregs[i]); 1949 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1950 VMRS_APSR(); 1951 flag = CC_LS; 1952 break; 1953 1954 case VC_NE: // c = s[i] != t[i] 1955 fpr.MapInInV(sregs[i], tregs[i]); 1956 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1957 VMRS_APSR(); 1958 flag = CC_NEQ; 1959 break; 1960 1961 case VC_GE: // c = s[i] >= t[i] 1962 fpr.MapInInV(sregs[i], tregs[i]); 1963 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1964 VMRS_APSR(); 1965 flag = CC_GE; 1966 break; 1967 1968 case VC_GT: // c = s[i] > t[i] 1969 fpr.MapInInV(sregs[i], tregs[i]); 1970 VCMP(fpr.V(sregs[i]), fpr.V(tregs[i])); 1971 VMRS_APSR(); 1972 flag = CC_GT; 1973 break; 1974 1975 case VC_EZ: // c = s[i] == 0.0f || s[i] == -0.0f 1976 fpr.MapRegV(sregs[i]); 1977 VCMP(fpr.V(sregs[i])); // vcmp(sregs[i], #0.0) 1978 VMRS_APSR(); 1979 flag = CC_EQ; 1980 break; 1981 1982 case VC_NZ: // c = s[i] != 0 1983 fpr.MapRegV(sregs[i]); 1984 VCMP(fpr.V(sregs[i])); // vcmp(sregs[i], #0.0) 1985 VMRS_APSR(); 1986 flag = CC_NEQ; 1987 break; 1988 1989 default: 1990 DISABLE; 1991 } 1992 if (flag != CC_AL) { 1993 SetCC(flag); 1994 if (i == 0) { 1995 if (n == 1) { 1996 MOVI2R(SCRATCHREG1, 0x31); 1997 } else { 1998 MOVI2R(SCRATCHREG1, 1); // 1 << i, but i == 0 1999 } 2000 } else { 2001 ORR(SCRATCHREG1, SCRATCHREG1, 1 << i); 2002 } 2003 SetCC(CC_AL); 2004 } 2005 2006 affected_bits |= 1 << i; 2007 } 2008 2009 // Aggregate the bits. Urgh, expensive. Can optimize for the case of one comparison, which is the most common 2010 // after all. 2011 if (n > 1) { 2012 CMP(SCRATCHREG1, affected_bits & 0xF); 2013 SetCC(CC_EQ); 2014 ORR(SCRATCHREG1, SCRATCHREG1, 1 << 5); 2015 SetCC(CC_AL); 2016 2017 CMP(SCRATCHREG1, 0); 2018 SetCC(CC_NEQ); 2019 ORR(SCRATCHREG1, SCRATCHREG1, 1 << 4); 2020 SetCC(CC_AL); 2021 } 2022 2023 gpr.MapReg(MIPS_REG_VFPUCC, MAP_DIRTY); 2024 BIC(gpr.R(MIPS_REG_VFPUCC), gpr.R(MIPS_REG_VFPUCC), affected_bits); 2025 ORR(gpr.R(MIPS_REG_VFPUCC), gpr.R(MIPS_REG_VFPUCC), SCRATCHREG1); 2026 2027 fpr.ReleaseSpillLocksAndDiscardTemps(); 2028 } 2029 Comp_Vcmov(MIPSOpcode op)2030 void ArmJit::Comp_Vcmov(MIPSOpcode op) { 2031 NEON_IF_AVAILABLE(CompNEON_Vcmov); 2032 CONDITIONAL_DISABLE(VFPU_COMP); 2033 if (js.HasUnknownPrefix()) { 2034 DISABLE; 2035 } 2036 2037 VectorSize sz = GetVecSize(op); 2038 int n = GetNumVectorElements(sz); 2039 2040 u8 sregs[4], dregs[4]; 2041 GetVectorRegsPrefixS(sregs, sz, _VS); 2042 GetVectorRegsPrefixD(dregs, sz, _VD); 2043 int tf = (op >> 19) & 1; 2044 int imm3 = (op >> 16) & 7; 2045 2046 for (int i = 0; i < n; ++i) { 2047 // Simplification: Disable if overlap unsafe 2048 if (!IsOverlapSafeAllowS(dregs[i], i, n, sregs)) { 2049 DISABLE; 2050 } 2051 } 2052 2053 if (imm3 < 6) { 2054 // Test one bit of CC. This bit decides whether none or all subregisters are copied. 2055 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_DIRTY); 2056 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 2057 gpr.MapReg(MIPS_REG_VFPUCC); 2058 TST(gpr.R(MIPS_REG_VFPUCC), 1 << imm3); 2059 SetCC(tf ? CC_EQ : CC_NEQ); 2060 for (int i = 0; i < n; i++) { 2061 VMOV(fpr.V(dregs[i]), fpr.V(sregs[i])); 2062 } 2063 SetCC(CC_AL); 2064 } else { 2065 // Look at the bottom four bits of CC to individually decide if the subregisters should be copied. 2066 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_DIRTY); 2067 fpr.MapRegsAndSpillLockV(sregs, sz, 0); 2068 gpr.MapReg(MIPS_REG_VFPUCC); 2069 for (int i = 0; i < n; i++) { 2070 TST(gpr.R(MIPS_REG_VFPUCC), 1 << i); 2071 SetCC(tf ? CC_EQ : CC_NEQ); 2072 VMOV(fpr.V(dregs[i]), fpr.V(sregs[i])); 2073 SetCC(CC_AL); 2074 } 2075 } 2076 2077 ApplyPrefixD(dregs, sz); 2078 fpr.ReleaseSpillLocksAndDiscardTemps(); 2079 } 2080 Comp_Viim(MIPSOpcode op)2081 void ArmJit::Comp_Viim(MIPSOpcode op) { 2082 NEON_IF_AVAILABLE(CompNEON_Viim); 2083 CONDITIONAL_DISABLE(VFPU_XFER); 2084 if (js.HasUnknownPrefix()) { 2085 DISABLE; 2086 } 2087 2088 u8 dreg; 2089 GetVectorRegs(&dreg, V_Single, _VT); 2090 2091 s32 imm = SignExtend16ToS32(op); 2092 fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT); 2093 MOVI2F(fpr.V(dreg), (float)imm, SCRATCHREG1); 2094 2095 ApplyPrefixD(&dreg, V_Single); 2096 fpr.ReleaseSpillLocksAndDiscardTemps(); 2097 } 2098 Comp_Vfim(MIPSOpcode op)2099 void ArmJit::Comp_Vfim(MIPSOpcode op) { 2100 NEON_IF_AVAILABLE(CompNEON_Vfim); 2101 CONDITIONAL_DISABLE(VFPU_XFER); 2102 if (js.HasUnknownPrefix()) { 2103 DISABLE; 2104 } 2105 2106 u8 dreg; 2107 GetVectorRegs(&dreg, V_Single, _VT); 2108 2109 FP16 half; 2110 half.u = op & 0xFFFF; 2111 FP32 fval = half_to_float_fast5(half); 2112 fpr.MapRegV(dreg, MAP_DIRTY | MAP_NOINIT); 2113 MOVI2F(fpr.V(dreg), fval.f, SCRATCHREG1); 2114 2115 ApplyPrefixD(&dreg, V_Single); 2116 fpr.ReleaseSpillLocksAndDiscardTemps(); 2117 } 2118 Comp_Vcst(MIPSOpcode op)2119 void ArmJit::Comp_Vcst(MIPSOpcode op) { 2120 NEON_IF_AVAILABLE(CompNEON_Vcst); 2121 CONDITIONAL_DISABLE(VFPU_XFER); 2122 if (js.HasUnknownPrefix()) { 2123 DISABLE; 2124 } 2125 2126 int conNum = (op >> 16) & 0x1f; 2127 int vd = _VD; 2128 2129 VectorSize sz = GetVecSize(op); 2130 int n = GetNumVectorElements(sz); 2131 2132 u8 dregs[4]; 2133 GetVectorRegsPrefixD(dregs, sz, _VD); 2134 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_NOINIT | MAP_DIRTY); 2135 2136 gpr.SetRegImm(SCRATCHREG1, (u32)(void *)&cst_constants[conNum]); 2137 VLDR(S0, SCRATCHREG1, 0); 2138 for (int i = 0; i < n; ++i) 2139 VMOV(fpr.V(dregs[i]), S0); 2140 2141 ApplyPrefixD(dregs, sz); 2142 fpr.ReleaseSpillLocksAndDiscardTemps(); 2143 } 2144 SinCos(float angle)2145 static double SinCos(float angle) { 2146 union { struct { float sin; float cos; }; double out; } sincos; 2147 vfpu_sincos(angle, sincos.sin, sincos.cos); 2148 return sincos.out; 2149 } 2150 SinCosNegSin(float angle)2151 static double SinCosNegSin(float angle) { 2152 union { struct { float sin; float cos; }; double out; } sincos; 2153 vfpu_sincos(angle, sincos.sin, sincos.cos); 2154 sincos.sin = -sincos.sin; 2155 return sincos.out; 2156 } 2157 CompVrotShuffle(u8 * dregs,int imm,VectorSize sz,bool negSin)2158 void ArmJit::CompVrotShuffle(u8 *dregs, int imm, VectorSize sz, bool negSin) { 2159 int n = GetNumVectorElements(sz); 2160 char what[4] = {'0', '0', '0', '0'}; 2161 if (((imm >> 2) & 3) == (imm & 3)) { 2162 for (int i = 0; i < 4; i++) 2163 what[i] = 'S'; 2164 } 2165 what[(imm >> 2) & 3] = 'S'; 2166 what[imm & 3] = 'C'; 2167 2168 fpr.MapRegsAndSpillLockV(dregs, sz, MAP_DIRTY | MAP_NOINIT); 2169 for (int i = 0; i < n; i++) { 2170 switch (what[i]) { 2171 case 'C': VMOV(fpr.V(dregs[i]), S1); break; 2172 case 'S': if (negSin) VNEG(fpr.V(dregs[i]), S0); else VMOV(fpr.V(dregs[i]), S0); break; 2173 case '0': 2174 { 2175 MOVI2F(fpr.V(dregs[i]), 0.0f, SCRATCHREG1); 2176 break; 2177 } 2178 default: 2179 ERROR_LOG(JIT, "Bad what in vrot"); 2180 break; 2181 } 2182 } 2183 } 2184 2185 // Very heavily used by FF:CC. Should be replaced by a fast approximation instead of 2186 // calling the math library. 2187 // Apparently this may not work on hardfp. I don't think we have any platforms using this though. Comp_VRot(MIPSOpcode op)2188 void ArmJit::Comp_VRot(MIPSOpcode op) { 2189 NEON_IF_AVAILABLE(CompNEON_VRot); 2190 // VRot probably doesn't accept prefixes anyway. 2191 CONDITIONAL_DISABLE(VFPU_VEC); 2192 if (js.HasUnknownPrefix()) { 2193 DISABLE; 2194 } 2195 2196 #if PPSSPP_ARCH(ARM_HARDFP) 2197 DISABLE; 2198 #endif 2199 2200 int vd = _VD; 2201 int vs = _VS; 2202 2203 VectorSize sz = GetVecSize(op); 2204 int n = GetNumVectorElements(sz); 2205 2206 u8 dregs[4]; 2207 u8 dregs2[4]; 2208 2209 MIPSOpcode nextOp = GetOffsetInstruction(1); 2210 int vd2 = -1; 2211 int imm2 = -1; 2212 if ((nextOp >> 26) == 60 && ((nextOp >> 21) & 0x1F) == 29 && _VS == MIPS_GET_VS(nextOp)) { 2213 // Pair of vrot. Let's join them. 2214 vd2 = MIPS_GET_VD(nextOp); 2215 imm2 = (nextOp >> 16) & 0x1f; 2216 // NOTICE_LOG(JIT, "Joint VFPU at %08x", js.blockStart); 2217 } 2218 u8 sreg; 2219 GetVectorRegs(dregs, sz, vd); 2220 if (vd2 >= 0) 2221 GetVectorRegs(dregs2, sz, vd2); 2222 GetVectorRegs(&sreg, V_Single, vs); 2223 2224 int imm = (op >> 16) & 0x1f; 2225 2226 gpr.FlushBeforeCall(); 2227 fpr.FlushAll(); 2228 2229 bool negSin1 = (imm & 0x10) ? true : false; 2230 2231 fpr.MapRegV(sreg); 2232 // We should write a custom pure-asm function instead. 2233 #if defined(__ARM_PCS_VFP) // Hardfp 2234 VMOV(S0, fpr.V(sreg)); 2235 #else // Softfp 2236 VMOV(R0, fpr.V(sreg)); 2237 #endif 2238 // FlushBeforeCall saves R1. 2239 QuickCallFunction(R1, negSin1 ? (void *)&SinCosNegSin : (void *)&SinCos); 2240 #if !defined(__ARM_PCS_VFP) 2241 // Returns D0 on hardfp and R0,R1 on softfp due to union joining the two floats 2242 VMOV(D0, R0, R1); 2243 #endif 2244 CompVrotShuffle(dregs, imm, sz, false); 2245 if (vd2 != -1) { 2246 // If the negsin setting differs between the two joint invocations, we need to flip the second one. 2247 bool negSin2 = (imm2 & 0x10) ? true : false; 2248 CompVrotShuffle(dregs2, imm2, sz, negSin1 != negSin2); 2249 EatInstruction(nextOp); 2250 } 2251 2252 fpr.ReleaseSpillLocksAndDiscardTemps(); 2253 } 2254 Comp_Vsgn(MIPSOpcode op)2255 void ArmJit::Comp_Vsgn(MIPSOpcode op) { 2256 NEON_IF_AVAILABLE(CompNEON_Vsgn); 2257 CONDITIONAL_DISABLE(VFPU_VEC); 2258 if (js.HasUnknownPrefix()) { 2259 DISABLE; 2260 } 2261 2262 VectorSize sz = GetVecSize(op); 2263 int n = GetNumVectorElements(sz); 2264 2265 u8 sregs[4], dregs[4]; 2266 GetVectorRegsPrefixS(sregs, sz, _VS); 2267 GetVectorRegsPrefixD(dregs, sz, _VD); 2268 2269 MIPSReg tempregs[4]; 2270 for (int i = 0; i < n; ++i) { 2271 if (!IsOverlapSafe(dregs[i], i, n, sregs)) { 2272 tempregs[i] = fpr.GetTempV(); 2273 } else { 2274 tempregs[i] = dregs[i]; 2275 } 2276 } 2277 2278 for (int i = 0; i < n; ++i) { 2279 fpr.MapDirtyInV(tempregs[i], sregs[i]); 2280 VCMP(fpr.V(sregs[i])); // vcmp(sregs[i], #0.0) 2281 VMOV(SCRATCHREG1, fpr.V(sregs[i])); 2282 VMRS_APSR(); // Move FP flags from FPSCR to APSR (regular flags). 2283 SetCC(CC_NEQ); 2284 AND(SCRATCHREG1, SCRATCHREG1, AssumeMakeOperand2(0x80000000)); 2285 ORR(SCRATCHREG1, SCRATCHREG1, AssumeMakeOperand2(0x3F800000)); 2286 SetCC(CC_EQ); 2287 MOV(SCRATCHREG1, AssumeMakeOperand2(0x0)); 2288 SetCC(CC_AL); 2289 VMOV(fpr.V(tempregs[i]), SCRATCHREG1); 2290 } 2291 2292 for (int i = 0; i < n; ++i) { 2293 if (dregs[i] != tempregs[i]) { 2294 fpr.MapDirtyInV(dregs[i], tempregs[i]); 2295 VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); 2296 } 2297 } 2298 2299 ApplyPrefixD(dregs, sz); 2300 2301 fpr.ReleaseSpillLocksAndDiscardTemps(); 2302 } 2303 Comp_Vocp(MIPSOpcode op)2304 void ArmJit::Comp_Vocp(MIPSOpcode op) { 2305 NEON_IF_AVAILABLE(CompNEON_Vocp); 2306 CONDITIONAL_DISABLE(VFPU_VEC); 2307 if (js.HasUnknownPrefix()) { 2308 DISABLE; 2309 } 2310 2311 VectorSize sz = GetVecSize(op); 2312 int n = GetNumVectorElements(sz); 2313 2314 // This is a hack that modifies prefixes. We eat them later, so just overwrite. 2315 // S prefix forces the negate flags. 2316 js.prefixS |= 0x000F0000; 2317 // T prefix forces constants on and regnum to 1. 2318 // That means negate still works, and abs activates a different constant. 2319 js.prefixT = (js.prefixT & ~0x000000FF) | 0x00000055 | 0x0000F000; 2320 2321 u8 sregs[4], tregs[4], dregs[4]; 2322 GetVectorRegsPrefixS(sregs, sz, _VS); 2323 GetVectorRegsPrefixT(tregs, sz, _VS); 2324 GetVectorRegsPrefixD(dregs, sz, _VD); 2325 2326 MIPSReg tempregs[4]; 2327 for (int i = 0; i < n; ++i) { 2328 if (!IsOverlapSafe(dregs[i], i, n, sregs)) { 2329 tempregs[i] = fpr.GetTempV(); 2330 } else { 2331 tempregs[i] = dregs[i]; 2332 } 2333 } 2334 2335 for (int i = 0; i < n; ++i) { 2336 fpr.MapDirtyInInV(tempregs[i], sregs[i], tregs[i]); 2337 VADD(fpr.V(tempregs[i]), fpr.V(tregs[i]), fpr.V(sregs[i])); 2338 } 2339 2340 for (int i = 0; i < n; ++i) { 2341 if (dregs[i] != tempregs[i]) { 2342 fpr.MapDirtyInV(dregs[i], tempregs[i]); 2343 VMOV(fpr.V(dregs[i]), fpr.V(tempregs[i])); 2344 } 2345 } 2346 2347 ApplyPrefixD(dregs, sz); 2348 2349 fpr.ReleaseSpillLocksAndDiscardTemps(); 2350 } 2351 Comp_ColorConv(MIPSOpcode op)2352 void ArmJit::Comp_ColorConv(MIPSOpcode op) { 2353 DISABLE; 2354 } 2355 Comp_Vbfy(MIPSOpcode op)2356 void ArmJit::Comp_Vbfy(MIPSOpcode op) { 2357 DISABLE; 2358 } 2359 } 2360 2361 #endif // PPSSPP_ARCH(ARM) 2362