1 #include "qemu/osdep.h"
2 #include "cpu.h"
3 #include "internal.h"
4 #include "migration/cpu.h"
5 
cpu_post_load(void * opaque,int version_id)6 static int cpu_post_load(void *opaque, int version_id)
7 {
8     MIPSCPU *cpu = opaque;
9     CPUMIPSState *env = &cpu->env;
10 
11     restore_fp_status(env);
12     restore_msa_fp_status(env);
13     compute_hflags(env);
14     restore_pamask(env);
15 
16     return 0;
17 }
18 
19 /* FPU state */
20 
get_fpr(QEMUFile * f,void * pv,size_t size,const VMStateField * field)21 static int get_fpr(QEMUFile *f, void *pv, size_t size,
22                    const VMStateField *field)
23 {
24     int i;
25     fpr_t *v = pv;
26     /* Restore entire MSA vector register */
27     for (i = 0; i < MSA_WRLEN / 64; i++) {
28         qemu_get_sbe64s(f, &v->wr.d[i]);
29     }
30     return 0;
31 }
32 
put_fpr(QEMUFile * f,void * pv,size_t size,const VMStateField * field,QJSON * vmdesc)33 static int put_fpr(QEMUFile *f, void *pv, size_t size,
34                    const VMStateField *field, QJSON *vmdesc)
35 {
36     int i;
37     fpr_t *v = pv;
38     /* Save entire MSA vector register */
39     for (i = 0; i < MSA_WRLEN / 64; i++) {
40         qemu_put_sbe64s(f, &v->wr.d[i]);
41     }
42 
43     return 0;
44 }
45 
46 const VMStateInfo vmstate_info_fpr = {
47     .name = "fpr",
48     .get  = get_fpr,
49     .put  = put_fpr,
50 };
51 
52 #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v)                     \
53     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t)
54 
55 #define VMSTATE_FPR_ARRAY(_f, _s, _n)                           \
56     VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0)
57 
58 static VMStateField vmstate_fpu_fields[] = {
59     VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32),
60     VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
61     VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
62     VMSTATE_END_OF_LIST()
63 };
64 
65 const VMStateDescription vmstate_fpu = {
66     .name = "cpu/fpu",
67     .version_id = 1,
68     .minimum_version_id = 1,
69     .fields = vmstate_fpu_fields
70 };
71 
72 const VMStateDescription vmstate_inactive_fpu = {
73     .name = "cpu/inactive_fpu",
74     .version_id = 1,
75     .minimum_version_id = 1,
76     .fields = vmstate_fpu_fields
77 };
78 
79 /* TC state */
80 
81 static VMStateField vmstate_tc_fields[] = {
82     VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
83 #ifdef TARGET_CHERI
84     VMSTATE_UINTTL(PCC._cr_cursor, TCState),
85 #else
86     VMSTATE_UINTTL(PC, TCState),
87 #endif
88     VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
89     VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
90     VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
91     VMSTATE_UINTTL(DSPControl, TCState),
92     VMSTATE_INT32(CP0_TCStatus, TCState),
93     VMSTATE_INT32(CP0_TCBind, TCState),
94     VMSTATE_UINTTL(CP0_TCHalt, TCState),
95     VMSTATE_UINTTL(CP0_TCContext, TCState),
96     VMSTATE_UINTTL(CP0_TCSchedule, TCState),
97     VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
98     VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
99     VMSTATE_UINTTL(CP0_UserLocal, TCState),
100     VMSTATE_INT32(msacsr, TCState),
101     VMSTATE_END_OF_LIST()
102 };
103 
104 const VMStateDescription vmstate_tc = {
105     .name = "cpu/tc",
106     .version_id = 1,
107     .minimum_version_id = 1,
108     .fields = vmstate_tc_fields
109 };
110 
111 const VMStateDescription vmstate_inactive_tc = {
112     .name = "cpu/inactive_tc",
113     .version_id = 1,
114     .minimum_version_id = 1,
115     .fields = vmstate_tc_fields
116 };
117 
118 /* MVP state */
119 
120 const VMStateDescription vmstate_mvp = {
121     .name = "cpu/mvp",
122     .version_id = 1,
123     .minimum_version_id = 1,
124     .fields = (VMStateField[]) {
125         VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext),
126         VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext),
127         VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext),
128         VMSTATE_END_OF_LIST()
129     }
130 };
131 
132 /* TLB state */
133 
get_tlb(QEMUFile * f,void * pv,size_t size,const VMStateField * field)134 static int get_tlb(QEMUFile *f, void *pv, size_t size,
135                    const VMStateField *field)
136 {
137     r4k_tlb_t *v = pv;
138     uint16_t flags;
139 
140     qemu_get_betls(f, &v->VPN);
141     qemu_get_be32s(f, &v->PageMask);
142     qemu_get_be16s(f, &v->ASID);
143     qemu_get_be16s(f, &flags);
144     v->G = (flags >> 10) & 1;
145     v->C0 = (flags >> 7) & 3;
146     v->C1 = (flags >> 4) & 3;
147     v->V0 = (flags >> 3) & 1;
148     v->V1 = (flags >> 2) & 1;
149     v->D0 = (flags >> 1) & 1;
150     v->D1 = (flags >> 0) & 1;
151     v->EHINV = (flags >> 15) & 1;
152 #if defined(TARGET_CHERI)
153     v->S1 = (flags >> 14) & 1;
154     v->S0 = (flags >> 13) & 1;
155     v->L1 = (flags >> 12) & 1;
156     v->L0 = (flags >> 11) & 1;
157 #else
158     v->RI1 = (flags >> 14) & 1;
159     v->RI0 = (flags >> 13) & 1;
160     v->XI1 = (flags >> 12) & 1;
161     v->XI0 = (flags >> 11) & 1;
162 #endif /* TARGET_CHERI */
163     qemu_get_be64s(f, &v->PFN[0]);
164     qemu_get_be64s(f, &v->PFN[1]);
165 
166     return 0;
167 }
168 
put_tlb(QEMUFile * f,void * pv,size_t size,const VMStateField * field,QJSON * vmdesc)169 static int put_tlb(QEMUFile *f, void *pv, size_t size,
170                    const VMStateField *field, QJSON *vmdesc)
171 {
172     r4k_tlb_t *v = pv;
173 
174     uint16_t asid = v->ASID;
175     uint16_t flags = ((v->EHINV << 15) |
176 #if defined(TARGET_CHERI)
177                       (v->S1 << 14) |
178                       (v->S0 << 13) |
179                       (v->L1 << 12) |
180                       (v->L0 << 11) |
181 #else
182                       (v->RI1 << 14) |
183                       (v->RI0 << 13) |
184                       (v->XI1 << 12) |
185                       (v->XI0 << 11) |
186 #endif /* TARGET_CHERI */
187                       (v->G << 10) |
188                       (v->C0 << 7) |
189                       (v->C1 << 4) |
190                       (v->V0 << 3) |
191                       (v->V1 << 2) |
192                       (v->D0 << 1) |
193                       (v->D1 << 0));
194 
195     qemu_put_betls(f, &v->VPN);
196     qemu_put_be32s(f, &v->PageMask);
197     qemu_put_be16s(f, &asid);
198     qemu_put_be16s(f, &flags);
199     qemu_put_be64s(f, &v->PFN[0]);
200     qemu_put_be64s(f, &v->PFN[1]);
201 
202     return 0;
203 }
204 
205 const VMStateInfo vmstate_info_tlb = {
206     .name = "tlb_entry",
207     .get  = get_tlb,
208     .put  = put_tlb,
209 };
210 
211 #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v)                     \
212     VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t)
213 
214 #define VMSTATE_TLB_ARRAY(_f, _s, _n)                           \
215     VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0)
216 
217 const VMStateDescription vmstate_tlb = {
218     .name = "cpu/tlb",
219     .version_id = 2,
220     .minimum_version_id = 2,
221     .fields = (VMStateField[]) {
222         VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),
223         VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),
224         VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX),
225         VMSTATE_END_OF_LIST()
226     }
227 };
228 
229 /* MIPS CPU state */
230 
231 const VMStateDescription vmstate_mips_cpu = {
232     .name = "cpu",
233     .version_id = 19,
234     .minimum_version_id = 19,
235     .post_load = cpu_post_load,
236     .fields = (VMStateField[]) {
237         /* Active TC */
238         VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState),
239 
240         /* Active FPU */
241         VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu,
242                        CPUMIPSFPUContext),
243 
244         /* MVP */
245         VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp,
246                                CPUMIPSMVPContext),
247 
248         /* TLB */
249         VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb,
250                                CPUMIPSTLBContext),
251 
252         /* CPU metastate */
253         VMSTATE_UINT32(env.current_tc, MIPSCPU),
254         VMSTATE_UINT32(env.current_fpu, MIPSCPU),
255         VMSTATE_INT32(env.error_code, MIPSCPU),
256         VMSTATE_UINTTL(env.btarget, MIPSCPU),
257         VMSTATE_UINTTL(env.bcond, MIPSCPU),
258 
259         /* Remaining CP0 registers */
260         VMSTATE_INT32(env.CP0_Index, MIPSCPU),
261         VMSTATE_INT32(env.CP0_Random, MIPSCPU),
262         VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU),
263         VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU),
264         VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU),
265         VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU),
266         VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU),
267         VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU),
268         VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU),
269         VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
270         VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
271         VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
272         VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
273         VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
274         VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
275         VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),
276         VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU),
277         VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU),
278         VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU),
279         VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
280         VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
281         VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
282         VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
283         VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
284         VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
285         VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
286         VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU),
287         VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU),
288         VMSTATE_INT32(env.CP0_HWREna, MIPSCPU),
289         VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU),
290         VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU),
291         VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU),
292         VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU),
293         VMSTATE_INT32(env.CP0_Count, MIPSCPU),
294         VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU),
295         VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2),
296         VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU),
297         VMSTATE_INT32(env.CP0_Compare, MIPSCPU),
298         VMSTATE_INT32(env.CP0_Status, MIPSCPU),
299         VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU),
300         VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU),
301         VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU),
302         VMSTATE_INT32(env.CP0_Cause, MIPSCPU),
303 #ifndef TARGET_CHERI
304         // FIXME: would be nice to print for CHERI but needs direct field access
305         VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU),
306 #endif
307         VMSTATE_INT32(env.CP0_PRid, MIPSCPU),
308         VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU),
309         VMSTATE_INT32(env.CP0_Config0, MIPSCPU),
310         VMSTATE_INT32(env.CP0_Config1, MIPSCPU),
311         VMSTATE_INT32(env.CP0_Config2, MIPSCPU),
312         VMSTATE_INT32(env.CP0_Config3, MIPSCPU),
313         VMSTATE_INT32(env.CP0_Config6, MIPSCPU),
314         VMSTATE_INT32(env.CP0_Config7, MIPSCPU),
315         VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU),
316         VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX),
317         VMSTATE_INT32(env.CP0_MAARI, MIPSCPU),
318         VMSTATE_UINTTL(env.lladdr, MIPSCPU),
319         VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8),
320         VMSTATE_UINT64_ARRAY(env.CP0_WatchHi, MIPSCPU, 8),
321         VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU),
322         VMSTATE_INT32(env.CP0_Framemask, MIPSCPU),
323         VMSTATE_INT32(env.CP0_Debug, MIPSCPU),
324         VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU),
325         VMSTATE_INT32(env.CP0_Performance0, MIPSCPU),
326         VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU),
327         VMSTATE_INT32(env.CP0_DataLo, MIPSCPU),
328         VMSTATE_INT32(env.CP0_TagHi, MIPSCPU),
329         VMSTATE_INT32(env.CP0_DataHi, MIPSCPU),
330 #ifndef TARGET_CHERI
331         // FIXME: would be nice to print for CHERI but needs direct field access
332         VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU),
333 #endif
334         VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU),
335         VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM),
336 
337         /* Inactive TC */
338         VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1,
339                              vmstate_inactive_tc, TCState),
340         VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1,
341                              vmstate_inactive_fpu, CPUMIPSFPUContext),
342 
343         VMSTATE_END_OF_LIST()
344     },
345 };
346