1 /*
2 * qemu user cpu loop
3 *
4 * Copyright (c) 2003-2008 Fabrice Bellard
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu.h"
23 #include "user-internals.h"
24 #include "cpu_loop-common.h"
25 #include "signal-common.h"
26 #include "qemu/guest-random.h"
27 #include "semihosting/common-semi.h"
28 #include "target/arm/syndrome.h"
29
30 #define get_user_code_u32(x, gaddr, env) \
31 ({ abi_long __r = get_user_u32((x), (gaddr)); \
32 if (!__r && bswap_code(arm_sctlr_b(env))) { \
33 (x) = bswap32(x); \
34 } \
35 __r; \
36 })
37
38 #define get_user_code_u16(x, gaddr, env) \
39 ({ abi_long __r = get_user_u16((x), (gaddr)); \
40 if (!__r && bswap_code(arm_sctlr_b(env))) { \
41 (x) = bswap16(x); \
42 } \
43 __r; \
44 })
45
46 #define get_user_data_u32(x, gaddr, env) \
47 ({ abi_long __r = get_user_u32((x), (gaddr)); \
48 if (!__r && arm_cpu_bswap_data(env)) { \
49 (x) = bswap32(x); \
50 } \
51 __r; \
52 })
53
54 #define get_user_data_u16(x, gaddr, env) \
55 ({ abi_long __r = get_user_u16((x), (gaddr)); \
56 if (!__r && arm_cpu_bswap_data(env)) { \
57 (x) = bswap16(x); \
58 } \
59 __r; \
60 })
61
62 #define put_user_data_u32(x, gaddr, env) \
63 ({ typeof(x) __x = (x); \
64 if (arm_cpu_bswap_data(env)) { \
65 __x = bswap32(__x); \
66 } \
67 put_user_u32(__x, (gaddr)); \
68 })
69
70 #define put_user_data_u16(x, gaddr, env) \
71 ({ typeof(x) __x = (x); \
72 if (arm_cpu_bswap_data(env)) { \
73 __x = bswap16(__x); \
74 } \
75 put_user_u16(__x, (gaddr)); \
76 })
77
78 /* AArch64 main loop */
cpu_loop(CPUARMState * env)79 void cpu_loop(CPUARMState *env)
80 {
81 CPUState *cs = env_cpu(env);
82 int trapnr, ec, fsc, si_code;
83 abi_long ret;
84
85 for (;;) {
86 cpu_exec_start(cs);
87 trapnr = cpu_exec(cs);
88 cpu_exec_end(cs);
89 process_queued_cpu_work(cs);
90
91 switch (trapnr) {
92 case EXCP_SWI:
93 ret = do_syscall(env,
94 env->xregs[8],
95 env->xregs[0],
96 env->xregs[1],
97 env->xregs[2],
98 env->xregs[3],
99 env->xregs[4],
100 env->xregs[5],
101 0, 0);
102 if (ret == -TARGET_ERESTARTSYS) {
103 env->pc -= 4;
104 } else if (ret != -TARGET_QEMU_ESIGRETURN) {
105 env->xregs[0] = ret;
106 }
107 break;
108 case EXCP_INTERRUPT:
109 /* just indicate that signals should be handled asap */
110 break;
111 case EXCP_UDEF:
112 force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
113 break;
114 case EXCP_PREFETCH_ABORT:
115 case EXCP_DATA_ABORT:
116 /* We should only arrive here with EC in {DATAABORT, INSNABORT}. */
117 ec = syn_get_ec(env->exception.syndrome);
118 assert(ec == EC_DATAABORT || ec == EC_INSNABORT);
119
120 /* Both EC have the same format for FSC, or close enough. */
121 fsc = extract32(env->exception.syndrome, 0, 6);
122 switch (fsc) {
123 case 0x04 ... 0x07: /* Translation fault, level {0-3} */
124 si_code = TARGET_SEGV_MAPERR;
125 break;
126 case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */
127 case 0x0d ... 0x0f: /* Permission fault, level {1-3} */
128 si_code = TARGET_SEGV_ACCERR;
129 break;
130 case 0x11: /* Synchronous Tag Check Fault */
131 si_code = TARGET_SEGV_MTESERR;
132 break;
133 default:
134 g_assert_not_reached();
135 }
136
137 force_sig_fault(TARGET_SIGSEGV, si_code, env->exception.vaddress);
138 break;
139 case EXCP_DEBUG:
140 case EXCP_BKPT:
141 force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
142 break;
143 case EXCP_SEMIHOST:
144 env->xregs[0] = do_common_semihosting(cs);
145 env->pc += 4;
146 break;
147 case EXCP_YIELD:
148 /* nothing to do here for user-mode, just resume guest code */
149 break;
150 case EXCP_ATOMIC:
151 cpu_exec_step_atomic(cs);
152 break;
153 default:
154 EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
155 abort();
156 }
157
158 /* Check for MTE asynchronous faults */
159 if (unlikely(env->cp15.tfsr_el[0])) {
160 env->cp15.tfsr_el[0] = 0;
161 force_sig_fault(TARGET_SIGSEGV, TARGET_SEGV_MTEAERR, 0);
162 }
163
164 process_pending_signals(env);
165 /* Exception return on AArch64 always clears the exclusive monitor,
166 * so any return to running guest code implies this.
167 */
168 env->exclusive_addr = -1;
169 }
170 }
171
target_cpu_copy_regs(CPUArchState * env,struct target_pt_regs * regs)172 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
173 {
174 ARMCPU *cpu = env_archcpu(env);
175 CPUState *cs = env_cpu(env);
176 TaskState *ts = cs->opaque;
177 struct image_info *info = ts->info;
178 int i;
179
180 if (!(arm_feature(env, ARM_FEATURE_AARCH64))) {
181 fprintf(stderr,
182 "The selected ARM CPU does not support 64 bit mode\n");
183 exit(EXIT_FAILURE);
184 }
185
186 for (i = 0; i < 31; i++) {
187 env->xregs[i] = regs->regs[i];
188 }
189 env->pc = regs->pc;
190 env->xregs[31] = regs->sp;
191 #ifdef TARGET_WORDS_BIGENDIAN
192 env->cp15.sctlr_el[1] |= SCTLR_E0E;
193 for (i = 1; i < 4; ++i) {
194 env->cp15.sctlr_el[i] |= SCTLR_EE;
195 }
196 arm_rebuild_hflags(env);
197 #endif
198
199 if (cpu_isar_feature(aa64_pauth, cpu)) {
200 qemu_guest_getrandom_nofail(&env->keys, sizeof(env->keys));
201 }
202
203 ts->stack_base = info->start_stack;
204 ts->heap_base = info->brk;
205 /* This will be filled in on the first SYS_HEAPINFO call. */
206 ts->heap_limit = 0;
207 }
208