1 /*
2 * S/390 virtual CPU header
3 *
4 * For details on the s390x architecture and used definitions (e.g.,
5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to
6 * the "z/Architecture Principles of Operations" - a.k.a. PoP.
7 *
8 * Copyright (c) 2009 Ulrich Hecht
9 * Copyright IBM Corp. 2012, 2018
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #ifndef S390X_CPU_H
26 #define S390X_CPU_H
27
28 #include "cpu-qom.h"
29 #include "cpu_models.h"
30 #include "exec/cpu-defs.h"
31
32 #define ELF_MACHINE_UNAME "S390X"
33
34 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */
35 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
36
37 #define TARGET_INSN_START_EXTRA_WORDS 2
38
39 #define MMU_USER_IDX 0
40
41 #define S390_MAX_CPUS 248
42
43 #ifndef CONFIG_KVM
44 #define S390_ADAPTER_SUPPRESSIBLE 0x01
45 #else
46 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE
47 #endif
48
49 typedef struct PSW {
50 uint64_t mask;
51 uint64_t addr;
52 } PSW;
53
54 struct CPUS390XState {
55 uint64_t regs[16]; /* GP registers */
56 /*
57 * The floating point registers are part of the vector registers.
58 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
59 */
60 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
61 uint32_t aregs[16]; /* access registers */
62 uint64_t gscb[4]; /* guarded storage control */
63 uint64_t etoken; /* etoken */
64 uint64_t etoken_extension; /* etoken extension */
65
66 /* Fields up to this point are not cleared by initial CPU reset */
67 struct {} start_initial_reset_fields;
68
69 uint32_t fpc; /* floating-point control register */
70 uint32_t cc_op;
71 bool bpbc; /* branch prediction blocking */
72
73 float_status fpu_status; /* passed to softfloat lib */
74
75 /* The low part of a 128-bit return, or remainder of a divide. */
76 uint64_t retxl;
77
78 PSW psw;
79
80 S390CrashReason crash_reason;
81
82 uint64_t cc_src;
83 uint64_t cc_dst;
84 uint64_t cc_vr;
85
86 uint64_t ex_value;
87
88 uint64_t __excp_addr;
89 uint64_t psa;
90
91 uint32_t int_pgm_code;
92 uint32_t int_pgm_ilen;
93
94 uint32_t int_svc_code;
95 uint32_t int_svc_ilen;
96
97 uint64_t per_address;
98 uint16_t per_perc_atmid;
99
100 uint64_t cregs[16]; /* control registers */
101
102 uint64_t ckc;
103 uint64_t cputm;
104 uint32_t todpr;
105
106 uint64_t pfault_token;
107 uint64_t pfault_compare;
108 uint64_t pfault_select;
109
110 uint64_t gbea;
111 uint64_t pp;
112
113 /* Fields up to this point are not cleared by normal CPU reset */
114 struct {} start_normal_reset_fields;
115 uint8_t riccb[64]; /* runtime instrumentation control */
116
117 int pending_int;
118 uint16_t external_call_addr;
119 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
120
121 uint64_t diag318_info;
122
123 #if !defined(CONFIG_USER_ONLY)
124 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */
125 int tlb_fill_exc; /* exception number seen during tlb_fill */
126 #endif
127
128 /* Fields up to this point are cleared by a CPU reset */
129 struct {} end_reset_fields;
130
131 #if !defined(CONFIG_USER_ONLY)
132 uint32_t core_id; /* PoP "CPU address", same as cpu_index */
133 uint64_t cpuid;
134 #endif
135
136 QEMUTimer *tod_timer;
137
138 QEMUTimer *cpu_timer;
139
140 /*
141 * The cpu state represents the logical state of a cpu. In contrast to other
142 * architectures, there is a difference between a halt and a stop on s390.
143 * If all cpus are either stopped (including check stop) or in the disabled
144 * wait state, the vm can be shut down.
145 * The acceptable cpu_state values are defined in the CpuInfoS390State
146 * enum.
147 */
148 uint8_t cpu_state;
149
150 /* currently processed sigp order */
151 uint8_t sigp_order;
152
153 };
154
get_freg(CPUS390XState * cs,int nr)155 static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
156 {
157 return &cs->vregs[nr][0];
158 }
159
160 /**
161 * S390CPU:
162 * @env: #CPUS390XState.
163 *
164 * An S/390 CPU.
165 */
166 struct S390CPU {
167 /*< private >*/
168 CPUState parent_obj;
169 /*< public >*/
170
171 CPUNegativeOffsetState neg;
172 CPUS390XState env;
173 S390CPUModel *model;
174 /* needed for live migration */
175 void *irqstate;
176 uint32_t irqstate_saved_size;
177 };
178
179
180 #ifndef CONFIG_USER_ONLY
181 extern const VMStateDescription vmstate_s390_cpu;
182 #endif
183
184 /* distinguish between 24 bit and 31 bit addressing */
185 #define HIGH_ORDER_BIT 0x80000000
186
187 /* Interrupt Codes */
188 /* Program Interrupts */
189 #define PGM_OPERATION 0x0001
190 #define PGM_PRIVILEGED 0x0002
191 #define PGM_EXECUTE 0x0003
192 #define PGM_PROTECTION 0x0004
193 #define PGM_ADDRESSING 0x0005
194 #define PGM_SPECIFICATION 0x0006
195 #define PGM_DATA 0x0007
196 #define PGM_FIXPT_OVERFLOW 0x0008
197 #define PGM_FIXPT_DIVIDE 0x0009
198 #define PGM_DEC_OVERFLOW 0x000a
199 #define PGM_DEC_DIVIDE 0x000b
200 #define PGM_HFP_EXP_OVERFLOW 0x000c
201 #define PGM_HFP_EXP_UNDERFLOW 0x000d
202 #define PGM_HFP_SIGNIFICANCE 0x000e
203 #define PGM_HFP_DIVIDE 0x000f
204 #define PGM_SEGMENT_TRANS 0x0010
205 #define PGM_PAGE_TRANS 0x0011
206 #define PGM_TRANS_SPEC 0x0012
207 #define PGM_SPECIAL_OP 0x0013
208 #define PGM_OPERAND 0x0015
209 #define PGM_TRACE_TABLE 0x0016
210 #define PGM_VECTOR_PROCESSING 0x001b
211 #define PGM_SPACE_SWITCH 0x001c
212 #define PGM_HFP_SQRT 0x001d
213 #define PGM_PC_TRANS_SPEC 0x001f
214 #define PGM_AFX_TRANS 0x0020
215 #define PGM_ASX_TRANS 0x0021
216 #define PGM_LX_TRANS 0x0022
217 #define PGM_EX_TRANS 0x0023
218 #define PGM_PRIM_AUTH 0x0024
219 #define PGM_SEC_AUTH 0x0025
220 #define PGM_ALET_SPEC 0x0028
221 #define PGM_ALEN_SPEC 0x0029
222 #define PGM_ALE_SEQ 0x002a
223 #define PGM_ASTE_VALID 0x002b
224 #define PGM_ASTE_SEQ 0x002c
225 #define PGM_EXT_AUTH 0x002d
226 #define PGM_STACK_FULL 0x0030
227 #define PGM_STACK_EMPTY 0x0031
228 #define PGM_STACK_SPEC 0x0032
229 #define PGM_STACK_TYPE 0x0033
230 #define PGM_STACK_OP 0x0034
231 #define PGM_ASCE_TYPE 0x0038
232 #define PGM_REG_FIRST_TRANS 0x0039
233 #define PGM_REG_SEC_TRANS 0x003a
234 #define PGM_REG_THIRD_TRANS 0x003b
235 #define PGM_MONITOR 0x0040
236 #define PGM_PER 0x0080
237 #define PGM_CRYPTO 0x0119
238
239 /* External Interrupts */
240 #define EXT_INTERRUPT_KEY 0x0040
241 #define EXT_CLOCK_COMP 0x1004
242 #define EXT_CPU_TIMER 0x1005
243 #define EXT_MALFUNCTION 0x1200
244 #define EXT_EMERGENCY 0x1201
245 #define EXT_EXTERNAL_CALL 0x1202
246 #define EXT_ETR 0x1406
247 #define EXT_SERVICE 0x2401
248 #define EXT_VIRTIO 0x2603
249
250 /* PSW defines */
251 #undef PSW_MASK_PER
252 #undef PSW_MASK_UNUSED_2
253 #undef PSW_MASK_UNUSED_3
254 #undef PSW_MASK_DAT
255 #undef PSW_MASK_IO
256 #undef PSW_MASK_EXT
257 #undef PSW_MASK_KEY
258 #undef PSW_SHIFT_KEY
259 #undef PSW_MASK_MCHECK
260 #undef PSW_MASK_WAIT
261 #undef PSW_MASK_PSTATE
262 #undef PSW_MASK_ASC
263 #undef PSW_SHIFT_ASC
264 #undef PSW_MASK_CC
265 #undef PSW_MASK_PM
266 #undef PSW_MASK_RI
267 #undef PSW_SHIFT_MASK_PM
268 #undef PSW_MASK_64
269 #undef PSW_MASK_32
270 #undef PSW_MASK_ESA_ADDR
271
272 #define PSW_MASK_PER 0x4000000000000000ULL
273 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL
274 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL
275 #define PSW_MASK_DAT 0x0400000000000000ULL
276 #define PSW_MASK_IO 0x0200000000000000ULL
277 #define PSW_MASK_EXT 0x0100000000000000ULL
278 #define PSW_MASK_KEY 0x00F0000000000000ULL
279 #define PSW_SHIFT_KEY 52
280 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
281 #define PSW_MASK_MCHECK 0x0004000000000000ULL
282 #define PSW_MASK_WAIT 0x0002000000000000ULL
283 #define PSW_MASK_PSTATE 0x0001000000000000ULL
284 #define PSW_MASK_ASC 0x0000C00000000000ULL
285 #define PSW_SHIFT_ASC 46
286 #define PSW_MASK_CC 0x0000300000000000ULL
287 #define PSW_MASK_PM 0x00000F0000000000ULL
288 #define PSW_SHIFT_MASK_PM 40
289 #define PSW_MASK_RI 0x0000008000000000ULL
290 #define PSW_MASK_64 0x0000000100000000ULL
291 #define PSW_MASK_32 0x0000000080000000ULL
292 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
293 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
294
295 #undef PSW_ASC_PRIMARY
296 #undef PSW_ASC_ACCREG
297 #undef PSW_ASC_SECONDARY
298 #undef PSW_ASC_HOME
299
300 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
301 #define PSW_ASC_ACCREG 0x0000400000000000ULL
302 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
303 #define PSW_ASC_HOME 0x0000C00000000000ULL
304
305 /* the address space values shifted */
306 #define AS_PRIMARY 0
307 #define AS_ACCREG 1
308 #define AS_SECONDARY 2
309 #define AS_HOME 3
310
311 /* tb flags */
312
313 #define FLAG_MASK_PSW_SHIFT 31
314 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
315 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
316 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
317 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
318 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
319 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
320 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
321 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
322
323 /* we'll use some unused PSW positions to store CR flags in tb flags */
324 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
325 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
326
327 /* Control register 0 bits */
328 #define CR0_LOWPROT 0x0000000010000000ULL
329 #define CR0_SECONDARY 0x0000000004000000ULL
330 #define CR0_EDAT 0x0000000000800000ULL
331 #define CR0_AFP 0x0000000000040000ULL
332 #define CR0_VECTOR 0x0000000000020000ULL
333 #define CR0_IEP 0x0000000000100000ULL
334 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
335 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
336 #define CR0_CKC_SC 0x0000000000000800ULL
337 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
338 #define CR0_SERVICE_SC 0x0000000000000200ULL
339
340 /* Control register 14 bits */
341 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
342
343 /* MMU */
344 #define MMU_PRIMARY_IDX 0
345 #define MMU_SECONDARY_IDX 1
346 #define MMU_HOME_IDX 2
347 #define MMU_REAL_IDX 3
348
cpu_mmu_index(CPUS390XState * env,bool ifetch)349 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
350 {
351 #ifdef CONFIG_USER_ONLY
352 return MMU_USER_IDX;
353 #else
354 if (!(env->psw.mask & PSW_MASK_DAT)) {
355 return MMU_REAL_IDX;
356 }
357
358 if (ifetch) {
359 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
360 return MMU_HOME_IDX;
361 }
362 return MMU_PRIMARY_IDX;
363 }
364
365 switch (env->psw.mask & PSW_MASK_ASC) {
366 case PSW_ASC_PRIMARY:
367 return MMU_PRIMARY_IDX;
368 case PSW_ASC_SECONDARY:
369 return MMU_SECONDARY_IDX;
370 case PSW_ASC_HOME:
371 return MMU_HOME_IDX;
372 case PSW_ASC_ACCREG:
373 /* Fallthrough: access register mode is not yet supported */
374 default:
375 abort();
376 }
377 #endif
378 }
379
cpu_get_tb_cpu_state(CPUS390XState * env,target_ulong * pc,target_ulong * cs_base,uint32_t * flags)380 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
381 target_ulong *cs_base, uint32_t *flags)
382 {
383 *pc = env->psw.addr;
384 *cs_base = env->ex_value;
385 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
386 if (env->cregs[0] & CR0_AFP) {
387 *flags |= FLAG_MASK_AFP;
388 }
389 if (env->cregs[0] & CR0_VECTOR) {
390 *flags |= FLAG_MASK_VECTOR;
391 }
392 }
393
394 /* PER bits from control register 9 */
395 #define PER_CR9_EVENT_BRANCH 0x80000000
396 #define PER_CR9_EVENT_IFETCH 0x40000000
397 #define PER_CR9_EVENT_STORE 0x20000000
398 #define PER_CR9_EVENT_STORE_REAL 0x08000000
399 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
400 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
401 #define PER_CR9_CONTROL_ALTERATION 0x00200000
402
403 /* PER bits from the PER CODE/ATMID/AI in lowcore */
404 #define PER_CODE_EVENT_BRANCH 0x8000
405 #define PER_CODE_EVENT_IFETCH 0x4000
406 #define PER_CODE_EVENT_STORE 0x2000
407 #define PER_CODE_EVENT_STORE_REAL 0x0800
408 #define PER_CODE_EVENT_NULLIFICATION 0x0100
409
410 #define EXCP_EXT 1 /* external interrupt */
411 #define EXCP_SVC 2 /* supervisor call (syscall) */
412 #define EXCP_PGM 3 /* program interruption */
413 #define EXCP_RESTART 4 /* restart interrupt */
414 #define EXCP_STOP 5 /* stop interrupt */
415 #define EXCP_IO 7 /* I/O interrupt */
416 #define EXCP_MCHK 8 /* machine check */
417
418 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
419 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
420 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
421 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
422 #define INTERRUPT_RESTART (1 << 7)
423 #define INTERRUPT_STOP (1 << 8)
424
425 /* Program Status Word. */
426 #define S390_PSWM_REGNUM 0
427 #define S390_PSWA_REGNUM 1
428 /* General Purpose Registers. */
429 #define S390_R0_REGNUM 2
430 #define S390_R1_REGNUM 3
431 #define S390_R2_REGNUM 4
432 #define S390_R3_REGNUM 5
433 #define S390_R4_REGNUM 6
434 #define S390_R5_REGNUM 7
435 #define S390_R6_REGNUM 8
436 #define S390_R7_REGNUM 9
437 #define S390_R8_REGNUM 10
438 #define S390_R9_REGNUM 11
439 #define S390_R10_REGNUM 12
440 #define S390_R11_REGNUM 13
441 #define S390_R12_REGNUM 14
442 #define S390_R13_REGNUM 15
443 #define S390_R14_REGNUM 16
444 #define S390_R15_REGNUM 17
445 /* Total Core Registers. */
446 #define S390_NUM_CORE_REGS 18
447
setcc(S390CPU * cpu,uint64_t cc)448 static inline void setcc(S390CPU *cpu, uint64_t cc)
449 {
450 CPUS390XState *env = &cpu->env;
451
452 env->psw.mask &= ~(3ull << 44);
453 env->psw.mask |= (cc & 3) << 44;
454 env->cc_op = cc;
455 }
456
457 /* STSI */
458 #define STSI_R0_FC_MASK 0x00000000f0000000ULL
459 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL
460 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
461 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
462 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
463 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
464 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
465 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
466 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
467
468 /* Basic Machine Configuration */
469 typedef struct SysIB_111 {
470 uint8_t res1[32];
471 uint8_t manuf[16];
472 uint8_t type[4];
473 uint8_t res2[12];
474 uint8_t model[16];
475 uint8_t sequence[16];
476 uint8_t plant[4];
477 uint8_t res3[3996];
478 } SysIB_111;
479 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
480
481 /* Basic Machine CPU */
482 typedef struct SysIB_121 {
483 uint8_t res1[80];
484 uint8_t sequence[16];
485 uint8_t plant[4];
486 uint8_t res2[2];
487 uint16_t cpu_addr;
488 uint8_t res3[3992];
489 } SysIB_121;
490 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
491
492 /* Basic Machine CPUs */
493 typedef struct SysIB_122 {
494 uint8_t res1[32];
495 uint32_t capability;
496 uint16_t total_cpus;
497 uint16_t conf_cpus;
498 uint16_t standby_cpus;
499 uint16_t reserved_cpus;
500 uint16_t adjustments[2026];
501 } SysIB_122;
502 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
503
504 /* LPAR CPU */
505 typedef struct SysIB_221 {
506 uint8_t res1[80];
507 uint8_t sequence[16];
508 uint8_t plant[4];
509 uint16_t cpu_id;
510 uint16_t cpu_addr;
511 uint8_t res3[3992];
512 } SysIB_221;
513 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
514
515 /* LPAR CPUs */
516 typedef struct SysIB_222 {
517 uint8_t res1[32];
518 uint16_t lpar_num;
519 uint8_t res2;
520 uint8_t lcpuc;
521 uint16_t total_cpus;
522 uint16_t conf_cpus;
523 uint16_t standby_cpus;
524 uint16_t reserved_cpus;
525 uint8_t name[8];
526 uint32_t caf;
527 uint8_t res3[16];
528 uint16_t dedicated_cpus;
529 uint16_t shared_cpus;
530 uint8_t res4[4020];
531 } SysIB_222;
532 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
533
534 /* VM CPUs */
535 typedef struct SysIB_322 {
536 uint8_t res1[31];
537 uint8_t count;
538 struct {
539 uint8_t res2[4];
540 uint16_t total_cpus;
541 uint16_t conf_cpus;
542 uint16_t standby_cpus;
543 uint16_t reserved_cpus;
544 uint8_t name[8];
545 uint32_t caf;
546 uint8_t cpi[16];
547 uint8_t res5[3];
548 uint8_t ext_name_encoding;
549 uint32_t res3;
550 uint8_t uuid[16];
551 } vm[8];
552 uint8_t res4[1504];
553 uint8_t ext_names[8][256];
554 } SysIB_322;
555 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
556
557 typedef union SysIB {
558 SysIB_111 sysib_111;
559 SysIB_121 sysib_121;
560 SysIB_122 sysib_122;
561 SysIB_221 sysib_221;
562 SysIB_222 sysib_222;
563 SysIB_322 sysib_322;
564 } SysIB;
565 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
566
567 /* MMU defines */
568 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
569 #define ASCE_SUBSPACE 0x200 /* subspace group control */
570 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */
571 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
572 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */
573 #define ASCE_REAL_SPACE 0x20 /* real space control */
574 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */
575 #define ASCE_TYPE_REGION1 0x0c /* region first table type */
576 #define ASCE_TYPE_REGION2 0x08 /* region second table type */
577 #define ASCE_TYPE_REGION3 0x04 /* region third table type */
578 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
579 #define ASCE_TABLE_LENGTH 0x03 /* region table length */
580
581 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL
582 #define REGION_ENTRY_P 0x0000000000000200ULL
583 #define REGION_ENTRY_TF 0x00000000000000c0ULL
584 #define REGION_ENTRY_I 0x0000000000000020ULL
585 #define REGION_ENTRY_TT 0x000000000000000cULL
586 #define REGION_ENTRY_TL 0x0000000000000003ULL
587
588 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL
589 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL
590 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL
591
592 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL
593 #define REGION3_ENTRY_AV 0x0000000000010000ULL
594 #define REGION3_ENTRY_ACC 0x000000000000f000ULL
595 #define REGION3_ENTRY_F 0x0000000000000800ULL
596 #define REGION3_ENTRY_FC 0x0000000000000400ULL
597 #define REGION3_ENTRY_IEP 0x0000000000000100ULL
598 #define REGION3_ENTRY_CR 0x0000000000000010ULL
599
600 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL
601 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL
602 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL
603 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL
604 #define SEGMENT_ENTRY_F 0x0000000000000800ULL
605 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL
606 #define SEGMENT_ENTRY_P 0x0000000000000200ULL
607 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL
608 #define SEGMENT_ENTRY_I 0x0000000000000020ULL
609 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL
610 #define SEGMENT_ENTRY_TT 0x000000000000000cULL
611
612 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL
613
614 #define PAGE_ENTRY_0 0x0000000000000800ULL
615 #define PAGE_ENTRY_I 0x0000000000000400ULL
616 #define PAGE_ENTRY_P 0x0000000000000200ULL
617 #define PAGE_ENTRY_IEP 0x0000000000000100ULL
618
619 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL
620 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL
621 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL
622 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL
623 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL
624
625 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
626 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
627 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
628 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
629 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
630
631 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62)
632 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51)
633 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40)
634 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29)
635
636 #define SK_C (0x1 << 1)
637 #define SK_R (0x1 << 2)
638 #define SK_F (0x1 << 3)
639 #define SK_ACC_MASK (0xf << 4)
640
641 /* SIGP order codes */
642 #define SIGP_SENSE 0x01
643 #define SIGP_EXTERNAL_CALL 0x02
644 #define SIGP_EMERGENCY 0x03
645 #define SIGP_START 0x04
646 #define SIGP_STOP 0x05
647 #define SIGP_RESTART 0x06
648 #define SIGP_STOP_STORE_STATUS 0x09
649 #define SIGP_INITIAL_CPU_RESET 0x0b
650 #define SIGP_CPU_RESET 0x0c
651 #define SIGP_SET_PREFIX 0x0d
652 #define SIGP_STORE_STATUS_ADDR 0x0e
653 #define SIGP_SET_ARCH 0x12
654 #define SIGP_COND_EMERGENCY 0x13
655 #define SIGP_SENSE_RUNNING 0x15
656 #define SIGP_STORE_ADTL_STATUS 0x17
657
658 /* SIGP condition codes */
659 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
660 #define SIGP_CC_STATUS_STORED 1
661 #define SIGP_CC_BUSY 2
662 #define SIGP_CC_NOT_OPERATIONAL 3
663
664 /* SIGP status bits */
665 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
666 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
667 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
668 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
669 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
670 #define SIGP_STAT_STOPPED 0x00000040UL
671 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
672 #define SIGP_STAT_CHECK_STOP 0x00000010UL
673 #define SIGP_STAT_INOPERATIVE 0x00000004UL
674 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
675 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
676
677 /* SIGP SET ARCHITECTURE modes */
678 #define SIGP_MODE_ESA_S390 0
679 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
680 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
681
682 /* SIGP order code mask corresponding to bit positions 56-63 */
683 #define SIGP_ORDER_MASK 0x000000ff
684
685 /* machine check interruption code */
686
687 /* subclasses */
688 #define MCIC_SC_SD 0x8000000000000000ULL
689 #define MCIC_SC_PD 0x4000000000000000ULL
690 #define MCIC_SC_SR 0x2000000000000000ULL
691 #define MCIC_SC_CD 0x0800000000000000ULL
692 #define MCIC_SC_ED 0x0400000000000000ULL
693 #define MCIC_SC_DG 0x0100000000000000ULL
694 #define MCIC_SC_W 0x0080000000000000ULL
695 #define MCIC_SC_CP 0x0040000000000000ULL
696 #define MCIC_SC_SP 0x0020000000000000ULL
697 #define MCIC_SC_CK 0x0010000000000000ULL
698
699 /* subclass modifiers */
700 #define MCIC_SCM_B 0x0002000000000000ULL
701 #define MCIC_SCM_DA 0x0000000020000000ULL
702 #define MCIC_SCM_AP 0x0000000000080000ULL
703
704 /* storage errors */
705 #define MCIC_SE_SE 0x0000800000000000ULL
706 #define MCIC_SE_SC 0x0000400000000000ULL
707 #define MCIC_SE_KE 0x0000200000000000ULL
708 #define MCIC_SE_DS 0x0000100000000000ULL
709 #define MCIC_SE_IE 0x0000000080000000ULL
710
711 /* validity bits */
712 #define MCIC_VB_WP 0x0000080000000000ULL
713 #define MCIC_VB_MS 0x0000040000000000ULL
714 #define MCIC_VB_PM 0x0000020000000000ULL
715 #define MCIC_VB_IA 0x0000010000000000ULL
716 #define MCIC_VB_FA 0x0000008000000000ULL
717 #define MCIC_VB_VR 0x0000004000000000ULL
718 #define MCIC_VB_EC 0x0000002000000000ULL
719 #define MCIC_VB_FP 0x0000001000000000ULL
720 #define MCIC_VB_GR 0x0000000800000000ULL
721 #define MCIC_VB_CR 0x0000000400000000ULL
722 #define MCIC_VB_ST 0x0000000100000000ULL
723 #define MCIC_VB_AR 0x0000000040000000ULL
724 #define MCIC_VB_GS 0x0000000008000000ULL
725 #define MCIC_VB_PR 0x0000000000200000ULL
726 #define MCIC_VB_FC 0x0000000000100000ULL
727 #define MCIC_VB_CT 0x0000000000020000ULL
728 #define MCIC_VB_CC 0x0000000000010000ULL
729
s390_build_validity_mcic(void)730 static inline uint64_t s390_build_validity_mcic(void)
731 {
732 uint64_t mcic;
733
734 /*
735 * Indicate all validity bits (no damage) only. Other bits have to be
736 * added by the caller. (storage errors, subclasses and subclass modifiers)
737 */
738 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
739 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
740 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
741 if (s390_has_feat(S390_FEAT_VECTOR)) {
742 mcic |= MCIC_VB_VR;
743 }
744 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
745 mcic |= MCIC_VB_GS;
746 }
747 return mcic;
748 }
749
s390_do_cpu_full_reset(CPUState * cs,run_on_cpu_data arg)750 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
751 {
752 cpu_reset(cs);
753 }
754
s390_do_cpu_reset(CPUState * cs,run_on_cpu_data arg)755 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
756 {
757 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
758
759 scc->reset(cs, S390_CPU_RESET_NORMAL);
760 }
761
s390_do_cpu_initial_reset(CPUState * cs,run_on_cpu_data arg)762 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
763 {
764 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
765
766 scc->reset(cs, S390_CPU_RESET_INITIAL);
767 }
768
s390_do_cpu_load_normal(CPUState * cs,run_on_cpu_data arg)769 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
770 {
771 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
772
773 scc->load_normal(cs);
774 }
775
776
777 /* cpu.c */
778 void s390_crypto_reset(void);
779 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
780 void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
781 void s390_cmma_reset(void);
782 void s390_enable_css_support(S390CPU *cpu);
783 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg);
784 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
785 int vq, bool assign);
786 #ifndef CONFIG_USER_ONLY
787 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
788 #else
s390_cpu_set_state(uint8_t cpu_state,S390CPU * cpu)789 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
790 {
791 return 0;
792 }
793 #endif /* CONFIG_USER_ONLY */
s390_cpu_get_state(S390CPU * cpu)794 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
795 {
796 return cpu->env.cpu_state;
797 }
798
799
800 /* cpu_models.c */
801 void s390_cpu_list(void);
802 #define cpu_list s390_cpu_list
803 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
804 const S390FeatInit feat_init);
805
806
807 /* helper.c */
808 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
809 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
810 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
811
812 /* interrupt.c */
813 #define RA_IGNORED 0
814 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);
815 /* service interrupts are floating therefore we must not pass an cpustate */
816 void s390_sclp_extint(uint32_t parm);
817
818 /* mmu_helper.c */
819 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
820 int len, bool is_write);
821 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
822 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
823 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
824 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
825 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
826 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
827 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
828 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
829 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
830 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
831 int len, bool is_write);
832 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \
833 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
834 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \
835 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
836
837 /* sigp.c */
838 int s390_cpu_restart(S390CPU *cpu);
839 void s390_init_sigp(void);
840
841 /* helper.c */
842 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
843 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env);
844
845 /* outside of target/s390x/ */
846 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
847
848 typedef CPUS390XState CPUArchState;
849 typedef S390CPU ArchCPU;
850
851 #include "exec/cpu-all.h"
852
853 #endif
854