1 /* 2 * Copyright (c) 2008-2011 Atheros Communications Inc. 3 * 4 * Modified for iPXE by Scott K Logan <logans@cottsay.net> July 2011 5 * Original from Linux kernel 3.0.1 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef MAC_H 21 #define MAC_H 22 23 FILE_LICENCE ( BSD2 ); 24 25 #include <unistd.h> 26 27 #define RXSTATUS_RATE(ah, ads) (AR_SREV_5416_20_OR_LATER(ah) ? \ 28 MS(ads->ds_rxstatus0, AR_RxRate) : \ 29 (ads->ds_rxstatus3 >> 2) & 0xFF) 30 31 #define set11nTries(_series, _index) \ 32 (SM((_series)[_index].Tries, AR_XmitDataTries##_index)) 33 34 #define set11nRate(_series, _index) \ 35 (SM((_series)[_index].Rate, AR_XmitRate##_index)) 36 37 #define set11nPktDurRTSCTS(_series, _index) \ 38 (SM((_series)[_index].PktDuration, AR_PacketDur##_index) | \ 39 ((_series)[_index].RateFlags & ATH9K_RATESERIES_RTS_CTS ? \ 40 AR_RTSCTSQual##_index : 0)) 41 42 #define set11nRateFlags(_series, _index) \ 43 (((_series)[_index].RateFlags & ATH9K_RATESERIES_2040 ? \ 44 AR_2040_##_index : 0) \ 45 |((_series)[_index].RateFlags & ATH9K_RATESERIES_HALFGI ? \ 46 AR_GI##_index : 0) \ 47 |((_series)[_index].RateFlags & ATH9K_RATESERIES_STBC ? \ 48 AR_STBC##_index : 0) \ 49 |SM((_series)[_index].ChSel, AR_ChainSel##_index)) 50 51 #define CCK_SIFS_TIME 10 52 #define CCK_PREAMBLE_BITS 144 53 #define CCK_PLCP_BITS 48 54 55 #define OFDM_SIFS_TIME 16 56 #define OFDM_PREAMBLE_TIME 20 57 #define OFDM_PLCP_BITS 22 58 #define OFDM_SYMBOL_TIME 4 59 60 #define OFDM_SIFS_TIME_HALF 32 61 #define OFDM_PREAMBLE_TIME_HALF 40 62 #define OFDM_PLCP_BITS_HALF 22 63 #define OFDM_SYMBOL_TIME_HALF 8 64 65 #define OFDM_SIFS_TIME_QUARTER 64 66 #define OFDM_PREAMBLE_TIME_QUARTER 80 67 #define OFDM_PLCP_BITS_QUARTER 22 68 #define OFDM_SYMBOL_TIME_QUARTER 16 69 70 #define INIT_AIFS 2 71 #define INIT_CWMIN 15 72 #define INIT_CWMIN_11B 31 73 #define INIT_CWMAX 1023 74 #define INIT_SH_RETRY 10 75 #define INIT_LG_RETRY 10 76 #define INIT_SSH_RETRY 32 77 #define INIT_SLG_RETRY 32 78 79 #define ATH9K_SLOT_TIME_6 6 80 #define ATH9K_SLOT_TIME_9 9 81 #define ATH9K_SLOT_TIME_20 20 82 83 #define ATH9K_TXERR_XRETRY 0x01 84 #define ATH9K_TXERR_FILT 0x02 85 #define ATH9K_TXERR_FIFO 0x04 86 #define ATH9K_TXERR_XTXOP 0x08 87 #define ATH9K_TXERR_TIMER_EXPIRED 0x10 88 #define ATH9K_TX_ACKED 0x20 89 #define ATH9K_TXERR_MASK \ 90 (ATH9K_TXERR_XRETRY | ATH9K_TXERR_FILT | ATH9K_TXERR_FIFO | \ 91 ATH9K_TXERR_XTXOP | ATH9K_TXERR_TIMER_EXPIRED) 92 93 #define ATH9K_TX_BA 0x01 94 #define ATH9K_TX_PWRMGMT 0x02 95 #define ATH9K_TX_DESC_CFG_ERR 0x04 96 #define ATH9K_TX_DATA_UNDERRUN 0x08 97 #define ATH9K_TX_DELIM_UNDERRUN 0x10 98 #define ATH9K_TX_SW_FILTERED 0x80 99 100 /* 64 bytes */ 101 #define MIN_TX_FIFO_THRESHOLD 0x1 102 103 /* 104 * Single stream device AR9285 and AR9271 require 2 KB 105 * to work around a hardware issue, all other devices 106 * have can use the max 4 KB limit. 107 */ 108 #define MAX_TX_FIFO_THRESHOLD ((4096 / 64) - 1) 109 110 struct ath_tx_status { 111 u32 ts_tstamp; 112 u16 ts_seqnum; 113 u8 ts_status; 114 u8 ts_rateindex; 115 int8_t ts_rssi; 116 u8 ts_shortretry; 117 u8 ts_longretry; 118 u8 ts_virtcol; 119 u8 ts_flags; 120 int8_t ts_rssi_ctl0; 121 int8_t ts_rssi_ctl1; 122 int8_t ts_rssi_ctl2; 123 int8_t ts_rssi_ext0; 124 int8_t ts_rssi_ext1; 125 int8_t ts_rssi_ext2; 126 u8 qid; 127 u16 desc_id; 128 u8 tid; 129 u32 ba_low; 130 u32 ba_high; 131 u32 evm0; 132 u32 evm1; 133 u32 evm2; 134 }; 135 136 struct ath_rx_status { 137 u32 rs_tstamp; 138 u16 rs_datalen; 139 u8 rs_status; 140 u8 rs_phyerr; 141 int8_t rs_rssi; 142 u8 rs_keyix; 143 u8 rs_rate; 144 u8 rs_antenna; 145 u8 rs_more; 146 int8_t rs_rssi_ctl0; 147 int8_t rs_rssi_ctl1; 148 int8_t rs_rssi_ctl2; 149 int8_t rs_rssi_ext0; 150 int8_t rs_rssi_ext1; 151 int8_t rs_rssi_ext2; 152 u8 rs_isaggr; 153 u8 rs_moreaggr; 154 u8 rs_num_delims; 155 u8 rs_flags; 156 u32 evm0; 157 u32 evm1; 158 u32 evm2; 159 u32 evm3; 160 u32 evm4; 161 }; 162 163 struct ath_htc_rx_status { 164 uint64_t rs_tstamp; 165 uint16_t rs_datalen; 166 u8 rs_status; 167 u8 rs_phyerr; 168 int8_t rs_rssi; 169 int8_t rs_rssi_ctl0; 170 int8_t rs_rssi_ctl1; 171 int8_t rs_rssi_ctl2; 172 int8_t rs_rssi_ext0; 173 int8_t rs_rssi_ext1; 174 int8_t rs_rssi_ext2; 175 u8 rs_keyix; 176 u8 rs_rate; 177 u8 rs_antenna; 178 u8 rs_more; 179 u8 rs_isaggr; 180 u8 rs_moreaggr; 181 u8 rs_num_delims; 182 u8 rs_flags; 183 u8 rs_dummy; 184 uint32_t evm0; 185 uint32_t evm1; 186 uint32_t evm2; 187 }; 188 189 #define ATH9K_RXERR_CRC 0x01 190 #define ATH9K_RXERR_PHY 0x02 191 #define ATH9K_RXERR_FIFO 0x04 192 #define ATH9K_RXERR_DECRYPT 0x08 193 #define ATH9K_RXERR_MIC 0x10 194 195 #define ATH9K_RX_MORE 0x01 196 #define ATH9K_RX_MORE_AGGR 0x02 197 #define ATH9K_RX_GI 0x04 198 #define ATH9K_RX_2040 0x08 199 #define ATH9K_RX_DELIM_CRC_PRE 0x10 200 #define ATH9K_RX_DELIM_CRC_POST 0x20 201 #define ATH9K_RX_DECRYPT_BUSY 0x40 202 203 #define ATH9K_RXKEYIX_INVALID ((u8)-1) 204 #define ATH9K_TXKEYIX_INVALID ((u32)-1) 205 206 enum ath9k_phyerr { 207 ATH9K_PHYERR_UNDERRUN = 0, /* Transmit underrun */ 208 ATH9K_PHYERR_TIMING = 1, /* Timing error */ 209 ATH9K_PHYERR_PARITY = 2, /* Illegal parity */ 210 ATH9K_PHYERR_RATE = 3, /* Illegal rate */ 211 ATH9K_PHYERR_LENGTH = 4, /* Illegal length */ 212 ATH9K_PHYERR_RADAR = 5, /* Radar detect */ 213 ATH9K_PHYERR_SERVICE = 6, /* Illegal service */ 214 ATH9K_PHYERR_TOR = 7, /* Transmit override receive */ 215 216 ATH9K_PHYERR_OFDM_TIMING = 17, 217 ATH9K_PHYERR_OFDM_SIGNAL_PARITY = 18, 218 ATH9K_PHYERR_OFDM_RATE_ILLEGAL = 19, 219 ATH9K_PHYERR_OFDM_LENGTH_ILLEGAL = 20, 220 ATH9K_PHYERR_OFDM_POWER_DROP = 21, 221 ATH9K_PHYERR_OFDM_SERVICE = 22, 222 ATH9K_PHYERR_OFDM_RESTART = 23, 223 ATH9K_PHYERR_FALSE_RADAR_EXT = 24, 224 225 ATH9K_PHYERR_CCK_TIMING = 25, 226 ATH9K_PHYERR_CCK_HEADER_CRC = 26, 227 ATH9K_PHYERR_CCK_RATE_ILLEGAL = 27, 228 ATH9K_PHYERR_CCK_SERVICE = 30, 229 ATH9K_PHYERR_CCK_RESTART = 31, 230 ATH9K_PHYERR_CCK_LENGTH_ILLEGAL = 32, 231 ATH9K_PHYERR_CCK_POWER_DROP = 33, 232 233 ATH9K_PHYERR_HT_CRC_ERROR = 34, 234 ATH9K_PHYERR_HT_LENGTH_ILLEGAL = 35, 235 ATH9K_PHYERR_HT_RATE_ILLEGAL = 36, 236 237 ATH9K_PHYERR_MAX = 37, 238 }; 239 240 struct ath_desc { 241 u32 ds_link; 242 u32 ds_data; 243 u32 ds_ctl0; 244 u32 ds_ctl1; 245 u32 ds_hw[20]; 246 // void *ds_vdata; 247 } __attribute__((packed, aligned(4))); 248 249 #define ATH9K_TXDESC_NOACK 0x0002 250 #define ATH9K_TXDESC_RTSENA 0x0004 251 #define ATH9K_TXDESC_CTSENA 0x0008 252 /* ATH9K_TXDESC_INTREQ forces a tx interrupt to be generated for 253 * the descriptor its marked on. We take a tx interrupt to reap 254 * descriptors when the h/w hits an EOL condition or 255 * when the descriptor is specifically marked to generate 256 * an interrupt with this flag. Descriptors should be 257 * marked periodically to insure timely replenishing of the 258 * supply needed for sending frames. Defering interrupts 259 * reduces system load and potentially allows more concurrent 260 * work to be done but if done to aggressively can cause 261 * senders to backup. When the hardware queue is left too 262 * large rate control information may also be too out of 263 * date. An Alternative for this is TX interrupt mitigation 264 * but this needs more testing. */ 265 #define ATH9K_TXDESC_INTREQ 0x0010 266 #define ATH9K_TXDESC_VEOL 0x0020 267 #define ATH9K_TXDESC_EXT_ONLY 0x0040 268 #define ATH9K_TXDESC_EXT_AND_CTL 0x0080 269 #define ATH9K_TXDESC_VMF 0x0100 270 #define ATH9K_TXDESC_FRAG_IS_ON 0x0200 271 #define ATH9K_TXDESC_LOWRXCHAIN 0x0400 272 #define ATH9K_TXDESC_LDPC 0x00010000 273 274 #define ATH9K_RXDESC_INTREQ 0x0020 275 276 struct ar5416_desc { 277 u32 ds_link; 278 u32 ds_data; 279 u32 ds_ctl0; 280 u32 ds_ctl1; 281 union { 282 struct { 283 u32 ctl2; 284 u32 ctl3; 285 u32 ctl4; 286 u32 ctl5; 287 u32 ctl6; 288 u32 ctl7; 289 u32 ctl8; 290 u32 ctl9; 291 u32 ctl10; 292 u32 ctl11; 293 u32 status0; 294 u32 status1; 295 u32 status2; 296 u32 status3; 297 u32 status4; 298 u32 status5; 299 u32 status6; 300 u32 status7; 301 u32 status8; 302 u32 status9; 303 } tx; 304 struct { 305 u32 status0; 306 u32 status1; 307 u32 status2; 308 u32 status3; 309 u32 status4; 310 u32 status5; 311 u32 status6; 312 u32 status7; 313 u32 status8; 314 } rx; 315 } u; 316 } __attribute__((packed, aligned(4))); 317 318 #define AR5416DESC(_ds) ((struct ar5416_desc *)(_ds)) 319 #define AR5416DESC_CONST(_ds) ((const struct ar5416_desc *)(_ds)) 320 321 #define ds_ctl2 u.tx.ctl2 322 #define ds_ctl3 u.tx.ctl3 323 #define ds_ctl4 u.tx.ctl4 324 #define ds_ctl5 u.tx.ctl5 325 #define ds_ctl6 u.tx.ctl6 326 #define ds_ctl7 u.tx.ctl7 327 #define ds_ctl8 u.tx.ctl8 328 #define ds_ctl9 u.tx.ctl9 329 #define ds_ctl10 u.tx.ctl10 330 #define ds_ctl11 u.tx.ctl11 331 332 #define ds_txstatus0 u.tx.status0 333 #define ds_txstatus1 u.tx.status1 334 #define ds_txstatus2 u.tx.status2 335 #define ds_txstatus3 u.tx.status3 336 #define ds_txstatus4 u.tx.status4 337 #define ds_txstatus5 u.tx.status5 338 #define ds_txstatus6 u.tx.status6 339 #define ds_txstatus7 u.tx.status7 340 #define ds_txstatus8 u.tx.status8 341 #define ds_txstatus9 u.tx.status9 342 343 #define ds_rxstatus0 u.rx.status0 344 #define ds_rxstatus1 u.rx.status1 345 #define ds_rxstatus2 u.rx.status2 346 #define ds_rxstatus3 u.rx.status3 347 #define ds_rxstatus4 u.rx.status4 348 #define ds_rxstatus5 u.rx.status5 349 #define ds_rxstatus6 u.rx.status6 350 #define ds_rxstatus7 u.rx.status7 351 #define ds_rxstatus8 u.rx.status8 352 353 #define AR_FrameLen 0x00000fff 354 #define AR_VirtMoreFrag 0x00001000 355 #define AR_TxCtlRsvd00 0x0000e000 356 #define AR_XmitPower 0x003f0000 357 #define AR_XmitPower_S 16 358 #define AR_RTSEnable 0x00400000 359 #define AR_VEOL 0x00800000 360 #define AR_ClrDestMask 0x01000000 361 #define AR_TxCtlRsvd01 0x1e000000 362 #define AR_TxIntrReq 0x20000000 363 #define AR_DestIdxValid 0x40000000 364 #define AR_CTSEnable 0x80000000 365 366 #define AR_TxMore 0x00001000 367 #define AR_DestIdx 0x000fe000 368 #define AR_DestIdx_S 13 369 #define AR_FrameType 0x00f00000 370 #define AR_FrameType_S 20 371 #define AR_NoAck 0x01000000 372 #define AR_InsertTS 0x02000000 373 #define AR_CorruptFCS 0x04000000 374 #define AR_ExtOnly 0x08000000 375 #define AR_ExtAndCtl 0x10000000 376 #define AR_MoreAggr 0x20000000 377 #define AR_IsAggr 0x40000000 378 379 #define AR_BurstDur 0x00007fff 380 #define AR_BurstDur_S 0 381 #define AR_DurUpdateEna 0x00008000 382 #define AR_XmitDataTries0 0x000f0000 383 #define AR_XmitDataTries0_S 16 384 #define AR_XmitDataTries1 0x00f00000 385 #define AR_XmitDataTries1_S 20 386 #define AR_XmitDataTries2 0x0f000000 387 #define AR_XmitDataTries2_S 24 388 #define AR_XmitDataTries3 0xf0000000 389 #define AR_XmitDataTries3_S 28 390 391 #define AR_XmitRate0 0x000000ff 392 #define AR_XmitRate0_S 0 393 #define AR_XmitRate1 0x0000ff00 394 #define AR_XmitRate1_S 8 395 #define AR_XmitRate2 0x00ff0000 396 #define AR_XmitRate2_S 16 397 #define AR_XmitRate3 0xff000000 398 #define AR_XmitRate3_S 24 399 400 #define AR_PacketDur0 0x00007fff 401 #define AR_PacketDur0_S 0 402 #define AR_RTSCTSQual0 0x00008000 403 #define AR_PacketDur1 0x7fff0000 404 #define AR_PacketDur1_S 16 405 #define AR_RTSCTSQual1 0x80000000 406 407 #define AR_PacketDur2 0x00007fff 408 #define AR_PacketDur2_S 0 409 #define AR_RTSCTSQual2 0x00008000 410 #define AR_PacketDur3 0x7fff0000 411 #define AR_PacketDur3_S 16 412 #define AR_RTSCTSQual3 0x80000000 413 414 #define AR_AggrLen 0x0000ffff 415 #define AR_AggrLen_S 0 416 #define AR_TxCtlRsvd60 0x00030000 417 #define AR_PadDelim 0x03fc0000 418 #define AR_PadDelim_S 18 419 #define AR_EncrType 0x0c000000 420 #define AR_EncrType_S 26 421 #define AR_TxCtlRsvd61 0xf0000000 422 #define AR_LDPC 0x80000000 423 424 #define AR_2040_0 0x00000001 425 #define AR_GI0 0x00000002 426 #define AR_ChainSel0 0x0000001c 427 #define AR_ChainSel0_S 2 428 #define AR_2040_1 0x00000020 429 #define AR_GI1 0x00000040 430 #define AR_ChainSel1 0x00000380 431 #define AR_ChainSel1_S 7 432 #define AR_2040_2 0x00000400 433 #define AR_GI2 0x00000800 434 #define AR_ChainSel2 0x00007000 435 #define AR_ChainSel2_S 12 436 #define AR_2040_3 0x00008000 437 #define AR_GI3 0x00010000 438 #define AR_ChainSel3 0x000e0000 439 #define AR_ChainSel3_S 17 440 #define AR_RTSCTSRate 0x0ff00000 441 #define AR_RTSCTSRate_S 20 442 #define AR_STBC0 0x10000000 443 #define AR_STBC1 0x20000000 444 #define AR_STBC2 0x40000000 445 #define AR_STBC3 0x80000000 446 447 #define AR_TxRSSIAnt00 0x000000ff 448 #define AR_TxRSSIAnt00_S 0 449 #define AR_TxRSSIAnt01 0x0000ff00 450 #define AR_TxRSSIAnt01_S 8 451 #define AR_TxRSSIAnt02 0x00ff0000 452 #define AR_TxRSSIAnt02_S 16 453 #define AR_TxStatusRsvd00 0x3f000000 454 #define AR_TxBaStatus 0x40000000 455 #define AR_TxStatusRsvd01 0x80000000 456 457 /* 458 * AR_FrmXmitOK - Frame transmission success flag. If set, the frame was 459 * transmitted successfully. If clear, no ACK or BA was received to indicate 460 * successful transmission when we were expecting an ACK or BA. 461 */ 462 #define AR_FrmXmitOK 0x00000001 463 #define AR_ExcessiveRetries 0x00000002 464 #define AR_FIFOUnderrun 0x00000004 465 #define AR_Filtered 0x00000008 466 #define AR_RTSFailCnt 0x000000f0 467 #define AR_RTSFailCnt_S 4 468 #define AR_DataFailCnt 0x00000f00 469 #define AR_DataFailCnt_S 8 470 #define AR_VirtRetryCnt 0x0000f000 471 #define AR_VirtRetryCnt_S 12 472 #define AR_TxDelimUnderrun 0x00010000 473 #define AR_TxDataUnderrun 0x00020000 474 #define AR_DescCfgErr 0x00040000 475 #define AR_TxTimerExpired 0x00080000 476 #define AR_TxStatusRsvd10 0xfff00000 477 478 #define AR_SendTimestamp ds_txstatus2 479 #define AR_BaBitmapLow ds_txstatus3 480 #define AR_BaBitmapHigh ds_txstatus4 481 482 #define AR_TxRSSIAnt10 0x000000ff 483 #define AR_TxRSSIAnt10_S 0 484 #define AR_TxRSSIAnt11 0x0000ff00 485 #define AR_TxRSSIAnt11_S 8 486 #define AR_TxRSSIAnt12 0x00ff0000 487 #define AR_TxRSSIAnt12_S 16 488 #define AR_TxRSSICombined 0xff000000 489 #define AR_TxRSSICombined_S 24 490 491 #define AR_TxTid 0xf0000000 492 #define AR_TxTid_S 28 493 494 #define AR_TxEVM0 ds_txstatus5 495 #define AR_TxEVM1 ds_txstatus6 496 #define AR_TxEVM2 ds_txstatus7 497 498 #define AR_TxDone 0x00000001 499 #define AR_SeqNum 0x00001ffe 500 #define AR_SeqNum_S 1 501 #define AR_TxStatusRsvd80 0x0001e000 502 #define AR_TxOpExceeded 0x00020000 503 #define AR_TxStatusRsvd81 0x001c0000 504 #define AR_FinalTxIdx 0x00600000 505 #define AR_FinalTxIdx_S 21 506 #define AR_TxStatusRsvd82 0x01800000 507 #define AR_PowerMgmt 0x02000000 508 #define AR_TxStatusRsvd83 0xfc000000 509 510 #define AR_RxCTLRsvd00 0xffffffff 511 512 #define AR_RxCtlRsvd00 0x00001000 513 #define AR_RxIntrReq 0x00002000 514 #define AR_RxCtlRsvd01 0xffffc000 515 516 #define AR_RxRSSIAnt00 0x000000ff 517 #define AR_RxRSSIAnt00_S 0 518 #define AR_RxRSSIAnt01 0x0000ff00 519 #define AR_RxRSSIAnt01_S 8 520 #define AR_RxRSSIAnt02 0x00ff0000 521 #define AR_RxRSSIAnt02_S 16 522 #define AR_RxRate 0xff000000 523 #define AR_RxRate_S 24 524 #define AR_RxStatusRsvd00 0xff000000 525 526 #define AR_DataLen 0x00000fff 527 #define AR_RxMore 0x00001000 528 #define AR_NumDelim 0x003fc000 529 #define AR_NumDelim_S 14 530 #define AR_RxStatusRsvd10 0xff800000 531 532 #define AR_RcvTimestamp ds_rxstatus2 533 534 #define AR_GI 0x00000001 535 #define AR_2040 0x00000002 536 #define AR_Parallel40 0x00000004 537 #define AR_Parallel40_S 2 538 #define AR_RxStatusRsvd30 0x000000f8 539 #define AR_RxAntenna 0xffffff00 540 #define AR_RxAntenna_S 8 541 542 #define AR_RxRSSIAnt10 0x000000ff 543 #define AR_RxRSSIAnt10_S 0 544 #define AR_RxRSSIAnt11 0x0000ff00 545 #define AR_RxRSSIAnt11_S 8 546 #define AR_RxRSSIAnt12 0x00ff0000 547 #define AR_RxRSSIAnt12_S 16 548 #define AR_RxRSSICombined 0xff000000 549 #define AR_RxRSSICombined_S 24 550 551 #define AR_RxEVM0 ds_rxstatus4 552 #define AR_RxEVM1 ds_rxstatus5 553 #define AR_RxEVM2 ds_rxstatus6 554 555 #define AR_RxDone 0x00000001 556 #define AR_RxFrameOK 0x00000002 557 #define AR_CRCErr 0x00000004 558 #define AR_DecryptCRCErr 0x00000008 559 #define AR_PHYErr 0x00000010 560 #define AR_MichaelErr 0x00000020 561 #define AR_PreDelimCRCErr 0x00000040 562 #define AR_RxStatusRsvd70 0x00000080 563 #define AR_RxKeyIdxValid 0x00000100 564 #define AR_KeyIdx 0x0000fe00 565 #define AR_KeyIdx_S 9 566 #define AR_PHYErrCode 0x0000ff00 567 #define AR_PHYErrCode_S 8 568 #define AR_RxMoreAggr 0x00010000 569 #define AR_RxAggr 0x00020000 570 #define AR_PostDelimCRCErr 0x00040000 571 #define AR_RxStatusRsvd71 0x3ff80000 572 #define AR_DecryptBusyErr 0x40000000 573 #define AR_KeyMiss 0x80000000 574 575 enum ath9k_tx_queue { 576 ATH9K_TX_QUEUE_INACTIVE = 0, 577 ATH9K_TX_QUEUE_DATA, 578 }; 579 580 #define ATH9K_NUM_TX_QUEUES 1 581 582 /* Used as a queue subtype instead of a WMM AC */ 583 #define ATH9K_WME_UPSD 4 584 585 enum ath9k_tx_queue_flags { 586 TXQ_FLAG_TXOKINT_ENABLE = 0x0001, 587 TXQ_FLAG_TXERRINT_ENABLE = 0x0001, 588 TXQ_FLAG_TXDESCINT_ENABLE = 0x0002, 589 TXQ_FLAG_TXEOLINT_ENABLE = 0x0004, 590 TXQ_FLAG_TXURNINT_ENABLE = 0x0008, 591 TXQ_FLAG_BACKOFF_DISABLE = 0x0010, 592 TXQ_FLAG_COMPRESSION_ENABLE = 0x0020, 593 TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE = 0x0040, 594 TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080, 595 }; 596 597 #define ATH9K_TXQ_USEDEFAULT ((u32) -1) 598 #define ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS 0x00000001 599 600 #define ATH9K_DECOMP_MASK_SIZE 128 601 #define ATH9K_READY_TIME_LO_BOUND 50 602 #define ATH9K_READY_TIME_HI_BOUND 96 603 604 enum ath9k_pkt_type { 605 ATH9K_PKT_TYPE_NORMAL = 0, 606 ATH9K_PKT_TYPE_ATIM, 607 ATH9K_PKT_TYPE_PSPOLL, 608 ATH9K_PKT_TYPE_BEACON, 609 ATH9K_PKT_TYPE_PROBE_RESP, 610 ATH9K_PKT_TYPE_CHIRP, 611 ATH9K_PKT_TYPE_GRP_POLL, 612 }; 613 614 struct ath9k_tx_queue_info { 615 u32 tqi_ver; 616 enum ath9k_tx_queue tqi_type; 617 int tqi_subtype; 618 enum ath9k_tx_queue_flags tqi_qflags; 619 u32 tqi_priority; 620 u32 tqi_aifs; 621 u32 tqi_cwmin; 622 u32 tqi_cwmax; 623 u16 tqi_shretry; 624 u16 tqi_lgretry; 625 u32 tqi_cbrPeriod; 626 u32 tqi_cbrOverflowLimit; 627 u32 tqi_burstTime; 628 u32 tqi_readyTime; 629 u32 tqi_physCompBuf; 630 u32 tqi_intFlags; 631 }; 632 633 enum ath9k_rx_filter { 634 ATH9K_RX_FILTER_UCAST = 0x00000001, 635 ATH9K_RX_FILTER_MCAST = 0x00000002, 636 ATH9K_RX_FILTER_BCAST = 0x00000004, 637 ATH9K_RX_FILTER_CONTROL = 0x00000008, 638 ATH9K_RX_FILTER_BEACON = 0x00000010, 639 ATH9K_RX_FILTER_PROM = 0x00000020, 640 ATH9K_RX_FILTER_PROBEREQ = 0x00000080, 641 ATH9K_RX_FILTER_PHYERR = 0x00000100, 642 ATH9K_RX_FILTER_MYBEACON = 0x00000200, 643 ATH9K_RX_FILTER_COMP_BAR = 0x00000400, 644 ATH9K_RX_FILTER_COMP_BA = 0x00000800, 645 ATH9K_RX_FILTER_UNCOMP_BA_BAR = 0x00001000, 646 ATH9K_RX_FILTER_PSPOLL = 0x00004000, 647 ATH9K_RX_FILTER_PHYRADAR = 0x00002000, 648 ATH9K_RX_FILTER_MCAST_BCAST_ALL = 0x00008000, 649 }; 650 651 #define ATH9K_RATESERIES_RTS_CTS 0x0001 652 #define ATH9K_RATESERIES_2040 0x0002 653 #define ATH9K_RATESERIES_HALFGI 0x0004 654 #define ATH9K_RATESERIES_STBC 0x0008 655 656 struct ath9k_11n_rate_series { 657 u32 Tries; 658 u32 Rate; 659 u32 PktDuration; 660 u32 ChSel; 661 u32 RateFlags; 662 }; 663 664 enum ath9k_key_type { 665 ATH9K_KEY_TYPE_CLEAR, 666 ATH9K_KEY_TYPE_WEP, 667 ATH9K_KEY_TYPE_AES, 668 ATH9K_KEY_TYPE_TKIP, 669 }; 670 671 struct ath_hw; 672 struct ath9k_channel; 673 674 u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q); 675 void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp); 676 void ath9k_hw_txstart(struct ath_hw *ah, u32 q); 677 void ath9k_hw_cleartxdesc(struct ath_hw *ah, void *ds); 678 u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q); 679 int ath9k_hw_updatetxtriglevel(struct ath_hw *ah, int bIncTrigLevel); 680 int ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q); 681 void ath9k_hw_abort_tx_dma(struct ath_hw *ah); 682 void ath9k_hw_gettxintrtxqs(struct ath_hw *ah, u32 *txqs); 683 int ath9k_hw_set_txq_props(struct ath_hw *ah, int q, 684 const struct ath9k_tx_queue_info *qinfo); 685 int ath9k_hw_get_txq_props(struct ath_hw *ah, int q, 686 struct ath9k_tx_queue_info *qinfo); 687 int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type, 688 const struct ath9k_tx_queue_info *qinfo); 689 int ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q); 690 int ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q); 691 int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds, 692 struct ath_rx_status *rs, u64 tsf); 693 void ath9k_hw_setuprxdesc(struct ath_hw *ah, struct ath_desc *ds, 694 u32 size, u32 flags); 695 int ath9k_hw_setrxabort(struct ath_hw *ah, int set); 696 void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp); 697 void ath9k_hw_startpcureceive(struct ath_hw *ah, int is_scanning); 698 void ath9k_hw_abortpcurecv(struct ath_hw *ah); 699 int ath9k_hw_stopdmarecv(struct ath_hw *ah, int *reset); 700 701 /* Interrupt Handling */ 702 int ath9k_hw_intrpend(struct ath_hw *ah); 703 void ath9k_hw_set_interrupts(struct ath_hw *ah, unsigned int ints); 704 void ath9k_hw_enable_interrupts(struct ath_hw *ah); 705 void ath9k_hw_disable_interrupts(struct ath_hw *ah); 706 707 void ar9002_hw_attach_mac_ops(struct ath_hw *ah); 708 709 #endif /* MAC_H */ 710