1Nest (NX) Accelerator Coprocessor 2================================= 3 4The NX coprocessor is present in P7+ or later processors. Each NX node 5represents a unique NX coprocessor. The nodes are located under an 6xscom node, as: :: 7 8 /xscom@<xscom_addr>/nx@<nx_addr> 9 10With unique xscom and nx addresses. Their compatible node contains 11"ibm,power-nx". 12 13 14NX Compression Coprocessor 15-------------------------- 16 17This is the memory compression coprocessor. which uses the IBM proprietary 18842 compression algorithm and format. Each NX node contains an 842 engine. :: 19 20 ibm,842-coprocessor-type : CT value common to all 842 coprocessors 21 ibm,842-coprocessor-instance : CI value unique to all 842 coprocessors 22 23Access to the coprocessor requires using the ICSWX instruction, which uses 24a specific format including a Coprocessor Type (CT) and Coprocessor Instance 25(CI) value to address each request to the right coprocessor. The driver should 26use the CT and CI values for a particular node to communicate with it. For 27all 842 coprocessors in the system, the CT value will (should) be the same, 28while each will have a different CI value. The driver can use CI 0 to allow 29the hardware to automatically select which coprocessor instance to use. 30 31On P9, this compression coprocessor also supports standard GZIP/ZLIB 32compression algorithm and format. Virtual Accelerator Swirchboard (VAS) is used 33to access this coprocessor. VAS writes each request to receive FIFOs (RXFIFO) 34which are either high or normal priority and these FIFOs are bound to 35coprocessor types (842 and gzip). 36 37VAS distinguishes NX requests for the target engines based on logical 38partition ID (lpid), process ID (pid) and Thread ID (tid). So (lpid, pid, tid) 39combination has to be unique in the system. Each NX node contains high and 40normal FIFOs for each 842 and GZIP engines. :: 41 42 /ibm,842-high-fifo : High priority 842 RxFIFO 43 /ibm,842-normal-fifo : Normal priority 842 RxFIFO 44 /ibm,gzip-high-fifo : High priority gzip RxFIFO 45 /ibm,gzip-normal-fifo : Normal priority gzip RxFIFO 46 47Each RxFIFO node contains: :: 48 49 compatible : ibm,p9-nx-842 or ibm,p9-nx-gzip 50 priority : High or Normal 51 rx-fifo-address : RxFIFO buffer address 52 rx-fifo-size : RxFIFO size 53 lpid : 0xfff (1's for 12 bits in UMAC notify match 54 register) 55 pid : Coprocessor type (either 842 or gzip) 56 tid : counter in each coprocessor type 57 58During initialization, the driver invokes VAS interface for each coprocessor 59type (842 and gzip) to configure the RxFIFO with rx_fifo_address, lpid, pid 60and tid for high and nornmal priority FIFOs. 61 62NX RNG Coprocessor 63------------------ 64 65This is the Random Number Generator (RNG) coprocessor, which is a part 66of each NX coprocessor. Each node represents a unique RNG coprocessor. 67Its nodes are not under the main nx node, they are located at: :: 68 69 /hwrng@<addr> : RNG at address <addr> 70 ibm,chip-id : chip id where the RNG is 71 reg : address of the register to read from 72 73Each read from the RNG register will provide a new random number. 74 75 76