1 /* Copyright 2017 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <phys-map.h>
18 #include <chip.h>
19 #include <skiboot.h>
20 #include <opal-api.h>
21 #include <stack.h>
22 #include <inttypes.h>
23
24 struct phys_map_entry {
25 enum phys_map_type type;
26 int index;
27 uint64_t addr;
28 uint64_t size;
29 };
30
31 struct phys_map_info {
32 int chip_select_shift;
33 const struct phys_map_entry *table;
34 };
35
36 static const struct phys_map_info *phys_map;
37
38 static const struct phys_map_entry phys_map_table_nimbus[] = {
39
40 /* System memory upto 4TB minus GPU memory */
41 { SYSTEM_MEM, 0, 0x0000000000000000ull, 0x0000034000000000ull },
42 /* GPU memory from 4TB - 128GB*GPU */
43 { GPU_MEM_4T_DOWN, 5, 0x0000034000000000ull, 0x0000002000000000ull },
44 { GPU_MEM_4T_DOWN, 4, 0x0000036000000000ull, 0x0000002000000000ull },
45 { GPU_MEM_4T_DOWN, 3, 0x0000038000000000ull, 0x0000002000000000ull },
46 { GPU_MEM_4T_DOWN, 2, 0x000003a000000000ull, 0x0000002000000000ull },
47 { GPU_MEM_4T_DOWN, 1, 0x000003c000000000ull, 0x0000002000000000ull },
48 { GPU_MEM_4T_DOWN, 0, 0x000003e000000000ull, 0x0000002000000000ull },
49 /* GPU memory from 4TB + 128GB*GPU. 4 GPUs only */
50 { GPU_MEM_4T_UP, 0, 0x0000040000000000ull, 0x0000002000000000ull },
51 { GPU_MEM_4T_UP, 1, 0x0000042000000000ull, 0x0000002000000000ull },
52 { GPU_MEM_4T_UP, 2, 0x0000044000000000ull, 0x0000002000000000ull },
53 { GPU_MEM_4T_UP, 3, 0x0000046000000000ull, 0x0000002000000000ull },
54
55 /*
56 * OpenCAPI LPC Memory - single 4TB range per chip, fills
57 * whole second non-mirrored region.
58 *
59 * Longer term, we're going to use chip address extension to
60 * enable >4TB to be allocated per chip. At that point, we
61 * may have to find another way of assigning these ranges
62 * outside of phys-map.
63 */
64 { OCAPI_MEM, 0, 0x0002000000000000ull, 0x0000040000000000ull },
65
66 /* 0 TB offset @ MMIO 0x0006000000000000ull */
67 { PHB4_64BIT_MMIO, 0, 0x0006000000000000ull, 0x0000004000000000ull },
68 { PHB4_64BIT_MMIO, 1, 0x0006004000000000ull, 0x0000004000000000ull },
69 { PHB4_64BIT_MMIO, 2, 0x0006008000000000ull, 0x0000004000000000ull },
70 { PHB4_32BIT_MMIO, 0, 0x000600c000000000ull, 0x0000000080000000ull },
71 { PHB4_32BIT_MMIO, 1, 0x000600c080000000ull, 0x0000000080000000ull },
72 { PHB4_32BIT_MMIO, 2, 0x000600c100000000ull, 0x0000000080000000ull },
73 { PHB4_32BIT_MMIO, 3, 0x000600c180000000ull, 0x0000000080000000ull },
74 { PHB4_32BIT_MMIO, 4, 0x000600c200000000ull, 0x0000000080000000ull },
75 { PHB4_32BIT_MMIO, 5, 0x000600c280000000ull, 0x0000000080000000ull },
76 { PHB4_XIVE_ESB , 0, 0x000600c300000000ull, 0x0000000020000000ull },
77 { PHB4_XIVE_ESB , 1, 0x000600c320000000ull, 0x0000000020000000ull },
78 { PHB4_XIVE_ESB , 2, 0x000600c340000000ull, 0x0000000020000000ull },
79 { PHB4_XIVE_ESB , 3, 0x000600c360000000ull, 0x0000000020000000ull },
80 { PHB4_XIVE_ESB , 4, 0x000600c380000000ull, 0x0000000020000000ull },
81 { PHB4_XIVE_ESB , 5, 0x000600c3a0000000ull, 0x0000000020000000ull },
82 { PHB4_REG_SPC , 0, 0x000600c3c0000000ull, 0x0000000000100000ull },
83 { PHB4_REG_SPC , 1, 0x000600c3c0100000ull, 0x0000000000100000ull },
84 { PHB4_REG_SPC , 2, 0x000600c3c0200000ull, 0x0000000000100000ull },
85 { PHB4_REG_SPC , 3, 0x000600c3c0300000ull, 0x0000000000100000ull },
86 { PHB4_REG_SPC , 4, 0x000600c3c0400000ull, 0x0000000000100000ull },
87 { PHB4_REG_SPC , 5, 0x000600c3c0500000ull, 0x0000000000100000ull },
88 { RESV , 0, 0x000600c3c0600000ull, 0x0000000c3fa00000ull },
89 { NPU_OCAPI_MMIO , 0, 0x000600d000000000ull, 0x0000000800000000ull },
90 { NPU_OCAPI_MMIO , 1, 0x000600d800000000ull, 0x0000000800000000ull },
91 { NPU_OCAPI_MMIO , 2, 0x000600e000000000ull, 0x0000000800000000ull },
92 { NPU_OCAPI_MMIO , 3, 0x000600e800000000ull, 0x0000000800000000ull },
93 { NPU_OCAPI_MMIO , 4, 0x000600f000000000ull, 0x0000000800000000ull },
94 { NPU_OCAPI_MMIO , 5, 0x000600f800000000ull, 0x0000000800000000ull },
95
96 /* 1 TB offset @ MMIO 0x0006000000000000ull */
97 { XIVE_VC , 0, 0x0006010000000000ull, 0x0000008000000000ull },
98 { XIVE_PC , 0, 0x0006018000000000ull, 0x0000001000000000ull },
99 { VAS_USER_WIN , 0, 0x0006019000000000ull, 0x0000000100000000ull },
100 { VAS_HYP_WIN , 0, 0x0006019100000000ull, 0x0000000002000000ull },
101 { RESV , 1, 0x0006019102000000ull, 0x000000001e000000ull },
102 { OCAB_XIVE_ESB , 0, 0x0006019120000000ull, 0x0000000020000000ull },
103 { RESV , 3, 0x0006019140000000ull, 0x0000006ec0000000ull },
104
105 /* 2 TB offset @ MMIO 0x0006000000000000ull */
106 { PHB4_64BIT_MMIO, 3, 0x0006020000000000ull, 0x0000004000000000ull },
107 { PHB4_64BIT_MMIO, 4, 0x0006024000000000ull, 0x0000004000000000ull },
108 { PHB4_64BIT_MMIO, 5, 0x0006028000000000ull, 0x0000004000000000ull },
109 { RESV , 4, 0x000602c000000000ull, 0x0000004000000000ull },
110
111 /* 3 TB offset @ MMIO 0x0006000000000000ull */
112 { LPC_BUS , 0, 0x0006030000000000ull, 0x0000000100000000ull },
113 { FSP_MMIO , 0, 0x0006030100000000ull, 0x0000000100000000ull },
114 { NPU_REGS , 0, 0x0006030200000000ull, 0x0000000001000000ull },
115 { NPU_USR , 0, 0x0006030201000000ull, 0x0000000000200000ull },
116 { NPU_PHY , 0, 0x0006030201200000ull, 0x0000000000200000ull },
117 { NPU_PHY , 1, 0x0006030201400000ull, 0x0000000000200000ull },
118 { NPU_NTL , 0, 0x0006030201600000ull, 0x0000000000020000ull },
119 { NPU_NTL , 1, 0x0006030201620000ull, 0x0000000000020000ull },
120 { NPU_NTL , 2, 0x0006030201640000ull, 0x0000000000020000ull },
121 { NPU_NTL , 3, 0x0006030201660000ull, 0x0000000000020000ull },
122 { NPU_NTL , 4, 0x0006030201680000ull, 0x0000000000020000ull },
123 { NPU_NTL , 5, 0x00060302016a0000ull, 0x0000000000020000ull },
124 { NPU_GENID , 0, 0x00060302016c0000ull, 0x0000000000020000ull },
125 { NPU_GENID , 1, 0x00060302016e0000ull, 0x0000000000020000ull },
126 { NPU_GENID , 2, 0x0006030201700000ull, 0x0000000000020000ull },
127 { RESV , 5, 0x0006030201720000ull, 0x00000000018e0000ull },
128 { PSIHB_REG , 0, 0x0006030203000000ull, 0x0000000000100000ull },
129 { XIVE_IC , 0, 0x0006030203100000ull, 0x0000000000080000ull },
130 { XIVE_TM , 0, 0x0006030203180000ull, 0x0000000000040000ull },
131 { PSIHB_ESB , 0, 0x00060302031c0000ull, 0x0000000000010000ull },
132 { NX_RNG , 0, 0x00060302031d0000ull, 0x0000000000010000ull },
133 { RESV , 6, 0x00060302031e0000ull, 0x000000001ce20000ull },
134 { CENTAUR_SCOM , 0, 0x0006030220000000ull, 0x0000000020000000ull },
135 { RESV , 7, 0x0006030240000000ull, 0x000000f9c0000000ull },
136 { XSCOM , 0, 0x000603fc00000000ull, 0x0000000400000000ull },
137
138 /* NULL entry at end */
139 { NULL_MAP, 0, 0, 0 },
140 };
141
142 static const struct phys_map_info phys_map_nimbus = {
143 .chip_select_shift = 42,
144 .table = phys_map_table_nimbus,
145 };
146
phys_map_entry_null(const struct phys_map_entry * e)147 static inline bool phys_map_entry_null(const struct phys_map_entry *e)
148 {
149 if (e->type == NULL_MAP)
150 return true;
151 return false;
152 }
153
154
155 /* This crashes skiboot on error as any bad calls here are almost
156 * certainly a developer error
157 */
phys_map_get(uint64_t gcid,enum phys_map_type type,int index,uint64_t * addr,uint64_t * size)158 void phys_map_get(uint64_t gcid, enum phys_map_type type,
159 int index, uint64_t *addr, uint64_t *size) {
160 const struct phys_map_entry *e;
161 uint64_t a;
162
163 if (!phys_map)
164 goto error;
165
166 /* Find entry in table */
167 for (e = phys_map->table; ; e++) {
168
169 /* End of table */
170 if (phys_map_entry_null(e))
171 goto error;
172
173 /* Is this our entry? */
174 if (e->type != type)
175 continue;
176 if (e->index != index)
177 continue;
178
179 /* Found entry! */
180 break;
181 }
182 a = e->addr;
183 a += gcid << phys_map->chip_select_shift;
184
185 if (addr)
186 *addr = a;
187 if (size)
188 *size = e->size;
189
190 prlog(PR_TRACE, "Assigning BAR [%"PRIx64"] type:%02i index:%x "
191 "0x%016"PRIx64" for 0x%016"PRIx64"\n",
192 gcid, type, index, a, e->size);
193
194 return;
195
196 error:
197 /* Something has gone really wrong */
198 prlog(PR_EMERG, "ERROR: Failed to lookup BAR type:%i index:%i\n",
199 type, index);
200 assert(0);
201 }
202
phys_map_init(void)203 void phys_map_init(void)
204 {
205 const char *name = "unused";
206
207 phys_map = NULL;
208
209 if (proc_gen == proc_gen_p9) {
210 name = "nimbus";
211 phys_map = &phys_map_nimbus;
212 }
213
214 prlog(PR_DEBUG, "Assigning physical memory map table for %s\n", name);
215
216 }
217
218