1 /* 2 * 3 * @par 4 * IXP400 SW Release version 2.0 5 * 6 * -- Copyright Notice -- 7 * 8 * @par 9 * Copyright 2001-2005, Intel Corporation. 10 * All rights reserved. 11 * 12 * @par 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. Neither the name of the Intel Corporation nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * @par 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' 27 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @par 39 * -- End of Copyright Notice -- 40 */ 41 42 43 #ifndef IxEthAccMac_p_H 44 #define IxEthAccMac_p_H 45 46 #include "IxOsal.h" 47 48 #define IX_ETH_ACC_MAX_MULTICAST_ADDRESSES 256 49 #define IX_ETH_ACC_NUM_PORTS 3 50 #define IX_ETH_ACC_MAX_FRAME_SIZE_DEFAULT 1536 51 #define IX_ETH_ACC_MAX_FRAME_SIZE_UPPER_RANGE (65536-64) 52 #define IX_ETH_ACC_MAX_FRAME_SIZE_LOWER_RANGE 64 53 54 /* 55 * 56 * MAC register definitions 57 * 58 */ 59 #define IX_ETH_ACC_MAC_0_BASE IX_OSAL_IXP400_ETHA_PHYS_BASE 60 #define IX_ETH_ACC_MAC_1_BASE IX_OSAL_IXP400_ETHB_PHYS_BASE 61 #define IX_ETH_ACC_MAC_2_BASE IX_OSAL_IXP400_ETH_NPEA_PHYS_BASE 62 63 #define IX_ETH_ACC_MAC_TX_CNTRL1 0x000 64 #define IX_ETH_ACC_MAC_TX_CNTRL2 0x004 65 #define IX_ETH_ACC_MAC_RX_CNTRL1 0x010 66 #define IX_ETH_ACC_MAC_RX_CNTRL2 0x014 67 #define IX_ETH_ACC_MAC_RANDOM_SEED 0x020 68 #define IX_ETH_ACC_MAC_THRESH_P_EMPTY 0x030 69 #define IX_ETH_ACC_MAC_THRESH_P_FULL 0x038 70 #define IX_ETH_ACC_MAC_BUF_SIZE_TX 0x040 71 #define IX_ETH_ACC_MAC_TX_DEFER 0x050 72 #define IX_ETH_ACC_MAC_RX_DEFER 0x054 73 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_1 0x060 74 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_2 0x064 75 #define IX_ETH_ACC_MAC_SLOT_TIME 0x070 76 #define IX_ETH_ACC_MAC_MDIO_CMD_1 0x080 77 #define IX_ETH_ACC_MAC_MDIO_CMD_2 0x084 78 #define IX_ETH_ACC_MAC_MDIO_CMD_3 0x088 79 #define IX_ETH_ACC_MAC_MDIO_CMD_4 0x08c 80 #define IX_ETH_ACC_MAC_MDIO_STS_1 0x090 81 #define IX_ETH_ACC_MAC_MDIO_STS_2 0x094 82 #define IX_ETH_ACC_MAC_MDIO_STS_3 0x098 83 #define IX_ETH_ACC_MAC_MDIO_STS_4 0x09c 84 #define IX_ETH_ACC_MAC_ADDR_MASK_1 0x0A0 85 #define IX_ETH_ACC_MAC_ADDR_MASK_2 0x0A4 86 #define IX_ETH_ACC_MAC_ADDR_MASK_3 0x0A8 87 #define IX_ETH_ACC_MAC_ADDR_MASK_4 0x0AC 88 #define IX_ETH_ACC_MAC_ADDR_MASK_5 0x0B0 89 #define IX_ETH_ACC_MAC_ADDR_MASK_6 0x0B4 90 #define IX_ETH_ACC_MAC_ADDR_1 0x0C0 91 #define IX_ETH_ACC_MAC_ADDR_2 0x0C4 92 #define IX_ETH_ACC_MAC_ADDR_3 0x0C8 93 #define IX_ETH_ACC_MAC_ADDR_4 0x0CC 94 #define IX_ETH_ACC_MAC_ADDR_5 0x0D0 95 #define IX_ETH_ACC_MAC_ADDR_6 0x0D4 96 #define IX_ETH_ACC_MAC_INT_CLK_THRESH 0x0E0 97 #define IX_ETH_ACC_MAC_UNI_ADDR_1 0x0F0 98 #define IX_ETH_ACC_MAC_UNI_ADDR_2 0x0F4 99 #define IX_ETH_ACC_MAC_UNI_ADDR_3 0x0F8 100 #define IX_ETH_ACC_MAC_UNI_ADDR_4 0x0FC 101 #define IX_ETH_ACC_MAC_UNI_ADDR_5 0x100 102 #define IX_ETH_ACC_MAC_UNI_ADDR_6 0x104 103 #define IX_ETH_ACC_MAC_CORE_CNTRL 0x1FC 104 105 106 /* 107 * 108 *Bit definitions 109 * 110 */ 111 112 /* TX Control Register 1*/ 113 114 #define IX_ETH_ACC_TX_CNTRL1_TX_EN BIT(0) 115 #define IX_ETH_ACC_TX_CNTRL1_DUPLEX BIT(1) 116 #define IX_ETH_ACC_TX_CNTRL1_RETRY BIT(2) 117 #define IX_ETH_ACC_TX_CNTRL1_PAD_EN BIT(3) 118 #define IX_ETH_ACC_TX_CNTRL1_FCS_EN BIT(4) 119 #define IX_ETH_ACC_TX_CNTRL1_2DEFER BIT(5) 120 #define IX_ETH_ACC_TX_CNTRL1_RMII BIT(6) 121 122 /* TX Control Register 2 */ 123 #define IX_ETH_ACC_TX_CNTRL2_RETRIES_MASK 0xf 124 125 /* RX Control Register 1 */ 126 #define IX_ETH_ACC_RX_CNTRL1_RX_EN BIT(0) 127 #define IX_ETH_ACC_RX_CNTRL1_PADSTRIP_EN BIT(1) 128 #define IX_ETH_ACC_RX_CNTRL1_CRC_EN BIT(2) 129 #define IX_ETH_ACC_RX_CNTRL1_PAUSE_EN BIT(3) 130 #define IX_ETH_ACC_RX_CNTRL1_LOOP_EN BIT(4) 131 #define IX_ETH_ACC_RX_CNTRL1_ADDR_FLTR_EN BIT(5) 132 #define IX_ETH_ACC_RX_CNTRL1_RX_RUNT_EN BIT(6) 133 #define IX_ETH_ACC_RX_CNTRL1_BCAST_DIS BIT(7) 134 135 /* RX Control Register 2 */ 136 #define IX_ETH_ACC_RX_CNTRL2_DEFER_EN BIT(0) 137 138 139 140 /* Core Control Register */ 141 #define IX_ETH_ACC_CORE_RESET BIT(0) 142 #define IX_ETH_ACC_CORE_RX_FIFO_FLUSH BIT(1) 143 #define IX_ETH_ACC_CORE_TX_FIFO_FLUSH BIT(2) 144 #define IX_ETH_ACC_CORE_SEND_JAM BIT(3) 145 #define IX_ETH_ACC_CORE_MDC_EN BIT(4) 146 147 /* 1st bit of 1st MAC octet */ 148 #define IX_ETH_ACC_ETH_MAC_BCAST_MCAST_BIT ( 1) 149 150 151 /* 152 * 153 * Default values 154 * 155 */ 156 157 158 #define IX_ETH_ACC_TX_CNTRL1_DEFAULT (IX_ETH_ACC_TX_CNTRL1_TX_EN | \ 159 IX_ETH_ACC_TX_CNTRL1_RETRY | \ 160 IX_ETH_ACC_TX_CNTRL1_FCS_EN | \ 161 IX_ETH_ACC_TX_CNTRL1_2DEFER | \ 162 IX_ETH_ACC_TX_CNTRL1_PAD_EN) 163 164 #define IX_ETH_ACC_TX_MAX_RETRIES_DEFAULT 0x0f 165 166 #define IX_ETH_ACC_RX_CNTRL1_DEFAULT (IX_ETH_ACC_RX_CNTRL1_CRC_EN \ 167 | IX_ETH_ACC_RX_CNTRL1_RX_EN) 168 169 #define IX_ETH_ACC_RX_CNTRL2_DEFAULT 0x0 170 171 /* Thresholds determined by NPE firmware FS */ 172 #define IX_ETH_ACC_MAC_THRESH_P_EMPTY_DEFAULT 0x12 173 #define IX_ETH_ACC_MAC_THRESH_P_FULL_DEFAULT 0x30 174 175 /* Number of bytes that must be in the tx fifo before 176 transmission commences*/ 177 #define IX_ETH_ACC_MAC_BUF_SIZE_TX_DEFAULT 0x8 178 179 /* One-part deferral values */ 180 #define IX_ETH_ACC_MAC_TX_DEFER_DEFAULT 0x15 181 #define IX_ETH_ACC_MAC_RX_DEFER_DEFAULT 0x16 182 183 /* Two-part deferral values... */ 184 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_1_DEFAULT 0x08 185 #define IX_ETH_ACC_MAC_TX_TWO_DEFER_2_DEFAULT 0x07 186 187 /* This value applies to MII */ 188 #define IX_ETH_ACC_MAC_SLOT_TIME_DEFAULT 0x80 189 190 /* This value applies to RMII */ 191 #define IX_ETH_ACC_MAC_SLOT_TIME_RMII_DEFAULT 0xFF 192 193 #define IX_ETH_ACC_MAC_ADDR_MASK_DEFAULT 0xFF 194 195 #define IX_ETH_ACC_MAC_INT_CLK_THRESH_DEFAULT 0x1 196 /*The following is a value chosen at random*/ 197 #define IX_ETH_ACC_RANDOM_SEED_DEFAULT 0x8 198 199 /*By default we must configure the MAC to generate the 200 MDC clock*/ 201 #define IX_ETH_ACC_CORE_DEFAULT (IX_ETH_ACC_CORE_MDC_EN) 202 203 #define IXP425_ETH_ACC_MAX_PHY 2 204 #define IXP425_ETH_ACC_MAX_AN_ENTRIES 20 205 #define IX_ETH_ACC_MAC_RESET_DELAY 1 206 207 #define IX_ETH_ACC_MAC_ALL_BITS_SET 0xFF 208 209 #define IX_ETH_ACC_MAC_MSGID_SHL 24 210 211 #define IX_ETH_ACC_PORT_DISABLE_DELAY_MSECS 20 212 #define IX_ETH_ACC_PORT_DISABLE_DELAY_COUNT 200 /* 4 seconds timeout */ 213 #define IX_ETH_ACC_PORT_DISABLE_RETRY_COUNT 3 214 #define IX_ETH_ACC_MIB_STATS_DELAY_MSECS 2000 /* 2 seconds delay for ethernet stats */ 215 216 /*Register access macros*/ 217 #if (CPU == SIMSPARCSOLARIS) 218 extern void registerWriteStub (UINT32 base, UINT32 offset, UINT32 val); 219 extern UINT32 registerReadStub (UINT32 base, UINT32 offset); 220 221 #define REG_WRITE(b,o,v) registerWriteStub(b, o, v) 222 #define REG_READ(b,o,v) do { v = registerReadStub(b, o); } while (0) 223 #else 224 #define REG_WRITE(b,o,v) IX_OSAL_WRITE_LONG((volatile UINT32 *)(b + o), v) 225 #define REG_READ(b,o,v) (v = IX_OSAL_READ_LONG((volatile UINT32 *)(b + o))) 226 227 #endif 228 229 void ixEthAccMacUnload(void); 230 IxEthAccStatus ixEthAccMacMemInit(void); 231 232 /* MAC core loopback */ 233 IxEthAccStatus ixEthAccPortLoopbackEnable(IxEthAccPortId portId); 234 IxEthAccStatus ixEthAccPortLoopbackDisable(IxEthAccPortId portId); 235 236 /* MAC core traffic control */ 237 IxEthAccStatus ixEthAccPortTxEnablePriv(IxEthAccPortId portId); 238 IxEthAccStatus ixEthAccPortTxDisablePriv(IxEthAccPortId portId); 239 IxEthAccStatus ixEthAccPortRxEnablePriv(IxEthAccPortId portId); 240 IxEthAccStatus ixEthAccPortRxDisablePriv(IxEthAccPortId portId); 241 IxEthAccStatus ixEthAccPortMacResetPriv(IxEthAccPortId portId); 242 243 /* NPE software loopback */ 244 IxEthAccStatus ixEthAccNpeLoopbackDisablePriv(IxEthAccPortId portId); 245 IxEthAccStatus ixEthAccNpeLoopbackEnablePriv(IxEthAccPortId portId); 246 247 #endif /*IxEthAccMac_p_H*/ 248 249