1 /*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * calculate the organization and timing parameter
6 * from ddr3 spd, please refer to the spec
7 * JEDEC standard No.21-C 4_01_02_11R18.pdf
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * Version 2 as published by the Free Software Foundation.
12 */
13
14 #include <common.h>
15 #include <asm/fsl_ddr_sdram.h>
16
17 #include "ddr.h"
18
19 /*
20 * Calculate the Density of each Physical Rank.
21 * Returned size is in bytes.
22 *
23 * each rank size =
24 * sdram capacity(bit) / 8 * primary bus width / sdram width
25 *
26 * where: sdram capacity = spd byte4[3:0]
27 * primary bus width = spd byte8[2:0]
28 * sdram width = spd byte7[2:0]
29 *
30 * SPD byte4 - sdram density and banks
31 * bit[3:0] size(bit) size(byte)
32 * 0000 256Mb 32MB
33 * 0001 512Mb 64MB
34 * 0010 1Gb 128MB
35 * 0011 2Gb 256MB
36 * 0100 4Gb 512MB
37 * 0101 8Gb 1GB
38 * 0110 16Gb 2GB
39 *
40 * SPD byte8 - module memory bus width
41 * bit[2:0] primary bus width
42 * 000 8bits
43 * 001 16bits
44 * 010 32bits
45 * 011 64bits
46 *
47 * SPD byte7 - module organiztion
48 * bit[2:0] sdram device width
49 * 000 4bits
50 * 001 8bits
51 * 010 16bits
52 * 011 32bits
53 *
54 */
55 static unsigned long long
compute_ranksize(const ddr3_spd_eeprom_t * spd)56 compute_ranksize(const ddr3_spd_eeprom_t *spd)
57 {
58 unsigned long long bsize;
59
60 int nbit_sdram_cap_bsize = 0;
61 int nbit_primary_bus_width = 0;
62 int nbit_sdram_width = 0;
63
64 if ((spd->density_banks & 0xf) < 7)
65 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
66 if ((spd->bus_width & 0x7) < 4)
67 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
68 if ((spd->organization & 0x7) < 4)
69 nbit_sdram_width = (spd->organization & 0x7) + 2;
70
71 bsize = 1ULL << (nbit_sdram_cap_bsize - 3
72 + nbit_primary_bus_width - nbit_sdram_width);
73
74 debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
75
76 return bsize;
77 }
78
79 /*
80 * ddr_compute_dimm_parameters for DDR3 SPD
81 *
82 * Compute DIMM parameters based upon the SPD information in spd.
83 * Writes the results to the dimm_params_t structure pointed by pdimm.
84 *
85 */
86 unsigned int
ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t * spd,dimm_params_t * pdimm,unsigned int dimm_number)87 ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
88 dimm_params_t *pdimm,
89 unsigned int dimm_number)
90 {
91 unsigned int retval;
92 unsigned int mtb_ps;
93
94 if (spd->mem_type) {
95 if (spd->mem_type != SPD_MEMTYPE_DDR3) {
96 printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number);
97 return 1;
98 }
99 } else {
100 memset(pdimm, 0, sizeof(dimm_params_t));
101 return 1;
102 }
103
104 retval = ddr3_spd_check(spd);
105 if (retval) {
106 printf("DIMM %u: failed checksum\n", dimm_number);
107 return 2;
108 }
109
110 /*
111 * The part name in ASCII in the SPD EEPROM is not null terminated.
112 * Guarantee null termination here by presetting all bytes to 0
113 * and copying the part name in ASCII from the SPD onto it
114 */
115 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
116 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
117
118 /* DIMM organization parameters */
119 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
120 pdimm->rank_density = compute_ranksize(spd);
121 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
122 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
123 if ((spd->bus_width >> 3) & 0x3)
124 pdimm->ec_sdram_width = 8;
125 else
126 pdimm->ec_sdram_width = 0;
127 pdimm->data_width = pdimm->primary_sdram_width
128 + pdimm->ec_sdram_width;
129
130 switch (spd->module_type & 0xf) {
131 case 0x01: /* RDIMM */
132 case 0x05: /* Mini-RDIMM */
133 pdimm->registered_dimm = 1; /* register buffered */
134 break;
135
136 case 0x02: /* UDIMM */
137 case 0x03: /* SO-DIMM */
138 case 0x04: /* Micro-DIMM */
139 case 0x06: /* Mini-UDIMM */
140 pdimm->registered_dimm = 0; /* unbuffered */
141 break;
142
143 default:
144 printf("unknown dimm_type 0x%02X\n", spd->module_type);
145 return 1;
146 }
147
148 /* SDRAM device parameters */
149 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
150 pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
151 pdimm->n_banks_per_sdram_device = 8 << ((spd->density_banks >> 4) & 0x7);
152
153 /*
154 * The SPD spec has not the ECC bit,
155 * We consider the DIMM as ECC capability
156 * when the extension bus exist
157 */
158 if (pdimm->ec_sdram_width)
159 pdimm->edc_config = 0x02;
160 else
161 pdimm->edc_config = 0x00;
162
163 /*
164 * The SPD spec has not the burst length byte
165 * but DDR3 spec has nature BL8 and BC4,
166 * BL8 -bit3, BC4 -bit2
167 */
168 pdimm->burst_lengths_bitmask = 0x0c;
169 pdimm->row_density = __ilog2(pdimm->rank_density);
170
171 /* MTB - medium timebase
172 * The unit in the SPD spec is ns,
173 * We convert it to ps.
174 * eg: MTB = 0.125ns (125ps)
175 */
176 mtb_ps = (spd->mtb_dividend * 1000) /spd->mtb_divisor;
177 pdimm->mtb_ps = mtb_ps;
178
179 /*
180 * sdram minimum cycle time
181 * we assume the MTB is 0.125ns
182 * eg:
183 * tCK_min=15 MTB (1.875ns) ->DDR3-1066
184 * =12 MTB (1.5ns) ->DDR3-1333
185 * =10 MTB (1.25ns) ->DDR3-1600
186 */
187 pdimm->tCKmin_X_ps = spd->tCK_min * mtb_ps;
188
189 /*
190 * CAS latency supported
191 * bit4 - CL4
192 * bit5 - CL5
193 * bit18 - CL18
194 */
195 pdimm->caslat_X = ((spd->caslat_msb << 8) | spd->caslat_lsb) << 4;
196
197 /*
198 * min CAS latency time
199 * eg: tAA_min =
200 * DDR3-800D 100 MTB (12.5ns)
201 * DDR3-1066F 105 MTB (13.125ns)
202 * DDR3-1333H 108 MTB (13.5ns)
203 * DDR3-1600H 90 MTB (11.25ns)
204 */
205 pdimm->tAA_ps = spd->tAA_min * mtb_ps;
206
207 /*
208 * min write recovery time
209 * eg:
210 * tWR_min = 120 MTB (15ns) -> all speed grades.
211 */
212 pdimm->tWR_ps = spd->tWR_min * mtb_ps;
213
214 /*
215 * min RAS to CAS delay time
216 * eg: tRCD_min =
217 * DDR3-800 100 MTB (12.5ns)
218 * DDR3-1066F 105 MTB (13.125ns)
219 * DDR3-1333H 108 MTB (13.5ns)
220 * DDR3-1600H 90 MTB (11.25)
221 */
222 pdimm->tRCD_ps = spd->tRCD_min * mtb_ps;
223
224 /*
225 * min row active to row active delay time
226 * eg: tRRD_min =
227 * DDR3-800(1KB page) 80 MTB (10ns)
228 * DDR3-1333(1KB page) 48 MTB (6ns)
229 */
230 pdimm->tRRD_ps = spd->tRRD_min * mtb_ps;
231
232 /*
233 * min row precharge delay time
234 * eg: tRP_min =
235 * DDR3-800D 100 MTB (12.5ns)
236 * DDR3-1066F 105 MTB (13.125ns)
237 * DDR3-1333H 108 MTB (13.5ns)
238 * DDR3-1600H 90 MTB (11.25ns)
239 */
240 pdimm->tRP_ps = spd->tRP_min * mtb_ps;
241
242 /* min active to precharge delay time
243 * eg: tRAS_min =
244 * DDR3-800D 300 MTB (37.5ns)
245 * DDR3-1066F 300 MTB (37.5ns)
246 * DDR3-1333H 288 MTB (36ns)
247 * DDR3-1600H 280 MTB (35ns)
248 */
249 pdimm->tRAS_ps = (((spd->tRAS_tRC_ext & 0xf) << 8) | spd->tRAS_min_lsb)
250 * mtb_ps;
251 /*
252 * min active to actice/refresh delay time
253 * eg: tRC_min =
254 * DDR3-800D 400 MTB (50ns)
255 * DDR3-1066F 405 MTB (50.625ns)
256 * DDR3-1333H 396 MTB (49.5ns)
257 * DDR3-1600H 370 MTB (46.25ns)
258 */
259 pdimm->tRC_ps = (((spd->tRAS_tRC_ext & 0xf0) << 4) | spd->tRC_min_lsb)
260 * mtb_ps;
261 /*
262 * min refresh recovery delay time
263 * eg: tRFC_min =
264 * 512Mb 720 MTB (90ns)
265 * 1Gb 880 MTB (110ns)
266 * 2Gb 1280 MTB (160ns)
267 */
268 pdimm->tRFC_ps = ((spd->tRFC_min_msb << 8) | spd->tRFC_min_lsb)
269 * mtb_ps;
270 /*
271 * min internal write to read command delay time
272 * eg: tWTR_min = 40 MTB (7.5ns) - all speed bins.
273 * tWRT is at least 4 mclk independent of operating freq.
274 */
275 pdimm->tWTR_ps = spd->tWTR_min * mtb_ps;
276
277 /*
278 * min internal read to precharge command delay time
279 * eg: tRTP_min = 40 MTB (7.5ns) - all speed bins.
280 * tRTP is at least 4 mclk independent of operating freq.
281 */
282 pdimm->tRTP_ps = spd->tRTP_min * mtb_ps;
283
284 /*
285 * Average periodic refresh interval
286 * tREFI = 7.8 us at normal temperature range
287 * = 3.9 us at ext temperature range
288 */
289 pdimm->refresh_rate_ps = 7800000;
290
291 /*
292 * min four active window delay time
293 * eg: tFAW_min =
294 * DDR3-800(1KB page) 320 MTB (40ns)
295 * DDR3-1066(1KB page) 300 MTB (37.5ns)
296 * DDR3-1333(1KB page) 240 MTB (30ns)
297 * DDR3-1600(1KB page) 240 MTB (30ns)
298 */
299 pdimm->tFAW_ps = (((spd->tFAW_msb & 0xf) << 8) | spd->tFAW_min)
300 * mtb_ps;
301
302 /*
303 * We need check the address mirror for unbuffered DIMM
304 * If SPD indicate the address map mirror, The DDR controller
305 * need care it.
306 */
307 if ((spd->module_type == SPD_MODULETYPE_UDIMM) ||
308 (spd->module_type == SPD_MODULETYPE_SODIMM) ||
309 (spd->module_type == SPD_MODULETYPE_MICRODIMM) ||
310 (spd->module_type == SPD_MODULETYPE_MINIUDIMM))
311 pdimm->mirrored_dimm = spd->mod_section.unbuffered.addr_mapping & 0x1;
312
313 return 0;
314 }
315