1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * with the reference on libata and ahci drvier in kernel
25 *
26 */
27 #include <common.h>
28
29 #include <command.h>
30 #include <pci.h>
31 #include <asm/processor.h>
32 #include <asm/errno.h>
33 #include <asm/io.h>
34 #include <malloc.h>
35 #include <scsi.h>
36 #include <ata.h>
37 #include <linux/ctype.h>
38 #include <ahci.h>
39
40 #define debug printf
41
42 struct ahci_probe_ent *probe_ent = NULL;
43 hd_driveid_t *ataid[AHCI_MAX_PORTS];
44
45 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
46
47
ahci_port_base(u32 base,u32 port)48 static inline u32 ahci_port_base(u32 base, u32 port)
49 {
50 return base + 0x100 + (port * 0x80);
51 }
52
53
ahci_setup_port(struct ahci_ioports * port,unsigned long base,unsigned int port_idx)54 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
55 unsigned int port_idx)
56 {
57 base = ahci_port_base(base, port_idx);
58
59 port->cmd_addr = base;
60 port->scr_addr = base + PORT_SCR;
61 }
62
63
64 #define msleep(a) udelay(a * 1000)
65 #define ssleep(a) msleep(a * 1000)
66
waiting_for_cmd_completed(volatile u8 * offset,int timeout_msec,u32 sign)67 static int waiting_for_cmd_completed(volatile u8 *offset,
68 int timeout_msec,
69 u32 sign)
70 {
71 int i;
72 u32 status;
73
74 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
75 msleep(1);
76
77 return (i < timeout_msec) ? 0 : -1;
78 }
79
ahci_enable_ahci(volatile u8 * mmio)80 static void ahci_enable_ahci(volatile u8 *mmio)
81 {
82 int i;
83 u32 tmp;
84
85 /* turn on AHCI_EN */
86 tmp = readl(mmio + HOST_CTL);
87
88 debug ("Setting AHCI_EN... (tmp = 0x%08x) ",tmp);
89 if (!(tmp & HOST_AHCI_EN))
90 {
91 /* Some controllers need AHCI_EN to be written multiple times.
92 * Try a few times before giving up.
93 */
94 for (i = 0; i < 5; i++) {
95 tmp |= HOST_AHCI_EN;
96 writel(tmp, mmio + HOST_CTL);
97 tmp = readl(mmio + HOST_CTL); /* flush && sanity check */
98 if (tmp & HOST_AHCI_EN)
99 break;
100
101 msleep(10);
102 }
103 }
104
105 debug("done\n");
106 }
107
ahci_host_init(struct ahci_probe_ent * probe_ent)108 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
109 {
110 pci_dev_t pdev = probe_ent->dev;
111 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
112 u32 tmp, cap_save;
113 u16 tmp16;
114 int i, j;
115 volatile u8 *port_mmio;
116 unsigned short vendor;
117
118 /* make sure AHCI mode is enabled before accessing CAP */
119 ahci_enable_ahci(mmio);
120
121 cap_save = readl(mmio + HOST_CAP);
122 debug ("old cap_save 0x%08x\n",cap_save);
123
124 cap_save &= ((1 << 28) | (1 << 17));
125 cap_save |= (1 << 27);
126
127 debug ("new cap_save 0x%08x\n",cap_save);
128
129 ahci_enable_ahci(mmio);
130
131 /* global controller reset */
132 tmp = readl(mmio + HOST_CTL);
133 if ((tmp & HOST_RESET) == 0)
134 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
135
136 /* reset must complete within 1 second, or
137 * the hardware should be considered fried.
138 */
139 ssleep(1);
140
141 tmp = readl(mmio + HOST_CTL);
142 if (tmp & HOST_RESET) {
143 debug("controller reset failed (0x%x)\n", tmp);
144 return -1;
145 }
146
147 /* turn on AHCI_EN */
148 ahci_enable_ahci(mmio);
149
150 writel(cap_save, mmio + HOST_CAP);
151 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
152
153 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
154
155 if (vendor == PCI_VENDOR_ID_INTEL) {
156 u16 tmp16;
157 pci_read_config_word(pdev, 0x92, &tmp16);
158 tmp16 |= 0xf;
159 pci_write_config_word(pdev, 0x92, tmp16);
160 }
161
162 probe_ent->cap = readl(mmio + HOST_CAP);
163 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
164 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
165
166 debug("cap 0x%x port_map 0x%x n_ports %d\n",
167 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
168
169 for (i = 0; i < probe_ent->n_ports; i++) {
170 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
171 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
172 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
173
174 /* make sure port is not active */
175 tmp = readl(port_mmio + PORT_CMD);
176 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
177 PORT_CMD_FIS_RX | PORT_CMD_START)) {
178 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
179 PORT_CMD_FIS_RX | PORT_CMD_START);
180 writel_with_flush(tmp, port_mmio + PORT_CMD);
181
182 /* spec says 500 msecs for each bit, so
183 * this is slightly incorrect.
184 */
185 msleep(500);
186 }
187
188 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
189
190 j = 0;
191 while (j < 100) {
192 msleep(10);
193 tmp = readl(port_mmio + PORT_SCR_STAT);
194 if ((tmp & 0xf) == 0x3)
195 break;
196 j++;
197 }
198
199 tmp = readl(port_mmio + PORT_SCR_ERR);
200 debug("PORT_SCR_ERR 0x%x\n", tmp);
201 writel(tmp, port_mmio + PORT_SCR_ERR);
202
203 /* ack any pending irq events for this port */
204 tmp = readl(port_mmio + PORT_IRQ_STAT);
205 debug("PORT_IRQ_STAT 0x%x\n", tmp);
206 if (tmp)
207 writel(tmp, port_mmio + PORT_IRQ_STAT);
208
209 writel(1 << probe_ent->n_ports, mmio + HOST_IRQ_STAT);
210
211 /* set irq mask (enables interrupts) */
212 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
213
214 /*register linkup ports */
215 tmp = readl(port_mmio + PORT_SCR_STAT);
216 debug("Port %d status: 0x%x\n", i, tmp);
217 if ((tmp & 0xf) == 0x03)
218 probe_ent->link_port_map |= (0x01 << i);
219 }
220
221 tmp = readl(mmio + HOST_CTL);
222 debug("HOST_CTL 0x%x\n", tmp);
223 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
224 tmp = readl(mmio + HOST_CTL);
225 debug("HOST_CTL 0x%x\n", tmp);
226
227 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
228 tmp16 |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY);
229 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
230
231 return 0;
232 }
233
234
ahci_print_info(struct ahci_probe_ent * probe_ent)235 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
236 {
237 pci_dev_t pdev = probe_ent->dev;
238 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
239 u32 vers, cap, impl, speed;
240 const char *speed_s;
241 u16 cc;
242 const char *scc_s;
243
244 vers = readl(mmio + HOST_VERSION);
245 cap = probe_ent->cap;
246 impl = probe_ent->port_map;
247
248 speed = (cap >> 20) & 0xf;
249 if (speed == 1)
250 speed_s = "1.5";
251 else if (speed == 2)
252 speed_s = "3";
253 else
254 speed_s = "?";
255
256 pci_read_config_word(pdev, 0x0a, &cc);
257 if (cc == 0x0101)
258 scc_s = "IDE";
259 else if (cc == 0x0106)
260 scc_s = "SATA";
261 else if (cc == 0x0104)
262 scc_s = "RAID";
263 else
264 scc_s = "unknown";
265
266 printf("AHCI %02x%02x.%02x%02x "
267 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
268 (vers >> 24) & 0xff,
269 (vers >> 16) & 0xff,
270 (vers >> 8) & 0xff,
271 vers & 0xff,
272 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
273
274 printf("flags: "
275 "%s%s%s%s%s%s"
276 "%s%s%s%s%s%s%s\n",
277 cap & (1 << 31) ? "64bit " : "",
278 cap & (1 << 30) ? "ncq " : "",
279 cap & (1 << 28) ? "ilck " : "",
280 cap & (1 << 27) ? "stag " : "",
281 cap & (1 << 26) ? "pm " : "",
282 cap & (1 << 25) ? "led " : "",
283 cap & (1 << 24) ? "clo " : "",
284 cap & (1 << 19) ? "nz " : "",
285 cap & (1 << 18) ? "only " : "",
286 cap & (1 << 17) ? "pmp " : "",
287 cap & (1 << 15) ? "pio " : "",
288 cap & (1 << 14) ? "slum " : "",
289 cap & (1 << 13) ? "part " : "");
290 }
291
ahci_init_one(pci_dev_t pdev)292 static int ahci_init_one(pci_dev_t pdev)
293 {
294 u16 vendor;
295 int rc;
296
297 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
298
299 probe_ent = malloc(sizeof(struct ahci_probe_ent));
300 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
301 probe_ent->dev = pdev;
302
303 probe_ent->host_flags = ATA_FLAG_SATA
304 | ATA_FLAG_NO_LEGACY
305 | ATA_FLAG_MMIO
306 | ATA_FLAG_PIO_DMA
307 | ATA_FLAG_NO_ATAPI;
308 probe_ent->pio_mask = 0x1f;
309 probe_ent->udma_mask = 0x1f; /*Fixme,assume to support UDMA4 */
310
311 probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
312 PCI_REGION_MEM);
313
314 /* Take from kernel:
315 * JMicron-specific fixup:
316 * make sure we're in AHCI mode
317 */
318 //pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
319 //if (vendor == 0x197b)
320 // pci_write_config_byte(pdev, 0x41, 0xa1);
321
322 /* initialize adapter */
323 rc = ahci_host_init(probe_ent);
324 if (rc)
325 goto err_out;
326
327 ahci_print_info(probe_ent);
328
329 return 0;
330
331 err_out:
332 return rc;
333 }
334
335
336 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
337
ahci_fill_sg(u8 port,unsigned char * buf,int buf_len)338 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
339 {
340 struct ahci_ioports *pp = &(probe_ent->port[port]);
341 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
342 u32 sg_count;
343 int i;
344
345 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
346 if (sg_count > AHCI_MAX_SG) {
347 printf("Error:Too much sg!\n");
348 return -1;
349 }
350
351 for (i = 0; i < sg_count; i++) {
352 ahci_sg->addr =
353 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
354 ahci_sg->addr_hi = 0;
355 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
356 (buf_len < MAX_DATA_BYTE_COUNT
357 ? (buf_len - 1)
358 : (MAX_DATA_BYTE_COUNT - 1)));
359 ahci_sg++;
360 buf_len -= MAX_DATA_BYTE_COUNT;
361 }
362
363 return sg_count;
364 }
365
366
ahci_fill_cmd_slot(struct ahci_ioports * pp,u32 opts)367 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
368 {
369 pp->cmd_slot->opts = cpu_to_le32(opts);
370 pp->cmd_slot->status = 0;
371 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
372 pp->cmd_slot->tbl_addr_hi = 0;
373 }
374
375
ahci_set_feature(u8 port)376 static void ahci_set_feature(u8 port)
377 {
378 struct ahci_ioports *pp = &(probe_ent->port[port]);
379 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
380 u32 cmd_fis_len = 5; /* five dwords */
381 u8 fis[20];
382
383 /*set feature */
384 memset(fis, 0, 20);
385 fis[0] = 0x27;
386 fis[1] = 1 << 7;
387 fis[2] = ATA_CMD_SETF;
388 fis[3] = SETFEATURES_XFER;
389 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
390
391 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
392 ahci_fill_cmd_slot(pp, cmd_fis_len);
393 writel(1, port_mmio + PORT_CMD_ISSUE);
394 //readl(port_mmio + PORT_CMD_ISSUE);
395 wait_ms(150);
396
397 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
398 printf("set feature error!\n");
399 }
400 }
401
402
ahci_port_start(u8 port)403 static int ahci_port_start(u8 port)
404 {
405 struct ahci_ioports *pp = &(probe_ent->port[port]);
406 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
407 u32 port_status;
408 u32 mem;
409
410 debug("Enter start port: %d\n", port);
411 port_status = readl(port_mmio + PORT_SCR_STAT);
412 debug("Port %d status: %x\n", port, port_status);
413 if ((port_status & 0xf) != 0x03) {
414 printf("No Link on this port!\n");
415 return -1;
416 }
417
418 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
419 if (!mem) {
420 free(pp);
421 printf("No mem for table!\n");
422 return -ENOMEM;
423 }
424
425 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
426 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
427
428 /*
429 * First item in chunk of DMA memory: 32-slot command table,
430 * 32 bytes each in size
431 */
432 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
433 debug("cmd_slot = 0x%x\n", pp->cmd_slot);
434 mem += (AHCI_CMD_SLOT_SZ + 224);
435
436 /*
437 * Second item: Received-FIS area
438 */
439 pp->rx_fis = mem;
440 mem += AHCI_RX_FIS_SZ;
441
442 /*
443 * Third item: data area for storing a single command
444 * and its scatter-gather table
445 */
446 pp->cmd_tbl = mem;
447 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
448
449 mem += AHCI_CMD_TBL_HDR;
450 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
451
452 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
453
454 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
455
456 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
457 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
458 PORT_CMD_START, port_mmio + PORT_CMD);
459
460 debug("Exit start port %d\n", port);
461
462 return 0;
463 }
464
465
get_ahci_device_data(u8 port,u8 * fis,int fis_len,u8 * buf,int buf_len)466 static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
467 int buf_len)
468 {
469
470 struct ahci_ioports *pp = &(probe_ent->port[port]);
471 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
472 u32 opts;
473 u32 port_status;
474 int sg_count;
475
476 debug("Enter get_ahci_device_data: for port %d\n", port);
477
478 if (port > probe_ent->n_ports) {
479 printf("Invaild port number %d\n", port);
480 return -1;
481 }
482
483 port_status = readl(port_mmio + PORT_SCR_STAT);
484 if ((port_status & 0xf) != 0x03) {
485 debug("No Link on port %d!\n", port);
486 return -1;
487 }
488
489 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
490
491 sg_count = ahci_fill_sg(port, buf, buf_len);
492 opts = (fis_len >> 2) | (sg_count << 16);
493 ahci_fill_cmd_slot(pp, opts);
494
495 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
496
497 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
498 printf("timeout exit!\n");
499 return -1;
500 }
501 debug("get_ahci_device_data: %d byte transferred.\n",
502 pp->cmd_slot->status);
503
504 return 0;
505 }
506
507
ata_id_strcpy(u16 * target,u16 * src,int len)508 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
509 {
510 int i;
511 for (i = 0; i < len / 2; i++)
512 target[i] = le16_to_cpu(src[i]);
513 return (char *)target;
514 }
515
516
dump_ataid(hd_driveid_t * ataid)517 static void dump_ataid(hd_driveid_t *ataid)
518 {
519 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
520 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
521 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
522 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
523 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
524 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
525 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
526 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
527 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
528 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
529 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
530 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
531 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
532 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
533 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
534 }
535
536
537 /*
538 * SCSI INQUIRY command operation.
539 */
ata_scsiop_inquiry(ccb * pccb)540 static int ata_scsiop_inquiry(ccb *pccb)
541 {
542 u8 hdr[] = {
543 0,
544 0,
545 0x5, /* claim SPC-3 version compatibility */
546 2,
547 95 - 4,
548 };
549 u8 fis[20];
550 u8 *tmpid;
551 u8 port;
552
553 /* Clean ccb data buffer */
554 memset(pccb->pdata, 0, pccb->datalen);
555
556 memcpy(pccb->pdata, hdr, sizeof(hdr));
557
558 if (pccb->datalen <= 35)
559 return 0;
560
561 memset(fis, 0, 20);
562 /* Construct the FIS */
563 fis[0] = 0x27; /* Host to device FIS. */
564 fis[1] = 1 << 7; /* Command FIS. */
565 fis[2] = ATA_CMD_IDENT; /* Command byte. */
566
567 /* Read id from sata */
568 port = pccb->target;
569 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
570 return -ENOMEM;
571
572 if (get_ahci_device_data(port, (u8 *) & fis, 20,
573 tmpid, sizeof(hd_driveid_t))) {
574 debug("scsi_ahci: SCSI inquiry command failure.\n");
575 return -EIO;
576 }
577
578 if (ataid[port])
579 free(ataid[port]);
580 ataid[port] = (hd_driveid_t *) tmpid;
581
582 memcpy(&pccb->pdata[8], "ATA ", 8);
583 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
584 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
585
586 dump_ataid(ataid[port]);
587 return 0;
588 }
589
590
591 /*
592 * SCSI READ10 command operation.
593 */
ata_scsiop_read10(ccb * pccb)594 static int ata_scsiop_read10(ccb * pccb)
595 {
596 u64 lba = 0;
597 u32 len = 0;
598 u8 fis[20];
599
600 lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
601 | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
602 len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
603
604 /* For 10-byte and 16-byte SCSI R/W commands, transfer
605 * length 0 means transfer 0 block of data.
606 * However, for ATA R/W commands, sector count 0 means
607 * 256 or 65536 sectors, not 0 sectors as in SCSI.
608 *
609 * WARNING: one or two older ATA drives treat 0 as 0...
610 */
611 if (!len)
612 return 0;
613 memset(fis, 0, 20);
614
615 /* Construct the FIS */
616 fis[0] = 0x27; /* Host to device FIS. */
617 fis[1] = 1 << 7; /* Command FIS. */
618 fis[2] = ATA_CMD_RD_DMA; /* Command byte. */
619
620 /* LBA address, only support LBA28 in this driver */
621 fis[4] = pccb->cmd[5];
622 fis[5] = pccb->cmd[4];
623 fis[6] = pccb->cmd[3];
624 fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
625
626 /* Sector Count */
627 fis[12] = pccb->cmd[8];
628 fis[13] = pccb->cmd[7];
629
630 /* Read from ahci */
631 if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
632 pccb->pdata, pccb->datalen)) {
633 debug("scsi_ahci: SCSI READ10 command failure.\n");
634 return -EIO;
635 }
636
637 return 0;
638 }
639
640
641 /*
642 * SCSI READ CAPACITY10 command operation.
643 */
ata_scsiop_read_capacity10(ccb * pccb)644 static int ata_scsiop_read_capacity10(ccb *pccb)
645 {
646 u32 cap;
647
648 if (!ataid[pccb->target]) {
649 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
650 "\tNo ATA info!\n"
651 "\tPlease run SCSI commmand INQUIRY firstly!\n");
652 return -EPERM;
653 }
654
655 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
656 memcpy(pccb->pdata, &cap, sizeof(cap));
657
658 pccb->pdata[4] = pccb->pdata[5] = 0;
659 pccb->pdata[6] = 512 >> 8;
660 pccb->pdata[7] = 512 & 0xff;
661
662 return 0;
663 }
664
665
666 /*
667 * SCSI TEST UNIT READY command operation.
668 */
ata_scsiop_test_unit_ready(ccb * pccb)669 static int ata_scsiop_test_unit_ready(ccb *pccb)
670 {
671 return (ataid[pccb->target]) ? 0 : -EPERM;
672 }
673
674
scsi_exec(ccb * pccb)675 int scsi_exec(ccb *pccb)
676 {
677 int ret;
678
679 switch (pccb->cmd[0]) {
680 case SCSI_READ10:
681 ret = ata_scsiop_read10(pccb);
682 break;
683 case SCSI_RD_CAPAC:
684 ret = ata_scsiop_read_capacity10(pccb);
685 break;
686 case SCSI_TST_U_RDY:
687 ret = ata_scsiop_test_unit_ready(pccb);
688 break;
689 case SCSI_INQUIRY:
690 ret = ata_scsiop_inquiry(pccb);
691 break;
692 default:
693 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
694 return FALSE;
695 }
696
697 if (ret) {
698 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
699 return FALSE;
700 }
701 return TRUE;
702
703 }
704
705
scsi_low_level_init(int busdevfunc)706 void scsi_low_level_init(int busdevfunc)
707 {
708 int i;
709 u32 linkmap;
710
711 ahci_init_one(busdevfunc);
712
713 linkmap = probe_ent->link_port_map;
714
715 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
716 if (((linkmap >> i) & 0x01)) {
717 if (ahci_port_start((u8) i)) {
718 printf("Can not start port %d\n", i);
719 continue;
720 }
721 ahci_set_feature((u8) i);
722 }
723 }
724 }
725
726
scsi_bus_reset(void)727 void scsi_bus_reset(void)
728 {
729 /*Not implement*/
730 }
731
732
scsi_print_error(ccb * pccb)733 void scsi_print_error(ccb * pccb)
734 {
735 /*The ahci error info can be read in the ahci driver*/
736 }
737