1 /* 2 * (C) Copyright 2000 3 * Murray Jensen <Murray.Jensen@cmst.csiro.au> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * Config header file for Cogent platform using an MPC8xx CPU module 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 /* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36 #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ 37 #define CONFIG_COGENT 1 /* using Cogent Modular Architecture */ 38 #define CONFIG_CPM2 1 /* Has a CPM2 */ 39 40 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ 41 #define CONFIG_MISC_INIT_R /* Use misc_init_r() */ 42 43 /* Cogent Modular Architecture options */ 44 #define CONFIG_CMA282 1 /* ...on a CMA282 CPU module */ 45 #define CONFIG_CMA111 1 /* ...on a CMA111 motherboard */ 46 47 /* 48 * select serial console configuration 49 * 50 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 51 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 52 * for SCC). 53 * 54 * if CONFIG_CONS_NONE is defined, then the serial console routines must 55 * defined elsewhere (for example, on the cogent platform, there are serial 56 * ports on the motherboard which are used for the serial console - see 57 * cogent/cma101/serial.[ch]). 58 */ 59 #define CONFIG_CONS_ON_SMC /* define if console on SMC */ 60 #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 61 #undef CONFIG_CONS_NONE /* define if console on something else*/ 62 #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ 63 #undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 64 #define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */ 65 #define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ 66 67 /* 68 * select ethernet configuration 69 * 70 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 71 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 72 * for FCC) 73 * 74 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 75 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 76 */ 77 #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 78 #undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 79 #define CONFIG_ETHER_NONE /* define if ether on something else */ 80 #define CONFIG_ETHER_INDEX 1 /* which channel for ether */ 81 82 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 83 #define CONFIG_8260_CLKIN 66666666 /* in Hz */ 84 85 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 86 #define CONFIG_BAUDRATE 230400 87 #else 88 #define CONFIG_BAUDRATE 9600 89 #endif 90 91 92 /* 93 * BOOTP options 94 */ 95 #define CONFIG_BOOTP_BOOTFILESIZE 96 #define CONFIG_BOOTP_BOOTPATH 97 #define CONFIG_BOOTP_GATEWAY 98 #define CONFIG_BOOTP_HOSTNAME 99 100 101 /* 102 * Command line configuration. 103 */ 104 #include <config_cmd_default.h> 105 106 #define CONFIG_CMD_KGDB 107 108 #undef CONFIG_CMD_NET 109 110 111 #ifdef DEBUG 112 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ 113 #else 114 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 115 #endif 116 #define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/ 117 118 #define CONFIG_BOOTARGS "root=/dev/ram rw" 119 120 #if defined(CONFIG_CMD_KGDB) 121 #define CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ 122 #undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ 123 #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ 124 #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ 125 #define CONFIG_KGDB_USE_EXTC /* SMC/SCC use ext clock not brg_clk */ 126 #define CONFIG_KGDB_EXTC_RATE 3686400 /* serial ext clk rate in Hz */ 127 #define CONFIG_KGDB_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/ 128 # if defined(CONFIG_KGDB_NONE) || defined(CONFIG_KGDB_USE_EXTC) 129 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port at */ 130 # else 131 #define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */ 132 # endif 133 #endif 134 135 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ 136 137 /* 138 * Miscellaneous configurable options 139 */ 140 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 141 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 142 #if defined(CONFIG_CMD_KGDB) 143 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 144 #else 145 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 146 #endif 147 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 148 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 149 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 150 151 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ 152 #define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */ 153 154 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 155 156 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 157 158 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 159 160 /* 161 * Low Level Configuration Settings 162 * (address mappings, register initial values, etc.) 163 * You should know what you are doing if you make changes here. 164 */ 165 166 /*----------------------------------------------------------------------- 167 * Low Level Cogent settings 168 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8260 CPM serial is not. 169 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be 170 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B 171 * (second 2 for CMA120 only) 172 */ 173 #define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */ 174 175 #include <configs/cogent_common.h> 176 177 #ifdef CONFIG_CONS_NONE 178 #define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */ 179 #endif 180 #define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */ 181 #define CONFIG_SHOW_ACTIVITY 182 183 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH) 184 /* 185 * flash exists on the motherboard 186 * set these four according to TOP dipsw: 187 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low ) 188 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high) 189 */ 190 #define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE 191 #define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE 192 #define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE 193 #define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE 194 #endif 195 #define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE 196 #define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE 197 198 /*----------------------------------------------------------------------- 199 * Hard Reset Configuration Words 200 * 201 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 202 * defines for the various registers affected by the HRCW e.g. changing 203 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 204 */ 205 #define CONFIG_SYS_HRCW_MASTER (HRCW_EBM|HRCW_BPS10|HRCW_L2CPC10|HRCW_DPPC11|\ 206 HRCW_ISB100|HRCW_MMR11|HRCW_MODCK_H0101) 207 /* no slaves so just duplicate the master hrcw */ 208 #define CONFIG_SYS_HRCW_SLAVE1 CONFIG_SYS_HRCW_MASTER 209 #define CONFIG_SYS_HRCW_SLAVE2 CONFIG_SYS_HRCW_MASTER 210 #define CONFIG_SYS_HRCW_SLAVE3 CONFIG_SYS_HRCW_MASTER 211 #define CONFIG_SYS_HRCW_SLAVE4 CONFIG_SYS_HRCW_MASTER 212 #define CONFIG_SYS_HRCW_SLAVE5 CONFIG_SYS_HRCW_MASTER 213 #define CONFIG_SYS_HRCW_SLAVE6 CONFIG_SYS_HRCW_MASTER 214 #define CONFIG_SYS_HRCW_SLAVE7 CONFIG_SYS_HRCW_MASTER 215 216 /*----------------------------------------------------------------------- 217 * Internal Memory Mapped Register 218 */ 219 #define CONFIG_SYS_IMMR 0xF0000000 220 221 /*----------------------------------------------------------------------- 222 * Definitions for initial stack pointer and data area (in DPRAM) 223 */ 224 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 225 #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ 226 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 227 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 228 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 229 230 /*----------------------------------------------------------------------- 231 * Start addresses for the final memory configuration 232 * (Set up by the startup code) 233 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 234 */ 235 #define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE 236 #ifdef CONFIG_CMA302 237 #define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */ 238 #else 239 #define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */ 240 #endif 241 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 242 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 243 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 244 245 /* 246 * For booting Linux, the board info and command line data 247 * have to be in the first 8 MB of memory, since this is 248 * the maximum mapped by the Linux kernel during initialization. 249 */ 250 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ 251 252 /*----------------------------------------------------------------------- 253 * FLASH organization 254 */ 255 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ 256 #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */ 257 258 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Flash Erase Timeout (in ms) */ 259 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 260 261 #define CONFIG_ENV_IS_IN_FLASH 1 262 #define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */ 263 #ifdef CONFIG_CMA302 264 #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ 265 #define CONFIG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */ 266 #else 267 #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 268 #endif 269 270 /*----------------------------------------------------------------------- 271 * Cache Configuration 272 */ 273 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 274 #if defined(CONFIG_CMD_KGDB) 275 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ 276 #endif 277 278 /*----------------------------------------------------------------------- 279 * HIDx - Hardware Implementation-dependent Registers 2-11 280 *----------------------------------------------------------------------- 281 * HID0 also contains cache control - initially enable both caches and 282 * invalidate contents, then the final state leaves only the instruction 283 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 284 * but Soft reset does not. 285 * 286 * HID1 has only read-only information - nothing to set. 287 */ 288 #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 289 HID0_IFEM|HID0_ABE) 290 #define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 291 #define CONFIG_SYS_HID2 0 292 293 /*----------------------------------------------------------------------- 294 * RMR - Reset Mode Register 5-5 295 *----------------------------------------------------------------------- 296 * turn on Checkstop Reset Enable 297 */ 298 #define CONFIG_SYS_RMR RMR_CSRE 299 300 /*----------------------------------------------------------------------- 301 * BCR - Bus Configuration 4-25 302 *----------------------------------------------------------------------- 303 */ 304 #define CONFIG_SYS_BCR BCR_EBM 305 306 /*----------------------------------------------------------------------- 307 * SIUMCR - SIU Module Configuration 4-31 308 *----------------------------------------------------------------------- 309 */ 310 #define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11|SIUMCR_L2CPC10|SIUMCR_MMR11) 311 312 /*----------------------------------------------------------------------- 313 * SYPCR - System Protection Control 4-35 314 * SYPCR can only be written once after reset! 315 *----------------------------------------------------------------------- 316 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 317 */ 318 #if defined(CONFIG_WATCHDOG) 319 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 320 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 321 #else 322 #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 323 SYPCR_SWRI|SYPCR_SWP) 324 #endif /* CONFIG_WATCHDOG */ 325 326 /*----------------------------------------------------------------------- 327 * TMCNTSC - Time Counter Status and Control 4-40 328 *----------------------------------------------------------------------- 329 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 330 * and enable Time Counter 331 */ 332 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 333 334 /*----------------------------------------------------------------------- 335 * PISCR - Periodic Interrupt Status and Control 4-42 336 *----------------------------------------------------------------------- 337 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 338 * Periodic timer 339 */ 340 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 341 342 /*----------------------------------------------------------------------- 343 * SCCR - System Clock Control 9-8 344 *----------------------------------------------------------------------- 345 * Ensure DFBRG is Divide by 16 346 */ 347 #define CONFIG_SYS_SCCR (SCCR_DFBRG01) 348 349 /*----------------------------------------------------------------------- 350 * RCCR - RISC Controller Configuration 13-7 351 *----------------------------------------------------------------------- 352 */ 353 #define CONFIG_SYS_RCCR 0 354 355 #if defined(CONFIG_CMA282) 356 357 /* 358 * Init Memory Controller: 359 * 360 * According to the Cogent manual, only CS0 and CS2 are used - CS0 for EPROM 361 * and CS2 for (optional) local bus RAM on the CPU module. 362 * 363 * Note the motherboard address space (256 Mbyte in size) is connected 364 * to the 60x Bus and is located starting at address 0. The Hard Reset 365 * Configuration Word should put the 60x Bus into External Bus Mode, since 366 * we dont set up any memory controller maps for it (see BCR[EBM], 4-26). 367 * 368 * (the *_SIZE vars must be a power of 2) 369 */ 370 371 #define CONFIG_SYS_CMA_CS0_BASE TEXT_BASE /* EPROM */ 372 #define CONFIG_SYS_CMA_CS0_SIZE (1 << 20) 373 #if 0 374 #define CONFIG_SYS_CMA_CS2_BASE 0x10000000 /* Local Bus SDRAM */ 375 #define CONFIG_SYS_CMA_CS2_SIZE (16 << 20) 376 #endif 377 378 /* 379 * CS0 maps the EPROM on the cpu module 380 * Set it for 10 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M 381 * 382 * Note: We must have already transferred control to the final location 383 * of the EPROM before these are used, because when BR0/OR0 are set, the 384 * mirror of the eprom at any other addresses will disappear. 385 */ 386 387 /* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm (60x bus) */ 388 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BRx_BA_MSK)|BRx_PS_16|BRx_WP|BRx_V) 389 /* mask size CONFIG_SYS_CMA_CS0_SIZE, csneg 1/4 early, adr-to-cs 1/2, 10-wait states */ 390 #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_CMA_CS0_SIZE)|\ 391 ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK) 392 393 /* 394 * CS2 enables the Local Bus SDRAM on the CPU Module 395 * 396 * Will leave this unset for the moment, because a) my CPU module has no 397 * SDRAM installed (it is optional); and b) it will require programming 398 * one of the UPMs in SDRAM mode - not a trivial job, and hard to get right 399 * if you can't test it. 400 */ 401 402 #if 0 403 /* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, ??? */ 404 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BRx_BA_MSK)|BRx_PS_32|/*???*/|BRx_V) 405 /* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, ??? */ 406 #define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&ORx_AM_MSK)|/*???*/) 407 #endif 408 409 #endif 410 411 /* 412 * Internal Definitions 413 * 414 * Boot Flags 415 */ 416 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ 417 #define BOOTFLAG_WARM 0x02 /* Software reboot */ 418 419 #endif /* __CONFIG_H */ 420