1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd 4 */ 5 6 #ifndef __ASM_ARCH_CRU_RK3328_H_ 7 #define __ASM_ARCH_CRU_RK3328_H_ 8 9 #include <common.h> 10 11 struct rk3328_clk_priv { 12 struct rk3328_cru *cru; 13 ulong rate; 14 }; 15 16 struct rk3328_cru { 17 u32 apll_con[5]; 18 u32 reserved1[3]; 19 u32 dpll_con[5]; 20 u32 reserved2[3]; 21 u32 cpll_con[5]; 22 u32 reserved3[3]; 23 u32 gpll_con[5]; 24 u32 reserved4[3]; 25 u32 mode_con; 26 u32 misc; 27 u32 reserved5[2]; 28 u32 glb_cnt_th; 29 u32 glb_rst_st; 30 u32 glb_srst_snd_value; 31 u32 glb_srst_fst_value; 32 u32 npll_con[5]; 33 u32 reserved6[(0x100 - 0xb4) / 4]; 34 u32 clksel_con[53]; 35 u32 reserved7[(0x200 - 0x1d4) / 4]; 36 u32 clkgate_con[29]; 37 u32 reserved8[3]; 38 u32 ssgtbl[32]; 39 u32 softrst_con[12]; 40 u32 reserved9[(0x380 - 0x330) / 4]; 41 u32 sdmmc_con[2]; 42 u32 sdio_con[2]; 43 u32 emmc_con[2]; 44 u32 sdmmc_ext_con[2]; 45 }; 46 check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c); 47 #define MHz 1000000 48 #define KHz 1000 49 #define OSC_HZ (24 * MHz) 50 #define APLL_HZ (600 * MHz) 51 #define GPLL_HZ (576 * MHz) 52 #define CPLL_HZ (594 * MHz) 53 54 #define CLK_CORE_HZ (600 * MHz) 55 #define ACLKM_CORE_HZ (300 * MHz) 56 #define PCLK_DBG_HZ (300 * MHz) 57 58 #define PERIHP_ACLK_HZ (144000 * KHz) 59 #define PERIHP_HCLK_HZ (72000 * KHz) 60 #define PERIHP_PCLK_HZ (72000 * KHz) 61 62 #define PWM_CLOCK_HZ (74 * MHz) 63 64 enum apll_frequencies { 65 APLL_816_MHZ, 66 APLL_600_MHZ, 67 }; 68 69 #endif /* __ASM_ARCH_CRU_RK3328_H_ */ 70