1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2011 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 */ 6 #ifndef _DV_PSC_DEFS_H_ 7 #define _DV_PSC_DEFS_H_ 8 9 /* 10 * Power/Sleep Ctrl Register structure 11 * See sprufb3.pdf, Chapter 7 12 */ 13 struct dv_psc_regs { 14 unsigned int pid; /* 0x000 */ 15 unsigned char rsvd0[16]; /* 0x004 */ 16 unsigned char rsvd1[4]; /* 0x014 */ 17 unsigned int inteval; /* 0x018 */ 18 unsigned char rsvd2[36]; /* 0x01C */ 19 unsigned int merrpr0; /* 0x040 */ 20 unsigned int merrpr1; /* 0x044 */ 21 unsigned char rsvd3[8]; /* 0x048 */ 22 unsigned int merrcr0; /* 0x050 */ 23 unsigned int merrcr1; /* 0x054 */ 24 unsigned char rsvd4[8]; /* 0x058 */ 25 unsigned int perrpr; /* 0x060 */ 26 unsigned char rsvd5[4]; /* 0x064 */ 27 unsigned int perrcr; /* 0x068 */ 28 unsigned char rsvd6[4]; /* 0x06C */ 29 unsigned int epcpr; /* 0x070 */ 30 unsigned char rsvd7[4]; /* 0x074 */ 31 unsigned int epccr; /* 0x078 */ 32 unsigned char rsvd8[144]; /* 0x07C */ 33 unsigned char rsvd9[20]; /* 0x10C */ 34 unsigned int ptcmd; /* 0x120 */ 35 unsigned char rsvd10[4]; /* 0x124 */ 36 unsigned int ptstat; /* 0x128 */ 37 unsigned char rsvd11[212]; /* 0x12C */ 38 unsigned int pdstat0; /* 0x200 */ 39 unsigned int pdstat1; /* 0x204 */ 40 unsigned char rsvd12[248]; /* 0x208 */ 41 unsigned int pdctl0; /* 0x300 */ 42 unsigned int pdctl1; /* 0x304 */ 43 unsigned char rsvd13[536]; /* 0x308 */ 44 unsigned int mckout0; /* 0x520 */ 45 unsigned int mckout1; /* 0x524 */ 46 unsigned char rsvd14[728]; /* 0x528 */ 47 unsigned int mdstat[52]; /* 0x800 */ 48 unsigned char rsvd15[304]; /* 0x8D0 */ 49 unsigned int mdctl[52]; /* 0xA00 */ 50 }; 51 52 /* PSC constants */ 53 #define EMURSTIE_MASK (0x00000200) 54 55 #define PD0 (0) 56 57 #define PSC_ENABLE (0x3) 58 #define PSC_DISABLE (0x2) 59 #define PSC_SYNCRESET (0x1) 60 #define PSC_SWRSTDISABLE (0x0) 61 62 #define PSC_GOSTAT (1 << 0) 63 #define PSC_MD_STATE_MSK (0x1f) 64 65 #define PSC_CMD_GO (1 << 0) 66 67 #define dv_psc_regs ((struct dv_psc_regs *)DAVINCI_PWR_SLEEP_CNTRL_BASE) 68 69 #endif /* _DV_PSC_DEFS_H_ */ 70