1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * (C) Copyright 2016
6 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 *
8 * Based on:
9 * Board functions for TI AM335X based boards
10 *
11 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
12 */
13
14 #include <common.h>
15 #include <errno.h>
16 #include <spl.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/omap.h>
20 #include <asm/arch/ddr_defs.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h>
26 #include <asm/io.h>
27 #include <asm/emif.h>
28 #include <asm/gpio.h>
29 #include <i2c.h>
30 #include <miiphy.h>
31 #include <cpsw.h>
32 #include <power/tps65217.h>
33 #include <environment.h>
34 #include <watchdog.h>
35 #include <environment.h>
36 #include "mmc.h"
37 #include "board.h"
38
39 DECLARE_GLOBAL_DATA_PTR;
40
41 #if defined(CONFIG_SPL_BUILD) || \
42 (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
44 #endif
45 static struct shc_eeprom __attribute__((section(".data"))) header;
46 static int shc_eeprom_valid;
47
48 /*
49 * Read header information from EEPROM into global structure.
50 */
read_eeprom(void)51 static int read_eeprom(void)
52 {
53 /* Check if baseboard eeprom is available */
54 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
55 puts("Could not probe the EEPROM; something fundamentally wrong on the I2C bus.\n");
56 return -ENODEV;
57 }
58
59 /* read the eeprom using i2c */
60 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
61 sizeof(header))) {
62 puts("Could not read the EEPROM; something fundamentally wrong on the I2C bus.\n");
63 return -EIO;
64 }
65
66 if (header.magic != HDR_MAGIC) {
67 printf("Incorrect magic number (0x%x) in EEPROM\n",
68 header.magic);
69 return -EIO;
70 }
71
72 shc_eeprom_valid = 1;
73
74 return 0;
75 }
76
shc_request_gpio(void)77 static void shc_request_gpio(void)
78 {
79 gpio_request(LED_PWR_BL_GPIO, "LED PWR BL");
80 gpio_request(LED_PWR_RD_GPIO, "LED PWR RD");
81 gpio_request(RESET_GPIO, "reset");
82 gpio_request(WIFI_REGEN_GPIO, "WIFI REGEN");
83 gpio_request(WIFI_RST_GPIO, "WIFI rst");
84 gpio_request(ZIGBEE_RST_GPIO, "ZigBee rst");
85 gpio_request(BIDCOS_RST_GPIO, "BIDCOS rst");
86 gpio_request(ENOC_RST_GPIO, "ENOC rst");
87 #if defined CONFIG_B_SAMPLE
88 gpio_request(LED_PWR_GN_GPIO, "LED PWR GN");
89 gpio_request(LED_CONN_BL_GPIO, "LED CONN BL");
90 gpio_request(LED_CONN_RD_GPIO, "LED CONN RD");
91 gpio_request(LED_CONN_GN_GPIO, "LED CONN GN");
92 #else
93 gpio_request(LED_LAN_BL_GPIO, "LED LAN BL");
94 gpio_request(LED_LAN_RD_GPIO, "LED LAN RD");
95 gpio_request(LED_CLOUD_BL_GPIO, "LED CLOUD BL");
96 gpio_request(LED_CLOUD_RD_GPIO, "LED CLOUD RD");
97 gpio_request(LED_PWM_GPIO, "LED PWM");
98 gpio_request(Z_WAVE_RST_GPIO, "Z WAVE rst");
99 #endif
100 gpio_request(BACK_BUTTON_GPIO, "Back button");
101 gpio_request(FRONT_BUTTON_GPIO, "Front button");
102 }
103
104 /*
105 * Function which forces all installed modules into running state for ICT
106 * testing. Called by SPL.
107 */
force_modules_running(void)108 static void __maybe_unused force_modules_running(void)
109 {
110 /* Wi-Fi power regulator enable - high = enabled */
111 gpio_direction_output(WIFI_REGEN_GPIO, 1);
112 /*
113 * Wait for Wi-Fi power regulator to reach a stable voltage
114 * (soft-start time, max. 350 µs)
115 */
116 __udelay(350);
117
118 /* Wi-Fi module reset - high = running */
119 gpio_direction_output(WIFI_RST_GPIO, 1);
120
121 /* ZigBee reset - high = running */
122 gpio_direction_output(ZIGBEE_RST_GPIO, 1);
123
124 /* BidCos reset - high = running */
125 gpio_direction_output(BIDCOS_RST_GPIO, 1);
126
127 #if !defined(CONFIG_B_SAMPLE)
128 /* Z-Wave reset - high = running */
129 gpio_direction_output(Z_WAVE_RST_GPIO, 1);
130 #endif
131
132 /* EnOcean reset - low = running */
133 gpio_direction_output(ENOC_RST_GPIO, 0);
134 }
135
136 /*
137 * Function which forces all installed modules into reset - to be released by
138 * the OS, called by SPL
139 */
force_modules_reset(void)140 static void __maybe_unused force_modules_reset(void)
141 {
142 /* Wi-Fi module reset - low = reset */
143 gpio_direction_output(WIFI_RST_GPIO, 0);
144
145 /* Wi-Fi power regulator enable - low = disabled */
146 gpio_direction_output(WIFI_REGEN_GPIO, 0);
147
148 /* ZigBee reset - low = reset */
149 gpio_direction_output(ZIGBEE_RST_GPIO, 0);
150
151 /* BidCos reset - low = reset */
152 /*gpio_direction_output(BIDCOS_RST_GPIO, 0);*/
153
154 #if !defined(CONFIG_B_SAMPLE)
155 /* Z-Wave reset - low = reset */
156 gpio_direction_output(Z_WAVE_RST_GPIO, 0);
157 #endif
158
159 /* EnOcean reset - high = reset*/
160 gpio_direction_output(ENOC_RST_GPIO, 1);
161 }
162
163 /*
164 * Function to set the LEDs in the state "Bootloader booting"
165 */
leds_set_booting(void)166 static void __maybe_unused leds_set_booting(void)
167 {
168 #if defined(CONFIG_B_SAMPLE)
169
170 /* Turn all red LEDs on */
171 gpio_direction_output(LED_PWR_RD_GPIO, 1);
172 gpio_direction_output(LED_CONN_RD_GPIO, 1);
173
174 #else /* All other SHCs starting with B2-Sample */
175 /* Set the PWM GPIO */
176 gpio_direction_output(LED_PWM_GPIO, 1);
177 /* Turn all red LEDs on */
178 gpio_direction_output(LED_PWR_RD_GPIO, 1);
179 gpio_direction_output(LED_LAN_RD_GPIO, 1);
180 gpio_direction_output(LED_CLOUD_RD_GPIO, 1);
181
182 #endif
183 }
184
185 /*
186 * Function to set the LEDs in the state "Bootloader error"
187 */
leds_set_failure(int state)188 static void leds_set_failure(int state)
189 {
190 #if defined(CONFIG_B_SAMPLE)
191 /* Turn all blue and green LEDs off */
192 gpio_set_value(LED_PWR_BL_GPIO, 0);
193 gpio_set_value(LED_PWR_GN_GPIO, 0);
194 gpio_set_value(LED_CONN_BL_GPIO, 0);
195 gpio_set_value(LED_CONN_GN_GPIO, 0);
196
197 /* Turn all red LEDs to 'state' */
198 gpio_set_value(LED_PWR_RD_GPIO, state);
199 gpio_set_value(LED_CONN_RD_GPIO, state);
200
201 #else /* All other SHCs starting with B2-Sample */
202 /* Set the PWM GPIO */
203 gpio_direction_output(LED_PWM_GPIO, 1);
204
205 /* Turn all blue LEDs off */
206 gpio_set_value(LED_PWR_BL_GPIO, 0);
207 gpio_set_value(LED_LAN_BL_GPIO, 0);
208 gpio_set_value(LED_CLOUD_BL_GPIO, 0);
209
210 /* Turn all red LEDs to 'state' */
211 gpio_set_value(LED_PWR_RD_GPIO, state);
212 gpio_set_value(LED_LAN_RD_GPIO, state);
213 gpio_set_value(LED_CLOUD_RD_GPIO, state);
214 #endif
215 }
216
217 /*
218 * Function to set the LEDs in the state "Bootloader finished"
219 */
leds_set_finish(void)220 static void leds_set_finish(void)
221 {
222 #if defined(CONFIG_B_SAMPLE)
223 /* Turn all LEDs off */
224 gpio_set_value(LED_PWR_BL_GPIO, 0);
225 gpio_set_value(LED_PWR_RD_GPIO, 0);
226 gpio_set_value(LED_PWR_GN_GPIO, 0);
227 gpio_set_value(LED_CONN_BL_GPIO, 0);
228 gpio_set_value(LED_CONN_RD_GPIO, 0);
229 gpio_set_value(LED_CONN_GN_GPIO, 0);
230 #else /* All other SHCs starting with B2-Sample */
231 /* Turn all LEDs off */
232 gpio_set_value(LED_PWR_BL_GPIO, 0);
233 gpio_set_value(LED_PWR_RD_GPIO, 0);
234 gpio_set_value(LED_LAN_BL_GPIO, 0);
235 gpio_set_value(LED_LAN_RD_GPIO, 0);
236 gpio_set_value(LED_CLOUD_BL_GPIO, 0);
237 gpio_set_value(LED_CLOUD_RD_GPIO, 0);
238
239 /* Turn off the PWM GPIO and mux it to EHRPWM */
240 gpio_set_value(LED_PWM_GPIO, 0);
241 enable_shc_board_pwm_pin_mux();
242 #endif
243 }
244
check_button_status(void)245 static void check_button_status(void)
246 {
247 ulong value;
248 gpio_direction_input(FRONT_BUTTON_GPIO);
249 value = gpio_get_value(FRONT_BUTTON_GPIO);
250
251 if (value == 0) {
252 printf("front button activated !\n");
253 env_set("harakiri", "1");
254 }
255 }
256
257 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
258 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)259 int spl_start_uboot(void)
260 {
261 return 1;
262 }
263 #endif
264
shc_board_early_init(void)265 static void shc_board_early_init(void)
266 {
267 shc_request_gpio();
268 # ifdef CONFIG_SHC_ICT
269 /* Force all modules into enabled state for ICT testing */
270 force_modules_running();
271 # else
272 /* Force all modules to enter Reset state until released by the OS */
273 force_modules_reset();
274 # endif
275 leds_set_booting();
276 }
277
278 #define MPU_SPREADING_PERMILLE 18 /* Spread 1.8 percent */
279 #define OSC (V_OSCK/1000000)
280 /* Bosch: Predivider must be fixed to 4, so N = 4-1 */
281 #define MPUPLL_N (4-1)
282 /* Bosch: Fref = 24 MHz / (N+1) = 24 MHz / 4 = 6 MHz */
283 #define MPUPLL_FREF (OSC / (MPUPLL_N + 1))
284
285 const struct dpll_params dpll_ddr_shc = {
286 400, OSC-1, 1, -1, -1, -1, -1};
287
get_dpll_ddr_params(void)288 const struct dpll_params *get_dpll_ddr_params(void)
289 {
290 return &dpll_ddr_shc;
291 }
292
293 /*
294 * As we enabled downspread SSC with 1.8%, the values needed to be corrected
295 * such that the 20% overshoot will not lead to too high frequencies.
296 * In all cases, this is achieved by subtracting one from M (6 MHz less).
297 * Example: 600 MHz CPU
298 * Step size: 24 MHz OSC, N = 4 (fix) --> Fref = 6 MHz
299 * 600 MHz - 6 MHz (1x Fref) = 594 MHz
300 * SSC: 594 MHz * 1.8% = 10.7 MHz SSC
301 * Overshoot: 10.7 MHz * 20 % = 2.2 MHz
302 * --> Fmax = 594 MHz + 2.2 MHz = 596.2 MHz, lower than 600 MHz --> OK!
303 */
304 const struct dpll_params dpll_mpu_shc_opp100 = {
305 99, MPUPLL_N, 1, -1, -1, -1, -1};
306
am33xx_spl_board_init(void)307 void am33xx_spl_board_init(void)
308 {
309 int sil_rev;
310 int mpu_vdd;
311
312 puts(BOARD_ID_STR);
313
314 /*
315 * Set CORE Frequency to OPP100
316 * Hint: DCDC3 (CORE) defaults to 1.100V (for OPP100)
317 */
318 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
319
320 sil_rev = readl(&cdev->deviceid) >> 28;
321 if (sil_rev < 2) {
322 puts("We do not support Silicon Revisions below 2.0!\n");
323 return;
324 }
325
326 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
327 if (i2c_probe(TPS65217_CHIP_PM))
328 return;
329
330 /*
331 * Retrieve the CPU max frequency by reading the efuse
332 * SHC-Default: 600 MHz
333 */
334 switch (dpll_mpu_opp100.m) {
335 case MPUPLL_M_1000:
336 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
337 break;
338 case MPUPLL_M_800:
339 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
340 break;
341 case MPUPLL_M_720:
342 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1200MV;
343 break;
344 case MPUPLL_M_600:
345 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1100MV;
346 break;
347 case MPUPLL_M_300:
348 mpu_vdd = TPS65217_DCDC_VOLT_SEL_950MV;
349 break;
350 default:
351 puts("Cannot determine the frequency, failing!\n");
352 return;
353 }
354
355 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
356 puts("tps65217_voltage_update failure\n");
357 return;
358 }
359
360 /* Set MPU Frequency to what we detected */
361 printf("MPU reference clock runs at %d MHz\n", MPUPLL_FREF);
362 printf("Setting MPU clock to %d MHz\n", MPUPLL_FREF *
363 dpll_mpu_shc_opp100.m);
364 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_shc_opp100);
365
366 /* Enable Spread Spectrum for this freq to be clean on EMI side */
367 set_mpu_spreadspectrum(MPU_SPREADING_PERMILLE);
368
369 /*
370 * Using the default voltages for the PMIC (TPS65217D)
371 * LS1 = 1.8V (VDD_1V8)
372 * LS2 = 3.3V (VDD_3V3A)
373 * LDO1 = 1.8V (VIO and VRTC)
374 * LDO2 = 3.3V (VDD_3V3AUX)
375 */
376 shc_board_early_init();
377 }
378
set_uart_mux_conf(void)379 void set_uart_mux_conf(void)
380 {
381 enable_uart0_pin_mux();
382 }
383
set_mux_conf_regs(void)384 void set_mux_conf_regs(void)
385 {
386 enable_shc_board_pin_mux();
387 }
388
389 const struct ctrl_ioregs ioregs_evmsk = {
390 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
391 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
392 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
393 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
394 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
395 };
396
397 static const struct ddr_data ddr3_shc_data = {
398 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
399 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
400 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
401 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
402 };
403
404 static const struct cmd_control ddr3_shc_cmd_ctrl_data = {
405 .cmd0csratio = MT41K256M16HA125E_RATIO,
406 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
407
408 .cmd1csratio = MT41K256M16HA125E_RATIO,
409 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
410
411 .cmd2csratio = MT41K256M16HA125E_RATIO,
412 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
413 };
414
415 static struct emif_regs ddr3_shc_emif_reg_data = {
416 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
417 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
418 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
419 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
420 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
421 .zq_config = MT41K256M16HA125E_ZQ_CFG,
422 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
423 PHY_EN_DYN_PWRDN,
424 };
425
sdram_init(void)426 void sdram_init(void)
427 {
428 /* Configure the DDR3 RAM */
429 config_ddr(400, &ioregs_evmsk, &ddr3_shc_data,
430 &ddr3_shc_cmd_ctrl_data, &ddr3_shc_emif_reg_data, 0);
431 }
432 #endif
433
434 /*
435 * Basic board specific setup. Pinmux has been handled already.
436 */
board_init(void)437 int board_init(void)
438 {
439 #if defined(CONFIG_HW_WATCHDOG)
440 hw_watchdog_init();
441 #endif
442 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
443 if (read_eeprom() < 0)
444 puts("EEPROM Content Invalid.\n");
445
446 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
447 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
448 gpmc_init();
449 #endif
450 shc_request_gpio();
451
452 return 0;
453 }
454
455 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)456 int board_late_init(void)
457 {
458 check_button_status();
459 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
460 if (shc_eeprom_valid)
461 if (is_valid_ethaddr(header.mac_addr))
462 eth_env_set_enetaddr("ethaddr", header.mac_addr);
463 #endif
464
465 return 0;
466 }
467 #endif
468
469 #ifndef CONFIG_DM_ETH
470 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
471 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
cpsw_control(int enabled)472 static void cpsw_control(int enabled)
473 {
474 /* VTP can be added here */
475
476 return;
477 }
478
479 static struct cpsw_slave_data cpsw_slaves[] = {
480 {
481 .slave_reg_ofs = 0x208,
482 .sliver_reg_ofs = 0xd80,
483 .phy_addr = 0,
484 },
485 {
486 .slave_reg_ofs = 0x308,
487 .sliver_reg_ofs = 0xdc0,
488 .phy_addr = 1,
489 },
490 };
491
492 static struct cpsw_platform_data cpsw_data = {
493 .mdio_base = CPSW_MDIO_BASE,
494 .cpsw_base = CPSW_BASE,
495 .mdio_div = 0xff,
496 .channels = 8,
497 .cpdma_reg_ofs = 0x800,
498 .slaves = 1,
499 .slave_data = cpsw_slaves,
500 .ale_reg_ofs = 0xd00,
501 .ale_entries = 1024,
502 .host_port_reg_ofs = 0x108,
503 .hw_stats_reg_ofs = 0x900,
504 .bd_ram_ofs = 0x2000,
505 .mac_control = (1 << 5),
506 .control = cpsw_control,
507 .host_port_num = 0,
508 .version = CPSW_CTRL_VERSION_2,
509 };
510 #endif
511
512 /*
513 * This function will:
514 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
515 * in the environment
516 * Perform fixups to the PHY present on certain boards. We only need this
517 * function in:
518 * - SPL with either CPSW or USB ethernet support
519 * - Full U-Boot, with either CPSW or USB ethernet
520 * Build in only these cases to avoid warnings about unused variables
521 * when we build an SPL that has neither option but full U-Boot will.
522 */
523 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || \
524 defined(CONFIG_SPL_USB_ETHER)) && \
525 defined(CONFIG_SPL_BUILD)) || \
526 ((defined(CONFIG_DRIVER_TI_CPSW) || \
527 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
528 !defined(CONFIG_SPL_BUILD))
board_eth_init(bd_t * bis)529 int board_eth_init(bd_t *bis)
530 {
531 int rv, n = 0;
532 uint8_t mac_addr[6];
533 uint32_t mac_hi, mac_lo;
534
535 /* try reading mac address from efuse */
536 mac_lo = readl(&cdev->macid0l);
537 mac_hi = readl(&cdev->macid0h);
538 mac_addr[0] = mac_hi & 0xFF;
539 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
540 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
541 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
542 mac_addr[4] = mac_lo & 0xFF;
543 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
544
545 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
546 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
547 if (!env_get("ethaddr")) {
548 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
549
550 if (is_valid_ethaddr(mac_addr))
551 eth_env_set_enetaddr("ethaddr", mac_addr);
552 }
553
554 writel(MII_MODE_ENABLE, &cdev->miisel);
555 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
556 cpsw_slaves[1].phy_if = cpsw_slaves[0].phy_if;
557 rv = cpsw_register(&cpsw_data);
558 if (rv < 0)
559 printf("Error %d registering CPSW switch\n", rv);
560 else
561 n += rv;
562 #endif
563
564 #if defined(CONFIG_USB_ETHER) && \
565 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
566 if (is_valid_ethaddr(mac_addr))
567 eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
568
569 rv = usb_eth_initialize(bis);
570 if (rv < 0)
571 printf("Error %d registering USB_ETHER\n", rv);
572 else
573 n += rv;
574 #endif
575 return n;
576 }
577 #endif
578
579 #endif /* CONFIG_DM_ETH */
580
581 #ifdef CONFIG_SHOW_BOOT_PROGRESS
bosch_check_reset_pin(void)582 static void bosch_check_reset_pin(void)
583 {
584 if (readl(GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0) & RESET_MASK) {
585 printf("Resetting ...\n");
586 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
587 disable_interrupts();
588 reset_cpu(0);
589 /*NOTREACHED*/
590 }
591 }
592
hang_bosch(const char * cause,int code)593 static void hang_bosch(const char *cause, int code)
594 {
595 int lv;
596
597 gpio_direction_input(RESET_GPIO);
598
599 /* Enable reset pin interrupt on falling edge */
600 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
601 writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_FALLINGDETECT);
602 enable_interrupts();
603
604 puts(cause);
605 for (;;) {
606 for (lv = 0; lv < code; lv++) {
607 bosch_check_reset_pin();
608 leds_set_failure(1);
609 __udelay(150 * 1000);
610 leds_set_failure(0);
611 __udelay(150 * 1000);
612 }
613 #if defined(BLINK_CODE)
614 __udelay(300 * 1000);
615 #endif
616 }
617 }
618
show_boot_progress(int val)619 void show_boot_progress(int val)
620 {
621 switch (val) {
622 case BOOTSTAGE_ID_NEED_RESET:
623 hang_bosch("need reset", 4);
624 break;
625 }
626 }
627 #endif
628
arch_preboot_os(void)629 void arch_preboot_os(void)
630 {
631 leds_set_finish();
632 }
633
634 #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)635 int board_mmc_init(bd_t *bis)
636 {
637 int ret;
638
639 /* Bosch: Do not enable 52MHz for eMMC device to avoid EMI */
640 ret = omap_mmc_init(0, MMC_MODE_HS_52MHz, 26000000, -1, -1);
641 if (ret)
642 return ret;
643
644 ret = omap_mmc_init(1, MMC_MODE_HS_52MHz, 26000000, -1, -1);
645 return ret;
646 }
647 #endif
648