1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * (C) Copyright 2006-2008
4 * Texas Instruments.
5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Syed Mohammed Khasim <x0khasim@ti.com>
7 *
8 * (C) Copyright 2012
9 * Corscience GmbH & Co. KG
10 * Thomas Weber <weber@corscience.de>
11 *
12 * Configuration settings for the Tricorder board.
13 */
14
15 #ifndef __CONFIG_H
16 #define __CONFIG_H
17
18 #define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER
19 /*
20 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
21 * 64 bytes before this address should be set aside for u-boot.img's
22 * header. That is 0x800FFFC0--0x80100000 should not be used for any
23 * other needs.
24 */
25
26 #include <asm/arch/cpu.h> /* get chip and board defs */
27 #include <asm/arch/omap.h>
28
29 /* Clock Defines */
30 #define V_OSCK 26000000 /* Clock output from T2 */
31 #define V_SCLK (V_OSCK >> 1)
32
33 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
34 #define CONFIG_SETUP_MEMORY_TAGS
35 #define CONFIG_INITRD_TAG
36 #define CONFIG_REVISION_TAG
37
38 /* Size of malloc() pool */
39 #define CONFIG_SYS_MALLOC_LEN (1024*1024)
40
41 /* Hardware drivers */
42
43 /* NS16550 Configuration */
44 #define CONFIG_SYS_NS16550_SERIAL
nsObjCExceptionLog(NSException * aException)45 #define CONFIG_SYS_NS16550_REG_SIZE (-4)
46 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
47
48 /* select serial console configuration */
49 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
50 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
51 115200}
52
53 /* I2C */
54 #define CONFIG_SYS_I2C
55
56
57 /* EEPROM */
58 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
59 #define CONFIG_SYS_EEPROM_BUS_NUM 1
60
61 /* TWL4030 */
62
63 /* Board NAND Info */
64 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
65 /* to access nand at */
66 /* CS0 */
67 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
68 /* devices */
69 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
70 #define CONFIG_SYS_NAND_MAX_ECCPOS 56
71
72 /* needed for ubi */
73
74 /* Environment information (this is the common part) */
75
76
77 /* hang() the board on panic() */
78
79 /* environment placement (for NAND), is different for FLASHCARD but does not
80 * harm there */
81 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
82 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
83 #define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */
84 #define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */
85
86 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
87 * value can not be used here! */
88 #define CONFIG_LOADADDR 0x82000000
89
90 #define CONFIG_COMMON_ENV_SETTINGS \
91 "console=ttyO2,115200n8\0" \
92 "mmcdev=0\0" \
93 "vram=3M\0" \
94 "defaultdisplay=lcd\0" \
95 "kernelopts=mtdoops.mtddev=3\0" \
96 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
97 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
98 "commonargs=" \
99 "setenv bootargs console=${console} " \
100 "${mtdparts} " \
101 "${kernelopts} " \
102 "vt.global_cursor_default=0 " \
103 "vram=${vram} " \
104 "omapdss.def_disp=${defaultdisplay}\0"
105
106 #define CONFIG_BOOTCOMMAND "run autoboot"
107
108 /* specific environment settings for different use cases
109 * FLASHCARD: used to run a rdimage from sdcard to program the device
110 * 'NORMAL': used to boot kernel from sdcard, nand, ...
111 *
112 * The main aim for the FLASHCARD skin is to have an embedded environment
113 * which will not be influenced by any data already on the device.
114 */
115 #ifdef CONFIG_FLASHCARD
116 /* the rdaddr is 16 MiB before the loadaddr */
117 #define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0"
118
119 #define CONFIG_EXTRA_ENV_SETTINGS \
120 CONFIG_COMMON_ENV_SETTINGS \
121 CONFIG_ENV_RDADDR \
122 "autoboot=" \
123 "run commonargs; " \
124 "setenv bootargs ${bootargs} " \
125 "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \
126 "rdinit=/sbin/init; " \
127 "mmc dev ${mmcdev}; mmc rescan; " \
128 "fatload mmc ${mmcdev} ${loadaddr} uImage; " \
129 "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \
130 "bootm ${loadaddr} ${rdaddr}\0"
131
132 #else /* CONFIG_FLASHCARD */
133
134 #define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
135
nsObjCExceptionAbort()136 #define CONFIG_EXTRA_ENV_SETTINGS \
137 CONFIG_COMMON_ENV_SETTINGS \
138 "mmcargs=" \
139 "run commonargs; " \
140 "setenv bootargs ${bootargs} " \
141 "root=/dev/mmcblk0p2 " \
142 "rootwait " \
143 "rw\0" \
144 "nandargs=" \
145 "run commonargs; " \
146 "setenv bootargs ${bootargs} " \
147 "root=ubi0:root " \
148 "ubi.mtd=7 " \
149 "rootfstype=ubifs " \
150 "ro\0" \
151 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
152 "bootscript=echo Running bootscript from mmc ...; " \
153 "source ${loadaddr}\0" \
154 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
155 "mmcboot=echo Booting from mmc ...; " \
156 "run mmcargs; " \
157 "bootm ${loadaddr}\0" \
158 "loaduimage_ubi=ubi part ubi; " \
159 "ubifsmount ubi:root; " \
160 "ubifsload ${loadaddr} /boot/uImage\0" \
161 "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \
162 "nandboot=echo Booting from nand ...; " \
163 "run nandargs; " \
164 "run loaduimage_nand; " \
165 "bootm ${loadaddr}\0" \
166 "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
167 "if run loadbootscript; then " \
168 "run bootscript; " \
169 "else " \
170 "if run loaduimage; then " \
171 "run mmcboot; " \
172 "else run nandboot; " \
173 "fi; " \
174 "fi; " \
175 "else run nandboot; fi\0"
176
177 #endif /* CONFIG_FLASHCARD */
178
179 /* Miscellaneous configurable options */
180 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
181
182 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000)
183 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
184 0x07000000) /* 112 MB */
185
186 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
187
188 /*
189 * OMAP3 has 12 GP timers, they can be driven by the system clock
190 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
191 * This rate is divided by a local divisor.
192 */
193 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
194 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
195
196 /* Physical Memory Map */
197 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
198 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
199
200 /* NAND and environment organization */
201 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
202
203 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
204 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
205 #define CONFIG_SYS_INIT_RAM_SIZE 0x800
206 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
207 CONFIG_SYS_INIT_RAM_SIZE - \
208 GENERATED_GBL_DATA_SIZE)
209
210 /* SRAM config */
211 #define CONFIG_SYS_SRAM_START 0x40200000
212 #define CONFIG_SYS_SRAM_SIZE 0x10000
213
214 /* Defines for SPL */
215
216 #define CONFIG_SPL_NAND_BASE
217 #define CONFIG_SPL_NAND_DRIVERS
218 #define CONFIG_SPL_NAND_ECC
219 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
220 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
221
222 #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
223 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
224 CONFIG_SPL_TEXT_BASE)
225
226 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
227 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
228
229 /* NAND boot config */
230 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
231 #define CONFIG_SYS_NAND_PAGE_COUNT 64
232 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
233 #define CONFIG_SYS_NAND_OOBSIZE 64
234 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
235 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
236 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
237 13, 14, 16, 17, 18, 19, 20, 21, 22, \
238 23, 24, 25, 26, 27, 28, 30, 31, 32, \
239 33, 34, 35, 36, 37, 38, 39, 40, 41, \
240 42, 44, 45, 46, 47, 48, 49, 50, 51, \
241 52, 53, 54, 55, 56}
242
243 #define CONFIG_SYS_NAND_ECCSIZE 512
244 #define CONFIG_SYS_NAND_ECCBYTES 13
245 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
246
247 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
248
249 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
250 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000
251
252 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
253 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
254
255 #define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000
256 #endif /* __CONFIG_H */
257