1 /*
2 * sPAPR CPU core device, acts as container of CPU thread devices.
3 *
4 * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or later.
7 * See the COPYING file in the top-level directory.
8 */
9 #include "qemu/osdep.h"
10 #include "hw/cpu/core.h"
11 #include "hw/ppc/spapr_cpu_core.h"
12 #include "target/ppc/cpu.h"
13 #include "hw/ppc/spapr.h"
14 #include "hw/boards.h"
15 #include "qapi/error.h"
16 #include "sysemu/cpus.h"
17 #include "sysemu/kvm.h"
18 #include "target/ppc/kvm_ppc.h"
19 #include "hw/ppc/ppc.h"
20 #include "target/ppc/mmu-hash64.h"
21 #include "sysemu/numa.h"
22 #include "sysemu/hw_accel.h"
23 #include "qemu/error-report.h"
24
spapr_cpu_reset(void * opaque)25 static void spapr_cpu_reset(void *opaque)
26 {
27 PowerPCCPU *cpu = opaque;
28 CPUState *cs = CPU(cpu);
29 CPUPPCState *env = &cpu->env;
30 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
31 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
32 target_ulong lpcr;
33
34 cpu_reset(cs);
35
36 /* All CPUs start halted. CPU0 is unhalted from the machine level
37 * reset code and the rest are explicitly started up by the guest
38 * using an RTAS call */
39 cs->halted = 1;
40
41 /* Set compatibility mode to match the boot CPU, which was either set
42 * by the machine reset code or by CAS. This should never fail.
43 */
44 ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, &error_abort);
45
46 env->spr[SPR_HIOR] = 0;
47
48 lpcr = env->spr[SPR_LPCR];
49
50 /* Set emulated LPCR to not send interrupts to hypervisor. Note that
51 * under KVM, the actual HW LPCR will be set differently by KVM itself,
52 * the settings below ensure proper operations with TCG in absence of
53 * a real hypervisor.
54 *
55 * Clearing VPM0 will also cause us to use RMOR in mmu-hash64.c for
56 * real mode accesses, which thankfully defaults to 0 and isn't
57 * accessible in guest mode.
58 *
59 * Disable Power-saving mode Exit Cause exceptions for the CPU, so
60 * we don't get spurious wakups before an RTAS start-cpu call.
61 */
62 lpcr &= ~(LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
63 lpcr |= LPCR_LPES0 | LPCR_LPES1;
64
65 /* Set RMLS to the max (ie, 16G) */
66 lpcr &= ~LPCR_RMLS;
67 lpcr |= 1ull << LPCR_RMLS_SHIFT;
68
69 ppc_store_lpcr(cpu, lpcr);
70
71 /* Set PSSCR:EC so that we don't wake up spuriously on POWER9 */
72 env->spr[SPR_PSSCR] = PSSCR_EC;
73
74 /* Set a full AMOR so guest can use the AMR as it sees fit */
75 env->spr[SPR_AMOR] = 0xffffffffffffffffull;
76
77 spapr_cpu->vpa_addr = 0;
78 spapr_cpu->slb_shadow_addr = 0;
79 spapr_cpu->slb_shadow_size = 0;
80 spapr_cpu->dtl_addr = 0;
81 spapr_cpu->dtl_size = 0;
82
83 spapr_caps_cpu_apply(SPAPR_MACHINE(qdev_get_machine()), cpu);
84
85 kvm_check_mmu(cpu, &error_fatal);
86 }
87
spapr_cpu_set_entry_state(PowerPCCPU * cpu,target_ulong nip,target_ulong r3)88 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip, target_ulong r3)
89 {
90 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
91 CPUPPCState *env = &cpu->env;
92
93 env->nip = nip;
94 env->gpr[3] = r3;
95 kvmppc_set_reg_ppc_online(cpu, 1);
96 CPU(cpu)->halted = 0;
97 /* Enable Power-saving mode Exit Cause exceptions */
98 ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
99 }
100
101 /*
102 * Return the sPAPR CPU core type for @model which essentially is the CPU
103 * model specified with -cpu cmdline option.
104 */
spapr_get_cpu_core_type(const char * cpu_type)105 const char *spapr_get_cpu_core_type(const char *cpu_type)
106 {
107 int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
108 char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
109 len, cpu_type);
110 ObjectClass *oc = object_class_by_name(core_type);
111
112 g_free(core_type);
113 if (!oc) {
114 return NULL;
115 }
116
117 return object_class_get_name(oc);
118 }
119
slb_shadow_needed(void * opaque)120 static bool slb_shadow_needed(void *opaque)
121 {
122 sPAPRCPUState *spapr_cpu = opaque;
123
124 return spapr_cpu->slb_shadow_addr != 0;
125 }
126
127 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
128 .name = "spapr_cpu/vpa/slb_shadow",
129 .version_id = 1,
130 .minimum_version_id = 1,
131 .needed = slb_shadow_needed,
132 .fields = (VMStateField[]) {
133 VMSTATE_UINT64(slb_shadow_addr, sPAPRCPUState),
134 VMSTATE_UINT64(slb_shadow_size, sPAPRCPUState),
135 VMSTATE_END_OF_LIST()
136 }
137 };
138
dtl_needed(void * opaque)139 static bool dtl_needed(void *opaque)
140 {
141 sPAPRCPUState *spapr_cpu = opaque;
142
143 return spapr_cpu->dtl_addr != 0;
144 }
145
146 static const VMStateDescription vmstate_spapr_cpu_dtl = {
147 .name = "spapr_cpu/vpa/dtl",
148 .version_id = 1,
149 .minimum_version_id = 1,
150 .needed = dtl_needed,
151 .fields = (VMStateField[]) {
152 VMSTATE_UINT64(dtl_addr, sPAPRCPUState),
153 VMSTATE_UINT64(dtl_size, sPAPRCPUState),
154 VMSTATE_END_OF_LIST()
155 }
156 };
157
vpa_needed(void * opaque)158 static bool vpa_needed(void *opaque)
159 {
160 sPAPRCPUState *spapr_cpu = opaque;
161
162 return spapr_cpu->vpa_addr != 0;
163 }
164
165 static const VMStateDescription vmstate_spapr_cpu_vpa = {
166 .name = "spapr_cpu/vpa",
167 .version_id = 1,
168 .minimum_version_id = 1,
169 .needed = vpa_needed,
170 .fields = (VMStateField[]) {
171 VMSTATE_UINT64(vpa_addr, sPAPRCPUState),
172 VMSTATE_END_OF_LIST()
173 },
174 .subsections = (const VMStateDescription * []) {
175 &vmstate_spapr_cpu_slb_shadow,
176 &vmstate_spapr_cpu_dtl,
177 NULL
178 }
179 };
180
181 static const VMStateDescription vmstate_spapr_cpu_state = {
182 .name = "spapr_cpu",
183 .version_id = 1,
184 .minimum_version_id = 1,
185 .fields = (VMStateField[]) {
186 VMSTATE_END_OF_LIST()
187 },
188 .subsections = (const VMStateDescription * []) {
189 &vmstate_spapr_cpu_vpa,
190 NULL
191 }
192 };
193
spapr_unrealize_vcpu(PowerPCCPU * cpu,sPAPRCPUCore * sc)194 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
195 {
196 if (!sc->pre_3_0_migration) {
197 vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
198 }
199 qemu_unregister_reset(spapr_cpu_reset, cpu);
200 object_unparent(cpu->intc);
201 cpu_remove_sync(CPU(cpu));
202 object_unparent(OBJECT(cpu));
203 }
204
spapr_cpu_core_unrealize(DeviceState * dev,Error ** errp)205 static void spapr_cpu_core_unrealize(DeviceState *dev, Error **errp)
206 {
207 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
208 CPUCore *cc = CPU_CORE(dev);
209 int i;
210
211 for (i = 0; i < cc->nr_threads; i++) {
212 spapr_unrealize_vcpu(sc->threads[i], sc);
213 }
214 g_free(sc->threads);
215 }
216
spapr_realize_vcpu(PowerPCCPU * cpu,sPAPRMachineState * spapr,sPAPRCPUCore * sc,Error ** errp)217 static void spapr_realize_vcpu(PowerPCCPU *cpu, sPAPRMachineState *spapr,
218 sPAPRCPUCore *sc, Error **errp)
219 {
220 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr);
221 CPUPPCState *env = &cpu->env;
222 CPUState *cs = CPU(cpu);
223 Error *local_err = NULL;
224
225 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err);
226 if (local_err) {
227 goto error;
228 }
229
230 /* Set time-base frequency to 512 MHz */
231 cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
232
233 cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
234 kvmppc_set_papr(cpu);
235
236 qemu_register_reset(spapr_cpu_reset, cpu);
237 spapr_cpu_reset(cpu);
238
239 cpu->intc = smc->irq->cpu_intc_create(spapr, OBJECT(cpu), &local_err);
240 if (local_err) {
241 goto error_unregister;
242 }
243
244 if (!sc->pre_3_0_migration) {
245 vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
246 cpu->machine_data);
247 }
248
249 return;
250
251 error_unregister:
252 qemu_unregister_reset(spapr_cpu_reset, cpu);
253 cpu_remove_sync(CPU(cpu));
254 error:
255 error_propagate(errp, local_err);
256 }
257
spapr_create_vcpu(sPAPRCPUCore * sc,int i,Error ** errp)258 static PowerPCCPU *spapr_create_vcpu(sPAPRCPUCore *sc, int i, Error **errp)
259 {
260 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
261 CPUCore *cc = CPU_CORE(sc);
262 Object *obj;
263 char *id;
264 CPUState *cs;
265 PowerPCCPU *cpu;
266 Error *local_err = NULL;
267
268 obj = object_new(scc->cpu_type);
269
270 cs = CPU(obj);
271 cpu = POWERPC_CPU(obj);
272 cs->cpu_index = cc->core_id + i;
273 spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
274 if (local_err) {
275 goto err;
276 }
277
278 cpu->node_id = sc->node_id;
279
280 id = g_strdup_printf("thread[%d]", i);
281 object_property_add_child(OBJECT(sc), id, obj, &local_err);
282 g_free(id);
283 if (local_err) {
284 goto err;
285 }
286
287 cpu->machine_data = g_new0(sPAPRCPUState, 1);
288
289 object_unref(obj);
290 return cpu;
291
292 err:
293 object_unref(obj);
294 error_propagate(errp, local_err);
295 return NULL;
296 }
297
spapr_delete_vcpu(PowerPCCPU * cpu,sPAPRCPUCore * sc)298 static void spapr_delete_vcpu(PowerPCCPU *cpu, sPAPRCPUCore *sc)
299 {
300 sPAPRCPUState *spapr_cpu = spapr_cpu_state(cpu);
301
302 cpu->machine_data = NULL;
303 g_free(spapr_cpu);
304 object_unparent(OBJECT(cpu));
305 }
306
spapr_cpu_core_realize(DeviceState * dev,Error ** errp)307 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
308 {
309 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
310 * tries to add a sPAPR CPU core to a non-pseries machine.
311 */
312 sPAPRMachineState *spapr =
313 (sPAPRMachineState *) object_dynamic_cast(qdev_get_machine(),
314 TYPE_SPAPR_MACHINE);
315 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
316 CPUCore *cc = CPU_CORE(OBJECT(dev));
317 Error *local_err = NULL;
318 int i, j;
319
320 if (!spapr) {
321 error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
322 return;
323 }
324
325 sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
326 for (i = 0; i < cc->nr_threads; i++) {
327 sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
328 if (local_err) {
329 goto err;
330 }
331 }
332
333 for (j = 0; j < cc->nr_threads; j++) {
334 spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
335 if (local_err) {
336 goto err_unrealize;
337 }
338 }
339 return;
340
341 err_unrealize:
342 while (--j >= 0) {
343 spapr_unrealize_vcpu(sc->threads[j], sc);
344 }
345 err:
346 while (--i >= 0) {
347 spapr_delete_vcpu(sc->threads[i], sc);
348 }
349 g_free(sc->threads);
350 error_propagate(errp, local_err);
351 }
352
353 static Property spapr_cpu_core_properties[] = {
354 DEFINE_PROP_INT32("node-id", sPAPRCPUCore, node_id, CPU_UNSET_NUMA_NODE_ID),
355 DEFINE_PROP_BOOL("pre-3.0-migration", sPAPRCPUCore, pre_3_0_migration,
356 false),
357 DEFINE_PROP_END_OF_LIST()
358 };
359
spapr_cpu_core_class_init(ObjectClass * oc,void * data)360 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
361 {
362 DeviceClass *dc = DEVICE_CLASS(oc);
363 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
364
365 dc->realize = spapr_cpu_core_realize;
366 dc->unrealize = spapr_cpu_core_unrealize;
367 dc->props = spapr_cpu_core_properties;
368 scc->cpu_type = data;
369 }
370
371 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
372 { \
373 .parent = TYPE_SPAPR_CPU_CORE, \
374 .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
375 .class_init = spapr_cpu_core_class_init, \
376 .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model), \
377 }
378
379 static const TypeInfo spapr_cpu_core_type_infos[] = {
380 {
381 .name = TYPE_SPAPR_CPU_CORE,
382 .parent = TYPE_CPU_CORE,
383 .abstract = true,
384 .instance_size = sizeof(sPAPRCPUCore),
385 .class_size = sizeof(sPAPRCPUCoreClass),
386 },
387 DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
388 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
389 DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
390 DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
391 DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
392 DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
393 DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
394 DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
395 DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
396 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
397 DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
398 #ifdef CONFIG_KVM
399 DEFINE_SPAPR_CPU_CORE_TYPE("host"),
400 #endif
401 };
402
403 DEFINE_TYPES(spapr_cpu_core_type_infos)
404