1 /*
2 * Intel XScale PXA255/270 OS Timers.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "qemu/osdep.h"
11 #include "hw/hw.h"
12 #include "qemu/timer.h"
13 #include "sysemu/sysemu.h"
14 #include "hw/arm/pxa.h"
15 #include "hw/sysbus.h"
16 #include "qemu/log.h"
17
18 #define OSMR0 0x00
19 #define OSMR1 0x04
20 #define OSMR2 0x08
21 #define OSMR3 0x0c
22 #define OSMR4 0x80
23 #define OSMR5 0x84
24 #define OSMR6 0x88
25 #define OSMR7 0x8c
26 #define OSMR8 0x90
27 #define OSMR9 0x94
28 #define OSMR10 0x98
29 #define OSMR11 0x9c
30 #define OSCR 0x10 /* OS Timer Count */
31 #define OSCR4 0x40
32 #define OSCR5 0x44
33 #define OSCR6 0x48
34 #define OSCR7 0x4c
35 #define OSCR8 0x50
36 #define OSCR9 0x54
37 #define OSCR10 0x58
38 #define OSCR11 0x5c
39 #define OSSR 0x14 /* Timer status register */
40 #define OWER 0x18
41 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
42 #define OMCR4 0xc0 /* OS Match Control registers */
43 #define OMCR5 0xc4
44 #define OMCR6 0xc8
45 #define OMCR7 0xcc
46 #define OMCR8 0xd0
47 #define OMCR9 0xd4
48 #define OMCR10 0xd8
49 #define OMCR11 0xdc
50 #define OSNR 0x20
51
52 #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
53 #define PXA27X_FREQ 3250000 /* 3.25 MHz */
54
55 static int pxa2xx_timer4_freq[8] = {
56 [0] = 0,
57 [1] = 32768,
58 [2] = 1000,
59 [3] = 1,
60 [4] = 1000000,
61 /* [5] is the "Externally supplied clock". Assign if necessary. */
62 [5 ... 7] = 0,
63 };
64
65 #define TYPE_PXA2XX_TIMER "pxa2xx-timer"
66 #define PXA2XX_TIMER(obj) \
67 OBJECT_CHECK(PXA2xxTimerInfo, (obj), TYPE_PXA2XX_TIMER)
68
69 typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
70
71 typedef struct {
72 uint32_t value;
73 qemu_irq irq;
74 QEMUTimer *qtimer;
75 int num;
76 PXA2xxTimerInfo *info;
77 } PXA2xxTimer0;
78
79 typedef struct {
80 PXA2xxTimer0 tm;
81 int32_t oldclock;
82 int32_t clock;
83 uint64_t lastload;
84 uint32_t freq;
85 uint32_t control;
86 } PXA2xxTimer4;
87
88 struct PXA2xxTimerInfo {
89 SysBusDevice parent_obj;
90
91 MemoryRegion iomem;
92 uint32_t flags;
93
94 int32_t clock;
95 int32_t oldclock;
96 uint64_t lastload;
97 uint32_t freq;
98 PXA2xxTimer0 timer[4];
99 uint32_t events;
100 uint32_t irq_enabled;
101 uint32_t reset3;
102 uint32_t snapshot;
103
104 qemu_irq irq4;
105 PXA2xxTimer4 tm4[8];
106 };
107
108 #define PXA2XX_TIMER_HAVE_TM4 0
109
pxa2xx_timer_has_tm4(PXA2xxTimerInfo * s)110 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
111 {
112 return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
113 }
114
pxa2xx_timer_update(void * opaque,uint64_t now_qemu)115 static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
116 {
117 PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
118 int i;
119 uint32_t now_vm;
120 uint64_t new_qemu;
121
122 now_vm = s->clock +
123 muldiv64(now_qemu - s->lastload, s->freq, NANOSECONDS_PER_SECOND);
124
125 for (i = 0; i < 4; i ++) {
126 new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
127 NANOSECONDS_PER_SECOND, s->freq);
128 timer_mod(s->timer[i].qtimer, new_qemu);
129 }
130 }
131
pxa2xx_timer_update4(void * opaque,uint64_t now_qemu,int n)132 static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
133 {
134 PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
135 uint32_t now_vm;
136 uint64_t new_qemu;
137 static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
138 int counter;
139
140 if (s->tm4[n].control & (1 << 7))
141 counter = n;
142 else
143 counter = counters[n];
144
145 if (!s->tm4[counter].freq) {
146 timer_del(s->tm4[n].tm.qtimer);
147 return;
148 }
149
150 now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
151 s->tm4[counter].lastload,
152 s->tm4[counter].freq, NANOSECONDS_PER_SECOND);
153
154 new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
155 NANOSECONDS_PER_SECOND, s->tm4[counter].freq);
156 timer_mod(s->tm4[n].tm.qtimer, new_qemu);
157 }
158
pxa2xx_timer_read(void * opaque,hwaddr offset,unsigned size)159 static uint64_t pxa2xx_timer_read(void *opaque, hwaddr offset,
160 unsigned size)
161 {
162 PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
163 int tm = 0;
164
165 switch (offset) {
166 case OSMR3: tm ++;
167 /* fall through */
168 case OSMR2: tm ++;
169 /* fall through */
170 case OSMR1: tm ++;
171 /* fall through */
172 case OSMR0:
173 return s->timer[tm].value;
174 case OSMR11: tm ++;
175 /* fall through */
176 case OSMR10: tm ++;
177 /* fall through */
178 case OSMR9: tm ++;
179 /* fall through */
180 case OSMR8: tm ++;
181 /* fall through */
182 case OSMR7: tm ++;
183 /* fall through */
184 case OSMR6: tm ++;
185 /* fall through */
186 case OSMR5: tm ++;
187 /* fall through */
188 case OSMR4:
189 if (!pxa2xx_timer_has_tm4(s))
190 goto badreg;
191 return s->tm4[tm].tm.value;
192 case OSCR:
193 return s->clock + muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
194 s->lastload, s->freq, NANOSECONDS_PER_SECOND);
195 case OSCR11: tm ++;
196 /* fall through */
197 case OSCR10: tm ++;
198 /* fall through */
199 case OSCR9: tm ++;
200 /* fall through */
201 case OSCR8: tm ++;
202 /* fall through */
203 case OSCR7: tm ++;
204 /* fall through */
205 case OSCR6: tm ++;
206 /* fall through */
207 case OSCR5: tm ++;
208 /* fall through */
209 case OSCR4:
210 if (!pxa2xx_timer_has_tm4(s))
211 goto badreg;
212
213 if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
214 if (s->tm4[tm - 1].freq)
215 s->snapshot = s->tm4[tm - 1].clock + muldiv64(
216 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
217 s->tm4[tm - 1].lastload,
218 s->tm4[tm - 1].freq, NANOSECONDS_PER_SECOND);
219 else
220 s->snapshot = s->tm4[tm - 1].clock;
221 }
222
223 if (!s->tm4[tm].freq)
224 return s->tm4[tm].clock;
225 return s->tm4[tm].clock +
226 muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
227 s->tm4[tm].lastload, s->tm4[tm].freq,
228 NANOSECONDS_PER_SECOND);
229 case OIER:
230 return s->irq_enabled;
231 case OSSR: /* Status register */
232 return s->events;
233 case OWER:
234 return s->reset3;
235 case OMCR11: tm ++;
236 /* fall through */
237 case OMCR10: tm ++;
238 /* fall through */
239 case OMCR9: tm ++;
240 /* fall through */
241 case OMCR8: tm ++;
242 /* fall through */
243 case OMCR7: tm ++;
244 /* fall through */
245 case OMCR6: tm ++;
246 /* fall through */
247 case OMCR5: tm ++;
248 /* fall through */
249 case OMCR4:
250 if (!pxa2xx_timer_has_tm4(s))
251 goto badreg;
252 return s->tm4[tm].control;
253 case OSNR:
254 return s->snapshot;
255 default:
256 qemu_log_mask(LOG_UNIMP,
257 "%s: unknown register 0x%02" HWADDR_PRIx "\n",
258 __func__, offset);
259 break;
260 badreg:
261 qemu_log_mask(LOG_GUEST_ERROR,
262 "%s: incorrect register 0x%02" HWADDR_PRIx "\n",
263 __func__, offset);
264 }
265
266 return 0;
267 }
268
pxa2xx_timer_write(void * opaque,hwaddr offset,uint64_t value,unsigned size)269 static void pxa2xx_timer_write(void *opaque, hwaddr offset,
270 uint64_t value, unsigned size)
271 {
272 int i, tm = 0;
273 PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
274
275 switch (offset) {
276 case OSMR3: tm ++;
277 /* fall through */
278 case OSMR2: tm ++;
279 /* fall through */
280 case OSMR1: tm ++;
281 /* fall through */
282 case OSMR0:
283 s->timer[tm].value = value;
284 pxa2xx_timer_update(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
285 break;
286 case OSMR11: tm ++;
287 /* fall through */
288 case OSMR10: tm ++;
289 /* fall through */
290 case OSMR9: tm ++;
291 /* fall through */
292 case OSMR8: tm ++;
293 /* fall through */
294 case OSMR7: tm ++;
295 /* fall through */
296 case OSMR6: tm ++;
297 /* fall through */
298 case OSMR5: tm ++;
299 /* fall through */
300 case OSMR4:
301 if (!pxa2xx_timer_has_tm4(s))
302 goto badreg;
303 s->tm4[tm].tm.value = value;
304 pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
305 break;
306 case OSCR:
307 s->oldclock = s->clock;
308 s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
309 s->clock = value;
310 pxa2xx_timer_update(s, s->lastload);
311 break;
312 case OSCR11: tm ++;
313 /* fall through */
314 case OSCR10: tm ++;
315 /* fall through */
316 case OSCR9: tm ++;
317 /* fall through */
318 case OSCR8: tm ++;
319 /* fall through */
320 case OSCR7: tm ++;
321 /* fall through */
322 case OSCR6: tm ++;
323 /* fall through */
324 case OSCR5: tm ++;
325 /* fall through */
326 case OSCR4:
327 if (!pxa2xx_timer_has_tm4(s))
328 goto badreg;
329 s->tm4[tm].oldclock = s->tm4[tm].clock;
330 s->tm4[tm].lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
331 s->tm4[tm].clock = value;
332 pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
333 break;
334 case OIER:
335 s->irq_enabled = value & 0xfff;
336 break;
337 case OSSR: /* Status register */
338 value &= s->events;
339 s->events &= ~value;
340 for (i = 0; i < 4; i ++, value >>= 1)
341 if (value & 1)
342 qemu_irq_lower(s->timer[i].irq);
343 if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
344 qemu_irq_lower(s->irq4);
345 break;
346 case OWER: /* XXX: Reset on OSMR3 match? */
347 s->reset3 = value;
348 break;
349 case OMCR7: tm ++;
350 /* fall through */
351 case OMCR6: tm ++;
352 /* fall through */
353 case OMCR5: tm ++;
354 /* fall through */
355 case OMCR4:
356 if (!pxa2xx_timer_has_tm4(s))
357 goto badreg;
358 s->tm4[tm].control = value & 0x0ff;
359 /* XXX Stop if running (shouldn't happen) */
360 if ((value & (1 << 7)) || tm == 0)
361 s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
362 else {
363 s->tm4[tm].freq = 0;
364 pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
365 }
366 break;
367 case OMCR11: tm ++;
368 /* fall through */
369 case OMCR10: tm ++;
370 /* fall through */
371 case OMCR9: tm ++;
372 /* fall through */
373 case OMCR8: tm += 4;
374 if (!pxa2xx_timer_has_tm4(s))
375 goto badreg;
376 s->tm4[tm].control = value & 0x3ff;
377 /* XXX Stop if running (shouldn't happen) */
378 if ((value & (1 << 7)) || !(tm & 1))
379 s->tm4[tm].freq =
380 pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
381 else {
382 s->tm4[tm].freq = 0;
383 pxa2xx_timer_update4(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tm);
384 }
385 break;
386 default:
387 qemu_log_mask(LOG_UNIMP,
388 "%s: unknown register 0x%02" HWADDR_PRIx " "
389 "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
390 break;
391 badreg:
392 qemu_log_mask(LOG_GUEST_ERROR,
393 "%s: incorrect register 0x%02" HWADDR_PRIx " "
394 "(value 0x%08" PRIx64 ")\n", __func__, offset, value);
395 }
396 }
397
398 static const MemoryRegionOps pxa2xx_timer_ops = {
399 .read = pxa2xx_timer_read,
400 .write = pxa2xx_timer_write,
401 .endianness = DEVICE_NATIVE_ENDIAN,
402 };
403
pxa2xx_timer_tick(void * opaque)404 static void pxa2xx_timer_tick(void *opaque)
405 {
406 PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
407 PXA2xxTimerInfo *i = t->info;
408
409 if (i->irq_enabled & (1 << t->num)) {
410 i->events |= 1 << t->num;
411 qemu_irq_raise(t->irq);
412 }
413
414 if (t->num == 3)
415 if (i->reset3 & 1) {
416 i->reset3 = 0;
417 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
418 }
419 }
420
pxa2xx_timer_tick4(void * opaque)421 static void pxa2xx_timer_tick4(void *opaque)
422 {
423 PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
424 PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
425
426 pxa2xx_timer_tick(&t->tm);
427 if (t->control & (1 << 3))
428 t->clock = 0;
429 if (t->control & (1 << 6))
430 pxa2xx_timer_update4(i, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), t->tm.num - 4);
431 if (i->events & 0xff0)
432 qemu_irq_raise(i->irq4);
433 }
434
pxa25x_timer_post_load(void * opaque,int version_id)435 static int pxa25x_timer_post_load(void *opaque, int version_id)
436 {
437 PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
438 int64_t now;
439 int i;
440
441 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
442 pxa2xx_timer_update(s, now);
443
444 if (pxa2xx_timer_has_tm4(s))
445 for (i = 0; i < 8; i ++)
446 pxa2xx_timer_update4(s, now, i);
447
448 return 0;
449 }
450
pxa2xx_timer_init(Object * obj)451 static void pxa2xx_timer_init(Object *obj)
452 {
453 PXA2xxTimerInfo *s = PXA2XX_TIMER(obj);
454 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
455
456 s->irq_enabled = 0;
457 s->oldclock = 0;
458 s->clock = 0;
459 s->lastload = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
460 s->reset3 = 0;
461
462 memory_region_init_io(&s->iomem, obj, &pxa2xx_timer_ops, s,
463 "pxa2xx-timer", 0x00001000);
464 sysbus_init_mmio(dev, &s->iomem);
465 }
466
pxa2xx_timer_realize(DeviceState * dev,Error ** errp)467 static void pxa2xx_timer_realize(DeviceState *dev, Error **errp)
468 {
469 PXA2xxTimerInfo *s = PXA2XX_TIMER(dev);
470 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
471 int i;
472
473 for (i = 0; i < 4; i ++) {
474 s->timer[i].value = 0;
475 sysbus_init_irq(sbd, &s->timer[i].irq);
476 s->timer[i].info = s;
477 s->timer[i].num = i;
478 s->timer[i].qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
479 pxa2xx_timer_tick, &s->timer[i]);
480 }
481
482 if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
483 sysbus_init_irq(sbd, &s->irq4);
484
485 for (i = 0; i < 8; i ++) {
486 s->tm4[i].tm.value = 0;
487 s->tm4[i].tm.info = s;
488 s->tm4[i].tm.num = i + 4;
489 s->tm4[i].freq = 0;
490 s->tm4[i].control = 0x0;
491 s->tm4[i].tm.qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
492 pxa2xx_timer_tick4, &s->tm4[i]);
493 }
494 }
495 }
496
497 static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
498 .name = "pxa2xx_timer0",
499 .version_id = 2,
500 .minimum_version_id = 2,
501 .fields = (VMStateField[]) {
502 VMSTATE_UINT32(value, PXA2xxTimer0),
503 VMSTATE_END_OF_LIST(),
504 },
505 };
506
507 static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
508 .name = "pxa2xx_timer4",
509 .version_id = 1,
510 .minimum_version_id = 1,
511 .fields = (VMStateField[]) {
512 VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
513 vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
514 VMSTATE_INT32(oldclock, PXA2xxTimer4),
515 VMSTATE_INT32(clock, PXA2xxTimer4),
516 VMSTATE_UINT64(lastload, PXA2xxTimer4),
517 VMSTATE_UINT32(freq, PXA2xxTimer4),
518 VMSTATE_UINT32(control, PXA2xxTimer4),
519 VMSTATE_END_OF_LIST(),
520 },
521 };
522
pxa2xx_timer_has_tm4_test(void * opaque,int version_id)523 static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
524 {
525 return pxa2xx_timer_has_tm4(opaque);
526 }
527
528 static const VMStateDescription vmstate_pxa2xx_timer_regs = {
529 .name = "pxa2xx_timer",
530 .version_id = 1,
531 .minimum_version_id = 1,
532 .post_load = pxa25x_timer_post_load,
533 .fields = (VMStateField[]) {
534 VMSTATE_INT32(clock, PXA2xxTimerInfo),
535 VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
536 VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
537 VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
538 vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
539 VMSTATE_UINT32(events, PXA2xxTimerInfo),
540 VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
541 VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
542 VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
543 VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
544 pxa2xx_timer_has_tm4_test, 0,
545 vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
546 VMSTATE_END_OF_LIST(),
547 }
548 };
549
550 static Property pxa25x_timer_dev_properties[] = {
551 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
552 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
553 PXA2XX_TIMER_HAVE_TM4, false),
554 DEFINE_PROP_END_OF_LIST(),
555 };
556
pxa25x_timer_dev_class_init(ObjectClass * klass,void * data)557 static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data)
558 {
559 DeviceClass *dc = DEVICE_CLASS(klass);
560
561 dc->desc = "PXA25x timer";
562 dc->props = pxa25x_timer_dev_properties;
563 }
564
565 static const TypeInfo pxa25x_timer_dev_info = {
566 .name = "pxa25x-timer",
567 .parent = TYPE_PXA2XX_TIMER,
568 .instance_size = sizeof(PXA2xxTimerInfo),
569 .class_init = pxa25x_timer_dev_class_init,
570 };
571
572 static Property pxa27x_timer_dev_properties[] = {
573 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
574 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
575 PXA2XX_TIMER_HAVE_TM4, true),
576 DEFINE_PROP_END_OF_LIST(),
577 };
578
pxa27x_timer_dev_class_init(ObjectClass * klass,void * data)579 static void pxa27x_timer_dev_class_init(ObjectClass *klass, void *data)
580 {
581 DeviceClass *dc = DEVICE_CLASS(klass);
582
583 dc->desc = "PXA27x timer";
584 dc->props = pxa27x_timer_dev_properties;
585 }
586
587 static const TypeInfo pxa27x_timer_dev_info = {
588 .name = "pxa27x-timer",
589 .parent = TYPE_PXA2XX_TIMER,
590 .instance_size = sizeof(PXA2xxTimerInfo),
591 .class_init = pxa27x_timer_dev_class_init,
592 };
593
pxa2xx_timer_class_init(ObjectClass * oc,void * data)594 static void pxa2xx_timer_class_init(ObjectClass *oc, void *data)
595 {
596 DeviceClass *dc = DEVICE_CLASS(oc);
597
598 dc->realize = pxa2xx_timer_realize;
599 dc->vmsd = &vmstate_pxa2xx_timer_regs;
600 }
601
602 static const TypeInfo pxa2xx_timer_type_info = {
603 .name = TYPE_PXA2XX_TIMER,
604 .parent = TYPE_SYS_BUS_DEVICE,
605 .instance_size = sizeof(PXA2xxTimerInfo),
606 .instance_init = pxa2xx_timer_init,
607 .abstract = true,
608 .class_init = pxa2xx_timer_class_init,
609 };
610
pxa2xx_timer_register_types(void)611 static void pxa2xx_timer_register_types(void)
612 {
613 type_register_static(&pxa2xx_timer_type_info);
614 type_register_static(&pxa25x_timer_dev_info);
615 type_register_static(&pxa27x_timer_dev_info);
616 }
617
618 type_init(pxa2xx_timer_register_types)
619