1 /* Copyright (c) 2018, IBM Corporation. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef PCI_HOST_PNV_PHB4_REGS_H 19 #define PCI_HOST_PNV_PHB4_REGS_H 20 21 /* 22 * PEC XSCOM registers 23 * 24 * There a 3 PECs in P9. Each PEC can have several PHBs. Each PEC has some 25 * "global" registers and some "per-stack" (per-PHB) registers. Those are 26 * organized in two XSCOM ranges, the "Nest" range and the "PCI" range, each 27 * range contains both some "PEC" registers and some "per-stack" registers. 28 * 29 * Finally the PCI range also contains an additional range per stack that 30 * passes through to some of the PHB own registers. 31 * 32 * PEC0 can contain 1 PHB (PHB0) 33 * PEC1 can contain 2 PHBs (PHB1 and PHB2) 34 * PEC2 can contain 3 PHBs (PHB3, PHB4 and PHB5) 35 */ 36 37 /* This is the "stack" offset, it's the offset from a given range base to 38 * the first "per-stack" registers and also the stride between stacks, 39 * thus for PEC2, the global registers are at offset 0, the PHB3 registers 40 * at offset 0x40, the PHB4 at offset 0x80 etc.... 41 * 42 * It is *also* the offset to the pass-through SCOM region but in this case 43 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc.. 44 */ 45 #define PEC_STACK_OFFSET 0x40 46 47 /* XSCOM Nest global registers */ 48 #define PEC_NEST_PBCQ_HW_CONFIG 0x00 49 #define PEC_NEST_DROP_PRIO_CTRL 0x01 50 #define PEC_NEST_PBCQ_ERR_INJECT 0x02 51 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03 52 #define PEC_NEST_PBCQ_PMON_CTRL 0x04 53 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05 54 #define PEC_NEST_PBCQ_PRED_VEC_TIMEOUT 0x06 55 #define PEC_NEST_CAPP_CTRL 0x07 56 #define PEC_NEST_PBCQ_READ_STK_OVR 0x08 57 #define PEC_NEST_PBCQ_WRITE_STK_OVR 0x09 58 #define PEC_NEST_PBCQ_STORE_STK_OVR 0x0a 59 #define PEC_NEST_PBCQ_RETRY_BKOFF_CTRL 0x0b 60 61 /* XSCOM Nest per-stack registers */ 62 #define PEC_NEST_STK_PCI_NEST_FIR 0x00 63 #define PEC_NEST_STK_PCI_NEST_FIR_CLR 0x01 64 #define PEC_NEST_STK_PCI_NEST_FIR_SET 0x02 65 #define PEC_NEST_STK_PCI_NEST_FIR_MSK 0x03 66 #define PEC_NEST_STK_PCI_NEST_FIR_MSKC 0x04 67 #define PEC_NEST_STK_PCI_NEST_FIR_MSKS 0x05 68 #define PEC_NEST_STK_PCI_NEST_FIR_ACT0 0x06 69 #define PEC_NEST_STK_PCI_NEST_FIR_ACT1 0x07 70 #define PEC_NEST_STK_PCI_NEST_FIR_WOF 0x08 71 #define PEC_NEST_STK_ERR_REPORT_0 0x0a 72 #define PEC_NEST_STK_ERR_REPORT_1 0x0b 73 #define PEC_NEST_STK_PBCQ_GNRL_STATUS 0x0c 74 #define PEC_NEST_STK_PBCQ_MODE 0x0d 75 #define PEC_NEST_STK_MMIO_BAR0 0x0e 76 #define PEC_NEST_STK_MMIO_BAR0_MASK 0x0f 77 #define PEC_NEST_STK_MMIO_BAR1 0x10 78 #define PEC_NEST_STK_MMIO_BAR1_MASK 0x11 79 #define PEC_NEST_STK_PHB_REGS_BAR 0x12 80 #define PEC_NEST_STK_INT_BAR 0x13 81 #define PEC_NEST_STK_BAR_EN 0x14 82 #define PEC_NEST_STK_BAR_EN_MMIO0 PPC_BIT(0) 83 #define PEC_NEST_STK_BAR_EN_MMIO1 PPC_BIT(1) 84 #define PEC_NEST_STK_BAR_EN_PHB PPC_BIT(2) 85 #define PEC_NEST_STK_BAR_EN_INT PPC_BIT(3) 86 #define PEC_NEST_STK_DATA_FRZ_TYPE 0x15 87 #define PEC_NEST_STK_PBCQ_TUN_BAR 0x16 88 89 /* XSCOM PCI global registers */ 90 #define PEC_PCI_PBAIB_HW_CONFIG 0x00 91 #define PEC_PCI_PBAIB_READ_STK_OVR 0x02 92 93 /* XSCOM PCI per-stack registers */ 94 #define PEC_PCI_STK_PCI_FIR 0x00 95 #define PEC_PCI_STK_PCI_FIR_CLR 0x01 96 #define PEC_PCI_STK_PCI_FIR_SET 0x02 97 #define PEC_PCI_STK_PCI_FIR_MSK 0x03 98 #define PEC_PCI_STK_PCI_FIR_MSKC 0x04 99 #define PEC_PCI_STK_PCI_FIR_MSKS 0x05 100 #define PEC_PCI_STK_PCI_FIR_ACT0 0x06 101 #define PEC_PCI_STK_PCI_FIR_ACT1 0x07 102 #define PEC_PCI_STK_PCI_FIR_WOF 0x08 103 #define PEC_PCI_STK_ETU_RESET 0x0a 104 #define PEC_PCI_STK_PBAIB_ERR_REPORT 0x0b 105 #define PEC_PCI_STK_PBAIB_TX_CMD_CRED 0x0d 106 #define PEC_PCI_STK_PBAIB_TX_DAT_CRED 0x0e 107 108 /* XSCOM PCI "pass-through" windo to PHB SCOM */ 109 #define PEC_PCI_SCOM_STK0 0x100 110 #define PEC_PCI_SCOM_STK1 0x140 111 #define PEC_PCI_SCOM_STK2 0x180 112 113 /* 114 * PHB "SCOM" registers. This is accessed via the above window 115 * and provides a backdoor to the PHB when the AIB bus is not 116 * functional. Some of these directly map some of the PHB MMIO 117 * registers, some are specific and allow indirect access to a 118 * wider range of PHB registers 119 */ 120 #define PHB_SCOM_HV_IND_ADDR 0x00 121 #define PHB_SCOM_HV_IND_ADDR_VALID PPC_BIT(0) 122 #define PHB_SCOM_HV_IND_ADDR_4B PPC_BIT(1) 123 #define PHB_SCOM_HV_IND_ADDR_AUTOINC PPC_BIT(2) 124 #define PHB_SCOM_HV_IND_ADDR_ADDR PPC_BITMASK(51,63) 125 #define PHB_SCOM_HV_IND_DATA 0x01 126 #define PHB_SCOM_ETU_LEM_FIR 0x08 127 #define PHB_SCOM_ETU_LEM_FIR_AND 0x09 128 #define PHB_SCOM_ETU_LEM_FIR_OR 0x0a 129 #define PHB_SCOM_ETU_LEM_FIR_MSK 0x0b 130 #define PHB_SCOM_ETU_LEM_ERR_MSK_AND 0x0c 131 #define PHB_SCOM_ETU_LEM_ERR_MSK_OR 0x0d 132 #define PHB_SCOM_ETU_LEM_ACT0 0x0e 133 #define PHB_SCOM_ETU_LEM_ACT1 0x0f 134 #define PHB_SCOM_ETU_LEM_WOF 0x10 135 #define PHB_SCOM_ETU_PMON_CONFIG 0x17 136 #define PHB_SCOM_ETU_PMON_CTR0 0x18 137 #define PHB_SCOM_ETU_PMON_CTR1 0x19 138 #define PHB_SCOM_ETU_PMON_CTR2 0x1a 139 #define PHB_SCOM_ETU_PMON_CTR3 0x1b 140 141 142 /* 143 * PHB MMIO registers 144 */ 145 146 /* PHB Fundamental register set A */ 147 #define PHB_LSI_SOURCE_ID 0x100 148 #define PHB_LSI_SRC_ID PPC_BITMASK(4, 12) 149 #define PHB_DMA_CHAN_STATUS 0x110 150 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) 151 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) 152 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) 153 #define PHB_CPU_LOADSTORE_STATUS 0x120 154 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) 155 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) 156 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) 157 #define PHB_CONFIG_DATA 0x130 158 #define PHB_LOCK0 0x138 159 #define PHB_CONFIG_ADDRESS 0x140 160 #define PHB_CA_ENABLE PPC_BIT(0) 161 #define PHB_CA_STATUS PPC_BITMASK(1,3) 162 #define PHB_CA_STATUS_GOOD 0 163 #define PHB_CA_STATUS_UR 1 164 #define PHB_CA_STATUS_CRS 2 165 #define PHB_CA_STATUS_CA 4 166 #define PHB_CA_BUS PPC_BITMASK(4,11) 167 #define PHB_CA_DEV PPC_BITMASK(12,16) 168 #define PHB_CA_FUNC PPC_BITMASK(17,19) 169 #define PHB_CA_BDFN PPC_BITMASK(4,19) /* bus,dev,func */ 170 #define PHB_CA_REG PPC_BITMASK(20,31) 171 #define PHB_CA_PE PPC_BITMASK(39,47) 172 #define PHB_LOCK1 0x148 173 #define PHB_PHB4_CONFIG 0x160 174 #define PHB_PHB4C_32BIT_MSI_EN PPC_BIT(8) 175 #define PHB_PHB4C_64BIT_MSI_EN PPC_BIT(14) 176 #define PHB_RTT_BAR 0x168 177 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) 178 #define PHB_RTT_BASE_ADDRESS_MASK PPC_BITMASK(8, 46) 179 #define PHB_PELTV_BAR 0x188 180 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) 181 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(8, 50) 182 #define PHB_M32_START_ADDR 0x1a0 183 #define PHB_PEST_BAR 0x1a8 184 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) 185 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8,51) 186 #define PHB_ASN_CMPM 0x1C0 187 #define PHB_ASN_CMPM_ENABLE PPC_BIT(63) 188 #define PHB_CAPI_CMPM 0x1C8 189 #define PHB_CAPI_CMPM_ENABLE PPC_BIT(63) 190 #define PHB_M64_AOMASK 0x1d0 191 #define PHB_M64_UPPER_BITS 0x1f0 192 #define PHB_NXLATE_PREFIX 0x1f8 193 #define PHB_DMARD_SYNC 0x200 194 #define PHB_DMARD_SYNC_START PPC_BIT(0) 195 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) 196 #define PHB_RTC_INVALIDATE 0x208 197 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) 198 #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16, 31) 199 #define PHB_TCE_KILL 0x210 200 #define PHB_TCE_KILL_ALL PPC_BIT(0) 201 #define PHB_TCE_KILL_PE PPC_BIT(1) 202 #define PHB_TCE_KILL_ONE PPC_BIT(2) 203 #define PHB_TCE_KILL_PSEL PPC_BIT(3) 204 #define PHB_TCE_KILL_64K 0x1000 /* Address override */ 205 #define PHB_TCE_KILL_2M 0x2000 /* Address override */ 206 #define PHB_TCE_KILL_1G 0x3000 /* Address override */ 207 #define PHB_TCE_KILL_PENUM PPC_BITMASK(55,63) 208 #define PHB_TCE_SPEC_CTL 0x218 209 #define PHB_IODA_ADDR 0x220 210 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 211 #define PHB_IODA_AD_TSEL PPC_BITMASK(11, 15) 212 #define PHB_IODA_AD_MIST_PWV PPC_BITMASK(28,31) 213 #define PHB_IODA_AD_TADR PPC_BITMASK(54, 63) 214 #define PHB_IODA_DATA0 0x228 215 #define PHB_PHB4_GEN_CAP 0x250 216 #define PHB_PHB4_TCE_CAP 0x258 217 #define PHB_PHB4_IRQ_CAP 0x260 218 #define PHB_PHB4_EEH_CAP 0x268 219 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 220 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 221 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 222 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 223 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 224 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 225 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 226 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 227 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 228 #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16,63) 229 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 230 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) 231 #define PHB_PAPR_ERR_INJ_MASK_CFG_ALL PPC_BITMASK(4,19) 232 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) 233 #define PHB_ETU_ERR_SUMMARY 0x2c8 234 #define PHB_INT_NOTIFY_ADDR 0x300 235 #define PHB_INT_NOTIFY_INDEX 0x308 236 237 /* Fundamental register set B */ 238 #define PHB_VERSION 0x800 239 #define PHB_CTRLR 0x810 240 #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) 241 #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) 242 #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) 243 #define PHB_CTRLR_MMIO_EEH_DISABLE PPC_BIT(14) 244 #define PHB_CTRLR_CFG_EEH_BLOCK PPC_BIT(15) 245 #define PHB_CTRLR_FENCE_LNKILL_DIS PPC_BIT(16) 246 #define PHB_CTRLR_TVT_ADDR_SEL PPC_BITMASK(17,19) 247 #define TVT_DD1_1_PER_PE 0 248 #define TVT_DD1_2_PER_PE 1 249 #define TVT_DD1_4_PER_PE 2 250 #define TVT_DD1_8_PER_PE 3 251 #define TVT_DD1_16_PER_PE 4 252 #define TVT_2_PER_PE 0 253 #define TVT_4_PER_PE 1 254 #define TVT_8_PER_PE 2 255 #define TVT_16_PER_PE 3 256 #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28,31) 257 #define PHB_AIB_FENCE_CTRL 0x860 258 #define PHB_TCE_TAG_ENABLE 0x868 259 #define PHB_TCE_WATERMARK 0x870 260 #define PHB_TIMEOUT_CTRL1 0x878 261 #define PHB_TIMEOUT_CTRL2 0x880 262 #define PHB_Q_DMA_R 0x888 263 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0) 264 #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1) 265 #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4) 266 #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5) 267 #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6) 268 #define PHB_Q_DMA_R_TCE_KILL_STATUS PPC_BIT(7) 269 #define PHB_TCE_TAG_STATUS 0x908 270 271 /* FIR & Error registers */ 272 #define PHB_LEM_FIR_ACCUM 0xc00 273 #define PHB_LEM_FIR_AND_MASK 0xc08 274 #define PHB_LEM_FIR_OR_MASK 0xc10 275 #define PHB_LEM_ERROR_MASK 0xc18 276 #define PHB_LEM_ERROR_AND_MASK 0xc20 277 #define PHB_LEM_ERROR_OR_MASK 0xc28 278 #define PHB_LEM_ACTION0 0xc30 279 #define PHB_LEM_ACTION1 0xc38 280 #define PHB_LEM_WOF 0xc40 281 #define PHB_ERR_STATUS 0xc80 282 #define PHB_ERR1_STATUS 0xc88 283 #define PHB_ERR_INJECT 0xc90 284 #define PHB_ERR_LEM_ENABLE 0xc98 285 #define PHB_ERR_IRQ_ENABLE 0xca0 286 #define PHB_ERR_FREEZE_ENABLE 0xca8 287 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 288 #define PHB_ERR_LOG_0 0xcc0 289 #define PHB_ERR_LOG_1 0xcc8 290 #define PHB_ERR_STATUS_MASK 0xcd0 291 #define PHB_ERR1_STATUS_MASK 0xcd8 292 293 #define PHB_TXE_ERR_STATUS 0xd00 294 #define PHB_TXE_ERR1_STATUS 0xd08 295 #define PHB_TXE_ERR_INJECT 0xd10 296 #define PHB_TXE_ERR_LEM_ENABLE 0xd18 297 #define PHB_TXE_ERR_IRQ_ENABLE 0xd20 298 #define PHB_TXE_ERR_FREEZE_ENABLE 0xd28 299 #define PHB_TXE_ERR_AIB_FENCE_ENABLE 0xd30 300 #define PHB_TXE_ERR_LOG_0 0xd40 301 #define PHB_TXE_ERR_LOG_1 0xd48 302 #define PHB_TXE_ERR_STATUS_MASK 0xd50 303 #define PHB_TXE_ERR1_STATUS_MASK 0xd58 304 305 #define PHB_RXE_ARB_ERR_STATUS 0xd80 306 #define PHB_RXE_ARB_ERR1_STATUS 0xd88 307 #define PHB_RXE_ARB_ERR_INJECT 0xd90 308 #define PHB_RXE_ARB_ERR_LEM_ENABLE 0xd98 309 #define PHB_RXE_ARB_ERR_IRQ_ENABLE 0xda0 310 #define PHB_RXE_ARB_ERR_FREEZE_ENABLE 0xda8 311 #define PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE 0xdb0 312 #define PHB_RXE_ARB_ERR_LOG_0 0xdc0 313 #define PHB_RXE_ARB_ERR_LOG_1 0xdc8 314 #define PHB_RXE_ARB_ERR_STATUS_MASK 0xdd0 315 #define PHB_RXE_ARB_ERR1_STATUS_MASK 0xdd8 316 317 #define PHB_RXE_MRG_ERR_STATUS 0xe00 318 #define PHB_RXE_MRG_ERR1_STATUS 0xe08 319 #define PHB_RXE_MRG_ERR_INJECT 0xe10 320 #define PHB_RXE_MRG_ERR_LEM_ENABLE 0xe18 321 #define PHB_RXE_MRG_ERR_IRQ_ENABLE 0xe20 322 #define PHB_RXE_MRG_ERR_FREEZE_ENABLE 0xe28 323 #define PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE 0xe30 324 #define PHB_RXE_MRG_ERR_LOG_0 0xe40 325 #define PHB_RXE_MRG_ERR_LOG_1 0xe48 326 #define PHB_RXE_MRG_ERR_STATUS_MASK 0xe50 327 #define PHB_RXE_MRG_ERR1_STATUS_MASK 0xe58 328 329 #define PHB_RXE_TCE_ERR_STATUS 0xe80 330 #define PHB_RXE_TCE_ERR1_STATUS 0xe88 331 #define PHB_RXE_TCE_ERR_INJECT 0xe90 332 #define PHB_RXE_TCE_ERR_LEM_ENABLE 0xe98 333 #define PHB_RXE_TCE_ERR_IRQ_ENABLE 0xea0 334 #define PHB_RXE_TCE_ERR_FREEZE_ENABLE 0xea8 335 #define PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE 0xeb0 336 #define PHB_RXE_TCE_ERR_LOG_0 0xec0 337 #define PHB_RXE_TCE_ERR_LOG_1 0xec8 338 #define PHB_RXE_TCE_ERR_STATUS_MASK 0xed0 339 #define PHB_RXE_TCE_ERR1_STATUS_MASK 0xed8 340 341 /* Performance monitor & Debug registers */ 342 #define PHB_TRACE_CONTROL 0xf80 343 #define PHB_PERFMON_CONFIG 0xf88 344 #define PHB_PERFMON_CTR0 0xf90 345 #define PHB_PERFMON_CTR1 0xf98 346 #define PHB_PERFMON_CTR2 0xfa0 347 #define PHB_PERFMON_CTR3 0xfa8 348 349 /* Root complex config space memory mapped */ 350 #define PHB_RC_CONFIG_BASE 0x1000 351 #define PHB_RC_CONFIG_SIZE 0x800 352 353 /* PHB4 REGB registers */ 354 355 /* PBL core */ 356 #define PHB_PBL_CONTROL 0x1800 357 #define PHB_PBL_TIMEOUT_CTRL 0x1810 358 #define PHB_PBL_NPTAG_ENABLE 0x1820 359 #define PHB_PBL_NBW_CMP_MASK 0x1830 360 #define PHB_PBL_NBW_MASK_ENABLE PPC_BIT(63) 361 #define PHB_PBL_SYS_LINK_INIT 0x1838 362 #define PHB_PBL_BUF_STATUS 0x1840 363 #define PHB_PBL_ERR_STATUS 0x1900 364 #define PHB_PBL_ERR1_STATUS 0x1908 365 #define PHB_PBL_ERR_INJECT 0x1910 366 #define PHB_PBL_ERR_INF_ENABLE 0x1920 367 #define PHB_PBL_ERR_ERC_ENABLE 0x1928 368 #define PHB_PBL_ERR_FAT_ENABLE 0x1930 369 #define PHB_PBL_ERR_LOG_0 0x1940 370 #define PHB_PBL_ERR_LOG_1 0x1948 371 #define PHB_PBL_ERR_STATUS_MASK 0x1950 372 #define PHB_PBL_ERR1_STATUS_MASK 0x1958 373 374 /* PCI-E stack */ 375 #define PHB_PCIE_SCR 0x1A00 376 #define PHB_PCIE_SCR_SLOT_CAP PPC_BIT(15) 377 #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32,35) 378 379 380 #define PHB_PCIE_CRESET 0x1A10 381 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) 382 #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1) 383 #define PHB_PCIE_CRESET_PBL PPC_BIT(2) 384 #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) 385 #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) 386 387 388 #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 389 #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) 390 391 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 392 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30,35) 393 #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36,39) 394 #define PHB_PCIE_DLP_LTSSM_TRC PPC_BITMASK(24,27) 395 #define PHB_PCIE_DLP_LTSSM_RESET 0 396 #define PHB_PCIE_DLP_LTSSM_DETECT 1 397 #define PHB_PCIE_DLP_LTSSM_POLLING 2 398 #define PHB_PCIE_DLP_LTSSM_CONFIG 3 399 #define PHB_PCIE_DLP_LTSSM_L0 4 400 #define PHB_PCIE_DLP_LTSSM_REC 5 401 #define PHB_PCIE_DLP_LTSSM_L1 6 402 #define PHB_PCIE_DLP_LTSSM_L2 7 403 #define PHB_PCIE_DLP_LTSSM_HOTRESET 8 404 #define PHB_PCIE_DLP_LTSSM_DISABLED 9 405 #define PHB_PCIE_DLP_LTSSM_LOOPBACK 10 406 #define PHB_PCIE_DLP_TL_LINKACT PPC_BIT(23) 407 #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) 408 #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) 409 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) 410 411 #define PHB_PCIE_DLP_CTL 0x1A78 412 #define PHB_PCIE_DLP_CTL_BYPASS_PH2 PPC_BIT(4) 413 #define PHB_PCIE_DLP_CTL_BYPASS_PH3 PPC_BIT(5) 414 415 #define PHB_PCIE_DLP_TRWCTL 0x1A80 416 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) 417 418 #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 419 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 420 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 421 #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 422 423 #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 424 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 425 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 426 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 427 #define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 428 #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 429 #define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */ 430 #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ 431 #define PHB_PCIE_TRACE_CTRL 0x1B20 432 #define PHB_PCIE_MISC_STRAP 0x1B30 433 434 /* Error */ 435 #define PHB_REGB_ERR_STATUS 0x1C00 436 #define PHB_REGB_ERR1_STATUS 0x1C08 437 #define PHB_REGB_ERR_INJECT 0x1C10 438 #define PHB_REGB_ERR_INF_ENABLE 0x1C20 439 #define PHB_REGB_ERR_ERC_ENABLE 0x1C28 440 #define PHB_REGB_ERR_FAT_ENABLE 0x1C30 441 #define PHB_REGB_ERR_LOG_0 0x1C40 442 #define PHB_REGB_ERR_LOG_1 0x1C48 443 #define PHB_REGB_ERR_STATUS_MASK 0x1C50 444 #define PHB_REGB_ERR1_STATUS_MASK 0x1C58 445 446 /* 447 * IODA3 on-chip tables 448 */ 449 450 #define IODA3_TBL_LIST 1 451 #define IODA3_TBL_MIST 2 452 #define IODA3_TBL_RCAM 5 453 #define IODA3_TBL_MRT 6 454 #define IODA3_TBL_PESTA 7 455 #define IODA3_TBL_PESTB 8 456 #define IODA3_TBL_TVT 9 457 #define IODA3_TBL_TCR 10 458 #define IODA3_TBL_TDR 11 459 #define IODA3_TBL_MBT 16 460 #define IODA3_TBL_MDT 17 461 #define IODA3_TBL_PEEV 20 462 463 /* LIST */ 464 #define IODA3_LIST_P PPC_BIT(6) 465 #define IODA3_LIST_Q PPC_BIT(7) 466 #define IODA3_LIST_STATE PPC_BIT(14) 467 468 /* MIST */ 469 #define IODA3_MIST_P3 PPC_BIT(48 + 0) 470 #define IODA3_MIST_Q3 PPC_BIT(48 + 1) 471 #define IODA3_MIST_PE3 PPC_BITMASK(48 + 4, 48 + 15) 472 473 /* TVT */ 474 #define IODA3_TVT_TABLE_ADDR PPC_BITMASK(0,47) 475 #define IODA3_TVT_NUM_LEVELS PPC_BITMASK(48,50) 476 #define IODA3_TVE_1_LEVEL 0 477 #define IODA3_TVE_2_LEVELS 1 478 #define IODA3_TVE_3_LEVELS 2 479 #define IODA3_TVE_4_LEVELS 3 480 #define IODA3_TVE_5_LEVELS 4 481 #define IODA3_TVT_TCE_TABLE_SIZE PPC_BITMASK(51,55) 482 #define IODA3_TVT_NON_TRANSLATE_50 PPC_BIT(56) 483 #define IODA3_TVT_IO_PSIZE PPC_BITMASK(59,63) 484 485 /* PESTA */ 486 #define IODA3_PESTA_MMIO_FROZEN PPC_BIT(0) 487 #define IODA3_PESTA_TRANS_TYPE PPC_BITMASK(5,7) 488 #define IODA3_PESTA_TRANS_TYPE_MMIOLOAD 0x4 489 #define IODA3_PESTA_CA_CMPLT_TMT PPC_BIT(8) 490 #define IODA3_PESTA_UR PPC_BIT(9) 491 492 /* PESTB */ 493 #define IODA3_PESTB_DMA_STOPPED PPC_BIT(0) 494 495 /* MDT */ 496 /* FIXME: check this field with Eric and add a B, C and D */ 497 #define IODA3_MDT_PE_A PPC_BITMASK(0,15) 498 #define IODA3_MDT_PE_B PPC_BITMASK(16,31) 499 #define IODA3_MDT_PE_C PPC_BITMASK(32,47) 500 #define IODA3_MDT_PE_D PPC_BITMASK(48,63) 501 502 /* MBT */ 503 #define IODA3_MBT0_ENABLE PPC_BIT(0) 504 #define IODA3_MBT0_TYPE PPC_BIT(1) 505 #define IODA3_MBT0_TYPE_M32 IODA3_MBT0_TYPE 506 #define IODA3_MBT0_TYPE_M64 0 507 #define IODA3_MBT0_MODE PPC_BITMASK(2,3) 508 #define IODA3_MBT0_MODE_PE_SEG 0 509 #define IODA3_MBT0_MODE_MDT 1 510 #define IODA3_MBT0_MODE_SINGLE_PE 2 511 #define IODA3_MBT0_SEG_DIV PPC_BITMASK(4,5) 512 #define IODA3_MBT0_SEG_DIV_MAX 0 513 #define IODA3_MBT0_SEG_DIV_128 1 514 #define IODA3_MBT0_SEG_DIV_64 2 515 #define IODA3_MBT0_SEG_DIV_8 3 516 #define IODA3_MBT0_MDT_COLUMN PPC_BITMASK(4,5) 517 #define IODA3_MBT0_BASE_ADDR PPC_BITMASK(8,51) 518 519 #define IODA3_MBT1_ENABLE PPC_BIT(0) 520 #define IODA3_MBT1_MASK PPC_BITMASK(8,51) 521 #define IODA3_MBT1_SEG_BASE PPC_BITMASK(55,63) 522 #define IODA3_MBT1_SINGLE_PE_NUM PPC_BITMASK(55,63) 523 524 /* 525 * IODA3 in-memory tables 526 */ 527 528 /* PEST 529 * 530 * 2x8 bytes entries, PEST0 and PEST1 531 */ 532 533 #define IODA3_PEST0_MMIO_CAUSE PPC_BIT(2) 534 #define IODA3_PEST0_CFG_READ PPC_BIT(3) 535 #define IODA3_PEST0_CFG_WRITE PPC_BIT(4) 536 #define IODA3_PEST0_TTYPE PPC_BITMASK(5,7) 537 #define PEST_TTYPE_DMA_WRITE 0 538 #define PEST_TTYPE_MSI 1 539 #define PEST_TTYPE_DMA_READ 2 540 #define PEST_TTYPE_DMA_READ_RESP 3 541 #define PEST_TTYPE_MMIO_LOAD 4 542 #define PEST_TTYPE_MMIO_STORE 5 543 #define PEST_TTYPE_OTHER 7 544 #define IODA3_PEST0_CA_RETURN PPC_BIT(8) 545 #define IODA3_PEST0_UR_RETURN PPC_BIT(9) 546 #define IODA3_PEST0_PCIE_NONFATAL PPC_BIT(10) 547 #define IODA3_PEST0_PCIE_FATAL PPC_BIT(11) 548 #define IODA3_PEST0_PARITY_UE PPC_BIT(13) 549 #define IODA3_PEST0_PCIE_CORRECTABLE PPC_BIT(14) 550 #define IODA3_PEST0_PCIE_INTERRUPT PPC_BIT(15) 551 #define IODA3_PEST0_MMIO_XLATE PPC_BIT(16) 552 #define IODA3_PEST0_IODA3_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 553 #define IODA3_PEST0_TCE_PAGE_FAULT PPC_BIT(18) 554 #define IODA3_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) 555 #define IODA3_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) 556 #define IODA3_PEST0_AIB_SIZE_INVALID PPC_BIT(21) 557 #define IODA3_PEST0_LEM_BIT PPC_BITMASK(26,31) 558 #define IODA3_PEST0_RID PPC_BITMASK(32,47) 559 #define IODA3_PEST0_MSI_DATA PPC_BITMASK(48,63) 560 561 #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3,63) 562 563 564 #endif /* PCI_HOST_PNV_PHB4_REGS_H */ 565