1 /*
2 * QEMU PowerPC XIVE interrupt controller model
3 *
4 * Copyright (c) 2017-2018, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #ifndef PPC_XIVE_H
11 #define PPC_XIVE_H
12
13 #include "hw/sysbus.h"
14 #include "hw/ppc/xive_regs.h"
15
16 /*
17 * XIVE Fabric (Interface between Source and Router)
18 */
19
20 typedef struct XiveFabric {
21 Object parent;
22 } XiveFabric;
23
24 #define TYPE_XIVE_FABRIC "xive-fabric"
25 #define XIVE_FABRIC(obj) \
26 OBJECT_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC)
27 #define XIVE_FABRIC_CLASS(klass) \
28 OBJECT_CLASS_CHECK(XiveFabricClass, (klass), TYPE_XIVE_FABRIC)
29 #define XIVE_FABRIC_GET_CLASS(obj) \
30 OBJECT_GET_CLASS(XiveFabricClass, (obj), TYPE_XIVE_FABRIC)
31
32 typedef struct XiveFabricClass {
33 InterfaceClass parent;
34 void (*notify)(XiveFabric *xf, uint32_t lisn);
35 } XiveFabricClass;
36
37 /*
38 * XIVE Interrupt Source
39 */
40
41 #define TYPE_XIVE_SOURCE_BASE "xive-source-base"
42 #define XIVE_SOURCE_BASE(obj) \
43 OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE_BASE)
44
45 #define TYPE_XIVE_SOURCE "xive-source"
46 #define XIVE_SOURCE(obj) OBJECT_CHECK(XiveSource, (obj), TYPE_XIVE_SOURCE)
47
48 /*
49 * XIVE Interrupt Source characteristics, which define how the ESB are
50 * controlled.
51 */
52 #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
53 #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
54
55 typedef struct XiveSource {
56 SysBusDevice parent;
57
58 /* IRQs */
59 uint32_t nr_irqs;
60 qemu_irq *qirqs;
61 unsigned long *lsi_map;
62 int32_t lsi_map_size; /* for VMSTATE_BITMAP */
63
64 /* PQ bits and LSI assertion bit */
65 uint8_t *status;
66
67 /* ESB memory region */
68 uint64_t esb_flags;
69 uint32_t esb_shift;
70 MemoryRegion esb_mmio;
71
72 /* KVM support */
73 void *esb_mmap;
74
75 XiveFabric *xive;
76 } XiveSource;
77
78 #define XIVE_SOURCE_BASE_CLASS(klass) \
79 OBJECT_CLASS_CHECK(XiveSourceClass, (klass), TYPE_XIVE_SOURCE_BASE)
80 #define XIVE_SOURCE_BASE_GET_CLASS(obj) \
81 OBJECT_GET_CLASS(XiveSourceClass, (obj), TYPE_XIVE_SOURCE_BASE)
82
83 typedef struct XiveSourceClass {
84 SysBusDeviceClass parent_class;
85
86 DeviceRealize parent_realize;
87 DeviceReset parent_reset;
88
89 void (*synchronize_state)(XiveSource *xsrc);
90 int (*pre_save)(XiveSource *xsrc);
91 int (*post_load)(XiveSource *xsrc, int version_id);
92 } XiveSourceClass;
93
94 /*
95 * ESB MMIO setting. Can be one page, for both source triggering and
96 * source management, or two different pages. See below for magic
97 * values.
98 */
99 #define XIVE_ESB_4K 12 /* PSI HB only */
100 #define XIVE_ESB_4K_2PAGE 13
101 #define XIVE_ESB_64K 16
102 #define XIVE_ESB_64K_2PAGE 17
103
xive_source_esb_has_2page(XiveSource * xsrc)104 static inline bool xive_source_esb_has_2page(XiveSource *xsrc)
105 {
106 return xsrc->esb_shift == XIVE_ESB_64K_2PAGE ||
107 xsrc->esb_shift == XIVE_ESB_4K_2PAGE;
108 }
109
110 /* The trigger page is always the first/even page */
xive_source_esb_page(XiveSource * xsrc,uint32_t srcno)111 static inline hwaddr xive_source_esb_page(XiveSource *xsrc, uint32_t srcno)
112 {
113 assert(srcno < xsrc->nr_irqs);
114 return (1ull << xsrc->esb_shift) * srcno;
115 }
116
117 /* In a two pages ESB MMIO setting, the odd page is for management */
xive_source_esb_mgmt(XiveSource * xsrc,int srcno)118 static inline hwaddr xive_source_esb_mgmt(XiveSource *xsrc, int srcno)
119 {
120 hwaddr addr = xive_source_esb_page(xsrc, srcno);
121
122 if (xive_source_esb_has_2page(xsrc)) {
123 addr += (1 << (xsrc->esb_shift - 1));
124 }
125
126 return addr;
127 }
128
129 /*
130 * Each interrupt source has a 2-bit state machine which can be
131 * controlled by MMIO. P indicates that an interrupt is pending (has
132 * been sent to a queue and is waiting for an EOI). Q indicates that
133 * the interrupt has been triggered while pending.
134 *
135 * This acts as a coalescing mechanism in order to guarantee that a
136 * given interrupt only occurs at most once in a queue.
137 *
138 * When doing an EOI, the Q bit will indicate if the interrupt
139 * needs to be re-triggered.
140 */
141 #define XIVE_STATUS_ASSERTED 0x4 /* Extra bit for LSI */
142 #define XIVE_ESB_VAL_P 0x2
143 #define XIVE_ESB_VAL_Q 0x1
144
145 #define XIVE_ESB_RESET 0x0
146 #define XIVE_ESB_PENDING XIVE_ESB_VAL_P
147 #define XIVE_ESB_QUEUED (XIVE_ESB_VAL_P | XIVE_ESB_VAL_Q)
148 #define XIVE_ESB_OFF XIVE_ESB_VAL_Q
149
150 /*
151 * "magic" Event State Buffer (ESB) MMIO offsets.
152 *
153 * The following offsets into the ESB MMIO allow to read or manipulate
154 * the PQ bits. They must be used with an 8-byte load instruction.
155 * They all return the previous state of the interrupt (atomically).
156 *
157 * Additionally, some ESB pages support doing an EOI via a store and
158 * some ESBs support doing a trigger via a separate trigger page.
159 */
160 #define XIVE_ESB_STORE_EOI 0x400 /* Store */
161 #define XIVE_ESB_LOAD_EOI 0x000 /* Load */
162 #define XIVE_ESB_GET 0x800 /* Load */
163 #define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
164 #define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
165 #define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
166 #define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
167
168 uint8_t xive_source_esb_get(XiveSource *xsrc, uint32_t srcno);
169 uint8_t xive_source_esb_set(XiveSource *xsrc, uint32_t srcno, uint8_t pq);
170
171 void xive_source_pic_print_info(XiveSource *xsrc, uint32_t offset,
172 Monitor *mon);
173
xive_source_qirq(XiveSource * xsrc,uint32_t srcno)174 static inline qemu_irq xive_source_qirq(XiveSource *xsrc, uint32_t srcno)
175 {
176 assert(srcno < xsrc->nr_irqs);
177 return xsrc->qirqs[srcno];
178 }
179
xive_source_irq_is_lsi(XiveSource * xsrc,uint32_t srcno)180 static inline bool xive_source_irq_is_lsi(XiveSource *xsrc, uint32_t srcno)
181 {
182 assert(srcno < xsrc->nr_irqs);
183 return test_bit(srcno, xsrc->lsi_map);
184 }
185
xive_source_irq_set(XiveSource * xsrc,uint32_t srcno,bool lsi)186 static inline void xive_source_irq_set(XiveSource *xsrc, uint32_t srcno,
187 bool lsi)
188 {
189 assert(srcno < xsrc->nr_irqs);
190 if (lsi) {
191 bitmap_set(xsrc->lsi_map, srcno, 1);
192 }
193 }
194
195 /*
196 * XIVE Router
197 */
198
199 typedef struct XiveRouter {
200 SysBusDevice parent;
201
202 uint32_t chip_id;
203 } XiveRouter;
204
205 #define TYPE_XIVE_ROUTER "xive-router"
206 #define XIVE_ROUTER(obj) \
207 OBJECT_CHECK(XiveRouter, (obj), TYPE_XIVE_ROUTER)
208 #define XIVE_ROUTER_CLASS(klass) \
209 OBJECT_CLASS_CHECK(XiveRouterClass, (klass), TYPE_XIVE_ROUTER)
210 #define XIVE_ROUTER_GET_CLASS(obj) \
211 OBJECT_GET_CLASS(XiveRouterClass, (obj), TYPE_XIVE_ROUTER)
212
213 typedef struct XiveRouterClass {
214 SysBusDeviceClass parent;
215
216 /* XIVE table accessors */
217 int (*get_eas)(XiveRouter *xrtr, uint32_t lisn, XiveEAS *eas);
218 int (*set_eas)(XiveRouter *xrtr, uint32_t lisn, XiveEAS *eas);
219 int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
220 XiveEND *end);
221 int (*set_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
222 XiveEND *end);
223 int (*get_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
224 XiveNVT *nvt);
225 int (*set_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
226 XiveNVT *nvt);
227 int (*get_nvt_info)(XiveRouter *xrtr, PowerPCCPU *cpu, uint8_t *nvt_blk,
228 uint32_t *nvt_idx);
229 } XiveRouterClass;
230
231 void xive_router_print_eas(XiveRouter *xrtr, uint32_t lisn, XiveEAS *eas,
232 Monitor *mon);
233 int xive_router_get_eas(XiveRouter *xrtr, uint32_t lisn, XiveEAS *eas);
234 int xive_router_set_eas(XiveRouter *xrtr, uint32_t lisn, XiveEAS *eas);
235 int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
236 XiveEND *end);
237 int xive_router_set_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
238 XiveEND *end);
239 int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
240 XiveNVT *nvt);
241 int xive_router_set_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
242 XiveNVT *nvt);
243 void xive_router_notify(XiveFabric *xf, uint32_t lisn);
244
245 /*
246 * XIVE END ESBs
247 */
248
249 #define TYPE_XIVE_END_SOURCE "xive-end-source"
250 #define XIVE_END_SOURCE(obj) \
251 OBJECT_CHECK(XiveENDSource, (obj), TYPE_XIVE_END_SOURCE)
252
253 typedef struct XiveENDSource {
254 SysBusDevice parent;
255
256 uint32_t nr_ends;
257
258 /* ESB memory region */
259 uint32_t esb_shift;
260 MemoryRegion esb_mmio;
261
262 XiveRouter *xrtr;
263 } XiveENDSource;
264
265 /*
266 * For legacy compatibility, the exceptions define up to 256 different
267 * priorities. P9 implements only 9 levels : 8 active levels [0 - 7]
268 * and the least favored level 0xFF.
269 */
270 #define XIVE_PRIORITY_MAX 7
271
272 void xive_end_reset(XiveEND *end);
273
274
275 /*
276 * XIVE Thread interrupt Management (TM) context
277 */
278
279 #define TYPE_XIVE_TCTX_BASE "xive-tctx-base"
280 #define XIVE_TCTX_BASE(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX_BASE)
281
282 #define TYPE_XIVE_TCTX "xive-tctx"
283 #define XIVE_TCTX(obj) OBJECT_CHECK(XiveTCTX, (obj), TYPE_XIVE_TCTX)
284
285 /*
286 * XIVE Thread interrupt Management register rings :
287 *
288 * QW-0 User event-based exception state
289 * QW-1 O/S OS context for priority management, interrupt acks
290 * QW-2 Pool hypervisor context for virtual processor being dispatched
291 * QW-3 Physical for the security monitor to manage the entire context
292 */
293 #define TM_RING_COUNT 4
294 #define TM_RING_SIZE 0x10
295
296 typedef struct XiveTCTX {
297 DeviceState parent_obj;
298
299 CPUState *cs;
300 qemu_irq hv_output;
301 qemu_irq os_output;
302
303 uint8_t regs[TM_RING_COUNT * TM_RING_SIZE];
304
305 XiveRouter *xrtr;
306
307 /* KVM support */
308 uint64_t opal[2];
309 } XiveTCTX;
310
311 #define XIVE_TCTX_BASE_CLASS(klass) \
312 OBJECT_CLASS_CHECK(XiveTCTXClass, (klass), TYPE_XIVE_TCTX_BASE)
313 #define XIVE_TCTX_BASE_GET_CLASS(obj) \
314 OBJECT_GET_CLASS(XiveTCTXClass, (obj), TYPE_XIVE_TCTX_BASE)
315
316 typedef struct XiveTCTXClass {
317 DeviceClass parent_class;
318
319 DeviceRealize parent_realize;
320
321 void (*synchronize_state)(XiveTCTX *tctx);
322 int (*pre_save)(XiveTCTX *tctx);
323 int (*post_load)(XiveTCTX *tctx, int version_id);
324 } XiveTCTXClass;
325
326 /*
327 * XIVE Thread Interrupt Management Aera (TIMA)
328 */
329 extern const MemoryRegionOps xive_tm_ops;
330
331 void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon);
332 Object *xive_tctx_create(Object *cpu, const char *type, XiveRouter *xrtr,
333 Error **errp);
334
335 #endif /* PPC_XIVE_H */
336