1 /*****************************************************************************
2 * Copyright (c) 2013 IBM Corporation
3 * All rights reserved.
4 * This program and the accompanying materials
5 * are made available under the terms of the BSD License
6 * which accompanies this distribution, and is available at
7 * http://www.opensource.org/licenses/bsd-license.php
8 *
9 * Contributors:
10 * IBM Corporation - initial implementation
11 *****************************************************************************/
12
13 #include <string.h>
14 #include "usb.h"
15 #include "usb-core.h"
16 #include "usb-xhci.h"
17 #include "tools.h"
18 #include "paflof.h"
19
20 #undef XHCI_DEBUG
21 //#define XHCI_DEBUG
22 #ifdef XHCI_DEBUG
23 #define dprintf(_x ...) do { printf("%s: ", __func__); printf(_x); } while (0)
24 #else
25 #define dprintf(_x ...)
26 #endif
27
28 struct port_state ps_array_usb2[] = {
29 {1, 0, 0, 0, PORTSC_PLS_U0, "ERROR"}
30 };
31
32 struct port_state ps_array_usb3[] = {
33 {0, 0, 0, 0, PORTSC_PLS_DISABLED, "Powered-OFF"},
34 {1, 0, 0, 0, PORTSC_PLS_POLLING, "Polling"},
35 {1, 0, 0, 0, PORTSC_PLS_U0, "Polling"},
36 {1, 0, 0, 0, PORTSC_PLS_RXDETECT, "*** Disconnected ***"},
37 {1, 0, 0, 0, PORTSC_PLS_DISABLED, "Disabled"},
38 {1, 0, 0, 0, PORTSC_PLS_INACTIVE, "Error"},
39 {1, 0, 0, 0, PORTSC_PLS_TEST_MODE,"Loopback"},
40 {1, 0, 0, 0, PORTSC_PLS_COMP_MODE,"Compliancek"},
41 {1, 1, 0, 1, PORTSC_PLS_U0, "****** Reset ******"},
42 {1, 1, 1, 0, PORTSC_PLS_U0, "****** Enabled ******"},
43 };
44
dump_xhci_regs(struct xhci_hcd * xhcd)45 static void dump_xhci_regs(struct xhci_hcd *xhcd)
46 {
47 #ifdef XHCI_DEBUG
48 struct xhci_cap_regs *cap;
49 struct xhci_op_regs *op;
50 struct xhci_run_regs *run;
51
52 cap = xhcd->cap_regs;
53 op = xhcd->op_regs;
54 run = xhcd->run_regs;
55
56 dprintf("\n");
57 dprintf(" - CAPLENGTH %02X\n", read_reg8 (&cap->caplength));
58 dprintf(" - HCIVERSION %04X\n", read_reg16(&cap->hciversion));
59 dprintf(" - HCSPARAMS1 %08X\n", read_reg32(&cap->hcsparams1));
60 dprintf(" - HCSPARAMS2 %08X\n", read_reg32(&cap->hcsparams2));
61 dprintf(" - HCSPARAMS3 %08X\n", read_reg32(&cap->hcsparams3));
62 dprintf(" - HCCPARAMS %08X\n", read_reg32(&cap->hccparams));
63 dprintf(" - DBOFF %08X\n", read_reg32(&cap->dboff));
64 dprintf(" - RTSOFF %08X\n", read_reg32(&cap->rtsoff));
65 dprintf("\n");
66
67 dprintf(" - USBCMD %08X\n", read_reg32(&op->usbcmd));
68 dprintf(" - USBSTS %08X\n", read_reg32(&op->usbsts));
69 dprintf(" - PAGESIZE %08X\n", read_reg32(&op->pagesize));
70 dprintf(" - DNCTRL %08X\n", read_reg32(&op->dnctrl));
71 dprintf(" - CRCR %016llX\n", read_reg64(&op->crcr));
72 dprintf(" - DCBAAP %016llX\n", read_reg64(&op->dcbaap));
73 dprintf(" - CONFIG %08X\n", read_reg32(&op->config));
74 dprintf("\n");
75
76 dprintf(" - MFINDEX %08X\n", read_reg32(&run->mfindex));
77 dprintf("\n");
78 #endif
79 }
80
print_port_status(struct xhci_port_regs * prs)81 static void print_port_status(struct xhci_port_regs *prs)
82 {
83 #ifdef XHCI_DEBUG
84 uint32_t portsc;
85 uint32_t CCS, PED, PP, PLS, i, PR = 0;
86
87 portsc = read_reg32(&prs->portsc);
88 dprintf("portsc %08x portpmsc %08x portli %08x\n",
89 portsc,
90 read_reg32(&prs->portpmsc),
91 read_reg32(&prs->portli));
92
93 if (portsc & PORTSC_CCS) {
94 printf("CCS ");
95 CCS = 1;
96 }
97 if (portsc & PORTSC_PED) {
98 printf("PED ");
99 PED = 1;
100 }
101 if (portsc & PORTSC_OCA)
102 printf("OCA ");
103 if (portsc & PORTSC_PR)
104 printf("OCA ");
105 PLS = (portsc & PORTSC_PLS_MASK) >> 5;
106 printf("PLS:%d ", PLS);
107 if (portsc & PORTSC_PP) {
108 printf("PP ");
109 PP = 1;
110 }
111 printf("PS:%d ", (portsc & PORTSC_PS_MASK) >> 10);
112 printf("PIC:%d ", (portsc & PORTSC_PIC_MASK) >> 14);
113 if (portsc & PORTSC_LWS)
114 printf("LWS ");
115 if (portsc & PORTSC_CSC)
116 printf("CSC ");
117 if (portsc & PORTSC_PEC)
118 printf("PEC ");
119 if (portsc & PORTSC_WRC)
120 printf("WRC ");
121 if (portsc & PORTSC_OCC)
122 printf("OCC ");
123 if (portsc & PORTSC_PRC)
124 printf("PRC ");
125 if (portsc & PORTSC_PLC)
126 printf("PLC ");
127 if (portsc & PORTSC_CEC)
128 printf("CEC ");
129 if (portsc & PORTSC_CAS)
130 printf("CAS ");
131 if (portsc & PORTSC_WCE)
132 printf("WCE ");
133 if (portsc & PORTSC_WDE)
134 printf("WDE ");
135 if (portsc & PORTSC_WOE)
136 printf("WOE ");
137 if (portsc & PORTSC_DR)
138 printf("DR ");
139 if (portsc & PORTSC_WPR)
140 printf("WPR ");
141 printf("\n");
142
143 for (i = 0 ; i < (sizeof(ps_array_usb3)/sizeof(struct port_state)); i++) {
144 if (PP == ps_array_usb3[i].PP) {
145 if (CCS == ps_array_usb3[i].CCS) {
146 if (PED == ps_array_usb3[i].PED) {
147 if (PR == ps_array_usb3[i].PR) {
148 dprintf("%s - PLS %d\n", ps_array_usb3[i].state, PLS);
149 break;
150 }
151 }
152 }
153 }
154 }
155 #endif
156
157 }
158
xhci_is_hc_ready(uint32_t * usbsts)159 static inline bool xhci_is_hc_ready(uint32_t *usbsts)
160 {
161 return !(read_reg32(usbsts) & XHCI_USBSTS_CNR);
162 }
163
xhci_wait_for_cnr(uint32_t * usbsts)164 static inline bool xhci_wait_for_cnr(uint32_t *usbsts)
165 {
166 /* Standard:
167 * Note: The xHC should halt within 16 ms. of software clearing the
168 * R/S bit to ‘0’.
169 * Give some more time... 32ms
170 */
171 int count = 320;
172 dprintf("Waiting for Controller ready ..");
173 while (!xhci_is_hc_ready(usbsts)) {
174 dprintf(".");
175 count--;
176 if (!count) {
177 dprintf(" failed %08X\n", read_reg32(usbsts));
178 return false;
179 }
180 SLOF_usleep(100);
181 }
182 dprintf(" done\n");
183 return true;
184 }
185
xhci_hcd_set_runstop(struct xhci_op_regs * op,bool run_req)186 static bool xhci_hcd_set_runstop(struct xhci_op_regs *op, bool run_req)
187 {
188 uint32_t reg;
189
190 dprintf("Request %s\n", run_req ? "RUN" : "STOP");
191 if (!xhci_is_hc_ready(&op->usbsts)) {
192 dprintf("Controller not ready\n");
193 return false;
194 }
195
196 reg = read_reg32(&op->usbcmd);
197 if (run_req)
198 reg |= run_req;
199 else
200 reg &= (uint32_t)~1;
201 dprintf("writing %08X\n", reg);
202 write_reg32(&op->usbcmd, reg);
203 mb();
204 xhci_wait_for_cnr(&op->usbsts);
205 return true;
206 }
207
xhci_hcd_reset(struct xhci_op_regs * op)208 static bool xhci_hcd_reset(struct xhci_op_regs *op)
209 {
210 uint32_t reg;
211
212 /* Check if the controller is halted, else halt it */
213 if (!(read_reg32(&op->usbsts) & XHCI_USBSTS_HCH)) {
214 dprintf("HCHalted not set\n");
215 if (!xhci_hcd_set_runstop(op, false))
216 return false;
217 }
218
219 if (read_reg32(&op->usbsts) & XHCI_USBSTS_CNR) {
220 dprintf("Controller not ready\n");
221 return false;
222 }
223
224 reg = read_reg32(&op->usbcmd) | XHCI_USBCMD_HCRST;
225 /* Ready to Reset the controller now */
226 write_reg32(&op->usbcmd, reg);
227 xhci_wait_for_cnr(&op->usbsts);
228 return true;
229 }
230
xhci_handle_cmd_completion(struct xhci_hcd * xhcd,struct xhci_event_trb * event)231 static void xhci_handle_cmd_completion(struct xhci_hcd *xhcd,
232 struct xhci_event_trb *event)
233 {
234 uint32_t flags, slot_id, status;
235
236 status = le32_to_cpu(event->status);
237 flags = le32_to_cpu(event->flags);
238 slot_id = TRB_SLOT_ID(flags);
239 if (TRB_STATUS(status) == COMP_SUCCESS)
240 xhcd->slot_id = slot_id;
241 else
242 xhcd->slot_id = 0;
243 }
244
xhci_poll_event(struct xhci_hcd * xhcd,uint32_t event_type)245 static uint64_t xhci_poll_event(struct xhci_hcd *xhcd,
246 uint32_t event_type)
247 {
248 struct xhci_event_trb *event;
249 uint64_t val, retval = 0;
250 uint32_t flags, time;
251 int index;
252
253 mb();
254 event = (struct xhci_event_trb *)xhcd->ering.deq;
255 flags = le32_to_cpu(event->flags);
256
257 dprintf("Reading from event ptr %p %08x\n", event, flags);
258 time = SLOF_GetTimer() + ((event_type == XHCI_POLL_NO_WAIT)? 0: USB_TIMEOUT);
259
260 while ((flags & TRB_CYCLE_STATE) != xhcd->ering.cycle_state) {
261 mb();
262 flags = le32_to_cpu(event->flags);
263 if (time < SLOF_GetTimer())
264 return 0;
265 }
266
267 mb();
268 flags = le32_to_cpu(event->flags);
269 switch(TRB_TYPE(flags))
270 {
271 case TRB_CMD_COMPLETION:
272 dprintf("CMD Completion\n");
273 xhci_handle_cmd_completion(xhcd, event);
274 break;
275 case TRB_PORT_STATUS:
276 dprintf("Port status event\n");
277 break;
278 case TRB_TRANSFER_EVENT:
279 dprintf("XFER event addr %16lx, status %08x, flags %08x\n",
280 le64_to_cpu(event->addr),
281 le32_to_cpu(event->status),
282 le32_to_cpu(event->flags));
283 break;
284 default:
285 printf("TRB_TYPE %d\n", TRB_TYPE(flags));
286 dprintf("Event addr %16lx, status %08x, flags %08x state %d\n",
287 le64_to_cpu(event->addr),
288 le32_to_cpu(event->status),
289 flags, xhcd->ering.cycle_state);
290 break;
291 }
292 xhcd->ering.deq = (uint64_t) (event + 1);
293 retval = le64_to_cpu(event->addr);
294
295 event->addr = 0;
296 event->status = 0;
297 event->flags = cpu_to_le32(xhcd->ering.cycle_state);
298
299 index = xhcd->ering.deq - (uint64_t)xhcd->ering.trbs;
300 val = xhcd->ering.trbs_dma;
301 val += (index % XHCI_EVENT_TRBS_SIZE);
302 if (!(index % XHCI_EVENT_TRBS_SIZE)) {
303 xhcd->ering.deq = (uint64_t)xhcd->ering.trbs;
304 xhcd->ering.cycle_state = xhcd->ering.cycle_state ? 0 : 1;
305 dprintf("Rounding %d\n", xhcd->ering.cycle_state);
306 }
307 dprintf("Update start %x deq %x index %d\n",
308 xhcd->ering.trbs_dma, val, index/sizeof(*event));
309 write_reg64(&xhcd->run_regs->irs[0].erdp, val);
310
311 if (retval == 0)
312 return (uint64_t)event;
313 else
314 return retval;
315 }
316
xhci_send_cmd(struct xhci_hcd * xhcd,uint32_t field1,uint32_t field2,uint32_t field3,uint32_t field4)317 static void xhci_send_cmd(struct xhci_hcd *xhcd, uint32_t field1,
318 uint32_t field2, uint32_t field3, uint32_t field4)
319 {
320 struct xhci_db_regs *dbr;
321 struct xhci_command_trb *cmd;
322 uint32_t val, cycle_state;
323
324 dbr = xhcd->db_regs;
325 cmd = (struct xhci_command_trb *)xhcd->crseg.enq;
326
327 cmd->field[0] = cpu_to_le32(field1);
328 cmd->field[1] = cpu_to_le32(field2);
329 cmd->field[2] = cpu_to_le32(field3);
330
331 val = le32_to_cpu(cmd->field[3]);
332 cycle_state = (val & 0x1) ? 0 : 1;
333 val = field4 | cycle_state;
334 cmd->field[3] = cpu_to_le32(val);
335
336 dprintf("CMD %016lx val %08x cycle_state %d field1 %08x, field2 %08x, field3 %08x field4 %08x\n",
337 cmd, val, cycle_state,
338 le32_to_cpu(cmd->field[0]),
339 le32_to_cpu(cmd->field[1]),
340 le32_to_cpu(cmd->field[2]),
341 le32_to_cpu(cmd->field[3])
342 );
343
344 /* Ring the doorbell */
345 write_reg32(&dbr->db[0], 0);
346 xhci_poll_event(xhcd, 0);
347 cmd++;
348 xhcd->crseg.enq = (uint64_t)cmd;
349 return;
350 }
351
xhci_send_enable_slot(struct xhci_hcd * xhcd,uint32_t port)352 static void xhci_send_enable_slot(struct xhci_hcd *xhcd, uint32_t port)
353 {
354 uint32_t field1, field2, field3, field4;
355
356 field1 = 0;
357 field2 = 0;
358 field3 = 0;
359 field4 = TRB_CMD_TYPE(TRB_ENABLE_SLOT);
360 xhci_send_cmd(xhcd, field1, field2, field3, field4);
361 }
362
xhci_send_addr_device(struct xhci_hcd * xhcd,uint32_t slot_id,uint64_t dma_in_ctx)363 static void xhci_send_addr_device(struct xhci_hcd *xhcd, uint32_t slot_id,
364 uint64_t dma_in_ctx)
365 {
366 uint32_t field1, field2, field3, field4;
367
368 dprintf("Address device %lx, low %x, high %x\n", dma_in_ctx,
369 TRB_ADDR_LOW(dma_in_ctx),
370 TRB_ADDR_HIGH(dma_in_ctx));
371 field1 = TRB_ADDR_LOW(dma_in_ctx) & ~0xF;
372 field2 = TRB_ADDR_HIGH(dma_in_ctx);
373 field3 = 0;
374 field4 = TRB_CMD_TYPE(TRB_ADDRESS_DEV) | TRB_CMD_SLOT_ID(slot_id);
375 xhci_send_cmd(xhcd, field1, field2, field3, field4);
376 }
377
xhci_get_epno(struct usb_pipe * pipe)378 static uint32_t xhci_get_epno(struct usb_pipe *pipe)
379 {
380 uint32_t x_epno;
381 x_epno = pipe->dir | 2 * pipe->epno;
382 dprintf("EPno %d:%d DIR %d\n", pipe->epno, x_epno, pipe->dir);
383 return x_epno;
384 }
385
xhci_configure_ep(struct xhci_hcd * xhcd,uint32_t slot_id,uint64_t dma_in_ctx)386 static void xhci_configure_ep(struct xhci_hcd *xhcd, uint32_t slot_id,
387 uint64_t dma_in_ctx)
388 {
389 uint32_t field1, field2, field3, field4;
390
391 dprintf("Configure EP %lx, low %x, high %x\n", dma_in_ctx,
392 TRB_ADDR_LOW(dma_in_ctx),
393 TRB_ADDR_HIGH(dma_in_ctx));
394 field1 = TRB_ADDR_LOW(dma_in_ctx) & ~0xF;
395 field2 = TRB_ADDR_HIGH(dma_in_ctx);
396 field3 = 0;
397 field4 = TRB_CMD_TYPE(TRB_CONFIG_EP) | TRB_CMD_SLOT_ID(slot_id);
398 xhci_send_cmd(xhcd, field1, field2, field3, field4);
399 }
400
xhci_init_seg(struct xhci_seg * seg,uint32_t size,uint32_t type)401 static void xhci_init_seg(struct xhci_seg *seg, uint32_t size, uint32_t type)
402 {
403 struct xhci_link_trb *link;
404
405 seg->size = size / XHCI_TRB_SIZE;
406 seg->next = NULL;
407 seg->type = type;
408 seg->cycle_state = 1;
409 seg->enq = (uint64_t)seg->trbs;
410 seg->deq = (uint64_t)seg->trbs;
411 memset((void *)seg->trbs, 0, size);
412
413 if (type != TYPE_EVENT) {
414 link =(struct xhci_link_trb *) (seg->trbs + seg->size - 1);
415 link->addr = cpu_to_le64(seg->trbs_dma);
416 link->field2 = 0;
417 link->field3 = cpu_to_le32(0x1 | TRB_CMD_TYPE(TRB_LINK));
418 }
419 return;
420 }
421
xhci_alloc_seg(struct xhci_seg * seg,uint32_t size,uint32_t type)422 static bool xhci_alloc_seg(struct xhci_seg *seg, uint32_t size, uint32_t type)
423 {
424 seg->trbs = (union xhci_trb *)SLOF_dma_alloc(size);
425 if (!seg->trbs) {
426 dprintf("Alloc failed\n");
427 return false;
428 }
429 xhci_init_seg(seg, size, type);
430 seg->trbs_dma = SLOF_dma_map_in((void *)seg->trbs, size, false);
431
432 dprintf(" TRBs %016lX TRBS-DMA %016lX\n", seg->trbs, seg->trbs_dma);
433 return true;
434 }
435
xhci_free_seg(struct xhci_seg * seg,uint32_t size)436 static void xhci_free_seg(struct xhci_seg *seg, uint32_t size)
437 {
438 if (seg->trbs) {
439 dprintf(" TRBs %016lX TRBS-DMA %016lX size %x\n", seg->trbs, seg->trbs_dma, size);
440 SLOF_dma_map_out(seg->trbs_dma, (void *)seg->trbs, size);
441 SLOF_dma_free((void *)seg->trbs, size);
442 }
443 memset(seg, 0, sizeof(*seg));
444 }
445
446 #define CTX_SIZE(x) ( (x) ? 64 : 32 )
447
xhci_alloc_ctx(struct xhci_ctx * ctx,uint32_t size,uint32_t type)448 static bool xhci_alloc_ctx(struct xhci_ctx *ctx, uint32_t size, uint32_t type)
449 {
450 ctx->addr = (uint8_t *)SLOF_dma_alloc(size);
451 if (!ctx->addr) {
452 dprintf("Alloc failed\n");
453 return false;
454 }
455 ctx->size = size;
456 ctx->type = type;
457 memset((void *)ctx->addr, 0, size);
458 ctx->dma_addr = SLOF_dma_map_in((void *)ctx->addr, size, false);
459 dprintf("ctx %llx, ctx_dma %llx\n", ctx->addr, ctx->dma_addr);
460 return true;
461 }
462
xhci_get_control_ctx(struct xhci_ctx * ctx)463 static struct xhci_control_ctx *xhci_get_control_ctx(struct xhci_ctx *ctx)
464 {
465 if (ctx->type == XHCI_CTX_TYPE_INPUT)
466 return (struct xhci_control_ctx *) ctx->addr;
467 return NULL;
468 }
469
xhci_get_slot_ctx(struct xhci_ctx * ctx,uint32_t ctx_size)470 static struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctx *ctx, uint32_t ctx_size)
471 {
472 uint32_t offset = 0;
473
474 if (ctx->type == XHCI_CTX_TYPE_INPUT)
475 offset += ctx_size;
476 return (struct xhci_slot_ctx *)(ctx->addr + offset);
477 }
478
xhci_get_ep0_ctx(struct xhci_ctx * ctx,uint32_t ctx_size)479 static struct xhci_ep_ctx *xhci_get_ep0_ctx(struct xhci_ctx *ctx, uint32_t ctx_size)
480 {
481 uint32_t offset = 0;
482
483 offset = ctx_size;
484 if (ctx->type == XHCI_CTX_TYPE_INPUT)
485 offset += ctx_size;
486 return (struct xhci_ep_ctx *)(ctx->addr + offset);
487 }
488
xhci_get_ep_ctx(struct xhci_ctx * ctx,uint32_t ctx_size,uint32_t epno)489 static struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctx *ctx, uint32_t ctx_size,
490 uint32_t epno)
491 {
492 uint32_t offset = 0;
493
494 offset = ctx_size * epno;
495 if (ctx->type == XHCI_CTX_TYPE_INPUT)
496 offset += ctx_size;
497 return (struct xhci_ep_ctx *)(ctx->addr + offset);
498 }
499
xhci_free_ctx(struct xhci_ctx * ctx,uint32_t size)500 static void xhci_free_ctx(struct xhci_ctx *ctx, uint32_t size)
501 {
502 SLOF_dma_map_out(ctx->dma_addr, (void *)ctx->addr, size);
503 SLOF_dma_free((void *)ctx->addr, size);
504 }
505
usb_control_max_packet(uint32_t speed)506 static uint32_t usb_control_max_packet(uint32_t speed)
507 {
508 uint32_t max_packet = 0;
509
510 switch(speed)
511 {
512 case USB_LOW_SPEED:
513 max_packet = 8;
514 break;
515 case USB_FULL_SPEED:
516 max_packet = 8;
517 break;
518 case USB_HIGH_SPEED:
519 max_packet = 64;
520 break;
521 case USB_SUPER_SPEED:
522 max_packet = 512;
523 break;
524 default:
525 /* should not reach here */
526 dprintf("Unknown speed\n");
527 }
528 return max_packet;
529 }
530
xhci_alloc_dev(struct xhci_hcd * xhcd,struct usb_dev * hub,uint32_t slot_id,uint32_t port,uint32_t slotspeed)531 static bool xhci_alloc_dev(struct xhci_hcd *xhcd, struct usb_dev *hub,
532 uint32_t slot_id, uint32_t port, uint32_t slotspeed)
533 {
534 struct usb_dev *dev;
535 struct xhci_dev *xdev;
536 struct xhci_slot_ctx *slot;
537 struct xhci_control_ctx *ctrl;
538 struct xhci_ep_ctx *ep0;
539 uint32_t ctx_size, val;
540 uint16_t max_packet;
541 uint32_t newport, rootport;
542
543 if (slot_id > XHCI_CONFIG_MAX_SLOT) {
544 printf("USB3 slot ID %d is too high (max is %d)\n", slot_id,
545 XHCI_CONFIG_MAX_SLOT);
546 return false;
547 }
548
549 ctx_size = CTX_SIZE(xhcd->hcc_csz_64);
550 xdev = &xhcd->xdevs[slot_id];
551 xdev->slot_id = slot_id;
552 xdev->ctx_size = ctx_size;
553
554 /* 4.3.3 Device Slot initialization */
555 /* Step 1 */
556 if (!xhci_alloc_ctx(&xdev->in_ctx, XHCI_CTX_BUF_SIZE, XHCI_CTX_TYPE_INPUT)) {
557 dprintf("Failed allocating in_ctx\n");
558 return false;
559 }
560
561 /* Step 2 */
562 ctrl = xhci_get_control_ctx(&xdev->in_ctx);
563 ctrl->a_flags = cpu_to_le32(0x3); /* A0, A1 */
564 ctrl->d_flags = 0;
565
566 /* Step 3 */
567 slot = xhci_get_slot_ctx(&xdev->in_ctx, ctx_size);
568 newport = rootport = port + 1;
569 val = newport & 0xf;
570 for (dev = hub; dev != NULL; dev = dev->hub) {
571 val = (val << 4) | (dev->port & 0xf); /* Build route string */
572 rootport = dev->port;
573 }
574 val >>= 4; /* Remove root hub ID from the string */
575 val |= LAST_CONTEXT(1) | slotspeed;
576 slot->field1 = cpu_to_le32(val);
577 slot->field2 = cpu_to_le32(ROOT_HUB_PORT(rootport));
578
579 /* Step 4 */
580 if (!xhci_alloc_seg(&xdev->control, XHCI_CONTROL_TRBS_SIZE, TYPE_CTRL)) {
581 dprintf("Failed allocating control\n");
582 goto fail_in_ctx;
583 }
584
585 /* Step 5 */
586 ep0 = xhci_get_ep0_ctx(&xdev->in_ctx, ctx_size);
587 val = 0;
588 max_packet = usb_control_max_packet(USB_SUPER_SPEED);
589 max_packet = 64;
590 val = EP_TYPE(EP_CTRL) | MAX_BURST(0) | ERROR_COUNT(3) |
591 MAX_PACKET_SIZE(max_packet);
592 ep0->field2 = cpu_to_le32(val);;
593 ep0->deq_addr = cpu_to_le64(xdev->control.trbs_dma | xdev->control.cycle_state);
594 ep0->field4 = cpu_to_le32(8);
595
596 /* Step 6 */
597 if (!xhci_alloc_ctx(&xdev->out_ctx, XHCI_CTX_BUF_SIZE, XHCI_CTX_TYPE_DEVICE)) {
598 dprintf("Failed allocating out_ctx\n");
599 goto fail_control_seg;
600 }
601
602 /* Step 7 */
603 xhcd->dcbaap[slot_id] = cpu_to_le64(xdev->out_ctx.dma_addr);
604
605 /* Step 8 */
606 slot = xhci_get_slot_ctx(&xdev->out_ctx, ctx_size);
607 ep0 = xhci_get_ep0_ctx(&xdev->out_ctx, ctx_size);
608
609 dprintf("Slot State %x \n", SLOT_STATE(le32_to_cpu(slot->field4)));
610 xhci_send_addr_device(xhcd, slot_id, xdev->in_ctx.dma_addr);
611 mb();
612 dprintf("Slot State %x \n", SLOT_STATE(le32_to_cpu(slot->field4)));
613
614 dprintf("EP0 f0 %08X f1 %08X %016lX %08X\n",
615 le32_to_cpu(ep0->field1),
616 le32_to_cpu(ep0->field2),
617 le64_to_cpu(ep0->deq_addr),
618 le32_to_cpu(ep0->field4));
619
620 /* Step 9 - configure ep */
621 ctrl->a_flags = cpu_to_le32(0x1); /* A0 */
622 ctrl->d_flags = 0;
623 xhci_configure_ep(xhcd, slot_id, xdev->in_ctx.dma_addr);
624 mb();
625 dprintf("Slot State %x \n", SLOT_STATE(le32_to_cpu(slot->field4)));
626 dprintf("USB Device address %d \n", USB_DEV_ADDRESS(le32_to_cpu(slot->field4)));
627 dprintf("EP0 f0 %08X f1 %08X %016lX %08X\n",
628 le32_to_cpu(ep0->field1),
629 le32_to_cpu(ep0->field2),
630 le64_to_cpu(ep0->deq_addr),
631 le32_to_cpu(ep0->field4));
632
633 dev = usb_devpool_get();
634 dprintf("allocated device %p\n", dev);
635 dev->hcidev = xhcd->hcidev;
636 dev->speed = USB_SUPER_SPEED;
637 dev->addr = USB_DEV_ADDRESS(slot->field4);
638 dev->port = newport;
639 dev->hub = hub;
640 dev->priv = xdev;
641 xdev->dev = dev;
642 if (usb_setup_new_device(dev, newport)) {
643 usb_slof_populate_new_device(dev);
644 return true;
645 }
646
647 xhci_free_ctx(&xdev->out_ctx, XHCI_CTX_BUF_SIZE);
648 fail_control_seg:
649 xhci_free_seg(&xdev->control, XHCI_CONTROL_TRBS_SIZE);
650 fail_in_ctx:
651 xhci_free_ctx(&xdev->in_ctx, XHCI_CTX_BUF_SIZE);
652 return false;
653 }
654
xhci_free_dev(struct xhci_dev * xdev)655 static void xhci_free_dev(struct xhci_dev *xdev)
656 {
657 xhci_free_seg(&xdev->bulk_in, XHCI_DATA_TRBS_SIZE);
658 xhci_free_seg(&xdev->bulk_out, XHCI_DATA_TRBS_SIZE);
659 xhci_free_seg(&xdev->intr, XHCI_INTR_TRBS_SIZE);
660 xhci_free_seg(&xdev->control, XHCI_CONTROL_TRBS_SIZE);
661 xhci_free_ctx(&xdev->in_ctx, XHCI_CTX_BUF_SIZE);
662 xhci_free_ctx(&xdev->out_ctx, XHCI_CTX_BUF_SIZE);
663 }
664
usb3_dev_init(struct xhci_hcd * xhcd,struct usb_dev * hub,uint32_t port,uint32_t slotspeed)665 bool usb3_dev_init(struct xhci_hcd *xhcd, struct usb_dev *hub, uint32_t port,
666 uint32_t slotspeed)
667 {
668 /* Device enable slot */
669 xhci_send_enable_slot(xhcd, port);
670 if (!xhcd->slot_id) {
671 dprintf("Unable to get slot id\n");
672 return false;
673 }
674 dprintf("SLOT ID: %d\n", xhcd->slot_id);
675 if (!xhci_alloc_dev(xhcd, hub, xhcd->slot_id, port, slotspeed)) {
676 dprintf("Unable to allocate device\n");
677 return false;
678 }
679 return true;
680 }
681
xhci_device_present(uint32_t portsc,uint32_t usb_ver)682 static int xhci_device_present(uint32_t portsc, uint32_t usb_ver)
683 {
684 if (usb_ver == USB_XHCI) {
685 /* Device present and enabled state */
686 if ((portsc & PORTSC_CCS) &&
687 (portsc & PORTSC_PP) &&
688 (portsc & PORTSC_PED)) {
689 return true;
690 }
691 } else if (usb_ver == USB_EHCI) {
692 /* Device present and in disabled state */
693 if ((portsc & PORTSC_CCS) && (portsc & PORTSC_CSC))
694 return true;
695 }
696 return false;
697 }
698
xhci_port_scan(struct xhci_hcd * xhcd,uint32_t usb_ver)699 static int xhci_port_scan(struct xhci_hcd *xhcd,
700 uint32_t usb_ver)
701 {
702 uint32_t num_ports, portsc, i;
703 struct xhci_op_regs *op;
704 struct xhci_port_regs *prs;
705 struct xhci_cap_regs *cap;
706 uint32_t xecp_off;
707 uint32_t *xecp_addr, *base;
708 uint32_t port_off = 0, port_cnt;
709
710 dprintf("enter\n");
711
712 op = xhcd->op_regs;
713 cap = xhcd->cap_regs;
714 port_cnt = num_ports = read_reg32(&cap->hcsparams1) >> 24;
715
716 /* Read the xHCI extented capability to find usb3 ports and offset*/
717 xecp_off = XHCI_HCCPARAMS_XECP(read_reg32(&cap->hccparams));
718 base = (uint32_t *)cap;
719 while (xecp_off > 0) {
720 xecp_addr = base + xecp_off;
721 dprintf("xecp_off %d %p %p \n", xecp_off, base, xecp_addr);
722
723 if (XHCI_XECP_CAP_ID(read_reg32(xecp_addr)) == XHCI_XECP_CAP_SP &&
724 XHCI_XECP_CAP_SP_MJ(read_reg32(xecp_addr)) == usb_ver &&
725 XHCI_XECP_CAP_SP_MN(read_reg32(xecp_addr)) == 0) {
726 port_cnt = XHCI_XECP_CAP_SP_PC(read_reg32(xecp_addr + 2));
727 port_off = XHCI_XECP_CAP_SP_PO(read_reg32(xecp_addr + 2));
728 dprintf("PortCount %d Portoffset %d\n", port_cnt, port_off);
729 }
730 base = xecp_addr;
731 xecp_off = XHCI_XECP_NEXT_PTR(read_reg32(xecp_addr));
732 }
733 if (port_off == 0) /* port_off should always start from 1 */
734 return false;
735 for (i = (port_off - 1); i < (port_off + port_cnt - 1); i++) {
736 prs = &op->prs[i];
737 portsc = read_reg32(&prs->portsc);
738 if (xhci_device_present(portsc, usb_ver)) {
739 /* Device present */
740 dprintf("Device present on port %d\n", i);
741 /* Reset the port */
742 portsc = read_reg32(&prs->portsc);
743 portsc = portsc | PORTSC_PR;
744 write_reg32(&prs->portsc, portsc);
745 /* FIXME poll for port event */
746 SLOF_msleep(20);
747 xhci_poll_event(xhcd, 0);
748 portsc = read_reg32(&prs->portsc);
749 if (portsc & ~PORTSC_PRC) {
750 dprintf("Port reset complete %d\n", i);
751 }
752 print_port_status(prs);
753 if (!usb3_dev_init(xhcd, NULL, i - (port_off - 1),
754 ((portsc >> 10) & 0xf) << 20)) {
755 dprintf("USB device initialization failed\n");
756 }
757 }
758 }
759 dprintf("exit\n");
760 return true;
761 }
762
xhci_hub_check_ports(struct xhci_hcd * xhcd)763 static int xhci_hub_check_ports(struct xhci_hcd *xhcd)
764 {
765 return xhci_port_scan(xhcd, USB_XHCI) | xhci_port_scan(xhcd, USB_EHCI);
766 }
767
xhci_hcd_init(struct xhci_hcd * xhcd)768 static bool xhci_hcd_init(struct xhci_hcd *xhcd)
769 {
770 struct xhci_op_regs *op;
771 struct xhci_int_regs *irs;
772 uint64_t val;
773 uint32_t reg;
774
775 if (!xhcd) {
776 dprintf("NULL pointer\n");
777 goto fail;
778 }
779
780 op = xhcd->op_regs;
781 irs = &xhcd->run_regs->irs[0];
782 if (!xhci_hcd_reset(op)) {
783 dprintf("Reset failed\n");
784 goto fail;
785 }
786
787 write_reg32(&op->config, XHCI_CONFIG_MAX_SLOT);
788 reg = read_reg32(&xhcd->cap_regs->hccparams);
789 /* 64byte context !! */
790 xhcd->hcc_csz_64 = (reg & XHCI_HCCPARAMS_CSZ) ? 1 : 0;
791
792 if (xhcd->hcc_csz_64) {
793 printf("usb-xhci: 64 Byte context not supported\n");
794 goto fail;
795 }
796 /*
797 * 6.1 Device Context Base Address Array
798 *
799 * Allocate memory and initialize
800 */
801 xhcd->dcbaap = (uint64_t *)SLOF_dma_alloc(XHCI_DCBAAP_MAX_SIZE);
802 if (!xhcd->dcbaap) {
803 dprintf("Alloc failed\n");
804 goto fail;
805 }
806 memset((void *)xhcd->dcbaap, 0, XHCI_DCBAAP_MAX_SIZE);
807 xhcd->dcbaap_dma = SLOF_dma_map_in((void *)xhcd->dcbaap,
808 XHCI_DCBAAP_MAX_SIZE, false);
809 dprintf("dcbaap %llx, dcbaap_phys %llx\n", xhcd->dcbaap, xhcd->dcbaap_dma);
810 write_reg64(&op->dcbaap, xhcd->dcbaap_dma);
811
812 /*
813 * Command Ring Control - TRB
814 * FIXME - better way to allocate it...
815 */
816 if (!xhci_alloc_seg(&xhcd->crseg, XHCI_CRCR_CRP_SIZE, TYPE_COMMAND))
817 goto fail_dcbaap;
818
819 val = read_reg64(&op->crcr) & ~XHCI_CRCR_CRP_MASK;
820 val = val | (xhcd->crseg.trbs_dma & XHCI_CRCR_CRP_MASK);
821 write_reg64(&op->crcr, val);
822
823 /*
824 * Event Ring Control - TRB
825 * Allocate event TRBS
826 */
827 if (!xhci_alloc_seg(&xhcd->ering, XHCI_EVENT_TRBS_SIZE, TYPE_EVENT))
828 goto fail_crseg;
829
830 /*
831 * Populate event ring segment table.
832 * Note: only using one segment.
833 */
834 xhcd->erst.entries = SLOF_dma_alloc(XHCI_EVENT_TRBS_SIZE);
835 if (!xhcd->erst.entries)
836 goto fail_ering;
837 xhcd->erst.dma = SLOF_dma_map_in((void *)xhcd->erst.entries,
838 XHCI_EVENT_TRBS_SIZE, false);
839 xhcd->erst.num_segs = XHCI_ERST_NUM_SEGS;
840
841 /* populate entries[0] */
842 write_reg64(&xhcd->erst.entries->addr, xhcd->ering.trbs_dma);
843 write_reg32(&xhcd->erst.entries->size, xhcd->ering.size);
844 write_reg32(&xhcd->erst.entries->reserved, 0);
845
846 /* populate erdp */
847 val = read_reg64(&irs->erdp) & ~XHCI_ERDP_MASK;
848 val = val | (xhcd->ering.trbs_dma & XHCI_ERDP_MASK);
849 write_reg64(&irs->erdp, val);
850
851 /* populate erstsz */
852 val = read_reg32(&irs->erstsz) & ~XHCI_ERST_SIZE_MASK;
853 val = val | xhcd->erst.num_segs;
854 write_reg32(&irs->erstsz, val);
855
856 /* Now write the erstba */
857 val = read_reg64(&irs->erstba) & ~XHCI_ERST_ADDR_MASK;
858 val = val | (xhcd->erst.dma & XHCI_ERST_ADDR_MASK);
859 write_reg64(&irs->erstba, val);
860
861 dprintf("ERDP %llx TRB-DMA %llx\n", read_reg64(&irs->erdp),
862 xhcd->ering.trbs_dma);
863 dprintf("ERST %llx, ERST DMA %llx, size %d\n",
864 (uint64_t)xhcd->erst.entries, xhcd->erst.dma,
865 xhcd->erst.num_segs);
866
867 mb();
868 if (!xhci_hcd_set_runstop(op, true))
869 goto fail_erst_entries;
870
871 if (!xhci_hub_check_ports(xhcd))
872 goto fail_erst_entries;
873
874 return true;
875 fail_erst_entries:
876 write_reg32(&irs->erstsz, 0);
877 write_reg64(&irs->erstba, 0);
878 mb();
879 SLOF_dma_map_out(xhcd->erst.dma, (void *)xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
880 SLOF_dma_free((void *)xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
881 fail_ering:
882 xhci_free_seg(&xhcd->ering, XHCI_EVENT_TRBS_SIZE);
883 fail_crseg:
884 val = read_reg64(&op->crcr) & ~XHCI_CRCR_CRP_MASK;
885 write_reg64(&op->crcr, val);
886 mb();
887 xhci_free_seg(&xhcd->crseg, XHCI_CRCR_CRP_SIZE);
888 fail_dcbaap:
889 write_reg64(&op->dcbaap, 0);
890 mb();
891 SLOF_dma_map_out(xhcd->dcbaap_dma, (void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
892 SLOF_dma_free((void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
893 fail:
894 return false;
895 }
896
xhci_hcd_exit(struct xhci_hcd * xhcd)897 static bool xhci_hcd_exit(struct xhci_hcd *xhcd)
898 {
899 struct xhci_op_regs *op;
900 struct xhci_int_regs *irs;
901 uint64_t val;
902 int i;
903
904 if (!xhcd) {
905 dprintf("NULL pointer\n");
906 return false;
907 }
908 op = xhcd->op_regs;
909
910 if (!xhci_hcd_set_runstop(op, false)) {
911 dprintf("NULL pointer\n");
912 }
913
914 for (i = 1; i < XHCI_CONFIG_MAX_SLOT; i++) {
915 if (xhcd->xdevs[i].dev)
916 xhci_free_dev(&xhcd->xdevs[i]);
917 }
918
919 irs = &xhcd->run_regs->irs[0];
920 write_reg32(&irs->erstsz, 0);
921 write_reg64(&irs->erstba, 0);
922 mb();
923 if (xhcd->erst.entries) {
924 SLOF_dma_map_out(xhcd->erst.dma, xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
925 SLOF_dma_free(xhcd->erst.entries, XHCI_EVENT_TRBS_SIZE);
926 }
927 xhci_free_seg(&xhcd->ering, XHCI_EVENT_TRBS_SIZE);
928
929 val = read_reg64(&op->crcr) & ~XHCI_CRCR_CRP_MASK;
930 write_reg64(&op->crcr, val);
931 xhci_free_seg(&xhcd->crseg, XHCI_CRCR_CRP_SIZE);
932 write_reg64(&op->dcbaap, 0);
933 if (xhcd->dcbaap) {
934 SLOF_dma_map_out(xhcd->dcbaap_dma, (void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
935 SLOF_dma_free((void *)xhcd->dcbaap, XHCI_DCBAAP_MAX_SIZE);
936 }
937
938 /*
939 * QEMU implementation of XHCI doesn't implement halt
940 * properly. It basically says that it's halted immediately
941 * but doesn't actually terminate ongoing activities and
942 * DMAs. This needs to be fixed in QEMU.
943 *
944 * For now, wait for 50ms grace time till qemu stops using
945 * this device.
946 */
947 SLOF_msleep(50);
948
949 return true;
950 }
951
xhci_init(struct usb_hcd_dev * hcidev)952 static void xhci_init(struct usb_hcd_dev *hcidev)
953 {
954 struct xhci_hcd *xhcd;
955
956 printf(" XHCI: Initializing\n");
957 dprintf("device base address %p\n", hcidev->base);
958
959 hcidev->base = (void *)((uint64_t)hcidev->base & ~7);
960 xhcd = SLOF_alloc_mem(sizeof(*xhcd));
961 if (!xhcd) {
962 printf("usb-xhci: Unable to allocate memory\n");
963 return;
964 }
965 memset(xhcd, 0, sizeof(*xhcd));
966
967 hcidev->nextaddr = 1;
968 hcidev->priv = xhcd;
969 xhcd->hcidev = hcidev;
970 xhcd->cap_regs = (struct xhci_cap_regs *)(hcidev->base);
971 xhcd->op_regs = (struct xhci_op_regs *)(hcidev->base +
972 read_reg8(&xhcd->cap_regs->caplength));
973 xhcd->run_regs = (struct xhci_run_regs *)(hcidev->base +
974 read_reg32(&xhcd->cap_regs->rtsoff));
975 xhcd->db_regs = (struct xhci_db_regs *)(hcidev->base +
976 read_reg32(&xhcd->cap_regs->dboff));
977 dump_xhci_regs(xhcd);
978 if (!xhci_hcd_init(xhcd))
979 printf("usb-xhci: failed to initialize XHCI controller.\n");
980 dump_xhci_regs(xhcd);
981 }
982
xhci_exit(struct usb_hcd_dev * hcidev)983 static void xhci_exit(struct usb_hcd_dev *hcidev)
984 {
985 struct xhci_hcd *xhcd;
986
987 dprintf("%s: enter \n", __func__);
988 if (!hcidev && !hcidev->priv) {
989 return;
990 }
991
992 xhcd = hcidev->priv;
993 xhci_hcd_exit(xhcd);
994 SLOF_free_mem(xhcd, sizeof(*xhcd));
995 hcidev->priv = NULL;
996 }
997
fill_trb_buff(struct xhci_command_trb * cmd,uint32_t field1,uint32_t field2,uint32_t field3,uint32_t field4)998 static void fill_trb_buff(struct xhci_command_trb *cmd, uint32_t field1,
999 uint32_t field2, uint32_t field3, uint32_t field4)
1000 {
1001 uint32_t val, cycle_state;
1002
1003 cmd->field[0] = cpu_to_le32(field1);
1004 cmd->field[1] = cpu_to_le32(field2);
1005 cmd->field[2] = cpu_to_le32(field3);
1006
1007 val = le32_to_cpu(cmd->field[3]);
1008 cycle_state = (val & 0x1) ? 0 : 1;
1009 val = cycle_state | (field4 & ~0x1);
1010 cmd->field[3] = cpu_to_le32(val);
1011 mb();
1012
1013 dprintf("CMD %016lx val %08x cycle_state %d field1 %08x, field2 %08x, field3 %08x field4 %08x\n",
1014 cmd, val, cycle_state,
1015 le32_to_cpu(cmd->field[0]),
1016 le32_to_cpu(cmd->field[1]),
1017 le32_to_cpu(cmd->field[2]),
1018 le32_to_cpu(cmd->field[3])
1019 );
1020
1021 return;
1022 }
1023
fill_setup_trb(struct xhci_command_trb * cmd,struct usb_dev_req * req,uint32_t size)1024 static void fill_setup_trb(struct xhci_command_trb *cmd, struct usb_dev_req *req,
1025 uint32_t size)
1026 {
1027 uint32_t field1, field2, field3, field4 = 0;
1028 uint64_t req_raw;
1029 uint32_t datalen = 0, pid = 0;
1030
1031 req_raw = *((uint64_t *)req);
1032 dprintf("%lx %lx \n", *((uint64_t *)req), req_raw);
1033 /* req_raw is already in right byte order... */
1034 field1 = cpu_to_le32(TRB_ADDR_HIGH(req_raw));
1035 field2 = cpu_to_le32(TRB_ADDR_LOW(req_raw));
1036 field3 = 8; /* ALWAYS 8 */
1037
1038 datalen = cpu_to_le16(req->wLength);
1039 if (datalen) {
1040 pid = (req->bmRequestType & REQT_DIR_IN) ? 3 : 2;
1041 field4 = TRB_TRT(pid);
1042 }
1043 field4 |= TRB_CMD_TYPE(TRB_SETUP_STAGE) | TRB_IDT;
1044 fill_trb_buff(cmd, field1, field2, field3, field4);
1045 }
1046
fill_setup_data(struct xhci_command_trb * cmd,void * data,uint32_t size,uint32_t dir)1047 static void fill_setup_data(struct xhci_command_trb *cmd, void *data,
1048 uint32_t size, uint32_t dir)
1049 {
1050 uint32_t field1, field2, field3, field4;
1051
1052 field1 = TRB_ADDR_LOW(data);
1053 field2 = TRB_ADDR_HIGH(data);
1054 field3 = size;
1055 field4 = TRB_CMD_TYPE(TRB_DATA_STAGE);
1056 if (dir)
1057 field4 |= TRB_DIR_IN;
1058 fill_trb_buff(cmd, field1, field2, field3, field4);
1059 }
1060
fill_status_trb(struct xhci_command_trb * cmd,uint32_t dir)1061 static void fill_status_trb(struct xhci_command_trb *cmd, uint32_t dir)
1062 {
1063 uint32_t field1, field2, field3, field4;
1064
1065 field1 = 0;
1066 field2 = 0;
1067 field3 = 0;
1068 field4 = TRB_CMD_TYPE(TRB_STATUS_STAGE) | TRB_IOC;
1069 if (dir)
1070 field4 |= TRB_DIR_IN;
1071 fill_trb_buff(cmd, field1, field2, field3, field4);
1072 }
1073
fill_normal_trb(struct xhci_transfer_trb * trb,void * data,uint32_t size)1074 static void fill_normal_trb(struct xhci_transfer_trb *trb, void *data,
1075 uint32_t size)
1076 {
1077 uint32_t field1, field2, field3, field4;
1078
1079 field1 = TRB_ADDR_LOW(data);
1080 field2 = TRB_ADDR_HIGH(data);
1081 field3 = size;
1082 field4 = TRB_CMD_TYPE(TRB_NORMAL) | TRB_IOC;
1083 fill_trb_buff((struct xhci_command_trb *)trb, field1, field2, field3, field4);
1084 }
1085
xhci_send_ctrl(struct usb_pipe * pipe,struct usb_dev_req * req,void * data)1086 static int xhci_send_ctrl(struct usb_pipe *pipe, struct usb_dev_req *req, void *data)
1087 {
1088 struct xhci_dev *xdev;
1089 struct xhci_seg *ctrl;
1090 struct xhci_hcd *xhcd;
1091 struct xhci_command_trb *cmd;
1092 struct xhci_db_regs *dbr;
1093 long req_phys = 0, data_phys = 0;
1094 int ret = true;
1095 uint32_t slot_id, pid = 0, datalen = 0;
1096
1097 if (!pipe->dev || !pipe->dev->hcidev) {
1098 dprintf(" NULL pointer\n");
1099 return false;
1100 }
1101
1102 xdev = pipe->dev->priv;
1103 slot_id = xdev->slot_id;
1104 ctrl = &xdev->control;
1105 xhcd = (struct xhci_hcd *)pipe->dev->hcidev->priv;
1106 dbr = xhcd->db_regs;
1107 if (!ctrl || !xdev || !xhcd) {
1108 dprintf(" NULL pointer\n");
1109 return false;
1110 }
1111
1112 cmd = (struct xhci_command_trb *)ctrl->enq;
1113 req_phys = SLOF_dma_map_in(req, sizeof(struct usb_dev_req), true);
1114 fill_setup_trb(cmd, req, sizeof(*req));
1115
1116 cmd++;
1117 datalen = cpu_to_le16(req->wLength);
1118 if (datalen)
1119 pid = 1;
1120 if (datalen) {
1121 data_phys = SLOF_dma_map_in(data, datalen, true);
1122 fill_setup_data(cmd, (void *) data_phys, datalen, pid);
1123 cmd++;
1124 }
1125
1126 fill_status_trb(cmd, pid);
1127 cmd++;
1128
1129 /* Ring the doorbell - ep0 */
1130 write_reg32(&dbr->db[slot_id], 1);
1131 if (!xhci_poll_event(xhcd, 0)) {
1132 dprintf("Command failed\n");
1133 ret = false;
1134 }
1135 ctrl->enq = (uint64_t) cmd;
1136 SLOF_dma_map_out(req_phys, req, sizeof(struct usb_dev_req));
1137 if (datalen)
1138 SLOF_dma_map_out(data_phys, data, datalen);
1139 return ret;
1140 }
1141
xhci_pipe_get_xpipe(struct usb_pipe * pipe)1142 static inline struct xhci_pipe *xhci_pipe_get_xpipe(struct usb_pipe *pipe)
1143 {
1144 struct xhci_pipe *xpipe;
1145 xpipe = container_of(pipe, struct xhci_pipe, pipe);
1146 dprintf("%s: xpipe is %p\n", __func__, xpipe);
1147 return xpipe;
1148 }
1149
xhci_pipe_get_seg(struct usb_pipe * pipe)1150 static inline struct xhci_seg *xhci_pipe_get_seg(struct usb_pipe *pipe)
1151 {
1152 struct xhci_pipe *xpipe;
1153 xpipe = xhci_pipe_get_xpipe(pipe);
1154 return xpipe->seg;
1155 }
1156
xhci_get_trb(struct xhci_seg * seg)1157 static inline void *xhci_get_trb(struct xhci_seg *seg)
1158 {
1159 uint64_t val, enq;
1160 int index;
1161 struct xhci_link_trb *link;
1162
1163 enq = val = seg->enq;
1164 val = val + XHCI_TRB_SIZE;
1165 index = (enq - (uint64_t)seg->trbs) / XHCI_TRB_SIZE + 1;
1166 dprintf("%s: enq %llx, val %llx %x\n", __func__, enq, val, index);
1167 /* TRBs being a cyclic buffer, here we cycle back to beginning. */
1168 if (index == (seg->size - 1)) {
1169 dprintf("%s: rounding \n", __func__);
1170 seg->enq = (uint64_t)seg->trbs;
1171 seg->cycle_state ^= seg->cycle_state;
1172 link = (struct xhci_link_trb *) (seg->trbs + seg->size - 1);
1173 link->addr = cpu_to_le64(seg->trbs_dma);
1174 link->field2 = 0;
1175 link->field3 = cpu_to_le32(0x1 | TRB_CMD_TYPE(TRB_LINK));
1176 mb();
1177 }
1178 else {
1179 seg->enq = seg->enq + XHCI_TRB_SIZE;
1180 }
1181
1182 return (void *)enq;
1183 }
1184
xhci_get_trb_deq(struct xhci_seg * seg)1185 static inline void *xhci_get_trb_deq(struct xhci_seg *seg)
1186 {
1187 uint64_t deq_next, deq;
1188 int index;
1189
1190 deq = seg->deq;
1191 deq_next = deq + XHCI_TRB_SIZE;
1192 index = (deq - (uint64_t)seg->trbs) / XHCI_TRB_SIZE + 1;
1193 dprintf("%s: deq %llx, deq_next %llx index %x\n", __func__, deq, deq_next, index);
1194 /* TRBs being a cyclic buffer, here we cycle back to beginning. */
1195 if (index == (seg->size - 1)) {
1196 dprintf("%s: rounding \n", __func__);
1197 seg->deq = (uint64_t)seg->trbs;
1198 }
1199 else {
1200 seg->deq = deq_next;
1201 }
1202 return (void *)deq;
1203 }
1204
xhci_get_trb_phys(struct xhci_seg * seg,uint64_t trb)1205 static uint64_t xhci_get_trb_phys(struct xhci_seg *seg, uint64_t trb)
1206 {
1207 return seg->trbs_dma + (trb - (uint64_t)seg->trbs);
1208 }
1209
xhci_trb_get_index(struct xhci_seg * seg,struct xhci_transfer_trb * trb)1210 static uint32_t xhci_trb_get_index(struct xhci_seg *seg, struct xhci_transfer_trb *trb)
1211 {
1212 return trb - (struct xhci_transfer_trb *)seg->trbs;
1213 }
1214
1215 static int usb_kb = false;
xhci_transfer_bulk(struct usb_pipe * pipe,void * td,void * td_phys,void * data,int datalen)1216 static int xhci_transfer_bulk(struct usb_pipe *pipe, void *td, void *td_phys,
1217 void *data, int datalen)
1218 {
1219 struct xhci_dev *xdev;
1220 struct xhci_seg *seg;
1221 struct xhci_hcd *xhcd;
1222 struct xhci_transfer_trb *trb;
1223 struct xhci_db_regs *dbr;
1224 int ret = true;
1225 uint32_t slot_id, epno, time;
1226 uint64_t trb_phys, event_phys;
1227
1228 if (!pipe->dev || !pipe->dev->hcidev) {
1229 dprintf(" NULL pointer\n");
1230 dprintf(" pipe dev %p hcidev %p\n", pipe->dev, pipe->dev->hcidev);
1231 return false;
1232 }
1233
1234 xdev = pipe->dev->priv;
1235 slot_id = xdev->slot_id;
1236 seg = xhci_pipe_get_seg(pipe);
1237 xhcd = (struct xhci_hcd *)pipe->dev->hcidev->priv;
1238 dbr = xhcd->db_regs;
1239 if (!seg || !xdev || !xhcd) {
1240 dprintf(" NULL pointer\n");
1241 dprintf(" seg %p xdev %p xhcd %p\n", seg, xdev, xhcd);
1242 return false;
1243 }
1244
1245 if (datalen > XHCI_MAX_BULK_SIZE) {
1246 printf("usb-xhci: bulk transfer size too big\n");
1247 return false;
1248 }
1249
1250 trb = xhci_get_trb(seg);
1251 trb_phys = xhci_get_trb_phys(seg, (uint64_t)trb);
1252 fill_normal_trb(trb, (void *)data, datalen);
1253
1254 epno = xhci_get_epno(pipe);
1255 write_reg32(&dbr->db[slot_id], epno);
1256
1257 time = SLOF_GetTimer() + USB_TIMEOUT;
1258 while (1) {
1259 event_phys = xhci_poll_event(xhcd, 0);
1260 if (event_phys == trb_phys) {
1261 break;
1262 } else if (event_phys == 0) { /* polling timed out */
1263 ret = false;
1264 break;
1265 } else
1266 usb_kb = true;
1267
1268 /* transfer timed out */
1269 if (time < SLOF_GetTimer())
1270 return false;
1271 }
1272 trb->addr = 0;
1273 trb->len = 0;
1274 trb->flags = 0;
1275 mb();
1276
1277 return ret;
1278 }
1279
xhci_alloc_pipe_pool(struct xhci_hcd * xhcd)1280 static int xhci_alloc_pipe_pool(struct xhci_hcd *xhcd)
1281 {
1282 struct xhci_pipe *xpipe, *curr, *prev;
1283 unsigned int i, count;
1284 long xpipe_phys = 0;
1285
1286 count = XHCI_PIPE_POOL_SIZE/sizeof(*xpipe);
1287 xhcd->pool = xpipe = SLOF_dma_alloc(XHCI_PIPE_POOL_SIZE);
1288 if (!xpipe)
1289 return -1;
1290 xhcd->pool_phys = xpipe_phys = SLOF_dma_map_in(xpipe, XHCI_PIPE_POOL_SIZE, true);
1291 dprintf("%s: xpipe %p, xpipe_phys %lx\n", __func__, xpipe, xpipe_phys);
1292
1293 /* Although an array, link them */
1294 for (i = 0, curr = xpipe, prev = NULL; i < count; i++, curr++) {
1295 if (prev)
1296 prev->pipe.next = &curr->pipe;
1297 curr->pipe.next = NULL;
1298 prev = curr;
1299 }
1300
1301 if (!xhcd->freelist)
1302 xhcd->freelist = &xpipe->pipe;
1303 else
1304 xhcd->end->next = &xpipe->pipe;
1305 xhcd->end = &prev->pipe;
1306
1307 return 0;
1308 }
1309
xhci_init_bulk_ep(struct usb_dev * dev,struct usb_pipe * pipe)1310 static void xhci_init_bulk_ep(struct usb_dev *dev, struct usb_pipe *pipe)
1311 {
1312 struct xhci_hcd *xhcd;
1313 struct xhci_dev *xdev;
1314 struct xhci_seg *seg;
1315 struct xhci_pipe *xpipe;
1316 struct xhci_control_ctx *ctrl;
1317 struct xhci_ep_ctx *ep;
1318 uint32_t x_epno, val, type;
1319
1320 if (!pipe || !dev || !dev->priv)
1321 return;
1322
1323 xdev = dev->priv;
1324 xhcd = dev->hcidev->priv;
1325 dprintf("dir %d\n", pipe->dir);
1326 seg = xhci_pipe_get_seg(pipe);
1327 xpipe = xhci_pipe_get_xpipe(pipe);
1328 if (pipe->dir) {
1329 type = EP_BULK_IN;
1330 seg = &xdev->bulk_in;
1331 }
1332 else {
1333 type = EP_BULK_OUT;
1334 seg = &xdev->bulk_out;
1335 }
1336
1337 if (!seg->trbs) {
1338 if (!xhci_alloc_seg(seg, XHCI_DATA_TRBS_SIZE, TYPE_BULK)) {
1339 printf("usb-xhci: allocation failed for bulk endpoint\n");
1340 return;
1341 }
1342 } else {
1343 xhci_init_seg(seg, XHCI_DATA_TRBS_SIZE, TYPE_BULK);
1344 }
1345
1346 pipe->mps = XHCI_MAX_BULK_SIZE;
1347 ctrl = xhci_get_control_ctx(&xdev->in_ctx);
1348 x_epno = xhci_get_epno(pipe);
1349 ep = xhci_get_ep_ctx(&xdev->in_ctx, xdev->ctx_size, x_epno);
1350 val = EP_TYPE(type) | MAX_BURST(0) | ERROR_COUNT(3) |
1351 MAX_PACKET_SIZE(pipe->mps);
1352 ep->field2 = cpu_to_le32(val);;
1353 ep->deq_addr = cpu_to_le64(seg->trbs_dma | seg->cycle_state);
1354 ep->field4 = cpu_to_le32(8);
1355 ctrl->a_flags = cpu_to_le32(BIT(x_epno) | 0x1);
1356 ctrl->d_flags = 0;
1357 xhci_configure_ep(xhcd, xdev->slot_id, xdev->in_ctx.dma_addr);
1358 xpipe->seg = seg;
1359 }
1360
xhci_get_pipe_intr(struct usb_pipe * pipe,struct xhci_hcd * xhcd,char * buf,size_t len)1361 static int xhci_get_pipe_intr(struct usb_pipe *pipe,
1362 struct xhci_hcd *xhcd,
1363 char *buf, size_t len)
1364 {
1365 struct xhci_dev *xdev;
1366 struct xhci_seg *seg;
1367 struct xhci_pipe *xpipe;
1368 struct xhci_control_ctx *ctrl;
1369 struct xhci_ep_ctx *ep;
1370 uint32_t x_epno, val, type;
1371 struct usb_dev *dev;
1372 struct xhci_transfer_trb *trb;
1373
1374 dev = pipe->dev;
1375 if (dev->class != DEV_HID_KEYB)
1376 return false;
1377
1378 xdev = dev->priv;
1379 pipe->mps = 8;
1380 seg = xhci_pipe_get_seg(pipe);
1381 xpipe = xhci_pipe_get_xpipe(pipe);
1382 type = EP_INT_IN;
1383 seg = &xdev->intr;
1384
1385 if (!seg->trbs) {
1386 if (!xhci_alloc_seg(seg, XHCI_INTR_TRBS_SIZE, TYPE_BULK)) {
1387 printf("usb-xhci: allocation failed for interrupt endpoint\n");
1388 return false;
1389 }
1390 } else {
1391 xhci_init_seg(seg, XHCI_EVENT_TRBS_SIZE, TYPE_BULK);
1392 }
1393
1394 xpipe->buflen = pipe->mps * XHCI_INTR_TRBS_SIZE/(sizeof(struct xhci_transfer_trb));
1395 xpipe->buf = SLOF_dma_alloc(xpipe->buflen);
1396 xpipe->buf_phys = SLOF_dma_map_in(xpipe->buf, xpipe->buflen, false);
1397
1398 ctrl = xhci_get_control_ctx(&xdev->in_ctx);
1399 x_epno = xhci_get_epno(pipe);
1400 ep = xhci_get_ep_ctx(&xdev->in_ctx, xdev->ctx_size, x_epno);
1401 val = EP_TYPE(type) | MAX_BURST(0) | ERROR_COUNT(3) |
1402 MAX_PACKET_SIZE(pipe->mps);
1403 ep->field2 = cpu_to_le32(val);
1404 ep->deq_addr = cpu_to_le64(seg->trbs_dma | seg->cycle_state);
1405 ep->field4 = cpu_to_le32(8);
1406 ctrl->a_flags = cpu_to_le32(BIT(x_epno) | 0x1);
1407 ctrl->d_flags = 0;
1408 xhci_configure_ep(xhcd, xdev->slot_id, xdev->in_ctx.dma_addr);
1409 xpipe->seg = seg;
1410
1411 trb = xhci_get_trb(seg);
1412 buf = (char *)(xpipe->buf_phys + xhci_trb_get_index(seg, trb) * pipe->mps);
1413 fill_normal_trb(trb, (void *)buf, pipe->mps);
1414 return true;
1415 }
1416
xhci_get_pipe(struct usb_dev * dev,struct usb_ep_descr * ep,char * buf,size_t len)1417 static struct usb_pipe* xhci_get_pipe(struct usb_dev *dev, struct usb_ep_descr *ep, char *buf, size_t len)
1418 {
1419 struct xhci_hcd *xhcd;
1420 struct usb_pipe *new = NULL;
1421
1422 if (!dev)
1423 return NULL;
1424
1425 xhcd = (struct xhci_hcd *)dev->hcidev->priv;
1426 if (!xhcd->freelist) {
1427 dprintf("usb-xhci: %s allocating pool\n", __func__);
1428 if (xhci_alloc_pipe_pool(xhcd))
1429 return NULL;
1430 }
1431
1432 new = xhcd->freelist;
1433 xhcd->freelist = xhcd->freelist->next;
1434 if (!xhcd->freelist)
1435 xhcd->end = NULL;
1436
1437 memset(new, 0, sizeof(*new));
1438 new->dev = dev;
1439 new->next = NULL;
1440 new->type = ep->bmAttributes & USB_EP_TYPE_MASK;
1441 new->speed = dev->speed;
1442 new->mps = ep->wMaxPacketSize;
1443 new->dir = (ep->bEndpointAddress & 0x80) >> 7;
1444 new->epno = ep->bEndpointAddress & 0x0f;
1445
1446 if (new->type == USB_EP_TYPE_INTR) {
1447 if (!xhci_get_pipe_intr(new, xhcd, buf, len)) {
1448 printf("usb-xhci: %s alloc_intr failed %p\n",
1449 __func__, new);
1450 }
1451 }
1452 if (new->type == USB_EP_TYPE_BULK)
1453 xhci_init_bulk_ep(dev, new);
1454
1455 return new;
1456 }
1457
xhci_put_pipe(struct usb_pipe * pipe)1458 static void xhci_put_pipe(struct usb_pipe *pipe)
1459 {
1460 struct xhci_hcd *xhcd;
1461 struct xhci_pipe *xpipe;
1462
1463 dprintf("usb-xhci: %s enter - %p\n", __func__, pipe);
1464 if (!pipe || !pipe->dev)
1465 return;
1466 xhcd = pipe->dev->hcidev->priv;
1467
1468 dprintf("dir %d\n", pipe->dir);
1469 if (pipe->type == USB_EP_TYPE_BULK) {
1470 xpipe = xhci_pipe_get_xpipe(pipe);
1471 xpipe->seg = NULL;
1472 } else if (pipe->type == USB_EP_TYPE_INTR) {
1473 xpipe = xhci_pipe_get_xpipe(pipe);
1474 SLOF_dma_map_out(xpipe->buf_phys, xpipe->buf, xpipe->buflen);
1475 SLOF_dma_free(xpipe->buf, xpipe->buflen);
1476 xpipe->seg = NULL;
1477 }
1478 if (xhcd->end)
1479 xhcd->end->next = pipe;
1480 else
1481 xhcd->freelist = pipe;
1482
1483 xhcd->end = pipe;
1484 pipe->next = NULL;
1485 pipe->dev = NULL;
1486 memset(pipe, 0, sizeof(*pipe));
1487
1488 dprintf("usb-xhci: %s exit\n", __func__);
1489 }
1490
xhci_poll_intr(struct usb_pipe * pipe,uint8_t * data)1491 static int xhci_poll_intr(struct usb_pipe *pipe, uint8_t *data)
1492 {
1493 struct xhci_transfer_trb *trb;
1494 struct xhci_seg *seg;
1495 struct xhci_pipe *xpipe;
1496 struct xhci_dev *xdev;
1497 struct xhci_hcd *xhcd;
1498 struct xhci_db_regs *dbr;
1499 uint32_t x_epno;
1500 uint8_t *buf, ret = 1;
1501
1502 if (!pipe || !pipe->dev || !pipe->dev->hcidev)
1503 return 0;
1504 xdev = pipe->dev->priv;
1505 xhcd = (struct xhci_hcd *)pipe->dev->hcidev->priv;
1506 x_epno = xhci_get_epno(pipe);
1507 seg = xhci_pipe_get_seg(pipe);
1508 xpipe = xhci_pipe_get_xpipe(pipe);
1509
1510 if (usb_kb == true) {
1511 /* This event was consumed by bulk transfer */
1512 usb_kb = false;
1513 xhci_get_trb_deq(seg);
1514 goto skip_poll;
1515 }
1516
1517 /* Ring the doorbell - x_epno */
1518 dbr = xhcd->db_regs;
1519 write_reg32(&dbr->db[xdev->slot_id], x_epno);
1520 if (!xhci_poll_event(xhcd, XHCI_POLL_NO_WAIT)) {
1521 return 0;
1522 }
1523 mb();
1524 trb = xhci_get_trb_deq(seg);
1525 buf = xpipe->buf + xhci_trb_get_index(seg, trb) * pipe->mps;
1526 memcpy(data, buf, 8);
1527 memset(buf, 0, 8);
1528
1529 skip_poll:
1530 trb = xhci_get_trb(seg);
1531 buf = (uint8_t *)(xpipe->buf_phys + xhci_trb_get_index(seg, trb) * pipe->mps);
1532 fill_normal_trb(trb, (void *)buf, pipe->mps);
1533 return ret;
1534 }
1535
1536 struct usb_hcd_ops xhci_ops = {
1537 .name = "xhci-hcd",
1538 .init = xhci_init,
1539 .exit = xhci_exit,
1540 .usb_type = USB_XHCI,
1541 .get_pipe = xhci_get_pipe,
1542 .put_pipe = xhci_put_pipe,
1543 .poll_intr = xhci_poll_intr,
1544 .send_ctrl = xhci_send_ctrl,
1545 .transfer_bulk = xhci_transfer_bulk,
1546 .next = NULL,
1547 };
1548
usb_xhci_register(void)1549 void usb_xhci_register(void)
1550 {
1551 usb_hcd_register(&xhci_ops);
1552 }
1553