1 /*
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
5 *
6 * Lightly modified for iPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>.
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 *
20 */
21
22 FILE_LICENCE ( MIT );
23
24 /******************************\
25 Hardware Descriptor Functions
26 \******************************/
27
28 #include "ath5k.h"
29 #include "reg.h"
30 #include "base.h"
31
32 /*
33 * TX Descriptors
34 */
35
36 #define FCS_LEN 4
37
38 /*
39 * Initialize the 2-word tx control descriptor on 5210/5211
40 */
41 static int
ath5k_hw_setup_2word_tx_desc(struct ath5k_hw * ah,struct ath5k_desc * desc,unsigned int pkt_len,unsigned int hdr_len,enum ath5k_pkt_type type,unsigned int tx_power __unused,unsigned int tx_rate0,unsigned int tx_tries0,unsigned int key_index __unused,unsigned int antenna_mode,unsigned int flags,unsigned int rtscts_rate __unused,unsigned int rtscts_duration)42 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
43 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
44 unsigned int tx_power __unused, unsigned int tx_rate0, unsigned int tx_tries0,
45 unsigned int key_index __unused, unsigned int antenna_mode, unsigned int flags,
46 unsigned int rtscts_rate __unused, unsigned int rtscts_duration)
47 {
48 u32 frame_type;
49 struct ath5k_hw_2w_tx_ctl *tx_ctl;
50 unsigned int frame_len;
51
52 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
53
54 /*
55 * Validate input
56 * - Zero retries don't make sense.
57 * - A zero rate will put the HW into a mode where it continously sends
58 * noise on the channel, so it is important to avoid this.
59 */
60 if (tx_tries0 == 0) {
61 DBG("ath5k: zero retries\n");
62 return -EINVAL;
63 }
64 if (tx_rate0 == 0) {
65 DBG("ath5k: zero rate\n");
66 return -EINVAL;
67 }
68
69 /* Clear descriptor */
70 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
71
72 /* Setup control descriptor */
73
74 /* Verify and set frame length */
75
76 frame_len = pkt_len + FCS_LEN;
77
78 if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
79 return -EINVAL;
80
81 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
82
83 /* Verify and set buffer length */
84
85 if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
86 return -EINVAL;
87
88 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
89
90 /*
91 * Verify and set header length
92 * XXX: I only found that on 5210 code, does it work on 5211 ?
93 */
94 if (ah->ah_version == AR5K_AR5210) {
95 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
96 return -EINVAL;
97 tx_ctl->tx_control_0 |=
98 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
99 }
100
101 /*Diferences between 5210-5211*/
102 if (ah->ah_version == AR5K_AR5210) {
103 switch (type) {
104 case AR5K_PKT_TYPE_BEACON:
105 case AR5K_PKT_TYPE_PROBE_RESP:
106 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
107 break;
108 case AR5K_PKT_TYPE_PIFS:
109 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
110 break;
111 default:
112 frame_type = type /*<< 2 ?*/;
113 break;
114 }
115
116 tx_ctl->tx_control_0 |=
117 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
118 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
119
120 } else {
121 tx_ctl->tx_control_0 |=
122 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
123 AR5K_REG_SM(antenna_mode,
124 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
125 tx_ctl->tx_control_1 |=
126 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
127 }
128 #define _TX_FLAGS(_c, _flag) \
129 if (flags & AR5K_TXDESC_##_flag) { \
130 tx_ctl->tx_control_##_c |= \
131 AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
132 }
133
134 _TX_FLAGS(0, CLRDMASK);
135 _TX_FLAGS(0, VEOL);
136 _TX_FLAGS(0, INTREQ);
137 _TX_FLAGS(0, RTSENA);
138 _TX_FLAGS(1, NOACK);
139
140 #undef _TX_FLAGS
141
142 /*
143 * RTS/CTS Duration [5210 ?]
144 */
145 if ((ah->ah_version == AR5K_AR5210) &&
146 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
147 tx_ctl->tx_control_1 |= rtscts_duration &
148 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
149
150 return 0;
151 }
152
153 /*
154 * Initialize the 4-word tx control descriptor on 5212
155 */
ath5k_hw_setup_4word_tx_desc(struct ath5k_hw * ah,struct ath5k_desc * desc,unsigned int pkt_len,unsigned int hdr_len __unused,enum ath5k_pkt_type type,unsigned int tx_power,unsigned int tx_rate0,unsigned int tx_tries0,unsigned int key_index __unused,unsigned int antenna_mode,unsigned int flags,unsigned int rtscts_rate,unsigned int rtscts_duration)156 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
157 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len __unused,
158 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
159 unsigned int tx_tries0, unsigned int key_index __unused,
160 unsigned int antenna_mode, unsigned int flags,
161 unsigned int rtscts_rate,
162 unsigned int rtscts_duration)
163 {
164 struct ath5k_hw_4w_tx_ctl *tx_ctl;
165 unsigned int frame_len;
166
167 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
168
169 /*
170 * Validate input
171 * - Zero retries don't make sense.
172 * - A zero rate will put the HW into a mode where it continously sends
173 * noise on the channel, so it is important to avoid this.
174 */
175 if (tx_tries0 == 0) {
176 DBG("ath5k: zero retries\n");
177 return -EINVAL;
178 }
179 if (tx_rate0 == 0) {
180 DBG("ath5k: zero rate\n");
181 return -EINVAL;
182 }
183
184 tx_power += ah->ah_txpower.txp_offset;
185 if (tx_power > AR5K_TUNE_MAX_TXPOWER)
186 tx_power = AR5K_TUNE_MAX_TXPOWER;
187
188 /* Clear descriptor */
189 memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
190
191 /* Setup control descriptor */
192
193 /* Verify and set frame length */
194
195 frame_len = pkt_len + FCS_LEN;
196
197 if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
198 return -EINVAL;
199
200 tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
201
202 /* Verify and set buffer length */
203
204 if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
205 return -EINVAL;
206
207 tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
208
209 tx_ctl->tx_control_0 |=
210 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
211 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
212 tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
213 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
214 tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
215 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
216 tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
217
218 #define _TX_FLAGS(_c, _flag) \
219 if (flags & AR5K_TXDESC_##_flag) { \
220 tx_ctl->tx_control_##_c |= \
221 AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
222 }
223
224 _TX_FLAGS(0, CLRDMASK);
225 _TX_FLAGS(0, VEOL);
226 _TX_FLAGS(0, INTREQ);
227 _TX_FLAGS(0, RTSENA);
228 _TX_FLAGS(0, CTSENA);
229 _TX_FLAGS(1, NOACK);
230
231 #undef _TX_FLAGS
232
233 /*
234 * RTS/CTS
235 */
236 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
237 if ((flags & AR5K_TXDESC_RTSENA) &&
238 (flags & AR5K_TXDESC_CTSENA))
239 return -EINVAL;
240 tx_ctl->tx_control_2 |= rtscts_duration &
241 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
242 tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
243 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
244 }
245
246 return 0;
247 }
248
249 /*
250 * Proccess the tx status descriptor on 5210/5211
251 */
ath5k_hw_proc_2word_tx_status(struct ath5k_hw * ah __unused,struct ath5k_desc * desc,struct ath5k_tx_status * ts)252 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah __unused,
253 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
254 {
255 struct ath5k_hw_2w_tx_ctl *tx_ctl;
256 struct ath5k_hw_tx_status *tx_status;
257
258 tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
259 tx_status = &desc->ud.ds_tx5210.tx_stat;
260
261 /* No frame has been send or error */
262 if ((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)
263 return -EINPROGRESS;
264
265 /*
266 * Get descriptor status
267 */
268 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
269 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
270 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
271 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
272 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
273 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
274 /*TODO: ts->ts_virtcol + test*/
275 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
276 AR5K_DESC_TX_STATUS1_SEQ_NUM);
277 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
278 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
279 ts->ts_antenna = 1;
280 ts->ts_status = 0;
281 ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
282 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
283 ts->ts_retry[0] = ts->ts_longretry;
284 ts->ts_final_idx = 0;
285
286 if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
287 if (tx_status->tx_status_0 &
288 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
289 ts->ts_status |= AR5K_TXERR_XRETRY;
290
291 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
292 ts->ts_status |= AR5K_TXERR_FIFO;
293
294 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
295 ts->ts_status |= AR5K_TXERR_FILT;
296 }
297
298 return 0;
299 }
300
301 /*
302 * Proccess a tx status descriptor on 5212
303 */
ath5k_hw_proc_4word_tx_status(struct ath5k_hw * ah __unused,struct ath5k_desc * desc,struct ath5k_tx_status * ts)304 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah __unused,
305 struct ath5k_desc *desc, struct ath5k_tx_status *ts)
306 {
307 struct ath5k_hw_4w_tx_ctl *tx_ctl;
308 struct ath5k_hw_tx_status *tx_status;
309
310 tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
311 tx_status = &desc->ud.ds_tx5212.tx_stat;
312
313 /* No frame has been send or error */
314 if (!(tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE))
315 return -EINPROGRESS;
316
317 /*
318 * Get descriptor status
319 */
320 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
321 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
322 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
323 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
324 ts->ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
325 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
326 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
327 AR5K_DESC_TX_STATUS1_SEQ_NUM);
328 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
329 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
330 ts->ts_antenna = (tx_status->tx_status_1 &
331 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
332 ts->ts_status = 0;
333
334 ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
335 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
336
337 ts->ts_retry[0] = ts->ts_longretry;
338 ts->ts_rate[0] = tx_ctl->tx_control_3 &
339 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
340
341 /* TX error */
342 if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
343 if (tx_status->tx_status_0 &
344 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
345 ts->ts_status |= AR5K_TXERR_XRETRY;
346
347 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
348 ts->ts_status |= AR5K_TXERR_FIFO;
349
350 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
351 ts->ts_status |= AR5K_TXERR_FILT;
352 }
353
354 return 0;
355 }
356
357 /*
358 * RX Descriptors
359 */
360
361 /*
362 * Initialize an rx control descriptor
363 */
ath5k_hw_setup_rx_desc(struct ath5k_hw * ah __unused,struct ath5k_desc * desc,u32 size,unsigned int flags)364 static int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah __unused,
365 struct ath5k_desc *desc,
366 u32 size, unsigned int flags)
367 {
368 struct ath5k_hw_rx_ctl *rx_ctl;
369
370 rx_ctl = &desc->ud.ds_rx.rx_ctl;
371
372 /*
373 * Clear the descriptor
374 * If we don't clean the status descriptor,
375 * while scanning we get too many results,
376 * most of them virtual, after some secs
377 * of scanning system hangs. M.F.
378 */
379 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
380
381 /* Setup descriptor */
382 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
383 if (rx_ctl->rx_control_1 != size)
384 return -EINVAL;
385
386 if (flags & AR5K_RXDESC_INTREQ)
387 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
388
389 return 0;
390 }
391
392 /*
393 * Proccess the rx status descriptor on 5210/5211
394 */
ath5k_hw_proc_5210_rx_status(struct ath5k_hw * ah __unused,struct ath5k_desc * desc,struct ath5k_rx_status * rs)395 static int ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah __unused,
396 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
397 {
398 struct ath5k_hw_rx_status *rx_status;
399
400 rx_status = &desc->ud.ds_rx.u.rx_stat;
401
402 /* No frame received / not ready */
403 if (!(rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_DONE))
404 return -EINPROGRESS;
405
406 /*
407 * Frame receive status
408 */
409 rs->rs_datalen = rx_status->rx_status_0 &
410 AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
411 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
412 AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
413 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
414 AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
415 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
416 AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA);
417 rs->rs_more = !!(rx_status->rx_status_0 &
418 AR5K_5210_RX_DESC_STATUS0_MORE);
419 /* TODO: this timestamp is 13 bit, later on we assume 15 bit */
420 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
421 AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
422 rs->rs_status = 0;
423 rs->rs_phyerr = 0;
424 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
425
426 /*
427 * Receive/descriptor errors
428 */
429 if (!(rx_status->rx_status_1 &
430 AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
431 if (rx_status->rx_status_1 &
432 AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
433 rs->rs_status |= AR5K_RXERR_CRC;
434
435 if (rx_status->rx_status_1 &
436 AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN)
437 rs->rs_status |= AR5K_RXERR_FIFO;
438
439 if (rx_status->rx_status_1 &
440 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
441 rs->rs_status |= AR5K_RXERR_PHY;
442 rs->rs_phyerr |= AR5K_REG_MS(rx_status->rx_status_1,
443 AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
444 }
445
446 if (rx_status->rx_status_1 &
447 AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
448 rs->rs_status |= AR5K_RXERR_DECRYPT;
449 }
450
451 return 0;
452 }
453
454 /*
455 * Proccess the rx status descriptor on 5212
456 */
ath5k_hw_proc_5212_rx_status(struct ath5k_hw * ah __unused,struct ath5k_desc * desc,struct ath5k_rx_status * rs)457 static int ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah __unused,
458 struct ath5k_desc *desc, struct ath5k_rx_status *rs)
459 {
460 struct ath5k_hw_rx_status *rx_status;
461 struct ath5k_hw_rx_error *rx_err;
462
463 rx_status = &desc->ud.ds_rx.u.rx_stat;
464
465 /* Overlay on error */
466 rx_err = &desc->ud.ds_rx.u.rx_err;
467
468 /* No frame received / not ready */
469 if (!(rx_status->rx_status_1 & AR5K_5212_RX_DESC_STATUS1_DONE))
470 return -EINPROGRESS;
471
472 /*
473 * Frame receive status
474 */
475 rs->rs_datalen = rx_status->rx_status_0 &
476 AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
477 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
478 AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
479 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
480 AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
481 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
482 AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
483 rs->rs_more = !!(rx_status->rx_status_0 &
484 AR5K_5212_RX_DESC_STATUS0_MORE);
485 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
486 AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
487 rs->rs_status = 0;
488 rs->rs_phyerr = 0;
489 rs->rs_keyix = AR5K_RXKEYIX_INVALID;
490
491 /*
492 * Receive/descriptor errors
493 */
494 if (!(rx_status->rx_status_1 &
495 AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
496 if (rx_status->rx_status_1 &
497 AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
498 rs->rs_status |= AR5K_RXERR_CRC;
499
500 if (rx_status->rx_status_1 &
501 AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
502 rs->rs_status |= AR5K_RXERR_PHY;
503 rs->rs_phyerr |= AR5K_REG_MS(rx_err->rx_error_1,
504 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
505 }
506
507 if (rx_status->rx_status_1 &
508 AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
509 rs->rs_status |= AR5K_RXERR_DECRYPT;
510
511 if (rx_status->rx_status_1 &
512 AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
513 rs->rs_status |= AR5K_RXERR_MIC;
514 }
515
516 return 0;
517 }
518
519 /*
520 * Init function pointers inside ath5k_hw struct
521 */
ath5k_hw_init_desc_functions(struct ath5k_hw * ah)522 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
523 {
524
525 if (ah->ah_version != AR5K_AR5210 &&
526 ah->ah_version != AR5K_AR5211 &&
527 ah->ah_version != AR5K_AR5212)
528 return -ENOTSUP;
529
530 if (ah->ah_version == AR5K_AR5212) {
531 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
532 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
533 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
534 } else {
535 ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
536 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
537 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
538 }
539
540 if (ah->ah_version == AR5K_AR5212)
541 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
542 else if (ah->ah_version <= AR5K_AR5211)
543 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
544
545 return 0;
546 }
547
548