1 /* Copyright 2013-2016 IBM Corp.
2 *
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 * http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
12 * implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #include <skiboot.h>
18 #include <opal-msg.h>
19 #include <pci-cfg.h>
20 #include <pci.h>
21 #include <pci-slot.h>
22
23 /* Debugging options */
24 #define PCIE_SLOT_PREFIX "PCIE-SLOT-%016llx "
25 #define PCIE_SLOT_DBG(s, fmt, a...) \
26 prlog(PR_DEBUG, PCIE_SLOT_PREFIX fmt, (s)->id, ##a)
27
pcie_slot_get_presence_state(struct pci_slot * slot,uint8_t * val)28 static int64_t pcie_slot_get_presence_state(struct pci_slot *slot, uint8_t *val)
29 {
30 struct phb *phb = slot->phb;
31 struct pci_device *pd = slot->pd;
32 uint32_t ecap;
33 uint16_t state;
34
35 /* The presence is always on if it's a switch upstream port */
36 if (pd->dev_type == PCIE_TYPE_SWITCH_UPPORT) {
37 *val = OPAL_PCI_SLOT_PRESENT;
38 return OPAL_SUCCESS;
39 }
40
41 /*
42 * The presence is always on if a switch downstream port
43 * doesn't support slot capability according to PCIE spec.
44 */
45 if (pd->dev_type == PCIE_TYPE_SWITCH_DNPORT &&
46 !(slot->pcie_cap & PCICAP_EXP_CAP_SLOT)) {
47 *val = OPAL_PCI_SLOT_PRESENT;
48 return OPAL_SUCCESS;
49 }
50
51 /* Retrieve presence status */
52 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
53 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTSTAT, &state);
54 if (state & PCICAP_EXP_SLOTSTAT_PDETECTST)
55 *val = OPAL_PCI_SLOT_PRESENT;
56 else
57 *val = OPAL_PCI_SLOT_EMPTY;
58
59 return OPAL_SUCCESS;
60 }
61
pcie_slot_get_link_state(struct pci_slot * slot,uint8_t * val)62 static int64_t pcie_slot_get_link_state(struct pci_slot *slot,
63 uint8_t *val)
64 {
65 struct phb *phb = slot->phb;
66 struct pci_device *pd = slot->pd;
67 uint32_t ecap;
68 int16_t state;
69
70 /*
71 * The link behind switch upstream port is always on
72 * since it doesn't have a valid link indicator.
73 */
74 if (pd->dev_type == PCIE_TYPE_SWITCH_UPPORT) {
75 *val = 1;
76 return OPAL_SUCCESS;
77 }
78
79 /* Retrieve link width */
80 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
81 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LSTAT, &state);
82 if (state & PCICAP_EXP_LSTAT_DLLL_ACT)
83 *val = ((state & PCICAP_EXP_LSTAT_WIDTH) >> 4);
84 else
85 *val = 0;
86
87 return OPAL_SUCCESS;
88 }
89
pcie_slot_get_power_state(struct pci_slot * slot __unused,uint8_t * val)90 static int64_t pcie_slot_get_power_state(struct pci_slot *slot __unused,
91 uint8_t *val)
92 {
93 /* We should return the cached power state that is same to
94 * the PCI slot hotplug state (added/removed). Otherwise,
95 * the OS will see mismatched states, causing the adapter
96 * behind the slot can't be probed successfully on request
97 * of hot add. So we could run into the situation where the
98 * OS sees power-off but it's on in hardware.
99 */
100 *val = slot->power_state;
101
102 return OPAL_SUCCESS;
103 }
104
pcie_slot_get_attention_state(struct pci_slot * slot,uint8_t * val)105 static int64_t pcie_slot_get_attention_state(struct pci_slot *slot,
106 uint8_t *val)
107 {
108 struct phb *phb = slot->phb;
109 struct pci_device *pd = slot->pd;
110 uint32_t ecap;
111 uint16_t state;
112
113 /* Attention is off if the capability is missing */
114 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_ATTNI)) {
115 *val = 0;
116 return OPAL_SUCCESS;
117 }
118
119 /* Retrieve attention state */
120 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
121 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state);
122 state = (state & PCICAP_EXP_SLOTCTL_ATTNI) >> 6;
123 switch (state) {
124 case PCIE_INDIC_ON:
125 *val = PCI_SLOT_ATTN_LED_ON;
126 break;
127 case PCIE_INDIC_BLINK:
128 *val = PCI_SLOT_ATTN_LED_BLINK;
129 break;
130 case PCIE_INDIC_OFF:
131 default:
132 *val = PCI_SLOT_ATTN_LED_OFF;
133 }
134
135 return OPAL_SUCCESS;
136 }
137
pcie_slot_get_latch_state(struct pci_slot * slot,uint8_t * val)138 static int64_t pcie_slot_get_latch_state(struct pci_slot *slot,
139 uint8_t *val)
140 {
141 struct phb *phb = slot->phb;
142 struct pci_device *pd = slot->pd;
143 uint32_t ecap;
144 uint16_t state;
145
146 /* Latch is off if MRL sensor doesn't exist */
147 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_MRLSENS)) {
148 *val = 0;
149 return OPAL_SUCCESS;
150 }
151
152 /* Retrieve MRL sensor state */
153 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
154 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTSTAT, &state);
155 if (state & PCICAP_EXP_SLOTSTAT_MRLSENSST)
156 *val = 1;
157 else
158 *val = 0;
159
160 return OPAL_SUCCESS;
161 }
162
pcie_slot_set_attention_state(struct pci_slot * slot,uint8_t val)163 static int64_t pcie_slot_set_attention_state(struct pci_slot *slot,
164 uint8_t val)
165 {
166 struct phb *phb = slot->phb;
167 struct pci_device *pd = slot->pd;
168 uint32_t ecap;
169 uint16_t state;
170
171 /* Drop the request if functionality doesn't exist */
172 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_ATTNI))
173 return OPAL_SUCCESS;
174
175 /* Update with the requested state */
176 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
177 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state);
178 state &= ~PCICAP_EXP_SLOTCTL_ATTNI;
179 switch (val) {
180 case PCI_SLOT_ATTN_LED_ON:
181 state |= (PCIE_INDIC_ON << 6);
182 break;
183 case PCI_SLOT_ATTN_LED_BLINK:
184 state |= (PCIE_INDIC_BLINK << 6);
185 break;
186 case PCI_SLOT_ATTN_LED_OFF:
187 state |= (PCIE_INDIC_OFF << 6);
188 break;
189 default:
190 prlog(PR_ERR, PCIE_SLOT_PREFIX
191 "Invalid attention state (0x%x)\n", slot->id, val);
192 return OPAL_PARAMETER;
193 }
194
195 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, state);
196 return OPAL_SUCCESS;
197 }
198
pcie_slot_set_power_state_ext(struct pci_slot * slot,uint8_t val,bool surprise_check)199 static int64_t pcie_slot_set_power_state_ext(struct pci_slot *slot, uint8_t val,
200 bool surprise_check)
201 {
202 struct phb *phb = slot->phb;
203 struct pci_device *pd = slot->pd;
204 uint32_t ecap;
205 uint16_t state;
206
207 if (slot->power_state == val)
208 return OPAL_PARAMETER;
209
210 /* Update the power state and return immediately if the power
211 * control functionality isn't supported on the PCI slot.
212 */
213 if (!(slot->slot_cap & PCICAP_EXP_SLOTCAP_PWCTRL)) {
214 slot->power_state = val;
215 return OPAL_SUCCESS;
216 }
217
218 /* The power supply to the slot should be always on when surprise
219 * hotplug is claimed. For this case, update with the requested
220 * power state and bail immediately.
221 *
222 * The PCIe link is likely down if we're powering on the slot upon
223 * the detected presence. Nothing behind the slot will be probed if
224 * we do it immediately even we do have PCI devices connected to the
225 * slot. For this case, we force upper layer to wait for the PCIe
226 * link to be up before probing the PCI devices behind the slot. It's
227 * only concerned in surprise hotplug path. In managed hot-add path,
228 * the PCIe link should have been ready before we power on the slot.
229 * However, it's not harmful to do so in managed hot-add path.
230 *
231 * When flag PCI_SLOT_FLAG_FORCE_POWERON is set for the PCI slot, we
232 * should turn on the slot's power supply on hardware on user's request
233 * because that might have been lost. Otherwise, the PCIe link behind
234 * the slot won't become ready for ever and PCI adapter behind the slot
235 * can't be probed successfully.
236 */
237 if (surprise_check && slot->surprise_pluggable) {
238 slot->power_state = val;
239 if (val == PCI_SLOT_POWER_OFF)
240 return OPAL_SUCCESS;
241
242 if (!pci_slot_has_flags(slot, PCI_SLOT_FLAG_FORCE_POWERON)) {
243 pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_DONE);
244 return OPAL_ASYNC_COMPLETION;
245 }
246 }
247
248 pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_START);
249 slot->power_state = val;
250 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
251 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, &state);
252 state &= ~(PCICAP_EXP_SLOTCTL_PWRCTLR | PCICAP_EXP_SLOTCTL_PWRI);
253 switch (val) {
254 case PCI_SLOT_POWER_OFF:
255 state |= (PCICAP_EXP_SLOTCTL_PWRCTLR | (PCIE_INDIC_OFF << 8));
256 break;
257 case PCI_SLOT_POWER_ON:
258 state |= (PCIE_INDIC_ON << 8);
259 break;
260 default:
261 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
262 prlog(PR_ERR, PCIE_SLOT_PREFIX
263 "Invalid power state (0x%x)\n", slot->id, val);
264 return OPAL_PARAMETER;
265 }
266
267 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL, state);
268 pci_slot_set_state(slot, PCI_SLOT_STATE_SPOWER_DONE);
269
270 return OPAL_ASYNC_COMPLETION;
271 }
272
pcie_slot_set_power_state(struct pci_slot * slot,uint8_t val)273 static int64_t pcie_slot_set_power_state(struct pci_slot *slot, uint8_t val)
274 {
275 return pcie_slot_set_power_state_ext(slot, val, true);
276 }
277
pcie_slot_sm_poll_link(struct pci_slot * slot)278 static int64_t pcie_slot_sm_poll_link(struct pci_slot *slot)
279 {
280 struct phb *phb = slot->phb;
281 struct pci_device *pd = slot->pd;
282 uint32_t ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
283 uint16_t val;
284 uint8_t presence = 0;
285
286 switch (slot->state) {
287 case PCI_SLOT_STATE_LINK_START_POLL:
288 PCIE_SLOT_DBG(slot, "LINK: Start polling\n");
289
290 /* Link is down for ever without devices attached */
291 if (slot->ops.get_presence_state)
292 slot->ops.get_presence_state(slot, &presence);
293 if (!presence) {
294 PCIE_SLOT_DBG(slot, "LINK: No adapter, end polling\n");
295 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
296 return OPAL_SUCCESS;
297 }
298
299 /* Enable the link without check */
300 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, &val);
301 val &= ~PCICAP_EXP_LCTL_LINK_DIS;
302 pci_cfg_write16(phb, pd->bdfn, ecap + PCICAP_EXP_LCTL, val);
303
304 /*
305 * If the link change report isn't supported, we expect
306 * the link is up and stabilized after one second.
307 */
308 if (!(slot->link_cap & PCICAP_EXP_LCAP_DL_ACT_REP)) {
309 pci_slot_set_state(slot,
310 PCI_SLOT_STATE_LINK_DELAY_FINALIZED);
311 return pci_slot_set_sm_timeout(slot, secs_to_tb(1));
312 }
313
314 /*
315 * Poll the link state if link state change report is
316 * supported on the link.
317 */
318 pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_POLLING);
319 slot->retries = 250;
320 return pci_slot_set_sm_timeout(slot, msecs_to_tb(20));
321 case PCI_SLOT_STATE_LINK_DELAY_FINALIZED:
322 PCIE_SLOT_DBG(slot, "LINK: No link report, end polling\n");
323 if (slot->ops.prepare_link_change)
324 slot->ops.prepare_link_change(slot, true);
325 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
326 return OPAL_SUCCESS;
327 case PCI_SLOT_STATE_LINK_POLLING:
328 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_LSTAT, &val);
329 if (val & PCICAP_EXP_LSTAT_DLLL_ACT) {
330 PCIE_SLOT_DBG(slot, "LINK: Link is up, end polling\n");
331 if (slot->ops.prepare_link_change)
332 slot->ops.prepare_link_change(slot, true);
333 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
334 return OPAL_SUCCESS;
335 }
336
337 /* Check link state again until timeout */
338 if (slot->retries-- == 0) {
339 prlog(PR_ERR, PCIE_SLOT_PREFIX
340 "LINK: Timeout waiting for up (%04x)\n",
341 slot->id, val);
342 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
343 return OPAL_SUCCESS;
344 }
345
346 return pci_slot_set_sm_timeout(slot, msecs_to_tb(20));
347 default:
348 prlog(PR_ERR, PCIE_SLOT_PREFIX
349 "Link: Unexpected slot state %08x\n",
350 slot->id, slot->state);
351 }
352
353 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
354 return OPAL_HARDWARE;
355 }
356
pcie_slot_reset(struct pci_slot * slot,bool assert)357 static void pcie_slot_reset(struct pci_slot *slot, bool assert)
358 {
359 struct phb *phb = slot->phb;
360 struct pci_device *pd = slot->pd;
361 uint16_t ctl;
362
363 pci_cfg_read16(phb, pd->bdfn, PCI_CFG_BRCTL, &ctl);
364 if (assert)
365 ctl |= PCI_CFG_BRCTL_SECONDARY_RESET;
366 else
367 ctl &= ~PCI_CFG_BRCTL_SECONDARY_RESET;
368 pci_cfg_write16(phb, pd->bdfn, PCI_CFG_BRCTL, ctl);
369 }
370
pcie_slot_sm_hreset(struct pci_slot * slot)371 static int64_t pcie_slot_sm_hreset(struct pci_slot *slot)
372 {
373 switch (slot->state) {
374 case PCI_SLOT_STATE_NORMAL:
375 PCIE_SLOT_DBG(slot, "HRESET: Starts\n");
376 if (slot->ops.prepare_link_change) {
377 PCIE_SLOT_DBG(slot, "HRESET: Prepare for link down\n");
378 slot->ops.prepare_link_change(slot, false);
379 }
380 /* fall through */
381 case PCI_SLOT_STATE_HRESET_START:
382 PCIE_SLOT_DBG(slot, "HRESET: Assert\n");
383 pcie_slot_reset(slot, true);
384 pci_slot_set_state(slot, PCI_SLOT_STATE_HRESET_HOLD);
385 return pci_slot_set_sm_timeout(slot, msecs_to_tb(250));
386 case PCI_SLOT_STATE_HRESET_HOLD:
387 PCIE_SLOT_DBG(slot, "HRESET: Deassert\n");
388 pcie_slot_reset(slot, false);
389 pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_START_POLL);
390 return pci_slot_set_sm_timeout(slot, msecs_to_tb(1800));
391 default:
392 PCIE_SLOT_DBG(slot, "HRESET: Unexpected slot state %08x\n",
393 slot->state);
394 }
395
396 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
397 return OPAL_HARDWARE;
398 }
399
400 /*
401 * Usually, individual platforms need to override the power
402 * management methods for fundamental reset, but the hot
403 * reset method is commonly shared.
404 */
pcie_slot_sm_freset(struct pci_slot * slot)405 static int64_t pcie_slot_sm_freset(struct pci_slot *slot)
406 {
407 uint8_t power_state = PCI_SLOT_POWER_ON;
408
409 switch (slot->state) {
410 case PCI_SLOT_STATE_NORMAL:
411 PCIE_SLOT_DBG(slot, "FRESET: Starts\n");
412 if (slot->ops.prepare_link_change)
413 slot->ops.prepare_link_change(slot, false);
414
415 /* Retrieve power state */
416 if (slot->ops.get_power_state) {
417 PCIE_SLOT_DBG(slot, "FRESET: Retrieve power state\n");
418 slot->ops.get_power_state(slot, &power_state);
419 }
420
421 /* In power on state, power it off */
422 if (power_state == PCI_SLOT_POWER_ON) {
423 PCIE_SLOT_DBG(slot, "FRESET: Power is on, turn off\n");
424 pcie_slot_set_power_state_ext(slot,
425 PCI_SLOT_POWER_OFF, false);
426 pci_slot_set_state(slot,
427 PCI_SLOT_STATE_FRESET_POWER_OFF);
428 return pci_slot_set_sm_timeout(slot, msecs_to_tb(50));
429 }
430 /* No power state change, */
431 /* fallthrough */
432 case PCI_SLOT_STATE_FRESET_POWER_OFF:
433 PCIE_SLOT_DBG(slot, "FRESET: Power is off, turn on\n");
434 pcie_slot_set_power_state_ext(slot, PCI_SLOT_POWER_ON, false);
435
436 pci_slot_set_state(slot, PCI_SLOT_STATE_LINK_START_POLL);
437 return pci_slot_set_sm_timeout(slot, msecs_to_tb(50));
438 default:
439 prlog(PR_ERR, PCIE_SLOT_PREFIX
440 "FRESET: Unexpected slot state %08x\n",
441 slot->id, slot->state);
442 }
443
444 pci_slot_set_state(slot, PCI_SLOT_STATE_NORMAL);
445 return OPAL_HARDWARE;
446 }
447
pcie_slot_create(struct phb * phb,struct pci_device * pd)448 struct pci_slot *pcie_slot_create(struct phb *phb, struct pci_device *pd)
449 {
450 struct pci_slot *slot;
451 uint32_t ecap;
452 uint16_t slot_ctl;
453
454 /* Allocate PCI slot */
455 slot = pci_slot_alloc(phb, pd);
456 if (!slot)
457 return NULL;
458
459 /* Cache the link and slot capabilities */
460 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
461 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_CAPABILITY_REG,
462 &slot->pcie_cap);
463 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_LCAP,
464 &slot->link_cap);
465
466 /* Leave PCI slot capability blank if PCI slot isn't supported */
467 if (slot->pcie_cap & PCICAP_EXP_CAP_SLOT)
468 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCAP,
469 &slot->slot_cap);
470 else
471 slot->slot_cap = 0;
472
473 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_HPLUG_CAP)
474 slot->pluggable = 1;
475
476 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_PWCTRL) {
477 slot->power_ctl = 1;
478
479 /* The power is on by default */
480 slot->power_state = PCI_SLOT_POWER_ON;
481 pci_cfg_read16(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCTL,
482 &slot_ctl);
483 if (((slot_ctl & PCICAP_EXP_SLOTCTL_PWRI) >> 8) == PCIE_INDIC_OFF)
484 slot->power_state = PCI_SLOT_POWER_OFF;
485 }
486
487 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_PWRI)
488 slot->power_led_ctl = PCI_SLOT_PWR_LED_CTL_KERNEL;
489 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_ATTNI)
490 slot->attn_led_ctl = PCI_SLOT_ATTN_LED_CTL_KERNEL;
491 slot->wired_lanes = ((slot->link_cap & PCICAP_EXP_LCAP_MAXWDTH) >> 4);
492
493 /* The surprise hotplug capability is claimed when it's supported
494 * in the slot's capability bits or link state change reporting is
495 * supported in PCIe link capability. It means the surprise hotplug
496 * relies on presence or link state change events. In order for the
497 * link state change event to be properly raised during surprise hot
498 * add/remove, the power supply to the slot should be always on.
499 *
500 * For PCI slots that don't claim surprise hotplug capability explicitly.
501 * Its PDC (Presence Detection Change) isn't reliable. To mark that as
502 * broken on them.
503 */
504 if (slot->pcie_cap & PCICAP_EXP_CAP_SLOT) {
505 if (slot->slot_cap & PCICAP_EXP_SLOTCAP_HPLUG_SURP) {
506 slot->surprise_pluggable = 1;
507 } else if (slot->link_cap & PCICAP_EXP_LCAP_DL_ACT_REP) {
508 slot->surprise_pluggable = 1;
509
510 pci_slot_add_flags(slot, PCI_SLOT_FLAG_BROKEN_PDC);
511 }
512 }
513
514 /* Standard slot operations */
515 slot->ops.get_presence_state = pcie_slot_get_presence_state;
516 slot->ops.get_link_state = pcie_slot_get_link_state;
517 slot->ops.get_power_state = pcie_slot_get_power_state;
518 slot->ops.get_attention_state = pcie_slot_get_attention_state;
519 slot->ops.get_latch_state = pcie_slot_get_latch_state;
520 slot->ops.set_power_state = pcie_slot_set_power_state;
521 slot->ops.set_attention_state = pcie_slot_set_attention_state;
522
523 /*
524 * State machine (SM) based reset stuff. The poll function is always
525 * unified for all cases.
526 */
527 slot->ops.poll_link = pcie_slot_sm_poll_link;
528 slot->ops.hreset = pcie_slot_sm_hreset;
529 slot->ops.freset = pcie_slot_sm_freset;
530
531 slot->wired_lanes = PCI_SLOT_WIRED_LANES_UNKNOWN;
532 slot->connector_type = PCI_SLOT_CONNECTOR_PCIE_NS;
533 slot->card_desc = PCI_SLOT_DESC_NON_STANDARD;
534 slot->card_mech = PCI_SLOT_MECH_NONE;
535 slot->power_led_ctl = PCI_SLOT_PWR_LED_CTL_NONE;
536 slot->attn_led_ctl = PCI_SLOT_ATTN_LED_CTL_NONE;
537
538 return slot;
539 }
540
541 /* FIXME: this is kind of insane */
pcie_slot_create_dynamic(struct phb * phb,struct pci_device * pd)542 struct pci_slot *pcie_slot_create_dynamic(struct phb *phb,
543 struct pci_device *pd)
544 {
545 uint32_t ecap, val;
546 struct pci_slot *slot;
547
548 if (!phb || !pd || pd->slot)
549 return NULL;
550
551 /* Try to create slot whose details aren't provided by platform.
552 * We only care the downstream ports of PCIe switch that connects
553 * to root port.
554 */
555 if (pd->dev_type != PCIE_TYPE_SWITCH_DNPORT ||
556 !pd->parent || !pd->parent->parent ||
557 pd->parent->parent->parent)
558 return NULL;
559
560 ecap = pci_cap(pd, PCI_CFG_CAP_ID_EXP, false);
561 pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCAP, &val);
562 if (!(val & PCICAP_EXP_SLOTCAP_HPLUG_CAP))
563 return NULL;
564
565 slot = pcie_slot_create(phb, pd);
566
567 /* On superMicro's "p8dnu" platform, we create dynamic PCI slots
568 * for all downstream ports of PEX9733 that is connected to PHB
569 * direct slot. The power supply to the PCI slot is lost after
570 * PCI adapter is removed from it. The power supply can't be
571 * turned on when the slot is in empty state. The power supply
572 * isn't turned on automatically when inserting PCI adapter to
573 * the slot at later point. We set a flag to the slot here, to
574 * turn on the power supply in (suprise or managed) hot-add path.
575 *
576 * We have same issue with PEX8718 as above on "p8dnu" platform.
577 */
578 if (dt_node_is_compatible(dt_root, "supermicro,p8dnu") && slot->pd &&
579 (slot->pd->vdid == 0x973310b5 || slot->pd->vdid == 0x871810b5))
580 pci_slot_add_flags(slot, PCI_SLOT_FLAG_FORCE_POWERON);
581
582 return slot;
583 }
584