1 /* Copyright 2013-2016 IBM Corp. 2 * 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or 12 * implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __PHB4_REGS_H 18 #define __PHB4_REGS_H 19 20 /* 21 * PHB registers 22 */ 23 24 /* PHB Fundamental register set A */ 25 /* phb4_spec_036.pdf, page 80, "5.4.1 ETU/RSB HV Register Address Map" */ 26 /* FIXME: check these (phb3 currently below) */ 27 #define PHB_LSI_SOURCE_ID 0x100 28 #define PHB_LSI_SRC_ID PPC_BITMASK(4,12) 29 #define PHB_DMA_CHAN_STATUS 0x110 30 #define PHB_DMA_CHAN_ANY_ERR PPC_BIT(27) 31 #define PHB_DMA_CHAN_ANY_ERR1 PPC_BIT(28) 32 #define PHB_DMA_CHAN_ANY_FREEZE PPC_BIT(29) 33 #define PHB_CPU_LOADSTORE_STATUS 0x120 34 #define PHB_CPU_LS_ANY_ERR PPC_BIT(27) 35 #define PHB_CPU_LS_ANY_ERR1 PPC_BIT(28) 36 #define PHB_CPU_LS_ANY_FREEZE PPC_BIT(29) 37 #define PHB_DMA_MSI_NODE_ID 0x128 38 #define PHB_DMAMSI_NID_FIXED PPC_BIT(0) 39 #define PHB_DMAMSI_NID PPC_BITMASK(24,31) 40 #define PHB_CONFIG_DATA 0x130 41 #define PHB_LOCK0 0x138 42 #define PHB_CONFIG_ADDRESS 0x140 43 #define PHB_CA_ENABLE PPC_BIT(0) 44 #define PHB_CA_STATUS PPC_BITMASK(1,3) 45 #define PHB_CA_BUS PPC_BITMASK(4,11) 46 #define PHB_CA_DEV PPC_BITMASK(12,16) 47 #define PHB_CA_FUNC PPC_BITMASK(17,19) 48 #define PHB_CA_BDFN PPC_BITMASK(4,19) /* bus,dev,func */ 49 #define PHB_CA_REG PPC_BITMASK(20,31) 50 #define PHB_CA_PE PPC_BITMASK(39,47) 51 #define PHB_LOCK1 0x148 52 #define PHB_IVT_BAR 0x150 53 #define PHB_IVT_BAR_ENABLE PPC_BIT(0) 54 #define PHB_IVT_BASE_ADDRESS PPC_BITMASK(14,48) 55 #define PHB_IVT_LENGTH PPC_BITMASK(52,63) 56 #define PHB_RBA_BAR 0x158 57 #define PHB_RBA_BAR_ENABLE PPC_BIT(0) 58 #define PHB_RBA_BASE_ADDRESS PPC_BITMASK(14,55) 59 #define PHB_PHB4_CONFIG 0x160 60 #define PHB_PHB4C_32BIT_MSI_EN PPC_BIT(8) 61 #define PHB_PHB4C_64BIT_MSI_EN PPC_BIT(14) 62 #define PHB_RTT_BAR 0x168 63 #define PHB_RTT_BAR_ENABLE PPC_BIT(0) 64 #define PHB_RTT_BASE_ADDRESS PPC_BITMASK(8,46) 65 #define PHB_PELTV_BAR 0x188 66 #define PHB_PELTV_BAR_ENABLE PPC_BIT(0) 67 #define PHB_PELTV_BASE_ADDRESS PPC_BITMASK(8,50) 68 #define PHB_M32_BASE_ADDR 0x190 69 #define PHB_M32_BASE_MASK 0x198 70 #define PHB_M32_START_ADDR 0x1a0 71 #define PHB_PEST_BAR 0x1a8 72 #define PHB_PEST_BAR_ENABLE PPC_BIT(0) 73 #define PHB_PEST_BASE_ADDRESS PPC_BITMASK(8,51) 74 #define PHB_PBL_ASN_CMPM 0x1C0 75 #define PHB_PBL_ASN_ENABLE PPC_BIT(63) 76 #define PHB_CAPI_CMPM 0x1C8 77 #define PHB_CAPI_CMPM_ENABLE PPC_BIT(63) 78 #define PHB_M64_UPPER_BITS 0x1f0 79 #define PHB_NXLATE_PREFIX 0x1f8 80 #define PHB_DMARD_SYNC 0x200 81 #define PHB_DMARD_SYNC_START PPC_BIT(0) 82 #define PHB_DMARD_SYNC_COMPLETE PPC_BIT(1) 83 #define PHB_RTC_INVALIDATE 0x208 84 #define PHB_RTC_INVALIDATE_ALL PPC_BIT(0) 85 #define PHB_RTC_INVALIDATE_RID PPC_BITMASK(16,31) 86 #define PHB_TCE_KILL 0x210 87 #define PHB_TCE_KILL_ALL PPC_BIT(0) 88 #define PHB_TCE_KILL_PE PPC_BIT(1) 89 #define PHB_TCE_KILL_ONE PPC_BIT(2) 90 #define PHB_TCE_KILL_PSEL PPC_BIT(3) 91 #define PHB_TCE_KILL_64K 0x1000 /* Address override */ 92 #define PHB_TCE_KILL_2M 0x2000 /* Address override */ 93 #define PHB_TCE_KILL_1G 0x3000 /* Address override */ 94 #define PHB_TCE_KILL_PENUM PPC_BITMASK(55,63) 95 #define PHB_TCE_SPEC_CTL 0x218 96 #define PHB_IODA_ADDR 0x220 97 #define PHB_IODA_AD_AUTOINC PPC_BIT(0) 98 #define PHB_IODA_AD_TSEL PPC_BITMASK(11,15) 99 #define PHB_IODA_AD_MIST_PWV PPC_BITMASK(28,31) 100 #define PHB_IODA_AD_TADR PPC_BITMASK(54,63) 101 #define PHB_IODA_DATA0 0x228 102 #define PHB_FFI_REQUEST 0x238 103 #define PHB_FFI_LOCK_CLEAR PPC_BIT(3) 104 #define PHB_FFI_REQUEST_ISN PPC_BITMASK(49,59) 105 #define PHB_FFI_LOCK 0x240 106 #define PHB_XIVE_UPDATE 0x248 /* Broken in DD1 */ 107 #define PHB_PHB4_GEN_CAP 0x250 108 #define PHB_PHB4_TCE_CAP 0x258 109 #define PHB_PHB4_IRQ_CAP 0x260 110 #define PHB_PHB4_EEH_CAP 0x268 111 #define PHB_PAPR_ERR_INJ_CTL 0x2b0 112 #define PHB_PAPR_ERR_INJ_CTL_INB PPC_BIT(0) 113 #define PHB_PAPR_ERR_INJ_CTL_OUTB PPC_BIT(1) 114 #define PHB_PAPR_ERR_INJ_CTL_STICKY PPC_BIT(2) 115 #define PHB_PAPR_ERR_INJ_CTL_CFG PPC_BIT(3) 116 #define PHB_PAPR_ERR_INJ_CTL_RD PPC_BIT(4) 117 #define PHB_PAPR_ERR_INJ_CTL_WR PPC_BIT(5) 118 #define PHB_PAPR_ERR_INJ_CTL_FREEZE PPC_BIT(6) 119 #define PHB_PAPR_ERR_INJ_ADDR 0x2b8 120 #define PHB_PAPR_ERR_INJ_ADDR_MMIO PPC_BITMASK(16,63) 121 #define PHB_PAPR_ERR_INJ_MASK 0x2c0 122 #define PHB_PAPR_ERR_INJ_MASK_CFG PPC_BITMASK(4,11) 123 #define PHB_PAPR_ERR_INJ_MASK_CFG_ALL PPC_BITMASK(4,19) 124 #define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16,63) 125 #define PHB_ETU_ERR_SUMMARY 0x2c8 126 #define PHB_INT_NOTIFY_ADDR 0x300 127 #define PHB_INT_NOTIFY_INDEX 0x308 128 129 #define PHB_VERSION 0x800 130 #define PHB_CTRLR 0x810 131 #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) 132 #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) 133 #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) 134 #define PHB_CTRLR_MMIO_EEH_DISABLE PPC_BIT(14) 135 #define PHB_CTRLR_CFG_EEH_BLOCK PPC_BIT(15) 136 #define PHB_CTRLR_FENCE_LNKILL_DIS PPC_BIT(16) 137 #define PHB_CTRLR_TVT_ADDR_SEL PPC_BITMASK(17,19) 138 #define TVT_DD1_1_PER_PE 0 139 #define TVT_DD1_2_PER_PE 1 140 #define TVT_DD1_4_PER_PE 2 141 #define TVT_DD1_8_PER_PE 3 142 #define TVT_DD1_16_PER_PE 4 143 #define TVT_2_PER_PE 0 144 #define TVT_4_PER_PE 1 145 #define TVT_8_PER_PE 2 146 #define TVT_16_PER_PE 3 147 #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28,31) 148 #define PHB_AIB_FENCE_CTRL 0x860 149 #define PHB_TCE_TAG_ENABLE 0x868 150 #define PHB_TCE_WATERMARK 0x870 151 #define PHB_TIMEOUT_CTRL1 0x878 152 #define PHB_TIMEOUT_CTRL2 0x880 153 #define PHB_Q_DMA_R 0x888 154 #define PHB_Q_DMA_R_QUIESCE_DMA PPC_BIT(0) 155 #define PHB_Q_DMA_R_AUTORESET PPC_BIT(1) 156 #define PHB_Q_DMA_R_DMA_RESP_STATUS PPC_BIT(4) 157 #define PHB_Q_DMA_R_MMIO_RESP_STATUS PPC_BIT(5) 158 #define PHB_Q_DMA_R_TCE_RESP_STATUS PPC_BIT(6) 159 #define PHB_Q_DMA_R_TCE_KILL_STATUS PPC_BIT(7) 160 #define PHB_TCE_TAG_STATUS 0x908 161 162 /* FIR & Error registers - identical to PHB3 */ 163 #define PHB_LEM_FIR_ACCUM 0xc00 164 #define PHB_LEM_FIR_AND_MASK 0xc08 165 #define PHB_LEM_FIR_OR_MASK 0xc10 166 #define PHB_LEM_ERROR_MASK 0xc18 167 #define PHB_LEM_ERROR_AND_MASK 0xc20 168 #define PHB_LEM_ERROR_OR_MASK 0xc28 169 #define PHB_LEM_ACTION0 0xc30 170 #define PHB_LEM_ACTION1 0xc38 171 #define PHB_LEM_WOF 0xc40 172 #define PHB_ERR_STATUS 0xc80 173 #define PHB_ERR1_STATUS 0xc88 174 #define PHB_ERR_INJECT 0xc90 175 #define PHB_ERR_LEM_ENABLE 0xc98 176 #define PHB_ERR_IRQ_ENABLE 0xca0 177 #define PHB_ERR_FREEZE_ENABLE 0xca8 178 #define PHB_ERR_AIB_FENCE_ENABLE 0xcb0 179 #define PHB_ERR_LOG_0 0xcc0 180 #define PHB_ERR_LOG_1 0xcc8 181 #define PHB_ERR_STATUS_MASK 0xcd0 182 #define PHB_ERR1_STATUS_MASK 0xcd8 183 184 /* 185 * Instead of MMIO outbound, inboundA and inboundB in PHB3, 186 * PHB4 has TXE (outbound), RXE_ARB, RXE_MRG and RXE_TCE. 187 */ 188 189 #define PHB_TXE_ERR_STATUS 0xd00 190 #define PHB_TXE_ERR1_STATUS 0xd08 191 #define PHB_TXE_ERR_INJECT 0xd10 192 #define PHB_TXE_ERR_LEM_ENABLE 0xd18 193 #define PHB_TXE_ERR_IRQ_ENABLE 0xd20 194 #define PHB_TXE_ERR_FREEZE_ENABLE 0xd28 195 #define PHB_TXE_ERR_AIB_FENCE_ENABLE 0xd30 196 #define PHB_TXE_ERR_LOG_0 0xd40 197 #define PHB_TXE_ERR_LOG_1 0xd48 198 #define PHB_TXE_ERR_STATUS_MASK 0xd50 199 #define PHB_TXE_ERR1_STATUS_MASK 0xd58 200 201 #define PHB_RXE_ARB_ERR_STATUS 0xd80 202 #define PHB_RXE_ARB_ERR1_STATUS 0xd88 203 #define PHB_RXE_ARB_ERR_INJECT 0xd90 204 #define PHB_RXE_ARB_ERR_LEM_ENABLE 0xd98 205 #define PHB_RXE_ARB_ERR_IRQ_ENABLE 0xda0 206 #define PHB_RXE_ARB_ERR_FREEZE_ENABLE 0xda8 207 #define PHB_RXE_ARB_ERR_AIB_FENCE_ENABLE 0xdb0 208 #define PHB_RXE_ARB_ERR_LOG_0 0xdc0 209 #define PHB_RXE_ARB_ERR_LOG_1 0xdc8 210 #define PHB_RXE_ARB_ERR_STATUS_MASK 0xdd0 211 #define PHB_RXE_ARB_ERR1_STATUS_MASK 0xdd8 212 213 #define PHB_RXE_MRG_ERR_STATUS 0xe00 214 #define PHB_RXE_MRG_ERR1_STATUS 0xe08 215 #define PHB_RXE_MRG_ERR_INJECT 0xe10 216 #define PHB_RXE_MRG_ERR_LEM_ENABLE 0xe18 217 #define PHB_RXE_MRG_ERR_IRQ_ENABLE 0xe20 218 #define PHB_RXE_MRG_ERR_FREEZE_ENABLE 0xe28 219 #define PHB_RXE_MRG_ERR_AIB_FENCE_ENABLE 0xe30 220 #define PHB_RXE_MRG_ERR_LOG_0 0xe40 221 #define PHB_RXE_MRG_ERR_LOG_1 0xe48 222 #define PHB_RXE_MRG_ERR_STATUS_MASK 0xe50 223 #define PHB_RXE_MRG_ERR1_STATUS_MASK 0xe58 224 225 #define PHB_RXE_TCE_ERR_STATUS 0xe80 226 #define PHB_RXE_TCE_ERR1_STATUS 0xe88 227 #define PHB_RXE_TCE_ERR_INJECT 0xe90 228 #define PHB_RXE_TCE_ERR_LEM_ENABLE 0xe98 229 #define PHB_RXE_TCE_ERR_IRQ_ENABLE 0xea0 230 #define PHB_RXE_TCE_ERR_FREEZE_ENABLE 0xea8 231 #define PHB_RXE_TCE_ERR_AIB_FENCE_ENABLE 0xeb0 232 #define PHB_RXE_TCE_ERR_LOG_0 0xec0 233 #define PHB_RXE_TCE_ERR_LOG_1 0xec8 234 #define PHB_RXE_TCE_ERR_STATUS_MASK 0xed0 235 #define PHB_RXE_TCE_ERR1_STATUS_MASK 0xed8 236 237 /* Performance monitor & Debug registers */ 238 #define PHB_TRACE_CONTROL 0xf80 239 #define PHB_PERFMON_CONFIG 0xf88 240 #define PHB_PERFMON_CTR0 0xf90 241 #define PHB_PERFMON_CTR1 0xf98 242 #define PHB_PERFMON_CTR2 0xfa0 243 #define PHB_PERFMON_CTR3 0xfa8 244 245 // FIXME add more here 246 #define PHB_RC_CONFIG_BASE 0x1000 247 #define PHB_RC_CONFIG_SIZE 0x800 248 249 /* PHB4 REGB registers */ 250 #define PHB_PBL_CONTROL 0x1800 251 #define PHB_PBL_TIMEOUT_CTRL 0x1810 252 #define PHB_PBL_NPTAG_ENABLE 0x1820 253 #define PHB_PBL_NBW_CMP_MASK 0x1830 254 #define PHB_PBL_NBW_MASK_ENABLE PPC_BIT(63) 255 #define PHB_PBL_SYS_LINK_INIT 0x1838 256 #define PHB_PBL_BUF_STATUS 0x1840 257 #define PHB_PBL_ERR_STATUS 0x1900 258 #define PHB_PBL_ERR1_STATUS 0x1908 259 #define PHB_PBL_ERR_INJECT 0x1910 260 #define PHB_PBL_ERR_INF_ENABLE 0x1920 261 #define PHB_PBL_ERR_ERC_ENABLE 0x1928 262 #define PHB_PBL_ERR_FAT_ENABLE 0x1930 263 #define PHB_PBL_ERR_LOG_0 0x1940 264 #define PHB_PBL_ERR_LOG_1 0x1948 265 #define PHB_PBL_ERR_STATUS_MASK 0x1950 266 #define PHB_PBL_ERR1_STATUS_MASK 0x1958 267 268 // FIXME add more here 269 #define PHB_PCIE_SCR 0x1A00 270 #define PHB_PCIE_SCR_MAXLINKSPEED PPC_BITMASK(32,35) 271 272 273 #define PHB_PCIE_CRESET 0x1A10 274 #define PHB_PCIE_CRESET_CFG_CORE PPC_BIT(0) 275 #define PHB_PCIE_CRESET_TLDLP PPC_BIT(1) 276 #define PHB_PCIE_CRESET_PBL PPC_BIT(2) 277 #define PHB_PCIE_CRESET_PERST_N PPC_BIT(3) 278 #define PHB_PCIE_CRESET_PIPE_N PPC_BIT(4) 279 280 281 #define PHB_PCIE_HOTPLUG_STATUS 0x1A20 282 #define PHB_PCIE_HPSTAT_PRESENCE PPC_BIT(10) 283 284 #define PHB_PCIE_DLP_TRAIN_CTL 0x1A40 285 #define PHB_PCIE_DLP_LINK_WIDTH PPC_BITMASK(30,35) 286 #define PHB_PCIE_DLP_LINK_SPEED PPC_BITMASK(36,39) 287 #define PHB_PCIE_DLP_LTSSM_TRC PPC_BITMASK(24,27) 288 #define PHB_PCIE_DLP_LTSSM_RESET 0 289 #define PHB_PCIE_DLP_LTSSM_DETECT 1 290 #define PHB_PCIE_DLP_LTSSM_POLLING 2 291 #define PHB_PCIE_DLP_LTSSM_CONFIG 3 292 #define PHB_PCIE_DLP_LTSSM_L0 4 293 #define PHB_PCIE_DLP_LTSSM_REC 5 294 #define PHB_PCIE_DLP_LTSSM_L1 6 295 #define PHB_PCIE_DLP_LTSSM_L2 7 296 #define PHB_PCIE_DLP_LTSSM_HOTRESET 8 297 #define PHB_PCIE_DLP_LTSSM_DISABLED 9 298 #define PHB_PCIE_DLP_LTSSM_LOOPBACK 10 299 #define PHB_PCIE_DLP_TL_LINKACT PPC_BIT(23) 300 #define PHB_PCIE_DLP_DL_PGRESET PPC_BIT(22) 301 #define PHB_PCIE_DLP_TRAINING PPC_BIT(20) 302 #define PHB_PCIE_DLP_INBAND_PRESENCE PPC_BIT(19) 303 304 #define PHB_PCIE_DLP_TRWCTL 0x1A80 305 #define PHB_PCIE_DLP_TRWCTL_EN PPC_BIT(0) 306 307 #define PHB_PCIE_DLP_ERRLOG1 0x1AA0 308 #define PHB_PCIE_DLP_ERRLOG2 0x1AA8 309 #define PHB_PCIE_DLP_ERR_STATUS 0x1AB0 310 #define PHB_PCIE_DLP_ERR_COUNTERS 0x1AB8 311 312 #define PHB_PCIE_LANE_EQ_CNTL0 0x1AD0 313 #define PHB_PCIE_LANE_EQ_CNTL1 0x1AD8 314 #define PHB_PCIE_LANE_EQ_CNTL2 0x1AE0 315 #define PHB_PCIE_LANE_EQ_CNTL3 0x1AE8 316 #define PHB_PCIE_LANE_EQ_CNTL20 0x1AF0 317 #define PHB_PCIE_LANE_EQ_CNTL21 0x1AF8 318 #define PHB_PCIE_LANE_EQ_CNTL22 0x1B00 /* DD1 only */ 319 #define PHB_PCIE_LANE_EQ_CNTL23 0x1B08 /* DD1 only */ 320 #define PHB_PCIE_TRACE_CTRL 0x1B20 321 #define PHB_PCIE_MISC_STRAP 0x1B30 322 323 #define PHB_REGB_ERR_STATUS 0x1C00 324 #define PHB_REGB_ERR1_STATUS 0x1C08 325 #define PHB_REGB_ERR_INJECT 0x1C10 326 #define PHB_REGB_ERR_INF_ENABLE 0x1C20 327 #define PHB_REGB_ERR_ERC_ENABLE 0x1C28 328 #define PHB_REGB_ERR_FAT_ENABLE 0x1C30 329 #define PHB_REGB_ERR_LOG_0 0x1C40 330 #define PHB_REGB_ERR_LOG_1 0x1C48 331 #define PHB_REGB_ERR_STATUS_MASK 0x1C50 332 #define PHB_REGB_ERR1_STATUS_MASK 0x1C58 333 334 /* 335 * PHB4 xscom address defines 336 */ 337 338 /* Nest base registers */ 339 #define XPEC_NEST_PBCQ_HW_CONFIG 0x0 340 #define XPEC_NEST_PBCQ_HW_CONFIG_PBINIT PPC_BIT(12) 341 #define XPEC_NEST_PBCQ_HW_CONFIG_CH_STR PPC_BIT(33) 342 #define XPEC_NEST_CAPP_CNTL 0x7 343 344 /* Nest base per-stack registers */ 345 #define XPEC_NEST_STK_PCI_NFIR 0x0 346 #define XPEC_NEST_STK_PCI_NFIR_CLR 0x1 347 #define XPEC_NEST_STK_PCI_NFIR_SET 0x2 348 #define XPEC_NEST_STK_PCI_NFIR_MSK 0x3 349 #define XPEC_NEST_STK_PCI_NFIR_MSK_CLR 0x4 350 #define XPEC_NEST_STK_PCI_NFIR_MSK_SET 0x5 351 #define XPEC_NEST_STK_PCI_NFIR_ACTION0 0x6 352 #define XPEC_NEST_STK_PCI_NFIR_ACTION1 0x7 353 #define XPEC_NEST_STK_PCI_NFIR_WOF 0x8 354 #define XPEC_NEST_STK_ERR_RPT0 0xa 355 #define XPEC_NEST_STK_ERR_RPT1 0xb 356 #define XPEC_NEST_STK_PBCQ_STAT 0xc 357 #define XPEC_NEST_STK_PBCQ_MODE 0xd 358 #define XPEC_NEST_STK_PBCQ_MODE_P2P PPC_BIT(0) 359 #define XPEC_NEST_STK_MMIO_BAR0 0xe 360 #define XPEC_NEST_STK_MMIO_BAR0_MASK 0xf 361 #define XPEC_NEST_STK_MMIO_BAR1 0x10 362 #define XPEC_NEST_STK_MMIO_BAR1_MASK 0x11 363 #define XPEC_NEST_STK_PHB_REG_BAR 0x12 364 #define XPEC_NEST_STK_IRQ_BAR 0x13 365 #define XPEC_NEST_STK_BAR_EN 0x14 366 #define XPEC_NEST_STK_BAR_EN_MMIO0 PPC_BIT(0) 367 #define XPEC_NEST_STK_BAR_EN_MMIO1 PPC_BIT(1) 368 #define XPEC_NEST_STK_BAR_EN_PHB PPC_BIT(2) 369 #define XPEC_NEST_STK_BAR_EN_INT PPC_BIT(3) 370 #define XPEC_NEST_STK_DATA_FREZ_TYPE 0x15 371 #define XPEC_NEST_STK_TUNNEL_BAR 0x16 372 373 /* PCI base registers */ 374 #define XPEC_PCI_PBAIB_HW_CONFIG 0x0 375 #define XPEC_PCI_CAPP_SEC_BAR 0x1 376 377 /* PCI base per-stack registers */ 378 #define XPEC_PCI_STK_PCI_FIR 0x0 379 #define XPEC_PCI_STK_PCI_FIR_CLR 0x1 380 #define XPEC_PCI_STK_PCI_FIR_SET 0x2 381 #define XPEC_PCI_STK_PCI_FIR_MSK 0x3 382 #define XPEC_PCI_STK_PCI_FIR_MSK_CLR 0x4 383 #define XPEC_PCI_STK_PCI_FIR_MSK_SET 0x5 384 #define XPEC_PCI_STK_PCI_FIR_ACTION0 0x6 385 #define XPEC_PCI_STK_PCI_FIR_ACTION1 0x7 386 #define XPEC_PCI_STK_PCI_FIR_WOF 0x8 387 #define XPEC_PCI_STK_ETU_RESET 0xa 388 #define XPEC_PCI_STK_PBAIB_ERR_REPORT 0xb 389 390 /* ETU XSCOM registers */ 391 #define XETU_HV_IND_ADDRESS 0x0 392 #define XETU_HV_IND_ADDR_VALID PPC_BIT(0) 393 #define XETU_HV_IND_ADDR_4B PPC_BIT(1) 394 #define XETU_HV_IND_ADDR_AUTOINC PPC_BIT(2) 395 #define XETU_HV_IND_DATA 0x1 396 397 /* 398 * IODA3 on-chip tables 399 */ 400 401 #define IODA3_TBL_LIST 1 402 #define IODA3_TBL_MIST 2 403 #define IODA3_TBL_RCAM 5 404 #define IODA3_TBL_MRT 6 405 #define IODA3_TBL_PESTA 7 406 #define IODA3_TBL_PESTB 8 407 #define IODA3_TBL_TVT 9 408 #define IODA3_TBL_TCAM 10 409 #define IODA3_TBL_TDR 11 410 #define IODA3_TBL_MBT 16 411 #define IODA3_TBL_MDT 17 412 #define IODA3_TBL_PEEV 20 413 414 /* LIST */ 415 #define IODA3_LIST_P PPC_BIT(6) 416 #define IODA3_LIST_Q PPC_BIT(7) 417 #define IODA3_LIST_STATE PPC_BIT(14) 418 419 /* MIST */ 420 #define IODA3_MIST_P3 PPC_BIT(48 + 0) 421 #define IODA3_MIST_Q3 PPC_BIT(48 + 1) 422 #define IODA3_MIST_PE3 PPC_BITMASK(48 + 4, 48 + 15) 423 424 /* TVT */ 425 #define IODA3_TVT_TABLE_ADDR PPC_BITMASK(0,47) 426 #define IODA3_TVT_NUM_LEVELS PPC_BITMASK(48,50) 427 #define IODA3_TVE_1_LEVEL 0 428 #define IODA3_TVE_2_LEVELS 1 429 #define IODA3_TVE_3_LEVELS 2 430 #define IODA3_TVE_4_LEVELS 3 431 #define IODA3_TVE_5_LEVELS 4 432 #define IODA3_TVT_TCE_TABLE_SIZE PPC_BITMASK(51,55) 433 #define IODA3_TVT_NON_TRANSLATE_50 PPC_BIT(56) 434 #define IODA3_TVT_IO_PSIZE PPC_BITMASK(59,63) 435 436 /* PESTA */ 437 #define IODA3_PESTA_MMIO_FROZEN PPC_BIT(0) 438 #define IODA3_PESTA_TRANS_TYPE PPC_BITMASK(5,7) 439 #define IODA3_PESTA_TRANS_TYPE_MMIOLOAD 0x4 440 #define IODA3_PESTA_CA_CMPLT_TMT PPC_BIT(8) 441 #define IODA3_PESTA_UR PPC_BIT(9) 442 443 /* PESTB */ 444 #define IODA3_PESTB_DMA_STOPPED PPC_BIT(0) 445 446 /* MDT */ 447 /* FIXME: check this field with Eric and add a B, C and D */ 448 #define IODA3_MDT_PE_A PPC_BITMASK(0,15) 449 #define IODA3_MDT_PE_B PPC_BITMASK(16,31) 450 #define IODA3_MDT_PE_C PPC_BITMASK(32,47) 451 #define IODA3_MDT_PE_D PPC_BITMASK(48,63) 452 453 /* MBT */ 454 #define IODA3_MBT0_ENABLE PPC_BIT(0) 455 #define IODA3_MBT0_TYPE PPC_BIT(1) 456 #define IODA3_MBT0_TYPE_M32 IODA3_MBT0_TYPE 457 #define IODA3_MBT0_TYPE_M64 0 458 #define IODA3_MBT0_MODE PPC_BITMASK(2,3) 459 #define IODA3_MBT0_MODE_PE_SEG 0 460 #define IODA3_MBT0_MODE_MDT 1 461 #define IODA3_MBT0_MODE_SINGLE_PE 2 462 #define IODA3_MBT0_SEG_DIV PPC_BITMASK(4,5) 463 #define IODA3_MBT0_SEG_DIV_MAX 0 464 #define IODA3_MBT0_SEG_DIV_128 1 465 #define IODA3_MBT0_SEG_DIV_64 2 466 #define IODA3_MBT0_SEG_DIV_8 3 467 #define IODA3_MBT0_MDT_COLUMN PPC_BITMASK(4,5) 468 #define IODA3_MBT0_BASE_ADDR PPC_BITMASK(8,51) 469 470 #define IODA3_MBT1_ENABLE PPC_BIT(0) 471 #define IODA3_MBT1_MASK PPC_BITMASK(8,51) 472 #define IODA3_MBT1_SEG_BASE PPC_BITMASK(55,63) 473 #define IODA3_MBT1_SINGLE_PE_NUM PPC_BITMASK(55,63) 474 475 /* 476 * IODA2 in-memory tables 477 */ 478 479 /* PEST 480 * 481 * 2x8 bytes entries, PEST0 and PEST1 482 */ 483 484 #define IODA3_PEST0_MMIO_CAUSE PPC_BIT(2) 485 #define IODA3_PEST0_CFG_READ PPC_BIT(3) 486 #define IODA3_PEST0_CFG_WRITE PPC_BIT(4) 487 #define IODA3_PEST0_TTYPE PPC_BITMASK(5,7) 488 #define PEST_TTYPE_DMA_WRITE 0 489 #define PEST_TTYPE_MSI 1 490 #define PEST_TTYPE_DMA_READ 2 491 #define PEST_TTYPE_DMA_READ_RESP 3 492 #define PEST_TTYPE_MMIO_LOAD 4 493 #define PEST_TTYPE_MMIO_STORE 5 494 #define PEST_TTYPE_OTHER 7 495 #define IODA3_PEST0_CA_RETURN PPC_BIT(8) 496 #define IODA3_PEST0_UR_RETURN PPC_BIT(9) 497 #define IODA3_PEST0_PCIE_NONFATAL PPC_BIT(10) 498 #define IODA3_PEST0_PCIE_FATAL PPC_BIT(11) 499 #define IODA3_PEST0_PARITY_UE PPC_BIT(13) 500 #define IODA3_PEST0_PCIE_CORRECTABLE PPC_BIT(14) 501 #define IODA3_PEST0_PCIE_INTERRUPT PPC_BIT(15) 502 #define IODA3_PEST0_MMIO_XLATE PPC_BIT(16) 503 #define IODA3_PEST0_IODA3_ERROR PPC_BIT(16) /* Same bit as MMIO xlate */ 504 #define IODA3_PEST0_TCE_PAGE_FAULT PPC_BIT(18) 505 #define IODA3_PEST0_TCE_ACCESS_FAULT PPC_BIT(19) 506 #define IODA3_PEST0_DMA_RESP_TIMEOUT PPC_BIT(20) 507 #define IODA3_PEST0_AIB_SIZE_INVALID PPC_BIT(21) 508 #define IODA3_PEST0_LEM_BIT PPC_BITMASK(26,31) 509 #define IODA3_PEST0_RID PPC_BITMASK(32,47) 510 #define IODA3_PEST0_MSI_DATA PPC_BITMASK(48,63) 511 512 #define IODA3_PEST1_FAIL_ADDR PPC_BITMASK(3,63) 513 514 515 #endif /* __PHB4_REGS_H */ 516