1 /*
2 * QEMU ARM CPU
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "target/arm/idau.h"
23 #include "qemu/error-report.h"
24 #include "qapi/error.h"
25 #include "cpu.h"
26 #include "internals.h"
27 #include "qemu-common.h"
28 #include "exec/exec-all.h"
29 #include "hw/qdev-properties.h"
30 #if !defined(CONFIG_USER_ONLY)
31 #include "hw/loader.h"
32 #endif
33 #include "hw/arm/arm.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/hw_accel.h"
36 #include "kvm_arm.h"
37 #include "disas/capstone.h"
38 #include "fpu/softfloat.h"
39
arm_cpu_set_pc(CPUState * cs,vaddr value)40 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
41 {
42 ARMCPU *cpu = ARM_CPU(cs);
43
44 cpu->env.regs[15] = value;
45 }
46
arm_cpu_has_work(CPUState * cs)47 static bool arm_cpu_has_work(CPUState *cs)
48 {
49 ARMCPU *cpu = ARM_CPU(cs);
50
51 return (cpu->power_state != PSCI_OFF)
52 && cs->interrupt_request &
53 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
54 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
55 | CPU_INTERRUPT_EXITTB);
56 }
57
arm_register_pre_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)58 void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
59 void *opaque)
60 {
61 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
62
63 entry->hook = hook;
64 entry->opaque = opaque;
65
66 QLIST_INSERT_HEAD(&cpu->pre_el_change_hooks, entry, node);
67 }
68
arm_register_el_change_hook(ARMCPU * cpu,ARMELChangeHookFn * hook,void * opaque)69 void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
70 void *opaque)
71 {
72 ARMELChangeHook *entry = g_new0(ARMELChangeHook, 1);
73
74 entry->hook = hook;
75 entry->opaque = opaque;
76
77 QLIST_INSERT_HEAD(&cpu->el_change_hooks, entry, node);
78 }
79
cp_reg_reset(gpointer key,gpointer value,gpointer opaque)80 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
81 {
82 /* Reset a single ARMCPRegInfo register */
83 ARMCPRegInfo *ri = value;
84 ARMCPU *cpu = opaque;
85
86 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
87 return;
88 }
89
90 if (ri->resetfn) {
91 ri->resetfn(&cpu->env, ri);
92 return;
93 }
94
95 /* A zero offset is never possible as it would be regs[0]
96 * so we use it to indicate that reset is being handled elsewhere.
97 * This is basically only used for fields in non-core coprocessors
98 * (like the pxa2xx ones).
99 */
100 if (!ri->fieldoffset) {
101 return;
102 }
103
104 if (cpreg_field_is_64bit(ri)) {
105 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
106 } else {
107 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
108 }
109 }
110
cp_reg_check_reset(gpointer key,gpointer value,gpointer opaque)111 static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
112 {
113 /* Purely an assertion check: we've already done reset once,
114 * so now check that running the reset for the cpreg doesn't
115 * change its value. This traps bugs where two different cpregs
116 * both try to reset the same state field but to different values.
117 */
118 ARMCPRegInfo *ri = value;
119 ARMCPU *cpu = opaque;
120 uint64_t oldvalue, newvalue;
121
122 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
123 return;
124 }
125
126 oldvalue = read_raw_cp_reg(&cpu->env, ri);
127 cp_reg_reset(key, value, opaque);
128 newvalue = read_raw_cp_reg(&cpu->env, ri);
129 assert(oldvalue == newvalue);
130 }
131
132 /* CPUClass::reset() */
arm_cpu_reset(CPUState * s)133 static void arm_cpu_reset(CPUState *s)
134 {
135 ARMCPU *cpu = ARM_CPU(s);
136 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
137 CPUARMState *env = &cpu->env;
138
139 acc->parent_reset(s);
140
141 memset(env, 0, offsetof(CPUARMState, end_reset_fields));
142
143 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
144 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
145
146 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
147 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
148 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
149 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
150
151 cpu->power_state = cpu->start_powered_off ? PSCI_OFF : PSCI_ON;
152 s->halted = cpu->start_powered_off;
153
154 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
155 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
156 }
157
158 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
159 /* 64 bit CPUs always start in 64 bit mode */
160 env->aarch64 = 1;
161 #if defined(CONFIG_USER_ONLY)
162 env->pstate = PSTATE_MODE_EL0t;
163 /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
164 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
165 /* and to the FP/Neon instructions */
166 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
167 /* and to the SVE instructions */
168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 16, 2, 3);
169 env->cp15.cptr_el[3] |= CPTR_EZ;
170 /* with maximum vector length */
171 env->vfp.zcr_el[1] = cpu->sve_max_vq - 1;
172 env->vfp.zcr_el[2] = env->vfp.zcr_el[1];
173 env->vfp.zcr_el[3] = env->vfp.zcr_el[1];
174 #else
175 /* Reset into the highest available EL */
176 if (arm_feature(env, ARM_FEATURE_EL3)) {
177 env->pstate = PSTATE_MODE_EL3h;
178 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
179 env->pstate = PSTATE_MODE_EL2h;
180 } else {
181 env->pstate = PSTATE_MODE_EL1h;
182 }
183 env->pc = cpu->rvbar;
184 #endif
185 } else {
186 #if defined(CONFIG_USER_ONLY)
187 /* Userspace expects access to cp10 and cp11 for FP/Neon */
188 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
189 #endif
190 }
191
192 #if defined(CONFIG_USER_ONLY)
193 env->uncached_cpsr = ARM_CPU_MODE_USR;
194 /* For user mode we must enable access to coprocessors */
195 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
196 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
197 env->cp15.c15_cpar = 3;
198 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
199 env->cp15.c15_cpar = 1;
200 }
201 #else
202
203 /*
204 * If the highest available EL is EL2, AArch32 will start in Hyp
205 * mode; otherwise it starts in SVC. Note that if we start in
206 * AArch64 then these values in the uncached_cpsr will be ignored.
207 */
208 if (arm_feature(env, ARM_FEATURE_EL2) &&
209 !arm_feature(env, ARM_FEATURE_EL3)) {
210 env->uncached_cpsr = ARM_CPU_MODE_HYP;
211 } else {
212 env->uncached_cpsr = ARM_CPU_MODE_SVC;
213 }
214 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
215
216 if (arm_feature(env, ARM_FEATURE_M)) {
217 uint32_t initial_msp; /* Loaded from 0x0 */
218 uint32_t initial_pc; /* Loaded from 0x4 */
219 uint8_t *rom;
220 uint32_t vecbase;
221
222 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
223 env->v7m.secure = true;
224 } else {
225 /* This bit resets to 0 if security is supported, but 1 if
226 * it is not. The bit is not present in v7M, but we set it
227 * here so we can avoid having to make checks on it conditional
228 * on ARM_FEATURE_V8 (we don't let the guest see the bit).
229 */
230 env->v7m.aircr = R_V7M_AIRCR_BFHFNMINS_MASK;
231 }
232
233 /* In v7M the reset value of this bit is IMPDEF, but ARM recommends
234 * that it resets to 1, so QEMU always does that rather than making
235 * it dependent on CPU model. In v8M it is RES1.
236 */
237 env->v7m.ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
238 env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
239 if (arm_feature(env, ARM_FEATURE_V8)) {
240 /* in v8M the NONBASETHRDENA bit [0] is RES1 */
241 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_NONBASETHRDENA_MASK;
242 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_NONBASETHRDENA_MASK;
243 }
244 if (!arm_feature(env, ARM_FEATURE_M_MAIN)) {
245 env->v7m.ccr[M_REG_NS] |= R_V7M_CCR_UNALIGN_TRP_MASK;
246 env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK;
247 }
248
249 /* Unlike A/R profile, M profile defines the reset LR value */
250 env->regs[14] = 0xffffffff;
251
252 env->v7m.vecbase[M_REG_S] = cpu->init_svtor & 0xffffff80;
253
254 /* Load the initial SP and PC from offset 0 and 4 in the vector table */
255 vecbase = env->v7m.vecbase[env->v7m.secure];
256 rom = rom_ptr(vecbase, 8);
257 if (rom) {
258 /* Address zero is covered by ROM which hasn't yet been
259 * copied into physical memory.
260 */
261 initial_msp = ldl_p(rom);
262 initial_pc = ldl_p(rom + 4);
263 } else {
264 /* Address zero not covered by a ROM blob, or the ROM blob
265 * is in non-modifiable memory and this is a second reset after
266 * it got copied into memory. In the latter case, rom_ptr
267 * will return a NULL pointer and we should use ldl_phys instead.
268 */
269 initial_msp = ldl_phys(s->as, vecbase);
270 initial_pc = ldl_phys(s->as, vecbase + 4);
271 }
272
273 env->regs[13] = initial_msp & 0xFFFFFFFC;
274 env->regs[15] = initial_pc & ~1;
275 env->thumb = initial_pc & 1;
276 }
277
278 /* AArch32 has a hard highvec setting of 0xFFFF0000. If we are currently
279 * executing as AArch32 then check if highvecs are enabled and
280 * adjust the PC accordingly.
281 */
282 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
283 env->regs[15] = 0xFFFF0000;
284 }
285
286 /* M profile requires that reset clears the exclusive monitor;
287 * A profile does not, but clearing it makes more sense than having it
288 * set with an exclusive access on address zero.
289 */
290 arm_clear_exclusive(env);
291
292 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
293 #endif
294
295 if (arm_feature(env, ARM_FEATURE_PMSA)) {
296 if (cpu->pmsav7_dregion > 0) {
297 if (arm_feature(env, ARM_FEATURE_V8)) {
298 memset(env->pmsav8.rbar[M_REG_NS], 0,
299 sizeof(*env->pmsav8.rbar[M_REG_NS])
300 * cpu->pmsav7_dregion);
301 memset(env->pmsav8.rlar[M_REG_NS], 0,
302 sizeof(*env->pmsav8.rlar[M_REG_NS])
303 * cpu->pmsav7_dregion);
304 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
305 memset(env->pmsav8.rbar[M_REG_S], 0,
306 sizeof(*env->pmsav8.rbar[M_REG_S])
307 * cpu->pmsav7_dregion);
308 memset(env->pmsav8.rlar[M_REG_S], 0,
309 sizeof(*env->pmsav8.rlar[M_REG_S])
310 * cpu->pmsav7_dregion);
311 }
312 } else if (arm_feature(env, ARM_FEATURE_V7)) {
313 memset(env->pmsav7.drbar, 0,
314 sizeof(*env->pmsav7.drbar) * cpu->pmsav7_dregion);
315 memset(env->pmsav7.drsr, 0,
316 sizeof(*env->pmsav7.drsr) * cpu->pmsav7_dregion);
317 memset(env->pmsav7.dracr, 0,
318 sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);
319 }
320 }
321 env->pmsav7.rnr[M_REG_NS] = 0;
322 env->pmsav7.rnr[M_REG_S] = 0;
323 env->pmsav8.mair0[M_REG_NS] = 0;
324 env->pmsav8.mair0[M_REG_S] = 0;
325 env->pmsav8.mair1[M_REG_NS] = 0;
326 env->pmsav8.mair1[M_REG_S] = 0;
327 }
328
329 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
330 if (cpu->sau_sregion > 0) {
331 memset(env->sau.rbar, 0, sizeof(*env->sau.rbar) * cpu->sau_sregion);
332 memset(env->sau.rlar, 0, sizeof(*env->sau.rlar) * cpu->sau_sregion);
333 }
334 env->sau.rnr = 0;
335 /* SAU_CTRL reset value is IMPDEF; we choose 0, which is what
336 * the Cortex-M33 does.
337 */
338 env->sau.ctrl = 0;
339 }
340
341 set_flush_to_zero(1, &env->vfp.standard_fp_status);
342 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
343 set_default_nan_mode(1, &env->vfp.standard_fp_status);
344 set_float_detect_tininess(float_tininess_before_rounding,
345 &env->vfp.fp_status);
346 set_float_detect_tininess(float_tininess_before_rounding,
347 &env->vfp.standard_fp_status);
348 set_float_detect_tininess(float_tininess_before_rounding,
349 &env->vfp.fp_status_f16);
350 #ifndef CONFIG_USER_ONLY
351 if (kvm_enabled()) {
352 kvm_arm_reset_vcpu(cpu);
353 }
354 #endif
355
356 hw_breakpoint_update_all(cpu);
357 hw_watchpoint_update_all(cpu);
358 }
359
arm_cpu_exec_interrupt(CPUState * cs,int interrupt_request)360 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
361 {
362 CPUClass *cc = CPU_GET_CLASS(cs);
363 CPUARMState *env = cs->env_ptr;
364 uint32_t cur_el = arm_current_el(env);
365 bool secure = arm_is_secure(env);
366 uint32_t target_el;
367 uint32_t excp_idx;
368 bool ret = false;
369
370 if (interrupt_request & CPU_INTERRUPT_FIQ) {
371 excp_idx = EXCP_FIQ;
372 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
373 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
374 cs->exception_index = excp_idx;
375 env->exception.target_el = target_el;
376 cc->do_interrupt(cs);
377 ret = true;
378 }
379 }
380 if (interrupt_request & CPU_INTERRUPT_HARD) {
381 excp_idx = EXCP_IRQ;
382 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
383 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
384 cs->exception_index = excp_idx;
385 env->exception.target_el = target_el;
386 cc->do_interrupt(cs);
387 ret = true;
388 }
389 }
390 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
391 excp_idx = EXCP_VIRQ;
392 target_el = 1;
393 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
394 cs->exception_index = excp_idx;
395 env->exception.target_el = target_el;
396 cc->do_interrupt(cs);
397 ret = true;
398 }
399 }
400 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
401 excp_idx = EXCP_VFIQ;
402 target_el = 1;
403 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
404 cs->exception_index = excp_idx;
405 env->exception.target_el = target_el;
406 cc->do_interrupt(cs);
407 ret = true;
408 }
409 }
410
411 return ret;
412 }
413
414 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
arm_v7m_cpu_exec_interrupt(CPUState * cs,int interrupt_request)415 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
416 {
417 CPUClass *cc = CPU_GET_CLASS(cs);
418 ARMCPU *cpu = ARM_CPU(cs);
419 CPUARMState *env = &cpu->env;
420 bool ret = false;
421
422 /* ARMv7-M interrupt masking works differently than -A or -R.
423 * There is no FIQ/IRQ distinction. Instead of I and F bits
424 * masking FIQ and IRQ interrupts, an exception is taken only
425 * if it is higher priority than the current execution priority
426 * (which depends on state like BASEPRI, FAULTMASK and the
427 * currently active exception).
428 */
429 if (interrupt_request & CPU_INTERRUPT_HARD
430 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
431 cs->exception_index = EXCP_IRQ;
432 cc->do_interrupt(cs);
433 ret = true;
434 }
435 return ret;
436 }
437 #endif
438
439 #ifndef CONFIG_USER_ONLY
arm_cpu_set_irq(void * opaque,int irq,int level)440 static void arm_cpu_set_irq(void *opaque, int irq, int level)
441 {
442 ARMCPU *cpu = opaque;
443 CPUARMState *env = &cpu->env;
444 CPUState *cs = CPU(cpu);
445 static const int mask[] = {
446 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
447 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
448 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
449 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
450 };
451
452 switch (irq) {
453 case ARM_CPU_VIRQ:
454 case ARM_CPU_VFIQ:
455 assert(arm_feature(env, ARM_FEATURE_EL2));
456 /* fall through */
457 case ARM_CPU_IRQ:
458 case ARM_CPU_FIQ:
459 if (level) {
460 cpu_interrupt(cs, mask[irq]);
461 } else {
462 cpu_reset_interrupt(cs, mask[irq]);
463 }
464 break;
465 default:
466 g_assert_not_reached();
467 }
468 }
469
arm_cpu_kvm_set_irq(void * opaque,int irq,int level)470 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
471 {
472 #ifdef CONFIG_KVM
473 ARMCPU *cpu = opaque;
474 CPUState *cs = CPU(cpu);
475 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
476
477 switch (irq) {
478 case ARM_CPU_IRQ:
479 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
480 break;
481 case ARM_CPU_FIQ:
482 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
483 break;
484 default:
485 g_assert_not_reached();
486 }
487 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
488 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
489 #endif
490 }
491
arm_cpu_virtio_is_big_endian(CPUState * cs)492 static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
493 {
494 ARMCPU *cpu = ARM_CPU(cs);
495 CPUARMState *env = &cpu->env;
496
497 cpu_synchronize_state(cs);
498 return arm_cpu_data_is_big_endian(env);
499 }
500
501 #endif
502
set_feature(CPUARMState * env,int feature)503 static inline void set_feature(CPUARMState *env, int feature)
504 {
505 env->features |= 1ULL << feature;
506 }
507
unset_feature(CPUARMState * env,int feature)508 static inline void unset_feature(CPUARMState *env, int feature)
509 {
510 env->features &= ~(1ULL << feature);
511 }
512
513 static int
print_insn_thumb1(bfd_vma pc,disassemble_info * info)514 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
515 {
516 return print_insn_arm(pc | 1, info);
517 }
518
arm_disas_set_info(CPUState * cpu,disassemble_info * info)519 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
520 {
521 ARMCPU *ac = ARM_CPU(cpu);
522 CPUARMState *env = &ac->env;
523 bool sctlr_b;
524
525 if (is_a64(env)) {
526 /* We might not be compiled with the A64 disassembler
527 * because it needs a C++ compiler. Leave print_insn
528 * unset in this case to use the caller default behaviour.
529 */
530 #if defined(CONFIG_ARM_A64_DIS)
531 info->print_insn = print_insn_arm_a64;
532 #endif
533 info->cap_arch = CS_ARCH_ARM64;
534 info->cap_insn_unit = 4;
535 info->cap_insn_split = 4;
536 } else {
537 int cap_mode;
538 if (env->thumb) {
539 info->print_insn = print_insn_thumb1;
540 info->cap_insn_unit = 2;
541 info->cap_insn_split = 4;
542 cap_mode = CS_MODE_THUMB;
543 } else {
544 info->print_insn = print_insn_arm;
545 info->cap_insn_unit = 4;
546 info->cap_insn_split = 4;
547 cap_mode = CS_MODE_ARM;
548 }
549 if (arm_feature(env, ARM_FEATURE_V8)) {
550 cap_mode |= CS_MODE_V8;
551 }
552 if (arm_feature(env, ARM_FEATURE_M)) {
553 cap_mode |= CS_MODE_MCLASS;
554 }
555 info->cap_arch = CS_ARCH_ARM;
556 info->cap_mode = cap_mode;
557 }
558
559 sctlr_b = arm_sctlr_b(env);
560 if (bswap_code(sctlr_b)) {
561 #ifdef TARGET_WORDS_BIGENDIAN
562 info->endian = BFD_ENDIAN_LITTLE;
563 #else
564 info->endian = BFD_ENDIAN_BIG;
565 #endif
566 }
567 info->flags &= ~INSN_ARM_BE32;
568 #ifndef CONFIG_USER_ONLY
569 if (sctlr_b) {
570 info->flags |= INSN_ARM_BE32;
571 }
572 #endif
573 }
574
arm_cpu_mp_affinity(int idx,uint8_t clustersz)575 uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz)
576 {
577 uint32_t Aff1 = idx / clustersz;
578 uint32_t Aff0 = idx % clustersz;
579 return (Aff1 << ARM_AFF1_SHIFT) | Aff0;
580 }
581
arm_cpu_initfn(Object * obj)582 static void arm_cpu_initfn(Object *obj)
583 {
584 CPUState *cs = CPU(obj);
585 ARMCPU *cpu = ARM_CPU(obj);
586
587 cs->env_ptr = &cpu->env;
588 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
589 g_free, g_free);
590
591 QLIST_INIT(&cpu->pre_el_change_hooks);
592 QLIST_INIT(&cpu->el_change_hooks);
593
594 #ifndef CONFIG_USER_ONLY
595 /* Our inbound IRQ and FIQ lines */
596 if (kvm_enabled()) {
597 /* VIRQ and VFIQ are unused with KVM but we add them to maintain
598 * the same interface as non-KVM CPUs.
599 */
600 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
601 } else {
602 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
603 }
604
605 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
606 arm_gt_ptimer_cb, cpu);
607 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
608 arm_gt_vtimer_cb, cpu);
609 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
610 arm_gt_htimer_cb, cpu);
611 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
612 arm_gt_stimer_cb, cpu);
613 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
614 ARRAY_SIZE(cpu->gt_timer_outputs));
615
616 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->gicv3_maintenance_interrupt,
617 "gicv3-maintenance-interrupt", 1);
618 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->pmu_interrupt,
619 "pmu-interrupt", 1);
620 #endif
621
622 /* DTB consumers generally don't in fact care what the 'compatible'
623 * string is, so always provide some string and trust that a hypothetical
624 * picky DTB consumer will also provide a helpful error message.
625 */
626 cpu->dtb_compatible = "qemu,unknown";
627 cpu->psci_version = 1; /* By default assume PSCI v0.1 */
628 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
629
630 if (tcg_enabled()) {
631 cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
632 }
633 }
634
635 static Property arm_cpu_reset_cbar_property =
636 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
637
638 static Property arm_cpu_reset_hivecs_property =
639 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
640
641 static Property arm_cpu_rvbar_property =
642 DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
643
644 static Property arm_cpu_has_el2_property =
645 DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
646
647 static Property arm_cpu_has_el3_property =
648 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
649
650 static Property arm_cpu_cfgend_property =
651 DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
652
653 /* use property name "pmu" to match other archs and virt tools */
654 static Property arm_cpu_has_pmu_property =
655 DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
656
657 static Property arm_cpu_has_mpu_property =
658 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
659
660 /* This is like DEFINE_PROP_UINT32 but it doesn't set the default value,
661 * because the CPU initfn will have already set cpu->pmsav7_dregion to
662 * the right value for that particular CPU type, and we don't want
663 * to override that with an incorrect constant value.
664 */
665 static Property arm_cpu_pmsav7_dregion_property =
666 DEFINE_PROP_UNSIGNED_NODEFAULT("pmsav7-dregion", ARMCPU,
667 pmsav7_dregion,
668 qdev_prop_uint32, uint32_t);
669
670 /* M profile: initial value of the Secure VTOR */
671 static Property arm_cpu_initsvtor_property =
672 DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
673
arm_cpu_post_init(Object * obj)674 static void arm_cpu_post_init(Object *obj)
675 {
676 ARMCPU *cpu = ARM_CPU(obj);
677
678 /* M profile implies PMSA. We have to do this here rather than
679 * in realize with the other feature-implication checks because
680 * we look at the PMSA bit to see if we should add some properties.
681 */
682 if (arm_feature(&cpu->env, ARM_FEATURE_M)) {
683 set_feature(&cpu->env, ARM_FEATURE_PMSA);
684 }
685
686 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
687 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
688 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
689 &error_abort);
690 }
691
692 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
693 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
694 &error_abort);
695 }
696
697 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
698 qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
699 &error_abort);
700 }
701
702 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
703 /* Add the has_el3 state CPU property only if EL3 is allowed. This will
704 * prevent "has_el3" from existing on CPUs which cannot support EL3.
705 */
706 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
707 &error_abort);
708
709 #ifndef CONFIG_USER_ONLY
710 object_property_add_link(obj, "secure-memory",
711 TYPE_MEMORY_REGION,
712 (Object **)&cpu->secure_memory,
713 qdev_prop_allow_set_link_before_realize,
714 OBJ_PROP_LINK_STRONG,
715 &error_abort);
716 #endif
717 }
718
719 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) {
720 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property,
721 &error_abort);
722 }
723
724 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
725 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
726 &error_abort);
727 }
728
729 if (arm_feature(&cpu->env, ARM_FEATURE_PMSA)) {
730 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
731 &error_abort);
732 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
733 qdev_property_add_static(DEVICE(obj),
734 &arm_cpu_pmsav7_dregion_property,
735 &error_abort);
736 }
737 }
738
739 if (arm_feature(&cpu->env, ARM_FEATURE_M_SECURITY)) {
740 object_property_add_link(obj, "idau", TYPE_IDAU_INTERFACE, &cpu->idau,
741 qdev_prop_allow_set_link_before_realize,
742 OBJ_PROP_LINK_STRONG,
743 &error_abort);
744 qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
745 &error_abort);
746 }
747
748 qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
749 &error_abort);
750 }
751
arm_cpu_finalizefn(Object * obj)752 static void arm_cpu_finalizefn(Object *obj)
753 {
754 ARMCPU *cpu = ARM_CPU(obj);
755 ARMELChangeHook *hook, *next;
756
757 g_hash_table_destroy(cpu->cp_regs);
758
759 QLIST_FOREACH_SAFE(hook, &cpu->pre_el_change_hooks, node, next) {
760 QLIST_REMOVE(hook, node);
761 g_free(hook);
762 }
763 QLIST_FOREACH_SAFE(hook, &cpu->el_change_hooks, node, next) {
764 QLIST_REMOVE(hook, node);
765 g_free(hook);
766 }
767 }
768
arm_cpu_realizefn(DeviceState * dev,Error ** errp)769 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
770 {
771 CPUState *cs = CPU(dev);
772 ARMCPU *cpu = ARM_CPU(dev);
773 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
774 CPUARMState *env = &cpu->env;
775 int pagebits;
776 Error *local_err = NULL;
777
778 /* If we needed to query the host kernel for the CPU features
779 * then it's possible that might have failed in the initfn, but
780 * this is the first point where we can report it.
781 */
782 if (cpu->host_cpu_probe_failed) {
783 if (!kvm_enabled()) {
784 error_setg(errp, "The 'host' CPU type can only be used with KVM");
785 } else {
786 error_setg(errp, "Failed to retrieve host CPU features");
787 }
788 return;
789 }
790
791 #ifndef CONFIG_USER_ONLY
792 /* The NVIC and M-profile CPU are two halves of a single piece of
793 * hardware; trying to use one without the other is a command line
794 * error and will result in segfaults if not caught here.
795 */
796 if (arm_feature(env, ARM_FEATURE_M)) {
797 if (!env->nvic) {
798 error_setg(errp, "This board cannot be used with Cortex-M CPUs");
799 return;
800 }
801 } else {
802 if (env->nvic) {
803 error_setg(errp, "This board can only be used with Cortex-M CPUs");
804 return;
805 }
806 }
807 #endif
808
809 cpu_exec_realizefn(cs, &local_err);
810 if (local_err != NULL) {
811 error_propagate(errp, local_err);
812 return;
813 }
814
815 /* Some features automatically imply others: */
816 if (arm_feature(env, ARM_FEATURE_V8)) {
817 set_feature(env, ARM_FEATURE_V7VE);
818 }
819 if (arm_feature(env, ARM_FEATURE_V7VE)) {
820 /* v7 Virtualization Extensions. In real hardware this implies
821 * EL2 and also the presence of the Security Extensions.
822 * For QEMU, for backwards-compatibility we implement some
823 * CPUs or CPU configs which have no actual EL2 or EL3 but do
824 * include the various other features that V7VE implies.
825 * Presence of EL2 itself is ARM_FEATURE_EL2, and of the
826 * Security Extensions is ARM_FEATURE_EL3.
827 */
828 set_feature(env, ARM_FEATURE_ARM_DIV);
829 set_feature(env, ARM_FEATURE_LPAE);
830 set_feature(env, ARM_FEATURE_V7);
831 }
832 if (arm_feature(env, ARM_FEATURE_V7)) {
833 set_feature(env, ARM_FEATURE_VAPA);
834 set_feature(env, ARM_FEATURE_THUMB2);
835 set_feature(env, ARM_FEATURE_MPIDR);
836 if (!arm_feature(env, ARM_FEATURE_M)) {
837 set_feature(env, ARM_FEATURE_V6K);
838 } else {
839 set_feature(env, ARM_FEATURE_V6);
840 }
841
842 /* Always define VBAR for V7 CPUs even if it doesn't exist in
843 * non-EL3 configs. This is needed by some legacy boards.
844 */
845 set_feature(env, ARM_FEATURE_VBAR);
846 }
847 if (arm_feature(env, ARM_FEATURE_V6K)) {
848 set_feature(env, ARM_FEATURE_V6);
849 set_feature(env, ARM_FEATURE_MVFR);
850 }
851 if (arm_feature(env, ARM_FEATURE_V6)) {
852 set_feature(env, ARM_FEATURE_V5);
853 set_feature(env, ARM_FEATURE_JAZELLE);
854 if (!arm_feature(env, ARM_FEATURE_M)) {
855 set_feature(env, ARM_FEATURE_AUXCR);
856 }
857 }
858 if (arm_feature(env, ARM_FEATURE_V5)) {
859 set_feature(env, ARM_FEATURE_V4T);
860 }
861 if (arm_feature(env, ARM_FEATURE_M)) {
862 set_feature(env, ARM_FEATURE_THUMB_DIV);
863 }
864 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
865 set_feature(env, ARM_FEATURE_THUMB_DIV);
866 }
867 if (arm_feature(env, ARM_FEATURE_VFP4)) {
868 set_feature(env, ARM_FEATURE_VFP3);
869 set_feature(env, ARM_FEATURE_VFP_FP16);
870 }
871 if (arm_feature(env, ARM_FEATURE_VFP3)) {
872 set_feature(env, ARM_FEATURE_VFP);
873 }
874 if (arm_feature(env, ARM_FEATURE_LPAE)) {
875 set_feature(env, ARM_FEATURE_V7MP);
876 set_feature(env, ARM_FEATURE_PXN);
877 }
878 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
879 set_feature(env, ARM_FEATURE_CBAR);
880 }
881 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
882 !arm_feature(env, ARM_FEATURE_M)) {
883 set_feature(env, ARM_FEATURE_THUMB_DSP);
884 }
885
886 if (arm_feature(env, ARM_FEATURE_V7) &&
887 !arm_feature(env, ARM_FEATURE_M) &&
888 !arm_feature(env, ARM_FEATURE_PMSA)) {
889 /* v7VMSA drops support for the old ARMv5 tiny pages, so we
890 * can use 4K pages.
891 */
892 pagebits = 12;
893 } else {
894 /* For CPUs which might have tiny 1K pages, or which have an
895 * MPU and might have small region sizes, stick with 1K pages.
896 */
897 pagebits = 10;
898 }
899 if (!set_preferred_target_page_bits(pagebits)) {
900 /* This can only ever happen for hotplugging a CPU, or if
901 * the board code incorrectly creates a CPU which it has
902 * promised via minimum_page_size that it will not.
903 */
904 error_setg(errp, "This CPU requires a smaller page size than the "
905 "system is using");
906 return;
907 }
908
909 /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
910 * We don't support setting cluster ID ([16..23]) (known as Aff2
911 * in later ARM ARM versions), or any of the higher affinity level fields,
912 * so these bits always RAZ.
913 */
914 if (cpu->mp_affinity == ARM64_AFFINITY_INVALID) {
915 cpu->mp_affinity = arm_cpu_mp_affinity(cs->cpu_index,
916 ARM_DEFAULT_CPUS_PER_CLUSTER);
917 }
918
919 if (cpu->reset_hivecs) {
920 cpu->reset_sctlr |= (1 << 13);
921 }
922
923 if (cpu->cfgend) {
924 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
925 cpu->reset_sctlr |= SCTLR_EE;
926 } else {
927 cpu->reset_sctlr |= SCTLR_B;
928 }
929 }
930
931 if (!cpu->has_el3) {
932 /* If the has_el3 CPU property is disabled then we need to disable the
933 * feature.
934 */
935 unset_feature(env, ARM_FEATURE_EL3);
936
937 /* Disable the security extension feature bits in the processor feature
938 * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
939 */
940 cpu->id_pfr1 &= ~0xf0;
941 cpu->id_aa64pfr0 &= ~0xf000;
942 }
943
944 if (!cpu->has_el2) {
945 unset_feature(env, ARM_FEATURE_EL2);
946 }
947
948 if (!cpu->has_pmu) {
949 unset_feature(env, ARM_FEATURE_PMU);
950 cpu->id_aa64dfr0 &= ~0xf00;
951 }
952
953 if (!arm_feature(env, ARM_FEATURE_EL2)) {
954 /* Disable the hypervisor feature bits in the processor feature
955 * registers if we don't have EL2. These are id_pfr1[15:12] and
956 * id_aa64pfr0_el1[11:8].
957 */
958 cpu->id_aa64pfr0 &= ~0xf00;
959 cpu->id_pfr1 &= ~0xf000;
960 }
961
962 /* MPU can be configured out of a PMSA CPU either by setting has-mpu
963 * to false or by setting pmsav7-dregion to 0.
964 */
965 if (!cpu->has_mpu) {
966 cpu->pmsav7_dregion = 0;
967 }
968 if (cpu->pmsav7_dregion == 0) {
969 cpu->has_mpu = false;
970 }
971
972 if (arm_feature(env, ARM_FEATURE_PMSA) &&
973 arm_feature(env, ARM_FEATURE_V7)) {
974 uint32_t nr = cpu->pmsav7_dregion;
975
976 if (nr > 0xff) {
977 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
978 return;
979 }
980
981 if (nr) {
982 if (arm_feature(env, ARM_FEATURE_V8)) {
983 /* PMSAv8 */
984 env->pmsav8.rbar[M_REG_NS] = g_new0(uint32_t, nr);
985 env->pmsav8.rlar[M_REG_NS] = g_new0(uint32_t, nr);
986 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
987 env->pmsav8.rbar[M_REG_S] = g_new0(uint32_t, nr);
988 env->pmsav8.rlar[M_REG_S] = g_new0(uint32_t, nr);
989 }
990 } else {
991 env->pmsav7.drbar = g_new0(uint32_t, nr);
992 env->pmsav7.drsr = g_new0(uint32_t, nr);
993 env->pmsav7.dracr = g_new0(uint32_t, nr);
994 }
995 }
996 }
997
998 if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
999 uint32_t nr = cpu->sau_sregion;
1000
1001 if (nr > 0xff) {
1002 error_setg(errp, "v8M SAU #regions invalid %" PRIu32, nr);
1003 return;
1004 }
1005
1006 if (nr) {
1007 env->sau.rbar = g_new0(uint32_t, nr);
1008 env->sau.rlar = g_new0(uint32_t, nr);
1009 }
1010 }
1011
1012 if (arm_feature(env, ARM_FEATURE_EL3)) {
1013 set_feature(env, ARM_FEATURE_VBAR);
1014 }
1015
1016 register_cp_regs_for_features(cpu);
1017 arm_cpu_register_gdb_regs_for_features(cpu);
1018
1019 init_cpreg_list(cpu);
1020
1021 #ifndef CONFIG_USER_ONLY
1022 if (cpu->has_el3 || arm_feature(env, ARM_FEATURE_M_SECURITY)) {
1023 cs->num_ases = 2;
1024
1025 if (!cpu->secure_memory) {
1026 cpu->secure_memory = cs->memory;
1027 }
1028 cpu_address_space_init(cs, ARMASIdx_S, "cpu-secure-memory",
1029 cpu->secure_memory);
1030 } else {
1031 cs->num_ases = 1;
1032 }
1033 cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
1034
1035 /* No core_count specified, default to smp_cpus. */
1036 if (cpu->core_count == -1) {
1037 cpu->core_count = smp_cpus;
1038 }
1039 #endif
1040
1041 qemu_init_vcpu(cs);
1042 cpu_reset(cs);
1043
1044 acc->parent_realize(dev, errp);
1045 }
1046
arm_cpu_class_by_name(const char * cpu_model)1047 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
1048 {
1049 ObjectClass *oc;
1050 char *typename;
1051 char **cpuname;
1052 const char *cpunamestr;
1053
1054 cpuname = g_strsplit(cpu_model, ",", 1);
1055 cpunamestr = cpuname[0];
1056 #ifdef CONFIG_USER_ONLY
1057 /* For backwards compatibility usermode emulation allows "-cpu any",
1058 * which has the same semantics as "-cpu max".
1059 */
1060 if (!strcmp(cpunamestr, "any")) {
1061 cpunamestr = "max";
1062 }
1063 #endif
1064 typename = g_strdup_printf(ARM_CPU_TYPE_NAME("%s"), cpunamestr);
1065 oc = object_class_by_name(typename);
1066 g_strfreev(cpuname);
1067 g_free(typename);
1068 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
1069 object_class_is_abstract(oc)) {
1070 return NULL;
1071 }
1072 return oc;
1073 }
1074
1075 /* CPU models. These are not needed for the AArch64 linux-user build. */
1076 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1077
arm926_initfn(Object * obj)1078 static void arm926_initfn(Object *obj)
1079 {
1080 ARMCPU *cpu = ARM_CPU(obj);
1081
1082 cpu->dtb_compatible = "arm,arm926";
1083 set_feature(&cpu->env, ARM_FEATURE_V5);
1084 set_feature(&cpu->env, ARM_FEATURE_VFP);
1085 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1086 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1087 set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
1088 cpu->midr = 0x41069265;
1089 cpu->reset_fpsid = 0x41011090;
1090 cpu->ctr = 0x1dd20d2;
1091 cpu->reset_sctlr = 0x00090078;
1092 }
1093
arm946_initfn(Object * obj)1094 static void arm946_initfn(Object *obj)
1095 {
1096 ARMCPU *cpu = ARM_CPU(obj);
1097
1098 cpu->dtb_compatible = "arm,arm946";
1099 set_feature(&cpu->env, ARM_FEATURE_V5);
1100 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1101 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1102 cpu->midr = 0x41059461;
1103 cpu->ctr = 0x0f004006;
1104 cpu->reset_sctlr = 0x00000078;
1105 }
1106
arm1026_initfn(Object * obj)1107 static void arm1026_initfn(Object *obj)
1108 {
1109 ARMCPU *cpu = ARM_CPU(obj);
1110
1111 cpu->dtb_compatible = "arm,arm1026";
1112 set_feature(&cpu->env, ARM_FEATURE_V5);
1113 set_feature(&cpu->env, ARM_FEATURE_VFP);
1114 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
1115 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1116 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
1117 set_feature(&cpu->env, ARM_FEATURE_JAZELLE);
1118 cpu->midr = 0x4106a262;
1119 cpu->reset_fpsid = 0x410110a0;
1120 cpu->ctr = 0x1dd20d2;
1121 cpu->reset_sctlr = 0x00090078;
1122 cpu->reset_auxcr = 1;
1123 {
1124 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
1125 ARMCPRegInfo ifar = {
1126 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
1127 .access = PL1_RW,
1128 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
1129 .resetvalue = 0
1130 };
1131 define_one_arm_cp_reg(cpu, &ifar);
1132 }
1133 }
1134
arm1136_r2_initfn(Object * obj)1135 static void arm1136_r2_initfn(Object *obj)
1136 {
1137 ARMCPU *cpu = ARM_CPU(obj);
1138 /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
1139 * older core than plain "arm1136". In particular this does not
1140 * have the v6K features.
1141 * These ID register values are correct for 1136 but may be wrong
1142 * for 1136_r2 (in particular r0p2 does not actually implement most
1143 * of the ID registers).
1144 */
1145
1146 cpu->dtb_compatible = "arm,arm1136";
1147 set_feature(&cpu->env, ARM_FEATURE_V6);
1148 set_feature(&cpu->env, ARM_FEATURE_VFP);
1149 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1150 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1151 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1152 cpu->midr = 0x4107b362;
1153 cpu->reset_fpsid = 0x410120b4;
1154 cpu->mvfr0 = 0x11111111;
1155 cpu->mvfr1 = 0x00000000;
1156 cpu->ctr = 0x1dd20d2;
1157 cpu->reset_sctlr = 0x00050078;
1158 cpu->id_pfr0 = 0x111;
1159 cpu->id_pfr1 = 0x1;
1160 cpu->id_dfr0 = 0x2;
1161 cpu->id_afr0 = 0x3;
1162 cpu->id_mmfr0 = 0x01130003;
1163 cpu->id_mmfr1 = 0x10030302;
1164 cpu->id_mmfr2 = 0x01222110;
1165 cpu->id_isar0 = 0x00140011;
1166 cpu->id_isar1 = 0x12002111;
1167 cpu->id_isar2 = 0x11231111;
1168 cpu->id_isar3 = 0x01102131;
1169 cpu->id_isar4 = 0x141;
1170 cpu->reset_auxcr = 7;
1171 }
1172
arm1136_initfn(Object * obj)1173 static void arm1136_initfn(Object *obj)
1174 {
1175 ARMCPU *cpu = ARM_CPU(obj);
1176
1177 cpu->dtb_compatible = "arm,arm1136";
1178 set_feature(&cpu->env, ARM_FEATURE_V6K);
1179 set_feature(&cpu->env, ARM_FEATURE_V6);
1180 set_feature(&cpu->env, ARM_FEATURE_VFP);
1181 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1182 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1183 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1184 cpu->midr = 0x4117b363;
1185 cpu->reset_fpsid = 0x410120b4;
1186 cpu->mvfr0 = 0x11111111;
1187 cpu->mvfr1 = 0x00000000;
1188 cpu->ctr = 0x1dd20d2;
1189 cpu->reset_sctlr = 0x00050078;
1190 cpu->id_pfr0 = 0x111;
1191 cpu->id_pfr1 = 0x1;
1192 cpu->id_dfr0 = 0x2;
1193 cpu->id_afr0 = 0x3;
1194 cpu->id_mmfr0 = 0x01130003;
1195 cpu->id_mmfr1 = 0x10030302;
1196 cpu->id_mmfr2 = 0x01222110;
1197 cpu->id_isar0 = 0x00140011;
1198 cpu->id_isar1 = 0x12002111;
1199 cpu->id_isar2 = 0x11231111;
1200 cpu->id_isar3 = 0x01102131;
1201 cpu->id_isar4 = 0x141;
1202 cpu->reset_auxcr = 7;
1203 }
1204
arm1176_initfn(Object * obj)1205 static void arm1176_initfn(Object *obj)
1206 {
1207 ARMCPU *cpu = ARM_CPU(obj);
1208
1209 cpu->dtb_compatible = "arm,arm1176";
1210 set_feature(&cpu->env, ARM_FEATURE_V6K);
1211 set_feature(&cpu->env, ARM_FEATURE_VFP);
1212 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1213 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1214 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1215 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1216 set_feature(&cpu->env, ARM_FEATURE_EL3);
1217 cpu->midr = 0x410fb767;
1218 cpu->reset_fpsid = 0x410120b5;
1219 cpu->mvfr0 = 0x11111111;
1220 cpu->mvfr1 = 0x00000000;
1221 cpu->ctr = 0x1dd20d2;
1222 cpu->reset_sctlr = 0x00050078;
1223 cpu->id_pfr0 = 0x111;
1224 cpu->id_pfr1 = 0x11;
1225 cpu->id_dfr0 = 0x33;
1226 cpu->id_afr0 = 0;
1227 cpu->id_mmfr0 = 0x01130003;
1228 cpu->id_mmfr1 = 0x10030302;
1229 cpu->id_mmfr2 = 0x01222100;
1230 cpu->id_isar0 = 0x0140011;
1231 cpu->id_isar1 = 0x12002111;
1232 cpu->id_isar2 = 0x11231121;
1233 cpu->id_isar3 = 0x01102131;
1234 cpu->id_isar4 = 0x01141;
1235 cpu->reset_auxcr = 7;
1236 }
1237
arm11mpcore_initfn(Object * obj)1238 static void arm11mpcore_initfn(Object *obj)
1239 {
1240 ARMCPU *cpu = ARM_CPU(obj);
1241
1242 cpu->dtb_compatible = "arm,arm11mpcore";
1243 set_feature(&cpu->env, ARM_FEATURE_V6K);
1244 set_feature(&cpu->env, ARM_FEATURE_VFP);
1245 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1246 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1247 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1248 cpu->midr = 0x410fb022;
1249 cpu->reset_fpsid = 0x410120b4;
1250 cpu->mvfr0 = 0x11111111;
1251 cpu->mvfr1 = 0x00000000;
1252 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
1253 cpu->id_pfr0 = 0x111;
1254 cpu->id_pfr1 = 0x1;
1255 cpu->id_dfr0 = 0;
1256 cpu->id_afr0 = 0x2;
1257 cpu->id_mmfr0 = 0x01100103;
1258 cpu->id_mmfr1 = 0x10020302;
1259 cpu->id_mmfr2 = 0x01222000;
1260 cpu->id_isar0 = 0x00100011;
1261 cpu->id_isar1 = 0x12002111;
1262 cpu->id_isar2 = 0x11221011;
1263 cpu->id_isar3 = 0x01102131;
1264 cpu->id_isar4 = 0x141;
1265 cpu->reset_auxcr = 1;
1266 }
1267
cortex_m0_initfn(Object * obj)1268 static void cortex_m0_initfn(Object *obj)
1269 {
1270 ARMCPU *cpu = ARM_CPU(obj);
1271 set_feature(&cpu->env, ARM_FEATURE_V6);
1272 set_feature(&cpu->env, ARM_FEATURE_M);
1273
1274 cpu->midr = 0x410cc200;
1275 }
1276
cortex_m3_initfn(Object * obj)1277 static void cortex_m3_initfn(Object *obj)
1278 {
1279 ARMCPU *cpu = ARM_CPU(obj);
1280 set_feature(&cpu->env, ARM_FEATURE_V7);
1281 set_feature(&cpu->env, ARM_FEATURE_M);
1282 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1283 cpu->midr = 0x410fc231;
1284 cpu->pmsav7_dregion = 8;
1285 cpu->id_pfr0 = 0x00000030;
1286 cpu->id_pfr1 = 0x00000200;
1287 cpu->id_dfr0 = 0x00100000;
1288 cpu->id_afr0 = 0x00000000;
1289 cpu->id_mmfr0 = 0x00000030;
1290 cpu->id_mmfr1 = 0x00000000;
1291 cpu->id_mmfr2 = 0x00000000;
1292 cpu->id_mmfr3 = 0x00000000;
1293 cpu->id_isar0 = 0x01141110;
1294 cpu->id_isar1 = 0x02111000;
1295 cpu->id_isar2 = 0x21112231;
1296 cpu->id_isar3 = 0x01111110;
1297 cpu->id_isar4 = 0x01310102;
1298 cpu->id_isar5 = 0x00000000;
1299 cpu->id_isar6 = 0x00000000;
1300 }
1301
cortex_m4_initfn(Object * obj)1302 static void cortex_m4_initfn(Object *obj)
1303 {
1304 ARMCPU *cpu = ARM_CPU(obj);
1305
1306 set_feature(&cpu->env, ARM_FEATURE_V7);
1307 set_feature(&cpu->env, ARM_FEATURE_M);
1308 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1309 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1310 cpu->midr = 0x410fc240; /* r0p0 */
1311 cpu->pmsav7_dregion = 8;
1312 cpu->id_pfr0 = 0x00000030;
1313 cpu->id_pfr1 = 0x00000200;
1314 cpu->id_dfr0 = 0x00100000;
1315 cpu->id_afr0 = 0x00000000;
1316 cpu->id_mmfr0 = 0x00000030;
1317 cpu->id_mmfr1 = 0x00000000;
1318 cpu->id_mmfr2 = 0x00000000;
1319 cpu->id_mmfr3 = 0x00000000;
1320 cpu->id_isar0 = 0x01141110;
1321 cpu->id_isar1 = 0x02111000;
1322 cpu->id_isar2 = 0x21112231;
1323 cpu->id_isar3 = 0x01111110;
1324 cpu->id_isar4 = 0x01310102;
1325 cpu->id_isar5 = 0x00000000;
1326 cpu->id_isar6 = 0x00000000;
1327 }
1328
cortex_m33_initfn(Object * obj)1329 static void cortex_m33_initfn(Object *obj)
1330 {
1331 ARMCPU *cpu = ARM_CPU(obj);
1332
1333 set_feature(&cpu->env, ARM_FEATURE_V8);
1334 set_feature(&cpu->env, ARM_FEATURE_M);
1335 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
1336 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
1337 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1338 cpu->midr = 0x410fd213; /* r0p3 */
1339 cpu->pmsav7_dregion = 16;
1340 cpu->sau_sregion = 8;
1341 cpu->id_pfr0 = 0x00000030;
1342 cpu->id_pfr1 = 0x00000210;
1343 cpu->id_dfr0 = 0x00200000;
1344 cpu->id_afr0 = 0x00000000;
1345 cpu->id_mmfr0 = 0x00101F40;
1346 cpu->id_mmfr1 = 0x00000000;
1347 cpu->id_mmfr2 = 0x01000000;
1348 cpu->id_mmfr3 = 0x00000000;
1349 cpu->id_isar0 = 0x01101110;
1350 cpu->id_isar1 = 0x02212000;
1351 cpu->id_isar2 = 0x20232232;
1352 cpu->id_isar3 = 0x01111131;
1353 cpu->id_isar4 = 0x01310132;
1354 cpu->id_isar5 = 0x00000000;
1355 cpu->id_isar6 = 0x00000000;
1356 cpu->clidr = 0x00000000;
1357 cpu->ctr = 0x8000c000;
1358 }
1359
arm_v7m_class_init(ObjectClass * oc,void * data)1360 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1361 {
1362 CPUClass *cc = CPU_CLASS(oc);
1363
1364 #ifndef CONFIG_USER_ONLY
1365 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1366 #endif
1367
1368 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1369 }
1370
1371 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1372 /* Dummy the TCM region regs for the moment */
1373 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1374 .access = PL1_RW, .type = ARM_CP_CONST },
1375 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1376 .access = PL1_RW, .type = ARM_CP_CONST },
1377 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
1378 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
1379 REGINFO_SENTINEL
1380 };
1381
cortex_r5_initfn(Object * obj)1382 static void cortex_r5_initfn(Object *obj)
1383 {
1384 ARMCPU *cpu = ARM_CPU(obj);
1385
1386 set_feature(&cpu->env, ARM_FEATURE_V7);
1387 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1388 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1389 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1390 set_feature(&cpu->env, ARM_FEATURE_PMSA);
1391 cpu->midr = 0x411fc153; /* r1p3 */
1392 cpu->id_pfr0 = 0x0131;
1393 cpu->id_pfr1 = 0x001;
1394 cpu->id_dfr0 = 0x010400;
1395 cpu->id_afr0 = 0x0;
1396 cpu->id_mmfr0 = 0x0210030;
1397 cpu->id_mmfr1 = 0x00000000;
1398 cpu->id_mmfr2 = 0x01200000;
1399 cpu->id_mmfr3 = 0x0211;
1400 cpu->id_isar0 = 0x02101111;
1401 cpu->id_isar1 = 0x13112111;
1402 cpu->id_isar2 = 0x21232141;
1403 cpu->id_isar3 = 0x01112131;
1404 cpu->id_isar4 = 0x0010142;
1405 cpu->id_isar5 = 0x0;
1406 cpu->id_isar6 = 0x0;
1407 cpu->mp_is_up = true;
1408 cpu->pmsav7_dregion = 16;
1409 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1410 }
1411
cortex_r5f_initfn(Object * obj)1412 static void cortex_r5f_initfn(Object *obj)
1413 {
1414 ARMCPU *cpu = ARM_CPU(obj);
1415
1416 cortex_r5_initfn(obj);
1417 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1418 }
1419
1420 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1421 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1422 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1423 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1424 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1425 REGINFO_SENTINEL
1426 };
1427
cortex_a8_initfn(Object * obj)1428 static void cortex_a8_initfn(Object *obj)
1429 {
1430 ARMCPU *cpu = ARM_CPU(obj);
1431
1432 cpu->dtb_compatible = "arm,cortex-a8";
1433 set_feature(&cpu->env, ARM_FEATURE_V7);
1434 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1435 set_feature(&cpu->env, ARM_FEATURE_NEON);
1436 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1437 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1438 set_feature(&cpu->env, ARM_FEATURE_EL3);
1439 cpu->midr = 0x410fc080;
1440 cpu->reset_fpsid = 0x410330c0;
1441 cpu->mvfr0 = 0x11110222;
1442 cpu->mvfr1 = 0x00011111;
1443 cpu->ctr = 0x82048004;
1444 cpu->reset_sctlr = 0x00c50078;
1445 cpu->id_pfr0 = 0x1031;
1446 cpu->id_pfr1 = 0x11;
1447 cpu->id_dfr0 = 0x400;
1448 cpu->id_afr0 = 0;
1449 cpu->id_mmfr0 = 0x31100003;
1450 cpu->id_mmfr1 = 0x20000000;
1451 cpu->id_mmfr2 = 0x01202000;
1452 cpu->id_mmfr3 = 0x11;
1453 cpu->id_isar0 = 0x00101111;
1454 cpu->id_isar1 = 0x12112111;
1455 cpu->id_isar2 = 0x21232031;
1456 cpu->id_isar3 = 0x11112131;
1457 cpu->id_isar4 = 0x00111142;
1458 cpu->dbgdidr = 0x15141000;
1459 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1460 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
1461 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
1462 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
1463 cpu->reset_auxcr = 2;
1464 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1465 }
1466
1467 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1468 /* power_control should be set to maximum latency. Again,
1469 * default to 0 and set by private hook
1470 */
1471 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1472 .access = PL1_RW, .resetvalue = 0,
1473 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1474 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1475 .access = PL1_RW, .resetvalue = 0,
1476 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1477 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1478 .access = PL1_RW, .resetvalue = 0,
1479 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1480 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1481 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1482 /* TLB lockdown control */
1483 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1484 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1485 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1486 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1487 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1488 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1489 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1490 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1491 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1492 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1493 REGINFO_SENTINEL
1494 };
1495
cortex_a9_initfn(Object * obj)1496 static void cortex_a9_initfn(Object *obj)
1497 {
1498 ARMCPU *cpu = ARM_CPU(obj);
1499
1500 cpu->dtb_compatible = "arm,cortex-a9";
1501 set_feature(&cpu->env, ARM_FEATURE_V7);
1502 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1503 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1504 set_feature(&cpu->env, ARM_FEATURE_NEON);
1505 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1506 set_feature(&cpu->env, ARM_FEATURE_EL3);
1507 /* Note that A9 supports the MP extensions even for
1508 * A9UP and single-core A9MP (which are both different
1509 * and valid configurations; we don't model A9UP).
1510 */
1511 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1512 set_feature(&cpu->env, ARM_FEATURE_CBAR);
1513 cpu->midr = 0x410fc090;
1514 cpu->reset_fpsid = 0x41033090;
1515 cpu->mvfr0 = 0x11110222;
1516 cpu->mvfr1 = 0x01111111;
1517 cpu->ctr = 0x80038003;
1518 cpu->reset_sctlr = 0x00c50078;
1519 cpu->id_pfr0 = 0x1031;
1520 cpu->id_pfr1 = 0x11;
1521 cpu->id_dfr0 = 0x000;
1522 cpu->id_afr0 = 0;
1523 cpu->id_mmfr0 = 0x00100103;
1524 cpu->id_mmfr1 = 0x20000000;
1525 cpu->id_mmfr2 = 0x01230000;
1526 cpu->id_mmfr3 = 0x00002111;
1527 cpu->id_isar0 = 0x00101111;
1528 cpu->id_isar1 = 0x13112111;
1529 cpu->id_isar2 = 0x21232041;
1530 cpu->id_isar3 = 0x11112131;
1531 cpu->id_isar4 = 0x00111142;
1532 cpu->dbgdidr = 0x35141000;
1533 cpu->clidr = (1 << 27) | (1 << 24) | 3;
1534 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1535 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1536 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1537 }
1538
1539 #ifndef CONFIG_USER_ONLY
a15_l2ctlr_read(CPUARMState * env,const ARMCPRegInfo * ri)1540 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1541 {
1542 /* Linux wants the number of processors from here.
1543 * Might as well set the interrupt-controller bit too.
1544 */
1545 return ((smp_cpus - 1) << 24) | (1 << 23);
1546 }
1547 #endif
1548
1549 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1550 #ifndef CONFIG_USER_ONLY
1551 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1552 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1553 .writefn = arm_cp_write_ignore, },
1554 #endif
1555 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1556 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1557 REGINFO_SENTINEL
1558 };
1559
cortex_a7_initfn(Object * obj)1560 static void cortex_a7_initfn(Object *obj)
1561 {
1562 ARMCPU *cpu = ARM_CPU(obj);
1563
1564 cpu->dtb_compatible = "arm,cortex-a7";
1565 set_feature(&cpu->env, ARM_FEATURE_V7VE);
1566 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1567 set_feature(&cpu->env, ARM_FEATURE_NEON);
1568 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1569 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1570 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1571 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1572 set_feature(&cpu->env, ARM_FEATURE_EL3);
1573 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
1574 cpu->midr = 0x410fc075;
1575 cpu->reset_fpsid = 0x41023075;
1576 cpu->mvfr0 = 0x10110222;
1577 cpu->mvfr1 = 0x11111111;
1578 cpu->ctr = 0x84448003;
1579 cpu->reset_sctlr = 0x00c50078;
1580 cpu->id_pfr0 = 0x00001131;
1581 cpu->id_pfr1 = 0x00011011;
1582 cpu->id_dfr0 = 0x02010555;
1583 cpu->pmceid0 = 0x00000000;
1584 cpu->pmceid1 = 0x00000000;
1585 cpu->id_afr0 = 0x00000000;
1586 cpu->id_mmfr0 = 0x10101105;
1587 cpu->id_mmfr1 = 0x40000000;
1588 cpu->id_mmfr2 = 0x01240000;
1589 cpu->id_mmfr3 = 0x02102211;
1590 /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
1591 * table 4-41 gives 0x02101110, which includes the arm div insns.
1592 */
1593 cpu->id_isar0 = 0x02101110;
1594 cpu->id_isar1 = 0x13112111;
1595 cpu->id_isar2 = 0x21232041;
1596 cpu->id_isar3 = 0x11112131;
1597 cpu->id_isar4 = 0x10011142;
1598 cpu->dbgdidr = 0x3515f005;
1599 cpu->clidr = 0x0a200023;
1600 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1601 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1602 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1603 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
1604 }
1605
cortex_a15_initfn(Object * obj)1606 static void cortex_a15_initfn(Object *obj)
1607 {
1608 ARMCPU *cpu = ARM_CPU(obj);
1609
1610 cpu->dtb_compatible = "arm,cortex-a15";
1611 set_feature(&cpu->env, ARM_FEATURE_V7VE);
1612 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1613 set_feature(&cpu->env, ARM_FEATURE_NEON);
1614 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1615 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1616 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1617 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1618 set_feature(&cpu->env, ARM_FEATURE_EL3);
1619 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1620 cpu->midr = 0x412fc0f1;
1621 cpu->reset_fpsid = 0x410430f0;
1622 cpu->mvfr0 = 0x10110222;
1623 cpu->mvfr1 = 0x11111111;
1624 cpu->ctr = 0x8444c004;
1625 cpu->reset_sctlr = 0x00c50078;
1626 cpu->id_pfr0 = 0x00001131;
1627 cpu->id_pfr1 = 0x00011011;
1628 cpu->id_dfr0 = 0x02010555;
1629 cpu->pmceid0 = 0x0000000;
1630 cpu->pmceid1 = 0x00000000;
1631 cpu->id_afr0 = 0x00000000;
1632 cpu->id_mmfr0 = 0x10201105;
1633 cpu->id_mmfr1 = 0x20000000;
1634 cpu->id_mmfr2 = 0x01240000;
1635 cpu->id_mmfr3 = 0x02102211;
1636 cpu->id_isar0 = 0x02101110;
1637 cpu->id_isar1 = 0x13112111;
1638 cpu->id_isar2 = 0x21232041;
1639 cpu->id_isar3 = 0x11112131;
1640 cpu->id_isar4 = 0x10011142;
1641 cpu->dbgdidr = 0x3515f021;
1642 cpu->clidr = 0x0a200023;
1643 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1644 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1645 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1646 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1647 }
1648
ti925t_initfn(Object * obj)1649 static void ti925t_initfn(Object *obj)
1650 {
1651 ARMCPU *cpu = ARM_CPU(obj);
1652 set_feature(&cpu->env, ARM_FEATURE_V4T);
1653 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1654 cpu->midr = ARM_CPUID_TI925T;
1655 cpu->ctr = 0x5109149;
1656 cpu->reset_sctlr = 0x00000070;
1657 }
1658
sa1100_initfn(Object * obj)1659 static void sa1100_initfn(Object *obj)
1660 {
1661 ARMCPU *cpu = ARM_CPU(obj);
1662
1663 cpu->dtb_compatible = "intel,sa1100";
1664 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1665 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1666 cpu->midr = 0x4401A11B;
1667 cpu->reset_sctlr = 0x00000070;
1668 }
1669
sa1110_initfn(Object * obj)1670 static void sa1110_initfn(Object *obj)
1671 {
1672 ARMCPU *cpu = ARM_CPU(obj);
1673 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1674 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1675 cpu->midr = 0x6901B119;
1676 cpu->reset_sctlr = 0x00000070;
1677 }
1678
pxa250_initfn(Object * obj)1679 static void pxa250_initfn(Object *obj)
1680 {
1681 ARMCPU *cpu = ARM_CPU(obj);
1682
1683 cpu->dtb_compatible = "marvell,xscale";
1684 set_feature(&cpu->env, ARM_FEATURE_V5);
1685 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1686 cpu->midr = 0x69052100;
1687 cpu->ctr = 0xd172172;
1688 cpu->reset_sctlr = 0x00000078;
1689 }
1690
pxa255_initfn(Object * obj)1691 static void pxa255_initfn(Object *obj)
1692 {
1693 ARMCPU *cpu = ARM_CPU(obj);
1694
1695 cpu->dtb_compatible = "marvell,xscale";
1696 set_feature(&cpu->env, ARM_FEATURE_V5);
1697 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1698 cpu->midr = 0x69052d00;
1699 cpu->ctr = 0xd172172;
1700 cpu->reset_sctlr = 0x00000078;
1701 }
1702
pxa260_initfn(Object * obj)1703 static void pxa260_initfn(Object *obj)
1704 {
1705 ARMCPU *cpu = ARM_CPU(obj);
1706
1707 cpu->dtb_compatible = "marvell,xscale";
1708 set_feature(&cpu->env, ARM_FEATURE_V5);
1709 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1710 cpu->midr = 0x69052903;
1711 cpu->ctr = 0xd172172;
1712 cpu->reset_sctlr = 0x00000078;
1713 }
1714
pxa261_initfn(Object * obj)1715 static void pxa261_initfn(Object *obj)
1716 {
1717 ARMCPU *cpu = ARM_CPU(obj);
1718
1719 cpu->dtb_compatible = "marvell,xscale";
1720 set_feature(&cpu->env, ARM_FEATURE_V5);
1721 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1722 cpu->midr = 0x69052d05;
1723 cpu->ctr = 0xd172172;
1724 cpu->reset_sctlr = 0x00000078;
1725 }
1726
pxa262_initfn(Object * obj)1727 static void pxa262_initfn(Object *obj)
1728 {
1729 ARMCPU *cpu = ARM_CPU(obj);
1730
1731 cpu->dtb_compatible = "marvell,xscale";
1732 set_feature(&cpu->env, ARM_FEATURE_V5);
1733 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1734 cpu->midr = 0x69052d06;
1735 cpu->ctr = 0xd172172;
1736 cpu->reset_sctlr = 0x00000078;
1737 }
1738
pxa270a0_initfn(Object * obj)1739 static void pxa270a0_initfn(Object *obj)
1740 {
1741 ARMCPU *cpu = ARM_CPU(obj);
1742
1743 cpu->dtb_compatible = "marvell,xscale";
1744 set_feature(&cpu->env, ARM_FEATURE_V5);
1745 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1746 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1747 cpu->midr = 0x69054110;
1748 cpu->ctr = 0xd172172;
1749 cpu->reset_sctlr = 0x00000078;
1750 }
1751
pxa270a1_initfn(Object * obj)1752 static void pxa270a1_initfn(Object *obj)
1753 {
1754 ARMCPU *cpu = ARM_CPU(obj);
1755
1756 cpu->dtb_compatible = "marvell,xscale";
1757 set_feature(&cpu->env, ARM_FEATURE_V5);
1758 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1759 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1760 cpu->midr = 0x69054111;
1761 cpu->ctr = 0xd172172;
1762 cpu->reset_sctlr = 0x00000078;
1763 }
1764
pxa270b0_initfn(Object * obj)1765 static void pxa270b0_initfn(Object *obj)
1766 {
1767 ARMCPU *cpu = ARM_CPU(obj);
1768
1769 cpu->dtb_compatible = "marvell,xscale";
1770 set_feature(&cpu->env, ARM_FEATURE_V5);
1771 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1772 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1773 cpu->midr = 0x69054112;
1774 cpu->ctr = 0xd172172;
1775 cpu->reset_sctlr = 0x00000078;
1776 }
1777
pxa270b1_initfn(Object * obj)1778 static void pxa270b1_initfn(Object *obj)
1779 {
1780 ARMCPU *cpu = ARM_CPU(obj);
1781
1782 cpu->dtb_compatible = "marvell,xscale";
1783 set_feature(&cpu->env, ARM_FEATURE_V5);
1784 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1785 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1786 cpu->midr = 0x69054113;
1787 cpu->ctr = 0xd172172;
1788 cpu->reset_sctlr = 0x00000078;
1789 }
1790
pxa270c0_initfn(Object * obj)1791 static void pxa270c0_initfn(Object *obj)
1792 {
1793 ARMCPU *cpu = ARM_CPU(obj);
1794
1795 cpu->dtb_compatible = "marvell,xscale";
1796 set_feature(&cpu->env, ARM_FEATURE_V5);
1797 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1798 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1799 cpu->midr = 0x69054114;
1800 cpu->ctr = 0xd172172;
1801 cpu->reset_sctlr = 0x00000078;
1802 }
1803
pxa270c5_initfn(Object * obj)1804 static void pxa270c5_initfn(Object *obj)
1805 {
1806 ARMCPU *cpu = ARM_CPU(obj);
1807
1808 cpu->dtb_compatible = "marvell,xscale";
1809 set_feature(&cpu->env, ARM_FEATURE_V5);
1810 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1811 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1812 cpu->midr = 0x69054117;
1813 cpu->ctr = 0xd172172;
1814 cpu->reset_sctlr = 0x00000078;
1815 }
1816
1817 #ifndef TARGET_AARCH64
1818 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
1819 * otherwise, a CPU with as many features enabled as our emulation supports.
1820 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1821 * this only needs to handle 32 bits.
1822 */
arm_max_initfn(Object * obj)1823 static void arm_max_initfn(Object *obj)
1824 {
1825 ARMCPU *cpu = ARM_CPU(obj);
1826
1827 if (kvm_enabled()) {
1828 kvm_arm_set_cpu_features_from_host(cpu);
1829 } else {
1830 cortex_a15_initfn(obj);
1831 #ifdef CONFIG_USER_ONLY
1832 /* We don't set these in system emulation mode for the moment,
1833 * since we don't correctly set the ID registers to advertise them,
1834 */
1835 set_feature(&cpu->env, ARM_FEATURE_V8);
1836 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1837 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1838 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1839 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1840 set_feature(&cpu->env, ARM_FEATURE_CRC);
1841 set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
1842 set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD);
1843 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
1844 #endif
1845 }
1846 }
1847 #endif
1848
1849 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1850
1851 typedef struct ARMCPUInfo {
1852 const char *name;
1853 void (*initfn)(Object *obj);
1854 void (*class_init)(ObjectClass *oc, void *data);
1855 } ARMCPUInfo;
1856
1857 static const ARMCPUInfo arm_cpus[] = {
1858 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1859 { .name = "arm926", .initfn = arm926_initfn },
1860 { .name = "arm946", .initfn = arm946_initfn },
1861 { .name = "arm1026", .initfn = arm1026_initfn },
1862 /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1863 * older core than plain "arm1136". In particular this does not
1864 * have the v6K features.
1865 */
1866 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1867 { .name = "arm1136", .initfn = arm1136_initfn },
1868 { .name = "arm1176", .initfn = arm1176_initfn },
1869 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1870 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1871 .class_init = arm_v7m_class_init },
1872 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1873 .class_init = arm_v7m_class_init },
1874 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1875 .class_init = arm_v7m_class_init },
1876 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1877 .class_init = arm_v7m_class_init },
1878 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1879 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1880 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1881 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1882 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1883 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1884 { .name = "ti925t", .initfn = ti925t_initfn },
1885 { .name = "sa1100", .initfn = sa1100_initfn },
1886 { .name = "sa1110", .initfn = sa1110_initfn },
1887 { .name = "pxa250", .initfn = pxa250_initfn },
1888 { .name = "pxa255", .initfn = pxa255_initfn },
1889 { .name = "pxa260", .initfn = pxa260_initfn },
1890 { .name = "pxa261", .initfn = pxa261_initfn },
1891 { .name = "pxa262", .initfn = pxa262_initfn },
1892 /* "pxa270" is an alias for "pxa270-a0" */
1893 { .name = "pxa270", .initfn = pxa270a0_initfn },
1894 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1895 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1896 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1897 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1898 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1899 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1900 #ifndef TARGET_AARCH64
1901 { .name = "max", .initfn = arm_max_initfn },
1902 #endif
1903 #ifdef CONFIG_USER_ONLY
1904 { .name = "any", .initfn = arm_max_initfn },
1905 #endif
1906 #endif
1907 { .name = NULL }
1908 };
1909
1910 static Property arm_cpu_properties[] = {
1911 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1912 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1913 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1914 DEFINE_PROP_UINT64("mp-affinity", ARMCPU,
1915 mp_affinity, ARM64_AFFINITY_INVALID),
1916 DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID),
1917 DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1),
1918 DEFINE_PROP_END_OF_LIST()
1919 };
1920
1921 #ifdef CONFIG_USER_ONLY
arm_cpu_handle_mmu_fault(CPUState * cs,vaddr address,int size,int rw,int mmu_idx)1922 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
1923 int rw, int mmu_idx)
1924 {
1925 ARMCPU *cpu = ARM_CPU(cs);
1926 CPUARMState *env = &cpu->env;
1927
1928 env->exception.vaddress = address;
1929 if (rw == 2) {
1930 cs->exception_index = EXCP_PREFETCH_ABORT;
1931 } else {
1932 cs->exception_index = EXCP_DATA_ABORT;
1933 }
1934 return 1;
1935 }
1936 #endif
1937
arm_gdb_arch_name(CPUState * cs)1938 static gchar *arm_gdb_arch_name(CPUState *cs)
1939 {
1940 ARMCPU *cpu = ARM_CPU(cs);
1941 CPUARMState *env = &cpu->env;
1942
1943 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1944 return g_strdup("iwmmxt");
1945 }
1946 return g_strdup("arm");
1947 }
1948
arm_cpu_class_init(ObjectClass * oc,void * data)1949 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1950 {
1951 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1952 CPUClass *cc = CPU_CLASS(acc);
1953 DeviceClass *dc = DEVICE_CLASS(oc);
1954
1955 device_class_set_parent_realize(dc, arm_cpu_realizefn,
1956 &acc->parent_realize);
1957 dc->props = arm_cpu_properties;
1958
1959 acc->parent_reset = cc->reset;
1960 cc->reset = arm_cpu_reset;
1961
1962 cc->class_by_name = arm_cpu_class_by_name;
1963 cc->has_work = arm_cpu_has_work;
1964 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1965 cc->dump_state = arm_cpu_dump_state;
1966 cc->set_pc = arm_cpu_set_pc;
1967 cc->gdb_read_register = arm_cpu_gdb_read_register;
1968 cc->gdb_write_register = arm_cpu_gdb_write_register;
1969 #ifdef CONFIG_USER_ONLY
1970 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1971 #else
1972 cc->do_interrupt = arm_cpu_do_interrupt;
1973 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1974 cc->do_transaction_failed = arm_cpu_do_transaction_failed;
1975 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1976 cc->asidx_from_attrs = arm_asidx_from_attrs;
1977 cc->vmsd = &vmstate_arm_cpu;
1978 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1979 cc->write_elf64_note = arm_cpu_write_elf64_note;
1980 cc->write_elf32_note = arm_cpu_write_elf32_note;
1981 #endif
1982 cc->gdb_num_core_regs = 26;
1983 cc->gdb_core_xml_file = "arm-core.xml";
1984 cc->gdb_arch_name = arm_gdb_arch_name;
1985 cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;
1986 cc->gdb_stop_before_watchpoint = true;
1987 cc->debug_excp_handler = arm_debug_excp_handler;
1988 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1989 #if !defined(CONFIG_USER_ONLY)
1990 cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
1991 #endif
1992
1993 cc->disas_set_info = arm_disas_set_info;
1994 #ifdef CONFIG_TCG
1995 cc->tcg_initialize = arm_translate_init;
1996 #endif
1997 }
1998
1999 #ifdef CONFIG_KVM
arm_host_initfn(Object * obj)2000 static void arm_host_initfn(Object *obj)
2001 {
2002 ARMCPU *cpu = ARM_CPU(obj);
2003
2004 kvm_arm_set_cpu_features_from_host(cpu);
2005 }
2006
2007 static const TypeInfo host_arm_cpu_type_info = {
2008 .name = TYPE_ARM_HOST_CPU,
2009 #ifdef TARGET_AARCH64
2010 .parent = TYPE_AARCH64_CPU,
2011 #else
2012 .parent = TYPE_ARM_CPU,
2013 #endif
2014 .instance_init = arm_host_initfn,
2015 };
2016
2017 #endif
2018
cpu_register(const ARMCPUInfo * info)2019 static void cpu_register(const ARMCPUInfo *info)
2020 {
2021 TypeInfo type_info = {
2022 .parent = TYPE_ARM_CPU,
2023 .instance_size = sizeof(ARMCPU),
2024 .instance_init = info->initfn,
2025 .class_size = sizeof(ARMCPUClass),
2026 .class_init = info->class_init,
2027 };
2028
2029 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
2030 type_register(&type_info);
2031 g_free((void *)type_info.name);
2032 }
2033
2034 static const TypeInfo arm_cpu_type_info = {
2035 .name = TYPE_ARM_CPU,
2036 .parent = TYPE_CPU,
2037 .instance_size = sizeof(ARMCPU),
2038 .instance_init = arm_cpu_initfn,
2039 .instance_post_init = arm_cpu_post_init,
2040 .instance_finalize = arm_cpu_finalizefn,
2041 .abstract = true,
2042 .class_size = sizeof(ARMCPUClass),
2043 .class_init = arm_cpu_class_init,
2044 };
2045
2046 static const TypeInfo idau_interface_type_info = {
2047 .name = TYPE_IDAU_INTERFACE,
2048 .parent = TYPE_INTERFACE,
2049 .class_size = sizeof(IDAUInterfaceClass),
2050 };
2051
arm_cpu_register_types(void)2052 static void arm_cpu_register_types(void)
2053 {
2054 const ARMCPUInfo *info = arm_cpus;
2055
2056 type_register_static(&arm_cpu_type_info);
2057 type_register_static(&idau_interface_type_info);
2058
2059 while (info->name) {
2060 cpu_register(info);
2061 info++;
2062 }
2063
2064 #ifdef CONFIG_KVM
2065 type_register_static(&host_arm_cpu_type_info);
2066 #endif
2067 }
2068
2069 type_init(arm_cpu_register_types)
2070