1 /*
2 * QEMU AArch64 CPU
3 *
4 * Copyright (c) 2013 Linaro Ltd
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "cpu.h"
24 #include "qemu-common.h"
25 #if !defined(CONFIG_USER_ONLY)
26 #include "hw/loader.h"
27 #endif
28 #include "hw/arm/arm.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/kvm.h"
31 #include "kvm_arm.h"
32 #include "qapi/visitor.h"
33
set_feature(CPUARMState * env,int feature)34 static inline void set_feature(CPUARMState *env, int feature)
35 {
36 env->features |= 1ULL << feature;
37 }
38
unset_feature(CPUARMState * env,int feature)39 static inline void unset_feature(CPUARMState *env, int feature)
40 {
41 env->features &= ~(1ULL << feature);
42 }
43
44 #ifndef CONFIG_USER_ONLY
a57_a53_l2ctlr_read(CPUARMState * env,const ARMCPRegInfo * ri)45 static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
46 {
47 ARMCPU *cpu = arm_env_get_cpu(env);
48
49 /* Number of cores is in [25:24]; otherwise we RAZ */
50 return (cpu->core_count - 1) << 24;
51 }
52 #endif
53
54 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
55 #ifndef CONFIG_USER_ONLY
56 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
57 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
58 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
59 .writefn = arm_cp_write_ignore },
60 { .name = "L2CTLR",
61 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
62 .access = PL1_RW, .readfn = a57_a53_l2ctlr_read,
63 .writefn = arm_cp_write_ignore },
64 #endif
65 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
66 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
67 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
68 { .name = "L2ECTLR",
69 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
70 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
71 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
72 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
73 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
74 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
75 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
76 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
77 { .name = "CPUACTLR",
78 .cp = 15, .opc1 = 0, .crm = 15,
79 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
80 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
81 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
82 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
83 { .name = "CPUECTLR",
84 .cp = 15, .opc1 = 1, .crm = 15,
85 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
86 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
87 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
88 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
89 { .name = "CPUMERRSR",
90 .cp = 15, .opc1 = 2, .crm = 15,
91 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
92 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
93 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
94 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
95 { .name = "L2MERRSR",
96 .cp = 15, .opc1 = 3, .crm = 15,
97 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
98 REGINFO_SENTINEL
99 };
100
aarch64_a57_initfn(Object * obj)101 static void aarch64_a57_initfn(Object *obj)
102 {
103 ARMCPU *cpu = ARM_CPU(obj);
104
105 cpu->dtb_compatible = "arm,cortex-a57";
106 set_feature(&cpu->env, ARM_FEATURE_V8);
107 set_feature(&cpu->env, ARM_FEATURE_VFP4);
108 set_feature(&cpu->env, ARM_FEATURE_NEON);
109 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
110 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
111 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
112 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
113 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
114 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
115 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
116 set_feature(&cpu->env, ARM_FEATURE_CRC);
117 set_feature(&cpu->env, ARM_FEATURE_EL2);
118 set_feature(&cpu->env, ARM_FEATURE_EL3);
119 set_feature(&cpu->env, ARM_FEATURE_PMU);
120 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
121 cpu->midr = 0x411fd070;
122 cpu->revidr = 0x00000000;
123 cpu->reset_fpsid = 0x41034070;
124 cpu->mvfr0 = 0x10110222;
125 cpu->mvfr1 = 0x12111111;
126 cpu->mvfr2 = 0x00000043;
127 cpu->ctr = 0x8444c004;
128 cpu->reset_sctlr = 0x00c50838;
129 cpu->id_pfr0 = 0x00000131;
130 cpu->id_pfr1 = 0x00011011;
131 cpu->id_dfr0 = 0x03010066;
132 cpu->id_afr0 = 0x00000000;
133 cpu->id_mmfr0 = 0x10101105;
134 cpu->id_mmfr1 = 0x40000000;
135 cpu->id_mmfr2 = 0x01260000;
136 cpu->id_mmfr3 = 0x02102211;
137 cpu->id_isar0 = 0x02101110;
138 cpu->id_isar1 = 0x13112111;
139 cpu->id_isar2 = 0x21232042;
140 cpu->id_isar3 = 0x01112131;
141 cpu->id_isar4 = 0x00011142;
142 cpu->id_isar5 = 0x00011121;
143 cpu->id_isar6 = 0;
144 cpu->id_aa64pfr0 = 0x00002222;
145 cpu->id_aa64dfr0 = 0x10305106;
146 cpu->pmceid0 = 0x00000000;
147 cpu->pmceid1 = 0x00000000;
148 cpu->id_aa64isar0 = 0x00011120;
149 cpu->id_aa64mmfr0 = 0x00001124;
150 cpu->dbgdidr = 0x3516d000;
151 cpu->clidr = 0x0a200023;
152 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
153 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
154 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
155 cpu->dcz_blocksize = 4; /* 64 bytes */
156 cpu->gic_num_lrs = 4;
157 cpu->gic_vpribits = 5;
158 cpu->gic_vprebits = 5;
159 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
160 }
161
aarch64_a53_initfn(Object * obj)162 static void aarch64_a53_initfn(Object *obj)
163 {
164 ARMCPU *cpu = ARM_CPU(obj);
165
166 cpu->dtb_compatible = "arm,cortex-a53";
167 set_feature(&cpu->env, ARM_FEATURE_V8);
168 set_feature(&cpu->env, ARM_FEATURE_VFP4);
169 set_feature(&cpu->env, ARM_FEATURE_NEON);
170 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
171 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
172 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
173 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
174 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
175 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
176 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
177 set_feature(&cpu->env, ARM_FEATURE_CRC);
178 set_feature(&cpu->env, ARM_FEATURE_EL2);
179 set_feature(&cpu->env, ARM_FEATURE_EL3);
180 set_feature(&cpu->env, ARM_FEATURE_PMU);
181 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
182 cpu->midr = 0x410fd034;
183 cpu->revidr = 0x00000000;
184 cpu->reset_fpsid = 0x41034070;
185 cpu->mvfr0 = 0x10110222;
186 cpu->mvfr1 = 0x12111111;
187 cpu->mvfr2 = 0x00000043;
188 cpu->ctr = 0x84448004; /* L1Ip = VIPT */
189 cpu->reset_sctlr = 0x00c50838;
190 cpu->id_pfr0 = 0x00000131;
191 cpu->id_pfr1 = 0x00011011;
192 cpu->id_dfr0 = 0x03010066;
193 cpu->id_afr0 = 0x00000000;
194 cpu->id_mmfr0 = 0x10101105;
195 cpu->id_mmfr1 = 0x40000000;
196 cpu->id_mmfr2 = 0x01260000;
197 cpu->id_mmfr3 = 0x02102211;
198 cpu->id_isar0 = 0x02101110;
199 cpu->id_isar1 = 0x13112111;
200 cpu->id_isar2 = 0x21232042;
201 cpu->id_isar3 = 0x01112131;
202 cpu->id_isar4 = 0x00011142;
203 cpu->id_isar5 = 0x00011121;
204 cpu->id_isar6 = 0;
205 cpu->id_aa64pfr0 = 0x00002222;
206 cpu->id_aa64dfr0 = 0x10305106;
207 cpu->id_aa64isar0 = 0x00011120;
208 cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
209 cpu->dbgdidr = 0x3516d000;
210 cpu->clidr = 0x0a200023;
211 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
212 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
213 cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
214 cpu->dcz_blocksize = 4; /* 64 bytes */
215 cpu->gic_num_lrs = 4;
216 cpu->gic_vpribits = 5;
217 cpu->gic_vprebits = 5;
218 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
219 }
220
aarch64_a72_initfn(Object * obj)221 static void aarch64_a72_initfn(Object *obj)
222 {
223 ARMCPU *cpu = ARM_CPU(obj);
224
225 cpu->dtb_compatible = "arm,cortex-a72";
226 set_feature(&cpu->env, ARM_FEATURE_V8);
227 set_feature(&cpu->env, ARM_FEATURE_VFP4);
228 set_feature(&cpu->env, ARM_FEATURE_NEON);
229 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
230 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
231 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
232 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
233 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
234 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
235 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
236 set_feature(&cpu->env, ARM_FEATURE_CRC);
237 set_feature(&cpu->env, ARM_FEATURE_EL2);
238 set_feature(&cpu->env, ARM_FEATURE_EL3);
239 set_feature(&cpu->env, ARM_FEATURE_PMU);
240 cpu->midr = 0x410fd083;
241 cpu->revidr = 0x00000000;
242 cpu->reset_fpsid = 0x41034080;
243 cpu->mvfr0 = 0x10110222;
244 cpu->mvfr1 = 0x12111111;
245 cpu->mvfr2 = 0x00000043;
246 cpu->ctr = 0x8444c004;
247 cpu->reset_sctlr = 0x00c50838;
248 cpu->id_pfr0 = 0x00000131;
249 cpu->id_pfr1 = 0x00011011;
250 cpu->id_dfr0 = 0x03010066;
251 cpu->id_afr0 = 0x00000000;
252 cpu->id_mmfr0 = 0x10201105;
253 cpu->id_mmfr1 = 0x40000000;
254 cpu->id_mmfr2 = 0x01260000;
255 cpu->id_mmfr3 = 0x02102211;
256 cpu->id_isar0 = 0x02101110;
257 cpu->id_isar1 = 0x13112111;
258 cpu->id_isar2 = 0x21232042;
259 cpu->id_isar3 = 0x01112131;
260 cpu->id_isar4 = 0x00011142;
261 cpu->id_isar5 = 0x00011121;
262 cpu->id_aa64pfr0 = 0x00002222;
263 cpu->id_aa64dfr0 = 0x10305106;
264 cpu->pmceid0 = 0x00000000;
265 cpu->pmceid1 = 0x00000000;
266 cpu->id_aa64isar0 = 0x00011120;
267 cpu->id_aa64mmfr0 = 0x00001124;
268 cpu->dbgdidr = 0x3516d000;
269 cpu->clidr = 0x0a200023;
270 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
271 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
272 cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
273 cpu->dcz_blocksize = 4; /* 64 bytes */
274 cpu->gic_num_lrs = 4;
275 cpu->gic_vpribits = 5;
276 cpu->gic_vprebits = 5;
277 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
278 }
279
cpu_max_get_sve_vq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)280 static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name,
281 void *opaque, Error **errp)
282 {
283 ARMCPU *cpu = ARM_CPU(obj);
284 visit_type_uint32(v, name, &cpu->sve_max_vq, errp);
285 }
286
cpu_max_set_sve_vq(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)287 static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
288 void *opaque, Error **errp)
289 {
290 ARMCPU *cpu = ARM_CPU(obj);
291 Error *err = NULL;
292
293 visit_type_uint32(v, name, &cpu->sve_max_vq, &err);
294
295 if (!err && (cpu->sve_max_vq == 0 || cpu->sve_max_vq > ARM_MAX_VQ)) {
296 error_setg(&err, "unsupported SVE vector length");
297 error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n",
298 ARM_MAX_VQ);
299 }
300 error_propagate(errp, err);
301 }
302
303 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
304 * otherwise, a CPU with as many features enabled as our emulation supports.
305 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
306 * this only needs to handle 64 bits.
307 */
aarch64_max_initfn(Object * obj)308 static void aarch64_max_initfn(Object *obj)
309 {
310 ARMCPU *cpu = ARM_CPU(obj);
311
312 if (kvm_enabled()) {
313 kvm_arm_set_cpu_features_from_host(cpu);
314 } else {
315 aarch64_a57_initfn(obj);
316 #ifdef CONFIG_USER_ONLY
317 /* We don't set these in system emulation mode for the moment,
318 * since we don't correctly set the ID registers to advertise them,
319 * and in some cases they're only available in AArch64 and not AArch32,
320 * whereas the architecture requires them to be present in both if
321 * present in either.
322 */
323 set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
324 set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
325 set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
326 set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
327 set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS);
328 set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
329 set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD);
330 set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
331 set_feature(&cpu->env, ARM_FEATURE_V8_FCMA);
332 set_feature(&cpu->env, ARM_FEATURE_SVE);
333 /* For usermode -cpu max we can use a larger and more efficient DCZ
334 * blocksize since we don't have to follow what the hardware does.
335 */
336 cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
337 cpu->dcz_blocksize = 7; /* 512 bytes */
338 #endif
339
340 cpu->sve_max_vq = ARM_MAX_VQ;
341 object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
342 cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
343 }
344 }
345
346 typedef struct ARMCPUInfo {
347 const char *name;
348 void (*initfn)(Object *obj);
349 void (*class_init)(ObjectClass *oc, void *data);
350 } ARMCPUInfo;
351
352 static const ARMCPUInfo aarch64_cpus[] = {
353 { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
354 { .name = "cortex-a53", .initfn = aarch64_a53_initfn },
355 { .name = "cortex-a72", .initfn = aarch64_a72_initfn },
356 { .name = "max", .initfn = aarch64_max_initfn },
357 { .name = NULL }
358 };
359
aarch64_cpu_get_aarch64(Object * obj,Error ** errp)360 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
361 {
362 ARMCPU *cpu = ARM_CPU(obj);
363
364 return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
365 }
366
aarch64_cpu_set_aarch64(Object * obj,bool value,Error ** errp)367 static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
368 {
369 ARMCPU *cpu = ARM_CPU(obj);
370
371 /* At this time, this property is only allowed if KVM is enabled. This
372 * restriction allows us to avoid fixing up functionality that assumes a
373 * uniform execution state like do_interrupt.
374 */
375 if (!kvm_enabled()) {
376 error_setg(errp, "'aarch64' feature cannot be disabled "
377 "unless KVM is enabled");
378 return;
379 }
380
381 if (value == false) {
382 unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
383 } else {
384 set_feature(&cpu->env, ARM_FEATURE_AARCH64);
385 }
386 }
387
aarch64_cpu_initfn(Object * obj)388 static void aarch64_cpu_initfn(Object *obj)
389 {
390 object_property_add_bool(obj, "aarch64", aarch64_cpu_get_aarch64,
391 aarch64_cpu_set_aarch64, NULL);
392 object_property_set_description(obj, "aarch64",
393 "Set on/off to enable/disable aarch64 "
394 "execution state ",
395 NULL);
396 }
397
aarch64_cpu_finalizefn(Object * obj)398 static void aarch64_cpu_finalizefn(Object *obj)
399 {
400 }
401
aarch64_cpu_set_pc(CPUState * cs,vaddr value)402 static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
403 {
404 ARMCPU *cpu = ARM_CPU(cs);
405 /* It's OK to look at env for the current mode here, because it's
406 * never possible for an AArch64 TB to chain to an AArch32 TB.
407 * (Otherwise we would need to use synchronize_from_tb instead.)
408 */
409 if (is_a64(&cpu->env)) {
410 cpu->env.pc = value;
411 } else {
412 cpu->env.regs[15] = value;
413 }
414 }
415
aarch64_gdb_arch_name(CPUState * cs)416 static gchar *aarch64_gdb_arch_name(CPUState *cs)
417 {
418 return g_strdup("aarch64");
419 }
420
aarch64_cpu_class_init(ObjectClass * oc,void * data)421 static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
422 {
423 CPUClass *cc = CPU_CLASS(oc);
424
425 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
426 cc->set_pc = aarch64_cpu_set_pc;
427 cc->gdb_read_register = aarch64_cpu_gdb_read_register;
428 cc->gdb_write_register = aarch64_cpu_gdb_write_register;
429 cc->gdb_num_core_regs = 34;
430 cc->gdb_core_xml_file = "aarch64-core.xml";
431 cc->gdb_arch_name = aarch64_gdb_arch_name;
432 }
433
aarch64_cpu_register(const ARMCPUInfo * info)434 static void aarch64_cpu_register(const ARMCPUInfo *info)
435 {
436 TypeInfo type_info = {
437 .parent = TYPE_AARCH64_CPU,
438 .instance_size = sizeof(ARMCPU),
439 .instance_init = info->initfn,
440 .class_size = sizeof(ARMCPUClass),
441 .class_init = info->class_init,
442 };
443
444 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
445 type_register(&type_info);
446 g_free((void *)type_info.name);
447 }
448
449 static const TypeInfo aarch64_cpu_type_info = {
450 .name = TYPE_AARCH64_CPU,
451 .parent = TYPE_ARM_CPU,
452 .instance_size = sizeof(ARMCPU),
453 .instance_init = aarch64_cpu_initfn,
454 .instance_finalize = aarch64_cpu_finalizefn,
455 .abstract = true,
456 .class_size = sizeof(AArch64CPUClass),
457 .class_init = aarch64_cpu_class_init,
458 };
459
aarch64_cpu_register_types(void)460 static void aarch64_cpu_register_types(void)
461 {
462 const ARMCPUInfo *info = aarch64_cpus;
463
464 type_register_static(&aarch64_cpu_type_info);
465
466 while (info->name) {
467 aarch64_cpu_register(info);
468 info++;
469 }
470 }
471
472 type_init(aarch64_cpu_register_types)
473